Integrated
in the MAIN domain:One Data Movement subsystem named DMSS can be used for efficient transfer of data
support between software, firmware and hardware in all combinations. It consists of the following
main modules:
- Packet DMA Controller
- Block Copy DMA Controller
- Ring Accelerator provides hardware acceleration
to enable straightforward passing of work between a producer and a consumer and has the following
main features:
- Supports 1024 independent memory-mapped ring
structures
- Supports various modes for each ring based on
usage and compatibility
- Provides single-word deep shared incoming
Transfer Response FIFO
- Provides bit-wide source VBUSM read/write target
interface for accesses from DMA controller entities
- Secure proxy module is a modified version of the
proxy module and in addition has the following main features:
- Supports a number of threads, where each has
their own independent proxy function
- Supports a programmable fixed queue for each
proxy thread
- Supports multiple producers all writing to the
same queue
- Supports programmable thresholds for when to
generate events
- Supports a max message count for outbound proxy
threads limiting the number of messages a thread can produce
- Interrupt Aggregator modules provide a
centralized machine which handles the termination of system events to that they can be coherently
processed by the host(s) in the system. Main features are as follows:
- 64-bit VBUSP target using 64-bit registers
- Provide a set of TI Interrupt Architecture
compliant interrupt status and mask registers which are used to pass specific event status to one or
more host blocks.
- Provide a set of Global Event Input (GEVI)
counters which can count events delivered via an ingress Event Transport Lane (ETL)
- Provides a set of Local Event Input (LEVI) to
Global event registers which can be used to convert pulsed discrete interrupt inputs or clock
synchronous rising edge events into Global events on an egress ETL
- Provides a set of GEVI 'Multicast' registers
which can take a Global event from an ingress ETL and generate two egress Global events on two
egress ETL interfaces
- One Timer Manager module to support timing
operations for the processes running on multiple processors, each with the following main features:
- 1024 × 32-bit RAM-based independent timers (2048
in total)
- Event interface to an interrupt aggregation
module in the NAVSS subsystem with events triggering when a timer expires or when an expired timer
is reset or deactivated
- Host access to determine which timer(s)
expired
- 32 registers with individual timeout status (one
bit per timer)
- Groups of 16 timers separated into pages of 4-K
address space
- Timer bits within each page to read expiration
status for each timer when software only has access to that page
- 10 μs time to cycle through all of the
timers
- Host access to reset individual timers
- Periodic hardware timers – a timer may be set to
automatically reprogram itself upon expiration without software intervention.
- Time Sync modules to facilitate host control of
time sync operations, each with the following main features:
- Supports a selection of multiple external clock
sources
- Software control of time sync events via
interrupt or polling
- Supports 8 hardware timestamp push inputs
- Supports timestamp counter compare output
- Supports timestamp counter bit output
- Supports 6 timestamp generator function
outputs
- 32-bit and 64-bit timestamp modes