SPRUIQ4 May   2019 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Introduction
    1.     Trademarks
    2.     Overview
  2. 1Getting Familiar With the Kit
    1. 1.1 Contents of the Kit
    2. 1.2 IDDK EVM Features
  3. 2Hardware Overview
    1. 2.1  IDDK Evaluation Board
    2. 2.2  Functional Blocks
    3. 2.3  Processor Section
    4. 2.4  Control Processor Slot – H1
    5. 2.5  Expansion Processor Slots
      1. 2.5.1 Real-time Connectivity – H7
      2. 2.5.2 Functional Safety – H8
    6. 2.6  Position Encoder Suite
      1. 2.6.1 QEP
      2. 2.6.2 Resolver
      3. 2.6.3 Sin-Cos Encoder
      4. 2.6.4 BiSS / EnDat Encoder
      5. 2.6.5 TI Design Interface Connector
    7. 2.7  Current Sensor Suite
      1. 2.7.1 Shunt Current Sensing
      2. 2.7.2 LEM Current Sensing
      3. 2.7.3 Sigma-Delta Current Sensing
      4. 2.7.4 Overcurrent Protection
    8. 2.8  Power Supplies and GND Plane Configurations
    9. 2.9  Rectifier and Inverter
      1. 2.9.1 Rectifier Stage
        1. 2.9.1.1 Connecting the External DC Supply to the DC Link
        2. 2.9.1.2 Connecting Rectifier Output to DC Link
      2. 2.9.2 Inverter Stage
    10. 2.10 DACs
    11. 2.11 Power Stage Disable Circuits
  4. 3Hardware Resource Mapping
    1. 3.1 Digital Signal Mapping
    2. 3.2 Analog Signal Mapping
    3. 3.3 Jumpers and Switches
    4. 3.4 Headers and Connectors

2.1 IDDK Evaluation Board

Figure 2-1 shows that the IDDK evaluation board is an open board without enclosures.

IDDK_EVM_kit_sprui23.pngFigure 2-1 IDDK EVM Kit

The board can be divided into the following functional blocks:

  • The processor (CPU) block for control, real-time connectivity, and functional safety
  • The position encoder suite
  • The current sensor suite
  • The power inverter and rectifier
  • Onboard power supplies

For experimentation, three GND planes are on the board: one plane is for safety and connectivity circuits, another plane is for control and interface, and a third plane is for high power circuits. Provisions are on the board to connect GND planes. If the control GND is tied to the power GND, ensure that position sensors and encoders connected to the board are properly grounded to earth.

NOTE

IDDK offers reconfigurable GND planes, an interprocessor interface, and power stage control. The GND plane configurations can change depending on the style of current sensing and position sensing in the drive solution. The default configuration of the GND planes is only intended for users to develop MCU software drivers to evaluate their topologies. TI does not recommend this configuration for any final drive design or solution. You can select and develop control strategies based on the GND plane reconfigurations and interprocessor interface.

The default isolation/GND configuration of revision R2.2.1 of this evaluation board is set up to have all controlCARDs (H1, H7, and H8) and their interface circuits be separate from the high voltage inverter GND. controlCARDS H1, H7, and H8 have COLD GND, while the inverter has HOT GND.

In the previous release of the board, IDDK R2.2, the control GND was tied to HOT GND in R2.2. In R2.2.1, control GND is tied to COLD GND. Take care while switching between these two boards considering the changes in control GND configuration..