SPRUIQ5 May   2019 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1 , TMS320F28379S

 

  1.   Introduction
    1.     Trademarks
    2.     DesignDRIVE IDDK Platform
  2. 1The Hardware Configuration
    1. 1.1 The DesignDRIVE Development kit (IDDK)
    2. 1.2 The Hardware Layout of IDDK
    3. 1.3 The IDDK Power Supplies
      1. 1.3.1 The Low-Voltage Power Domain
      2. 1.3.2 The High-Voltage Power Domain
  3. 2Setting Up the Test Hardware
    1. 2.1 Bringing Up the Board
  4. 3Setting Up the Software for IDDK Projects
    1. 3.1 Installing Code Composer and MotorControl SDK
    2. 3.2 Setting Up Code Composer Studio to Work With TMDXIDDK379D
    3. 3.3 Configuring a Project
    4. 3.4 Building and Loading the Project
    5. 3.5 Setting Up the Watch Window and Graphs
    6. 3.6 Running the Code
    7. 3.7 References

Building and Loading the Project

The TI motor control software has incremental builds where different components and macro blocks of the system are pieced together, one-by-one, to form the entire system. (This build structure helps to easily debug and understand the system.)

  1. Open the file fcl_qep_f2837x_tmdxiddk_settings.h from the CCS Edit Perspective.
  2. Set the BUILDLEVEL to LEVEL1.
  3. Save this file.
  4. NOTE

    After testing build 1, redefine BUILDLEVEL to LEVEL2 for the next level tests. Increment the BUILDLEVEL and perform the tests for each level until all builds are complete.

  5. Open the fcl_qep_f2837x_tmdxiddk.c file.
  6. Navigate to the motorControlISR() (or MainISR() in general) function.
  7. Locate the following piece of code in incremental build 1.
  8. DlogCh1=rg1.Out; DlogCh2=svgen1.Ta; DlogCh3=svgen1.Tb; DlogCh4=svgen1.Tc;
  9. Confirm that the datalog buffers point to the correct variables.
  10. NOTE

    These datalog buffers are large arrays that contain value-triggered data that can be displayed in a graph. In other incremental builds, variables may be put into this buffer to be graphed. The previous code is an example where the datalog buffers are pointed to the space vector generator module.

  11. Right-click on the project name.
  12. Click Rebuild Project.
  13. Ensure the console window is error free.
  14. When the build completes, click icon_debug_sprui24.png(Debug).
  15. NOTE

    A window as shown in Figure 3-5 may pop up if this is the first time opening the debug window. The window requests that you select one of the two CPUs in F28379x with which to connect.

    fig4-5_spruiq5.gifFigure 3-5 Selecting the CPU to Connect
  16. Click the box next to CPU1.
  17. NOTE

    The IDE automatically connects to the target.

  18. Load the output file into the device.
  19. Change to the debug perspective.
  20. Click Tools.
  21. Click Debugger Options.
  22. Click Program.
  23. Click Memory Load Options.
  24. Check Reset the target when loading or restarting the program to enable the debugger to reset the processor each time it reloads the program,.
  25. Click Remember My Settings to make this setting permanent,.
  26. Click icon_silicon_real_time_sprui24.png(Enable silicon real-time mode).
  27. NOTE

    Clicking this mode automatically selects icon_polite_real_time_sprui24.png (Enable polite real-time mode). This action lets you edit and view variables in real-time. Do not reset the CPU unless you disable these real-time options.

  28. If a message box appears, select yes to enable the debug events.
  29. NOTE

    This action sets bit 1 (the DGBM bit) of status register 1 (ST1) to 0. The DGBM is the debug enable mask bit. When the DGBM bit is set to 0, memory and register values can pass to the host processor to update the debugger windows.