SPRUIR8B april   2020  – july 2023

 

  1.   1
  2.   CLB Tool
  3.   Trademarks
  4. 1Introduction
    1. 1.1 CLB Tool Outline
    2. 1.2 Overview of the CLB Configuration Process
  5. 2Getting Started
    1. 2.1 CLB Related Collateral
    2. 2.2 Introduction
    3. 2.3 Installation
      1. 2.3.1 Installation to Compile SystemC
      2. 2.3.2 Install the Simulation Viewer
  6. 3Using the CLB Tool
    1. 3.1 Import the Empty CLB Project
    2. 3.2 Updating Variable Paths
    3. 3.3 Configuring a CLB Tile
    4. 3.4 Creating the CLB Diagram
    5. 3.5 Using the Simulator
      1. 3.5.1 The Statics Panel
      2. 3.5.2 Creating the Input Stimulus
      3. 3.5.3 Running the Simulation
      4. 3.5.4 Trace Signal Descriptions
  7. 4Examples
    1. 4.1 Foundational Examples
      1. 4.1.1  CLB Empty Project
      2. 4.1.2  Example 3 – PWM Generation
      3. 4.1.3  Example 7 – State Machine
      4. 4.1.4  Example 13 – PUSH-PULL Interface
      5. 4.1.5  Example 14 – Multi-Tile
      6. 4.1.6  Example 15 – Tile to Tile Delay
      7. 4.1.7  Example 16 - Glue Logic
      8. 4.1.8  Exampe 18 - AOC
      9. 4.1.9  Example 19 - AOC Release Control
      10. 4.1.10 Example 20 - CLB XBARs
    2. 4.2 Getting Started Examples
      1. 4.2.1  Example 1 – Combinatorial Logic
      2. 4.2.2  Example 2 – GPIO Input Filter
      3. 4.2.3  Example 4 – PWM Protection
      4. 4.2.4  Example 5 – Event Window
      5. 4.2.5  Example 6 – Signal Generation and Check
      6. 4.2.6  Example 8 – External AND Gate
      7. 4.2.7  Example 9 – Timer
      8. 4.2.8  Example 10 – Timer With Two States
      9. 4.2.9  Example 11 – Interrupt Tag
      10. 4.2.10 Example 12 – Output Intersect
      11. 4.2.11 Example 17 – One-Shot PWM Generation
      12. 4.2.12 Example 21 - Clock Prescaler and NMI
      13. 4.2.13 Example 22 - Serializer
      14. 4.2.14 Example 23 - LFSR
      15. 4.2.15 Example 24 - Lock Output Mask
      16. 4.2.16 Example 25 - Input Pipeline Mode
      17. 4.2.17 Example 26 - Clocking Pipeline Mode
    3. 4.3 Expert Examples
      1. 4.3.1 Example 27 - SPI Data Export
      2. 4.3.2 Example 28 - SPI Data Export DMA
      3. 4.3.3 Example 29 - Timestamp
      4. 4.3.4 Example 30 - Cyclic Redundancy Check
      5. 4.3.5 CLB TDM Serial Port
      6. 4.3.6 CLB LED Driver
      7. 4.3.7 FPGA/CPLD to C2000 Examples
  8. 5Enabling CLB Tool in Existing DriverLib Projects
  9. 6Frequently Asked Questions (FAQs)
  10. 7Revision History

3.5.4 Trace Signal Descriptions

This section includes a brief explanation for the different trace signals that are created in the "CLB.vcd" file. Note that some signals or groups are not available depending on the type of CLB available on the device for which the simulation is created.

Note: These conventions are used to abbreviate and shorten the list of trace signals:
  1. "TILE#" is the name of the Tile Design instance
  2. "N" represents 0 through 7, for multiple instances of the indicated signal
  3. "X" represents 0 through 2, for multiple instances of the indicated signal
  4. "Y" represents 0 through 3, for multiple instances of the indicated signal
Table 3-3 SystemC Top Level Trace Signals
Trace Signal Name Description
sc_top_clock Clock signal of the CLB
sc_top_reset Reset for the CLB
sc_top_enable CLB enable signal; used to enable the CLB submodules
Table 3-4 Asynchronous Output Conditioning Block Trace Signals (CLB Type 2)
Trace Signal Name Description
TILE#_AOC_N_clb_output Output from the AOC submodule
TILE#_AOC_N_mux_ctrl [15:0] AOC mux control value; value is in the same format as the CLB_OUTPUT_COND_CTRL_N register
TILE#_AOC_N_release_signal Release signal; determines when the CLB output is set, cleared, or delayed depending on the release option chosen in TILE#_AOC_N_mux_ctrl (default release signal does not alter CLB output)
TILE#_AOC_N_gate_signal Gate signal; this signal is logically combined with the CLB output using an AND, OR, or XOR depending on the selection chosen in TILE#_AOC_N_mux_ctrl (default gate signal does not alter output)
TILE#_AOC_N_mux_input_clb_tile_output CLB output signal corresponding to the same AOC number of the signal; i.e. CLB output 0 is an input option for AOC 0
TILE#_AOC_N_mux_input_boundary_input CLB boundary input signal corresponding to the same AOC number of the signal; i.e. CLB boundary input 0 is an input option for AOC 0
Table 3-5 Boundary Trace Signals
Trace Signal Name Description
TILE#_BOUNDARY_CLB_outputN CLB boundary output signal; this signal is routed out of the CLB peripheral to the rest of the device; this signal has passed through the AOC submodule if the device has this type of CLB (check the CLB Tile section in the device technical reference manual for more details)
TILE#_BOUNDARY_muxed_and_filtered_inputN Input to the CLB module after passing through any synchronization, input pipeline filters, or edge filters enabled
TILE#_BOUNDARY_inputN_ctrl [31:0] Control value for enabling synchronization, input pipeline filters, or edge filters
TILE#_BOUNDARY_original_inputN Input to the CLB module before any modification such as synchronization, pipelining, or edge filtering
TILE#_BOUNDARY_clock Clock signal of the CLB
Table 3-6 Counter Block Trace Signals
Trace Signal Name Description
TILE#_COUNTER_X_reconfig_pipeline_en Enable for reconfigurable pipelining which pipelines the operations of the HLC and counter submodules (this is not the same enable as the pipeline input filter enable)
TILE#_COUNTER_X_counter_equals_match2 This signal is high when the counter value equals the match reference 2 value; if the match reference 2 tap output is enabled for serializer mode, this signal is high when the counter bit position selected is high
TILE#_COUNTER_X_counter_equals_match1 This signal is high when the counter value equals the match reference 1 value; if the match reference 1 tap output is enabled for serializer mode, this signal is high when the counter bit position selected is high
TILE#_COUNTER_X_counter_equals_zero This signal is high when the counter value equals zero
TILE#_COUNTER_X_match2_val [31:0] Value of the match reference 2 value; can be modified by the HLC
TILE#_COUNTER_X_match1_val [31:0] Value of the match reference 1 value; can be modified by the HLC
TILE#_COUNTER_X_counter_output [31:0] Value of the counter itself
TILE#_COUNTER_X_hlc_match2_load_en Load enable which determines when to load the match reference 2 value from the HLC submodule; this matches the TILE#_HLC_hlc_counterX_match2_load_en signal
TILE#_COUNTER_X_hlc_match1_load_en Load enable which determines when to load the match reference 1 value from the HLC submodule; this matches the TILE#_HLC_hlc_counterX_match1_load_en signal
TILE#_COUNTER_X_hlc_counter_load_en Load enable which determines when to load the counter with a value from the HLC submodule; this matches the TILE#_HLC_hlc_counterX_load_en signal
TILE#_COUNTER_X_hlc_counter_load_val [31:0] Counter value loaded from the HLC submodule; this value is loaded to the match reference 1, match reference 2, or counter value depending on if the appropriate HLC load enable is set (i.e. depending on what instruction is being executed by the HLC). This matches the TILE#_HLC_counter_hlc_load_value signal
TILE#_COUNTER_X_match2_tap [4:0] Specifies which bit of the counter to tap for match reference 2
TILE#_COUNTER_X_match2_tap_en Enable which allows the counter to tap a bit specified by TILE#_COUNTER_X_match2_tap; TILE#_COUNTER_X_counter_equals_match2 is high when the appropriate tap bit is set, which effectively brings out a bit position from the counter to the match reference 2 output
TILE#_COUNTER_X_match1_tap [4:0] Specifies which bit of the counter to tap for match reference 1
TILE#_COUNTER_X_match1_tap_en Enable which allows the counter to tap a bit specified by TILE#_COUNTER_X_match1_tap; TILE#_COUNTER_X_counter_equals_match1 is high when the appropriate tap bit is set, which effectively brings out a bit position from the counter to the match reference 2 output
TILE#_COUNTER_X_lfsr_en Enable for the Linear Feedback Shift Register; this allows the counter submodule to compute the CRC on a serial bit stream
TILE#_COUNTER_X_global_serializer_en Enable for the serializer; when enabled, the counter loads either the next LFSR serial value or the appropriate serial value (see the device technical reference manual for more details)
TILE#_COUNTER_X_mode1 Controls the direction of the counter; counts up when set to 1, counts down when set to 0
TILE#_COUNTER_X_mode0 Controls whether the counter is stopped; enables counting when set to 1
TILE#_COUNTER_X_global_reset Reset for the CLB
TILE#_COUNTER_X_add_or_shift_dir When the counter event is enabled and not configured for a load event, this signal is high when the event adds or shifts the counter value left and is set 0 otherwise
TILE#_COUNTER_X_add_or_shift_on_event_en This signal is set high if the counter is configured to add or shift when an event occurs and is set 0 otherwise
TILE#_COUNTER_X_add_or_shift_mode This signal is set high if the counter is adding or subtracting and is set 0 otherwise
TILE#_COUNTER_X_global_en CLB enable signal
TILE#_COUNTER_X_event_load_val [31:0] When an event occurs and the event action is configured to be 'load', this value is loaded to the counter
TILE#_COUNTER_X_event This signal is high when an event has occurred or is occurring
TILE#_COUNTER_X_counter_reset Reset for the counter submodule
TILE#_COUNTER_X_clock Clock signal of the CLB
Table 3-7 Finite State Machine Block Trace Signals
Trace Signal Name Description
TILE#_FSM_X_fsm_lut_output Output for the FSM look-up table output equation
TILE#_FSM_X_fsm_s1_output Output for the FSM state 1 equation
TILE#_FSM_X_fsm_s0_output Output for the FSM state 0 equation
TILE#_FSM_X_LUT_output_equation [15:0] Value representing the FSM look-up table output equation
TILE#_FSM_X_state1_equation_output [15:0] Value representing the FSM state 1 equation
TILE#_FSM_X_state0_equation_output [15:0] Value representing the FSM state 0 equation
TILE#_FSM_X_extra_external_input_select1 Selects where the value of external input 3 (e3) is coming from; when high e3 is used, and when low state 1 (s1) is used
TILE#_FSM_X_extra_external_input_select0 Selects where the value of external input 2 (e2) is coming from; when high e2 is used, and when low state 0 (s0) is used
TILE#_FSM_X_extra_external_input1 Extra external input 1 (xe1) to the FSM submodule; the signal chosen as xe1 comes from within the CLB and can be used only in the look-up table output equation
TILE#_FSM_X_extra_external_input0 Extra external input 0 (xe0) to the FSM submodule; the signal chosen as xe0 comes from within the CLB and can be used only in the look-up table output equation
TILE#_FSM_X_external_input1 External input 1 (e1) to the FSM submodule; the signal chosen as e1 comes from within the CLB and can be used in the state 0, state 1, and look-up table output equations
TILE#_FSM_X_external_input0 External input 0 (e0) to the FSM submodule; the signal chosen as e0 comes from within the CLB and can be used in the state 0, state 1, and look-up table output equations
TILE#_FSM_X_global_reset Reset for the CLB
TILE#_FSM_X_global_en CLB enable signal
TILE#_FSM_X_clock Clock signal of the CLB
Table 3-8 High Level Controller Block Trace Signals
Trace Signal Name Description
TILE#_HLC_spi_export_receive_buffer [15:0] Representation of the data stored in a SPI RX buffer; this helps validate data exporting through the SPI buffer using the HLC submodule
TILE#_HLC_fifo_overflow_signal When high, this signal indicates a FIFO overflow has occurred (pushing when the FIFO is full)
TILE#_HLC_fifo_underflow_signal When high, this signal indicates a FIFO underflow has occurred (pulling when the FIFO is empty)
TILE#_HLC_fifo_write_pointer [1:0] Current value of the write pointer for the push FIFO (zero-indexed)
TILE#_HLC_fifo_read_pointer [1:0] Current value of the read pointer for the pull FIFO (zero-indexed)
TILE#_HLC_push_fifo(Y) [31:0] Represents the current values in the push FIFO
TILE#_HLC_pull_fifo(Y) [31:0] Represents the current values in the pull FIFO
TILE#_HLC_program_current_instruction [11:0] Signal which shows the opcode of the current instruction being executed by the HLC
TILE#_HLC_register(Y) [31:0] Represents the current values of the HLC registers R0 through R3
TILE#_HLC_program_interrupt_number [31:0] Signal which indicates which interrupt has been triggered by the HLC; the default values is 0xFFFF, otherwise the value represents the interrupt value from the last 6 bits of the interrupt opcode
TILE#_HLC_program_interrupt_flag This signal is high when the current instruction being executed by the HLC is an interrupt
TILE#_HLC_hlc_counterX_match2_load_en Enable which goes high when the HLC is loading the corresponding counter match reference 2 value using the MOV_T2 instruction; this matches the appropriate TILE#_COUNTER_X_hlc_match2_load_en signal
TILE#_HLC_hlc_counterX_match1_load_en Enable which goes high when the HLC is loading the the corresponding counter match reference 1 value using the MOV_T1 instruction; this matches the appropriate TILE#_COUNTER_X_hlc_match1_load_en signal
TILE#_HLC_hlc_counterX_load_en Enable which goes high when the HLC is loading the the corresponding counter value using the MOV instruction; this matches the appropriate TILE#_COUNTER_X_hlc_counter_load_en signal
TILE#_HLC_counter_hlc_load_value [31:0] Counter value loaded to the match reference 1, match reference 2, or counter value depending on what instruction is being executed by the HLC; this matches the appropriate TILE#_COUNTER_X_hlc_counter_load_val signal
TILE#_HLC_spi_export_enable This signal indicates that data export via the SPI RX buffer is enabled
TILE#_HLC_reconfig_pipeline_enable This signal indicates that the reconfigurable pipeline mode is enabled (this affects both the counter and HLC submodules)
TILE#_HLC_alternate_event_clb_async_output(N) This set of signals represents the asynchronous output of the CLB which comes from the AOC submodules; this is one of the alternate events used for the HLC
TILE#_HLC_alternate_event_clb_output(N) This set of signals represents the output of the CLB, which comes from the OUTLUT submodules; this is one of the alternate events used for the HLC
TILE#_HLC_hlc_event_trigger(31..0) A set of signals representing the triggers for the HLC events; to find which event trigger corresponds to which HLC event trigger value, check the device technical reference manual (note that alternate events are not part of this set of signals)
TILE#_HLC_alternate_event_input_selectY This selection indicates whether the alternate set of events is used for the corresponding HLC event
TILE#_HLC_spi_shift_value [4:0] Value determining which 16 bits of the 32-bit R0 register are exported to the SPI RX buffer (i.e. a value of 1 selects bits 16:1 of the R0 register)
TILE#_HLC_spi_event_trigger [4:0] This signal determines which HLC event causes the data export to the SPI RX buffer (note that the event options are from the static switch block as described in the device technical reference manual)
TILE#_HLC_programY_event_source [31:0] This value indicates which event trigger is being used for the corresponding HLC event; i.e. a value of 1 for TILE#_HLC_program0_event_source (with the alternate event input select set to 0) uses counter 0 match reference 2 for the source of event 0, which triggers HLC program 0
TILE#_HLC_counterX_value [31:0] Current value of the corresponding counter; this indicates what value is being used in the execution of HLC instructions with C0, C1, or C2 as operands
TILE#_HLC_program_global_load_en CLB enable signal
TILE#_HLC_program_reset Reset for the CLB
TILE#_HLC_program_clock Clock signal of the CLB
Table 3-9 Look-Up Table Block Trace Signals
Trace Signal Name Description
TILE#_LUT_X_output Output for the look-up table submodule
TILE#_LUT_X_output_equation [15:0] Value representing the look-up table logic equation
TILE#_LUT_X_inputY Input for the look-up table submodule
Table 3-10 Output Look-Up Table Block Trace Signals
Trace Signal Name Description
TILE#_OUTLUT_N_output Output for the output look-up table submodule
TILE#_OUTLUT_N_output_equation [7:0] Value representing the output look-up table logic equation
TILE#_OUTLUT_N_inputX Input for the look-up table submodule