SPRUIR8B april   2020  – july 2023

 

  1.   1
  2.   CLB Tool
  3.   Trademarks
  4. 1Introduction
    1. 1.1 CLB Tool Outline
    2. 1.2 Overview of the CLB Configuration Process
  5. 2Getting Started
    1. 2.1 CLB Related Collateral
    2. 2.2 Introduction
    3. 2.3 Installation
      1. 2.3.1 Installation to Compile SystemC
      2. 2.3.2 Install the Simulation Viewer
  6. 3Using the CLB Tool
    1. 3.1 Import the Empty CLB Project
    2. 3.2 Updating Variable Paths
    3. 3.3 Configuring a CLB Tile
    4. 3.4 Creating the CLB Diagram
    5. 3.5 Using the Simulator
      1. 3.5.1 The Statics Panel
      2. 3.5.2 Creating the Input Stimulus
      3. 3.5.3 Running the Simulation
      4. 3.5.4 Trace Signal Descriptions
  7. 4Examples
    1. 4.1 Foundational Examples
      1. 4.1.1  CLB Empty Project
      2. 4.1.2  Example 3 – PWM Generation
      3. 4.1.3  Example 7 – State Machine
      4. 4.1.4  Example 13 – PUSH-PULL Interface
      5. 4.1.5  Example 14 – Multi-Tile
      6. 4.1.6  Example 15 – Tile to Tile Delay
      7. 4.1.7  Example 16 - Glue Logic
      8. 4.1.8  Exampe 18 - AOC
      9. 4.1.9  Example 19 - AOC Release Control
      10. 4.1.10 Example 20 - CLB XBARs
    2. 4.2 Getting Started Examples
      1. 4.2.1  Example 1 – Combinatorial Logic
      2. 4.2.2  Example 2 – GPIO Input Filter
      3. 4.2.3  Example 4 – PWM Protection
      4. 4.2.4  Example 5 – Event Window
      5. 4.2.5  Example 6 – Signal Generation and Check
      6. 4.2.6  Example 8 – External AND Gate
      7. 4.2.7  Example 9 – Timer
      8. 4.2.8  Example 10 – Timer With Two States
      9. 4.2.9  Example 11 – Interrupt Tag
      10. 4.2.10 Example 12 – Output Intersect
      11. 4.2.11 Example 17 – One-Shot PWM Generation
      12. 4.2.12 Example 21 - Clock Prescaler and NMI
      13. 4.2.13 Example 22 - Serializer
      14. 4.2.14 Example 23 - LFSR
      15. 4.2.15 Example 24 - Lock Output Mask
      16. 4.2.16 Example 25 - Input Pipeline Mode
      17. 4.2.17 Example 26 - Clocking Pipeline Mode
    3. 4.3 Expert Examples
      1. 4.3.1 Example 27 - SPI Data Export
      2. 4.3.2 Example 28 - SPI Data Export DMA
      3. 4.3.3 Example 29 - Timestamp
      4. 4.3.4 Example 30 - Cyclic Redundancy Check
      5. 4.3.5 CLB TDM Serial Port
      6. 4.3.6 CLB LED Driver
      7. 4.3.7 FPGA/CPLD to C2000 Examples
  8. 5Enabling CLB Tool in Existing DriverLib Projects
  9. 6Frequently Asked Questions (FAQs)
  10. 7Revision History

3.2 Updating Variable Paths

The empty CLB project imported above has the capability to not only generate the “.out” file for the C28x target device, but also has the capability to generate the simulation files and the HTML/SVG block diagram of the design. To create the diagrams using the post-build steps, the proper path must be set for the location of the C2000Ware root and Node tool. To double check that these paths are correct:

  1. Right click on the project and select ‘Project Properties’.
  2. Under ‘Resources’, select ‘Linked Resources’.
  3. Check to make sure the path below is correct:
    1. C2000WARE_ROOT (This is used for the CLB diagrams and for other include paths)
      GUID-4B8F18D1-49DA-48D5-B769-144FAF7C80C9-low.png Figure 3-2 Linked Resources
  4. If the icon to the left of the name is not a folder, and is instead an exclamation point, the path does not exist on your system and you must manually select the correct one
  5. Check to make sure the path for the below system variable is correct:
    1. NODE_TOOL
      GUID-D409737B-E049-4792-AC80-DBD17D43E02F-low.png Figure 3-3 Build Variables

To generate the block diagram, the build variable GENERATE_DIAGRAM must be set to 1. The build variables for a project can be found by going to Project Properties > Build > Variables, as seen in Figure 3-4. This variable enables the post-build steps listed under 'Steps' to run after the project is built. The block diagrams can be found under the relevant build configuration of the project in the 'diagrams' directory, as seen in Figure 5-5.

Note: For Mac and Linux, the conditionals used in the post-build steps will not be able to execute properly. To generate the diagram, the test if ${GENERATE_DIAGRAM} == 1 must be removed.

GUID-4567E1AD-6347-4D8B-940E-B5053EE45CB4-low.png Figure 3-4 Build Variable to Generate Diagram