SPRUIR8B april   2020  – july 2023

 

  1.   1
  2.   CLB Tool
  3.   Trademarks
  4. 1Introduction
    1. 1.1 CLB Tool Outline
    2. 1.2 Overview of the CLB Configuration Process
  5. 2Getting Started
    1. 2.1 CLB Related Collateral
    2. 2.2 Introduction
    3. 2.3 Installation
      1. 2.3.1 Installation to Compile SystemC
      2. 2.3.2 Install the Simulation Viewer
  6. 3Using the CLB Tool
    1. 3.1 Import the Empty CLB Project
    2. 3.2 Updating Variable Paths
    3. 3.3 Configuring a CLB Tile
    4. 3.4 Creating the CLB Diagram
    5. 3.5 Using the Simulator
      1. 3.5.1 The Statics Panel
      2. 3.5.2 Creating the Input Stimulus
      3. 3.5.3 Running the Simulation
      4. 3.5.4 Trace Signal Descriptions
  7. 4Examples
    1. 4.1 Foundational Examples
      1. 4.1.1  CLB Empty Project
      2. 4.1.2  Example 3 – PWM Generation
      3. 4.1.3  Example 7 – State Machine
      4. 4.1.4  Example 13 – PUSH-PULL Interface
      5. 4.1.5  Example 14 – Multi-Tile
      6. 4.1.6  Example 15 – Tile to Tile Delay
      7. 4.1.7  Example 16 - Glue Logic
      8. 4.1.8  Exampe 18 - AOC
      9. 4.1.9  Example 19 - AOC Release Control
      10. 4.1.10 Example 20 - CLB XBARs
    2. 4.2 Getting Started Examples
      1. 4.2.1  Example 1 – Combinatorial Logic
      2. 4.2.2  Example 2 – GPIO Input Filter
      3. 4.2.3  Example 4 – PWM Protection
      4. 4.2.4  Example 5 – Event Window
      5. 4.2.5  Example 6 – Signal Generation and Check
      6. 4.2.6  Example 8 – External AND Gate
      7. 4.2.7  Example 9 – Timer
      8. 4.2.8  Example 10 – Timer With Two States
      9. 4.2.9  Example 11 – Interrupt Tag
      10. 4.2.10 Example 12 – Output Intersect
      11. 4.2.11 Example 17 – One-Shot PWM Generation
      12. 4.2.12 Example 21 - Clock Prescaler and NMI
      13. 4.2.13 Example 22 - Serializer
      14. 4.2.14 Example 23 - LFSR
      15. 4.2.15 Example 24 - Lock Output Mask
      16. 4.2.16 Example 25 - Input Pipeline Mode
      17. 4.2.17 Example 26 - Clocking Pipeline Mode
    3. 4.3 Expert Examples
      1. 4.3.1 Example 27 - SPI Data Export
      2. 4.3.2 Example 28 - SPI Data Export DMA
      3. 4.3.3 Example 29 - Timestamp
      4. 4.3.4 Example 30 - Cyclic Redundancy Check
      5. 4.3.5 CLB TDM Serial Port
      6. 4.3.6 CLB LED Driver
      7. 4.3.7 FPGA/CPLD to C2000 Examples
  8. 5Enabling CLB Tool in Existing DriverLib Projects
  9. 6Frequently Asked Questions (FAQs)
  10. 7Revision History

4.2.5 Example 6 – Signal Generation and Check

This example uses CLB1 to generate a rectangular wave and CLB2 to check the rectangular wave generated by CLB1 doesn’t exceed the defined duty cycle and period limits.

CLB1: This example uses the counter and FSM sub-modules of the CLB to implement a rectangular pulse generator. The counter0 generates events on Match1 and Match2 values programmed by the user. While Match2 value defines the period of the waveform generated, (Match2 – Match1) value would determine the ON time. State machine uses these events from the counter to generate the waveform – set the output on Match1 and clear the output on Match2 event. Hence the state bit S0 reflects the output waveform generated. This output is in turn brought out on CLB1 output 4 in order to pass this output to CLB2 via CLB X-Bar. In0 is used as an enable from software for the waveform generation. This too is passed to CLB2 via CLB1 Output 5.

CLB2: This example uses the LUTs, counter, FSM, HLC sub-modules of the CLB to implement a checker on the output generated by CLB1. Following is the signal connectivity to CLB2.

CLB1 Output 4 → CLB X-Bar AUXSIG0 → CLB2 in1 (via Global Mux)

CLB1 Output 5 → CLB X-Bar AUXSIG1 → CLB2 in2 (via Global Mux)

The counter0 counts during the ON time of the received signal on In1. Counter0 Match1 value is set to the limit value on the duty cycle. If match1 event occurs it means that the ON time has exceeded the desired value.

The counter1 resets and starts counting on the rising edge of the received signal on In1. Counter1 Match1 value is set to the limit value on the period. If match1 event occurs it means that the Period has exceeded the desired value.

State machine (FSM1 S0) is used to detect the rising edge of the received signal on In1 and in turn used as reset to counter 1.

Whenever either of the counter match1 events described above occur there will be an interrupt generated to CPU using HLC – as an indicator of the error.

Figure 4-11 gives an outline of how the tiles operate. The match1 event generates a CPU interrupt and the objective is to trigger a CLB interrupt upon error condition detected inside CLB2.

GUID-A00C9161-57C3-4D78-A295-6ED69D140810-low.gifFigure 4-11 Example 6: Duty Exceeding Pre-Set Value
GUID-27C9208A-3F5A-4E6B-A64A-8A4684BE3164-low.gifFigure 4-12 Example 6: Period Exceeding Pre-Set Value

The lower half shows the CLB counter, which commences counting at the start ON time. In the first figure, the duty cycle check and depicted and period check is depicted in the second. If the Match 1 value is reached, an interrupt is generated in either case. The CLB ISR contains an “ESTOP” instruction which acts like a software break-point in the program.

To run the example, follow this procedure:

  1. In CCS v9.0 or higher, click “Project → Import CCS Projects…”
  2. Navigate to the CLB tool example directory. The path is:
    1. [C2000Ware]\driverlib\f2837xd\examples\cpu1\clb\ccs, or
    2. [C2000Ware]\driverlib\f28004x\examples\clb\ccs, or
    3. [C2000Ware]\driverlib\f2838x\examples\c28x\clb\ccs

    In the description that follows, it is assumed the C2000Ware directory above is in use.

  3. 13. Select the project “clb_ex6_siggen”, and click “Finish”.
  4. 14. In the CCS Project Explorer window, expand the project “clb_ex6_siggen” and open the file “clb_ex6_siggen.syscfg”.
  5. From the CCS menu, select “Project → Build Project”.

Open the SysCfg file (clb_ex6_siggen.syscfg) in the CCS window and inspect the match 1/2 settings in counter 0 of the CLB1 module. Change these values to update the duty and period of the generated output.

Inspect the match 1 settings of counter 0/1 in the CLB2 module. Change these values to update the duty and period values being checked on the generated output.

Run the program with the default values and verify that the CLB interrupts to not trigger. Then, change the values to result in an error (ex: change CLB2 Counter1 Match1 to 400). Rebuild and run the program to see the code stop inside the CLB2 interrupt service routine.