SPRUIR8B april   2020  – july 2023

 

  1.   1
  2.   CLB Tool
  3.   Trademarks
  4. 1Introduction
    1. 1.1 CLB Tool Outline
    2. 1.2 Overview of the CLB Configuration Process
  5. 2Getting Started
    1. 2.1 CLB Related Collateral
    2. 2.2 Introduction
    3. 2.3 Installation
      1. 2.3.1 Installation to Compile SystemC
      2. 2.3.2 Install the Simulation Viewer
  6. 3Using the CLB Tool
    1. 3.1 Import the Empty CLB Project
    2. 3.2 Updating Variable Paths
    3. 3.3 Configuring a CLB Tile
    4. 3.4 Creating the CLB Diagram
    5. 3.5 Using the Simulator
      1. 3.5.1 The Statics Panel
      2. 3.5.2 Creating the Input Stimulus
      3. 3.5.3 Running the Simulation
      4. 3.5.4 Trace Signal Descriptions
  7. 4Examples
    1. 4.1 Foundational Examples
      1. 4.1.1  CLB Empty Project
      2. 4.1.2  Example 3 – PWM Generation
      3. 4.1.3  Example 7 – State Machine
      4. 4.1.4  Example 13 – PUSH-PULL Interface
      5. 4.1.5  Example 14 – Multi-Tile
      6. 4.1.6  Example 15 – Tile to Tile Delay
      7. 4.1.7  Example 16 - Glue Logic
      8. 4.1.8  Exampe 18 - AOC
      9. 4.1.9  Example 19 - AOC Release Control
      10. 4.1.10 Example 20 - CLB XBARs
    2. 4.2 Getting Started Examples
      1. 4.2.1  Example 1 – Combinatorial Logic
      2. 4.2.2  Example 2 – GPIO Input Filter
      3. 4.2.3  Example 4 – PWM Protection
      4. 4.2.4  Example 5 – Event Window
      5. 4.2.5  Example 6 – Signal Generation and Check
      6. 4.2.6  Example 8 – External AND Gate
      7. 4.2.7  Example 9 – Timer
      8. 4.2.8  Example 10 – Timer With Two States
      9. 4.2.9  Example 11 – Interrupt Tag
      10. 4.2.10 Example 12 – Output Intersect
      11. 4.2.11 Example 17 – One-Shot PWM Generation
      12. 4.2.12 Example 21 - Clock Prescaler and NMI
      13. 4.2.13 Example 22 - Serializer
      14. 4.2.14 Example 23 - LFSR
      15. 4.2.15 Example 24 - Lock Output Mask
      16. 4.2.16 Example 25 - Input Pipeline Mode
      17. 4.2.17 Example 26 - Clocking Pipeline Mode
    3. 4.3 Expert Examples
      1. 4.3.1 Example 27 - SPI Data Export
      2. 4.3.2 Example 28 - SPI Data Export DMA
      3. 4.3.3 Example 29 - Timestamp
      4. 4.3.4 Example 30 - Cyclic Redundancy Check
      5. 4.3.5 CLB TDM Serial Port
      6. 4.3.6 CLB LED Driver
      7. 4.3.7 FPGA/CPLD to C2000 Examples
  8. 5Enabling CLB Tool in Existing DriverLib Projects
  9. 6Frequently Asked Questions (FAQs)
  10. 7Revision History

3.5.2 Creating the Input Stimulus

Open the .syscfg file by double-clicking on the file name in the CCS Project Explorer Window. Expand the “Boundary” category by selecting it.

GUID-E890744D-F036-460F-9835-6DD034B4FC6F-low.png Figure 3-16 Boundary Input 0 to 7

A separate input stimulus can be defined for each of the eight CLB inputs using the drop-down menus. Click on the down-arrow on the right to reveal the options:

  • No Input – Default option, no stimulus is generated.
  • Square Wave – Defines a periodic PWM input with configurable initial signal position, initial delay, period, duty, and period repeat amount.
    GUID-8CAABB6E-EA9F-495B-A968-75CAFB7E6EAC-low.png Figure 3-17 Boundary Input Square Wave

    The “Input Edge Detection Pulse” option offers the user the choice of generating a pulse from the rising and/or falling edges of the PWM wave whose period and duty are set as 10 and 5 CLB clock pulses, respectively, in Figure 3-17.

    The "Input Pipeline Enable" check-box adds a single cycle delay to the input signal, which is used for synchronized signals which are routed to the CLB as inputs. Note that the pipeline filter is only available on certain CLB types. Check the CLB input mux section in the device-specific TRM for more details.

    The “Input Clock Synchronization” check-box forces the input waveform to be synchronized to the CLB clock (the synchronizer creates a 2-3 cycle delay, so there appropriate check-boxes for both timings since the exact delay cannot be predicted). This option is necessary for signals which are coming from asynchronous sources relative to the CLB. For more information, see the CLB input mux section in the device-specific TRM.

  • Low (0) or High (1) - Sets the stimulus to a constant low or high, respectively
  • Custom Wave Input – Generates a custom stimulus using pseduo-code.
    GUID-CF667F86-CB7C-4B25-A895-E4DD04BED79E-low.png Figure 3-18 Boundary Input Custom

    The “Input Edge Detection Pulse”, "Input Pipeline Enable", and “Input Clock Synchronization” work the same as the Square Wave stimulus, with the addition of the custom waveform pseudo-code. The numeric parameter for the 'high', 'low', and 'rpt' instructions can be hexadecimal (0x1A) or decimal (26).

    Table 3-2 Custom Waveform Code Instructions
    Instruction Description
    #define Pattern replacer used to define macros
    high(N) Sets waveform high for 'N' CLB cylces
    low(N) Sets waveform low for 'N' CLB cycles
    rpt(N) Starts a repeat block; code encapsulated with rpt(N) and rpt_end will be repeated a total of 'N' times
    rpt_end Denotes the end of a repeat block
  • Tile Output - Uses a selected tile output as the input stimulus for the current tile.
    GUID-7C7082B6-F074-42F5-BA03-EB66386E65FF-low.png Figure 3-19 Boundary Input Tile Output
  • "Tile Name" must be the name of a valid tile within the CLB Tool project. The "Input Pipeline Enable" should be enabled since the output of a CLB tile is synchronous. See the CLB input mux section in the device-specific TRM for more information.