SPRUIS4E March   2022  – January 2024

 

  1.   1
  2.   Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 REACH Compliance
    4. 1.4 EMC, EMI, and ESD Compliance
  5. 2J721E EVM Overview
    1. 2.1 J721E EVM Board Identification
    2. 2.2 J721E SOM Component Identification
    3. 2.3 Jacinto7 Common Processor Components Identification
    4. 2.4 Quad Ethernet Components Identification
  6. 3EVM User Setup/Configuration
    1. 3.1 Power Requirements
    2. 3.2 Power ON Switch and Power LEDs
      1. 3.2.1 Over Voltage and Under Voltage Protection Circuit
      2. 3.2.2 Power Regulators and Power Status LEDs
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM DIP Switches
      1. 3.4.1 EVM Configuration DIP Switch
      2. 3.4.2 SOM Configuration DIP Switch
      3. 3.4.3 Boot Modes
      4. 3.4.4 Other Selection Switches
    5. 3.5 EVM UART/COM Port Mapping
    6. 3.6 JTAG Emulation
  7. 4J721E EVM Hardware Architecture
    1. 4.1  J721E EVM Hardware Top level Diagram
    2. 4.2  J721E EVM Interface Mapping
    3. 4.3  I2C Address Mapping
    4. 4.4  GPIO Mapping
    5. 4.5  Power Supply
      1. 4.5.1 Power Sequencing
      2. 4.5.2 Voltage Supervisor
      3. 4.5.3 DDR I/O Voltage Selection
        1. 4.5.3.1 J721E SoC S2R Logic Flow Diagram
        2. 4.5.3.2 J721E SoC MCU Only Operation
        3. 4.5.3.3 Power Monitoring
    6. 4.6  Reset
    7. 4.7  Clock
      1. 4.7.1 Processor’s Primary Clock
      2. 4.7.2 Processor’s Secondary/SERDES Ref Clock
      3. 4.7.3 EVM Peripheral Ref Clock
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 OSPI Interface
      3. 4.8.3 UFS Interface
      4. 4.8.4 MMC Interface
        1. 4.8.4.1 MMC0 - eMMC Interface
        2. 4.8.4.2 MMC1 – Micro SD Interface
      5. 4.8.5 Board ID EEPROM Interface
      6. 4.8.6 Boot EEPROM Interface
    9. 4.9  MCU Ethernet Interface
      1. 4.9.1 Gigabit Ethernet PHY Default Configuration
    10. 4.10 QSGMII Ethernet Interface
    11. 4.11 PCIe Interface
      1. 4.11.1 X1 Lane PCIe Interface
      2. 4.11.2 X2 Lane PCIe Interface
      3. 4.11.3 M.2 PCIe Interface
    12. 4.12 USB Interface
      1. 4.12.1 USB 3.1 Interface
      2. 4.12.2 USB 2.0 Interface
      3. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port)
    13. 4.13 CAN Interface
    14. 4.14 FPD Interface (Audio Deserializer)
    15. 4.15 FPD Panel Interface (DSI Video Serializer)
    16. 4.16 Display Serial Interface (DSI) FPC
    17. 4.17 Audio Interface
    18. 4.18 Display Port Interface
    19. 4.19 MLB Interface
    20. 4.20 I3C Interface
    21. 4.21 ADC Interface
    22. 4.22 RTC Interface
    23. 4.23 Apple Authentication Header
    24. 4.24 EVM Expansion Connectors
    25. 4.25 ENET Expansion Connector
      1. 4.25.1 Power Requirements
      2. 4.25.2 Clock
        1. 4.25.2.1 Main Clock
        2. 4.25.2.2 Optional Clock
      3. 4.25.3 Reset Signals
      4. 4.25.4 Ethernet Interface
        1. 4.25.4.1 Quad Port SGMII PHY Default Configuration
      5. 4.25.5 Board ID EEPROM Interface
    26. 4.26 CSI Expansion Connector
  8. 5Revision History

4.11.1 X1 Lane PCIe Interface

The x1 lane PCIe interface includes one x4 lane PCIe connector of part number Amphenol 10142333-10111MLF, which supports PCIe Gen4 operation. The pin-out of the connector follows PCIe standard.

The SERDES0 port of J7 SoC is connected to x1 lane PCIe socket for data transfer. PCIe0, USB0_SS and SGMII1, 2 interfaces are pinmuxed with this SERDES0 port.

I2C0 from SoC is used for control purpose and is connected to SMBUS on the connector. I2C0 port is connected to both x1 lane and x2 lane PCIe connectors using a Mux TCA9543APWR.

GUID-46CAC349-3AC8-4C61-AE05-572E248A5091-low.gif Figure 4-19 PCIe Interface for SERDES0
GUID-52E34C82-23BE-4931-AF25-FC1310D712AD-low.gif Figure 4-20 PCIe SMBUS Block Diagram

Reset: A dip Switch is provided to select the reset source for host and end-point PCIe operation. In case of host mode, signal from GPIO Expander and PORz signals from SoC are ANDed and the output is connected to PCIe connector. The GPIO signal is pulled low to ensure PCIe Reset (#PERST) remains asserted until SoC releases reset.

Whereas, in case of PCIe end point operation, the CP board receives reset signal from the PCIe card.

GUID-88219E8F-A8A7-4136-BD9D-A1CD2AE57600-low.gif Figure 4-21 1L-PCIe Root Complex/Endpoint Selection Circuit

Clock: A clock generator (CDCI #1) is provided to drive 100 MHz HCSL clock for PCIe add on cards and SoC. Resistor options are provided to select the clock source for host and end point operation.

For PCIe host operation:

  • The add on cards can have clocks driven by SOC or clock generator. Selection can be made through resistors as shown in Table 4-13.
Table 4-13 Reference Clock Selection for PCIe Host Operation
Clock Selected Mount Unmount
Reference Clock for SOC from clock generator R194 R195, C92
R198 R199, C93
Reference Clock for PCIe connector from SOC R195, C92 R194, R109
R199, C93 R198, R110
Reference Clock for PCIe connector from clock generator R109 R195, C92
R110 R199, C93

For PCIe Endpoint operation:

  • The SOC can have the clock driven by add on cards or clock generator. Selection can be made through resistors as shown in Table 4-14.
Table 4-14 Reference Clock Selection for PCIe Endpoint Operation
Clock Selected Mount Unmount
Reference clock for SOC from clock generator R194 R195, C92
R198 R199, C93
Reference clock for SOC from PCIe connector R195, C92 R194, R109
R199, C93 R198, R110

Hot plug: The PRSNT1# and PRSNT2# signals are the hot plug presence detect signals. The PRSNT1# is pulled up and PRSNT2# is connected to GPIO expander, so that PRSNT1# will be pulled low when a add on card is plugged in as both the PRSNT signals in add on cards will be shorted. Optional resistor is provided to short the PRSNT1# and PRSNT2# to support host and device mode.

For choosing Host or device operation of PCIe card, following resistors must be mounted/unmounted as mentioned in Table 4-15.

Table 4-15 Resistors for Selecting PCIe Card Host or Device Operation
Mode Mount Demount
Host mode R674 R675
R679
Device mode R675 R674
R679

Additional Options:

Optional MDIO bus and USB2.0 interface is supported for external PCIe add on cards.

SoC Main domain (CPSW9G0) MDIO signals are interfaced to the x1L PCIe Socket (J11) through 0-Ω inline resistors (R137 and R136) when network (Ethernet) based add on cards inserted into J11. The path is disconnected by default.

Also, USB2.0 data signals from USB HUB downstream port is interfaced to 4 pin header (J2) and the 5 V supply is provided through the load switch.

GUID-C02D237D-1136-47EF-B275-442E47FF8A4F-low.gif Figure 4-22 USB2.0 Header Connection