SPRUIS4E March   2022  – January 2024

 

  1.   1
  2.   Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 REACH Compliance
    4. 1.4 EMC, EMI, and ESD Compliance
  5. 2J721E EVM Overview
    1. 2.1 J721E EVM Board Identification
    2. 2.2 J721E SOM Component Identification
    3. 2.3 Jacinto7 Common Processor Components Identification
    4. 2.4 Quad Ethernet Components Identification
  6. 3EVM User Setup/Configuration
    1. 3.1 Power Requirements
    2. 3.2 Power ON Switch and Power LEDs
      1. 3.2.1 Over Voltage and Under Voltage Protection Circuit
      2. 3.2.2 Power Regulators and Power Status LEDs
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM DIP Switches
      1. 3.4.1 EVM Configuration DIP Switch
      2. 3.4.2 SOM Configuration DIP Switch
      3. 3.4.3 Boot Modes
      4. 3.4.4 Other Selection Switches
    5. 3.5 EVM UART/COM Port Mapping
    6. 3.6 JTAG Emulation
  7. 4J721E EVM Hardware Architecture
    1. 4.1  J721E EVM Hardware Top level Diagram
    2. 4.2  J721E EVM Interface Mapping
    3. 4.3  I2C Address Mapping
    4. 4.4  GPIO Mapping
    5. 4.5  Power Supply
      1. 4.5.1 Power Sequencing
      2. 4.5.2 Voltage Supervisor
      3. 4.5.3 DDR I/O Voltage Selection
        1. 4.5.3.1 J721E SoC S2R Logic Flow Diagram
        2. 4.5.3.2 J721E SoC MCU Only Operation
        3. 4.5.3.3 Power Monitoring
    6. 4.6  Reset
    7. 4.7  Clock
      1. 4.7.1 Processor’s Primary Clock
      2. 4.7.2 Processor’s Secondary/SERDES Ref Clock
      3. 4.7.3 EVM Peripheral Ref Clock
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 OSPI Interface
      3. 4.8.3 UFS Interface
      4. 4.8.4 MMC Interface
        1. 4.8.4.1 MMC0 - eMMC Interface
        2. 4.8.4.2 MMC1 – Micro SD Interface
      5. 4.8.5 Board ID EEPROM Interface
      6. 4.8.6 Boot EEPROM Interface
    9. 4.9  MCU Ethernet Interface
      1. 4.9.1 Gigabit Ethernet PHY Default Configuration
    10. 4.10 QSGMII Ethernet Interface
    11. 4.11 PCIe Interface
      1. 4.11.1 X1 Lane PCIe Interface
      2. 4.11.2 X2 Lane PCIe Interface
      3. 4.11.3 M.2 PCIe Interface
    12. 4.12 USB Interface
      1. 4.12.1 USB 3.1 Interface
      2. 4.12.2 USB 2.0 Interface
      3. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port)
    13. 4.13 CAN Interface
    14. 4.14 FPD Interface (Audio Deserializer)
    15. 4.15 FPD Panel Interface (DSI Video Serializer)
    16. 4.16 Display Serial Interface (DSI) FPC
    17. 4.17 Audio Interface
    18. 4.18 Display Port Interface
    19. 4.19 MLB Interface
    20. 4.20 I3C Interface
    21. 4.21 ADC Interface
    22. 4.22 RTC Interface
    23. 4.23 Apple Authentication Header
    24. 4.24 EVM Expansion Connectors
    25. 4.25 ENET Expansion Connector
      1. 4.25.1 Power Requirements
      2. 4.25.2 Clock
        1. 4.25.2.1 Main Clock
        2. 4.25.2.2 Optional Clock
      3. 4.25.3 Reset Signals
      4. 4.25.4 Ethernet Interface
        1. 4.25.4.1 Quad Port SGMII PHY Default Configuration
      5. 4.25.5 Board ID EEPROM Interface
    26. 4.26 CSI Expansion Connector
  8. 5Revision History

3.2.2 Power Regulators and Power Status LEDs

The processor Card utilizes an array of DC-DC converters to supply the various memories, clocks and other components on the Card with the necessary voltage and the power required.

Dual Buck controller LM5140-Q1 provides the primary stage power conversion (12 V to 5 V / 3.3 V). These 3.3 V and 5 V is the primary voltages for the SoM power management resources.

Buck-Boost controller LM5175 and another Buck controller LM5141 provides 12 V and 3.3 V supplies to the expansion connectors. The power good signals of these power regulators are used to generate the SoC PORz.

Multiple power-indication LEDs are provided on board to give users positive confirmation of the status of output of major supplies. The LEDs indicated power in the various domains.

Table 3-3 Power LEDs
Sl No LED Power Status Sch Net Name
1 LD2 Input Power On/Off VINPUT
2 LD7 Regulated Power On/Off VSYS_3V3
3 LD5 SoC Main Domain On/Off VSYS_IO_3V3
4 LD6 SoC MCU Domain On/Off VSYS_MCUIO_3V3
GUID-FD60F358-7EBE-471F-BC10-BACF92C45AE9-low.gif Figure 3-4 Power Status LEDs

Test points for each system power rails are provided on the Common Processor Board (CPB) and are mentioned in Table 3-4. Location for each can be identified by searching the assembly drawing for the test point reference number.

Table 3-4 Power Test Points
Power Supply Test Point Nominal Voltage
VINPUT TP20 12.0V
VSYS_3V3 TP130 3.3V
VCC_12V0 TP39 12.0V
VSYS_5V0 TP26 5.0V
EXP_3V3 TP43 3.3V
VDD_2V5 TP63 2.5V
VDD_1V0 TP59 1.0V
VCC_1V1 TP60 1.1V
VSYS_MCU_5V0 TP117 5.0V
VDD_SD_DV TP44 3.3V
VSYS_MCUIO_3V3 TP113 3.3V
VSYS_IO_3V3 TP131 3.3V
VSYS_MCUIO_1V8 TP134 1.8V
VSYS_IO_1V8 TP132 1.8V
VDA_MCU_1V8 TP105 1.8V