SPRUIS4E March   2022  – January 2024

 

  1.   1
  2.   Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 REACH Compliance
    4. 1.4 EMC, EMI, and ESD Compliance
  5. 2J721E EVM Overview
    1. 2.1 J721E EVM Board Identification
    2. 2.2 J721E SOM Component Identification
    3. 2.3 Jacinto7 Common Processor Components Identification
    4. 2.4 Quad Ethernet Components Identification
  6. 3EVM User Setup/Configuration
    1. 3.1 Power Requirements
    2. 3.2 Power ON Switch and Power LEDs
      1. 3.2.1 Over Voltage and Under Voltage Protection Circuit
      2. 3.2.2 Power Regulators and Power Status LEDs
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM DIP Switches
      1. 3.4.1 EVM Configuration DIP Switch
      2. 3.4.2 SOM Configuration DIP Switch
      3. 3.4.3 Boot Modes
      4. 3.4.4 Other Selection Switches
    5. 3.5 EVM UART/COM Port Mapping
    6. 3.6 JTAG Emulation
  7. 4J721E EVM Hardware Architecture
    1. 4.1  J721E EVM Hardware Top level Diagram
    2. 4.2  J721E EVM Interface Mapping
    3. 4.3  I2C Address Mapping
    4. 4.4  GPIO Mapping
    5. 4.5  Power Supply
      1. 4.5.1 Power Sequencing
      2. 4.5.2 Voltage Supervisor
      3. 4.5.3 DDR I/O Voltage Selection
        1. 4.5.3.1 J721E SoC S2R Logic Flow Diagram
        2. 4.5.3.2 J721E SoC MCU Only Operation
        3. 4.5.3.3 Power Monitoring
    6. 4.6  Reset
    7. 4.7  Clock
      1. 4.7.1 Processor’s Primary Clock
      2. 4.7.2 Processor’s Secondary/SERDES Ref Clock
      3. 4.7.3 EVM Peripheral Ref Clock
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 OSPI Interface
      3. 4.8.3 UFS Interface
      4. 4.8.4 MMC Interface
        1. 4.8.4.1 MMC0 - eMMC Interface
        2. 4.8.4.2 MMC1 – Micro SD Interface
      5. 4.8.5 Board ID EEPROM Interface
      6. 4.8.6 Boot EEPROM Interface
    9. 4.9  MCU Ethernet Interface
      1. 4.9.1 Gigabit Ethernet PHY Default Configuration
    10. 4.10 QSGMII Ethernet Interface
    11. 4.11 PCIe Interface
      1. 4.11.1 X1 Lane PCIe Interface
      2. 4.11.2 X2 Lane PCIe Interface
      3. 4.11.3 M.2 PCIe Interface
    12. 4.12 USB Interface
      1. 4.12.1 USB 3.1 Interface
      2. 4.12.2 USB 2.0 Interface
      3. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port)
    13. 4.13 CAN Interface
    14. 4.14 FPD Interface (Audio Deserializer)
    15. 4.15 FPD Panel Interface (DSI Video Serializer)
    16. 4.16 Display Serial Interface (DSI) FPC
    17. 4.17 Audio Interface
    18. 4.18 Display Port Interface
    19. 4.19 MLB Interface
    20. 4.20 I3C Interface
    21. 4.21 ADC Interface
    22. 4.22 RTC Interface
    23. 4.23 Apple Authentication Header
    24. 4.24 EVM Expansion Connectors
    25. 4.25 ENET Expansion Connector
      1. 4.25.1 Power Requirements
      2. 4.25.2 Clock
        1. 4.25.2.1 Main Clock
        2. 4.25.2.2 Optional Clock
      3. 4.25.3 Reset Signals
      4. 4.25.4 Ethernet Interface
        1. 4.25.4.1 Quad Port SGMII PHY Default Configuration
      5. 4.25.5 Board ID EEPROM Interface
    26. 4.26 CSI Expansion Connector
  8. 5Revision History

4.4 GPIO Mapping

The general purpose I/Os (GPIOs) of the SoC have two major groups: WKUP/MCU and MAIN. Table 4-3 describes the detailed GPIO mapping of SoC with EVM peripherals.

Table 4-3 J721E SoC - GPIO Mapping Table
J721E SoC - GPIO Mapping Table
Package Signal Name GPIO Net name In/Out Default State Remarks
WKUP/MCU Domain
WKUP_
GPIO0_0		 WKUP_
GPIO0_0		 MCU_MCAN0_EN Output BOOTMODE Active High MCU CAN0 Enable
WKUP_
GPIO0_1		 WKUP_
GPIO0_1		 BOOT_EEPROM_
WP		 Output BOOTMODE Active High Boot EEPROM Write protect
WKUP_
GPIO0_2		 WKUP_
GPIO0_2		 MCU_CAN1_STB Output BOOTMODE Active High MCU CAN1 Standby
WKUP_
GPIO0_3		 WKUP_
GPIO0_3		 GPIO_MCU_
RGMII1_RST#		 Output PU Active low MCU_RGMII1_Reset
WKUP_
GPIO0_6		 WKUP_
GPIO0_6		 WKUP_GPIO0_6 I/O Test Point NA Terminated with Test point
WKUP_
GPIO0_7		 WKUP_
GPIO0_7		 SYS_IRQz Input PU Active low Push-button Interrupt, User Defined/Wake S2R ('0>1' - interrupt pending, '1' - normal operation)
WKUP_
GPIO0_8		 WKUP_
GPIO0_8		 OSPI/HYPER_
MUX_SEL		 Output DIP_SEL NA Flash Memory Selection ('0' - OSPI0, '1' - Hyperflash + HyperRam)
WKUP_
GPIO0_9		 WKUP_
GPIO0_9		 PMIC_MCU_INT# Input PU Active low Interrupt from PMIC
WKUP_
GPIO0_17		 WKUP_
GPIO0_17		 MCU_OSPI0_
ECC_FAIL		 Output NA Active High OSPI_ECC_FAIL (Mux option w/ HYPERBUS_CKn), MCU_OSPI0_ECC_FAIL is DNI resistor option.
MCU_SPI0_
CLK		 WKUP_
GPIO0_52		 WKUP_GPIO0_52 I/O BOOTMODE NA Terminated with Test point
MCU_SPI0_
CS0		 WKUP_
GPIO0_55		 MCU_RGMII1_
INT#		 Input PU Active Low MCU Ethernet Interrupt ('0' - interrupt pending, '1' - no interrupt)
MCU_SPI0_
D0		 WKUP_
GPIO0_53		 SYS_MCU_
PWRDN		 Output PD Active low System Power Down ('0' - normal operation, '1' -system power down)
MCU_SPI0_
D1		 WKUP_
GPIO0_54		 MCU_CAN0_STBz Output PD Active low MCU CAN0 Standby
Main Domain
EXTINTN GPIO0_0 SOC_EXTINTN Input PU Active low Push-button Interrupt, User Defined
RGMII6_RX_
CTL		 GPIO0_98 C_MCASP10_
AFSR		 NA PU Active low I2C0 I/O expander interrupt. ('0' - interrupt pending, '1' - no interrupt)(I2C0_IOEXP_INT#)
Note: GPIO only available from Trace/GPMC Mux
RGMII6_
RD3		 GPIO0_105 IMU_GPIO0 I/O NA NA Used as GPIO0 for IMU Sensor
SPI1_CS1 GPIO0_117 DSI_UB981_INTB Input PU Active low DSI FPD Link Serializer/Panel Interrupt.
Note: resistor option with CON_DSI0_INT#
UART1_
CTSN		 GPIO0_127 GPIO0_127/
EQEP0_S/MLB0_
MLBCLK		 Output PU Active High CP Board - MCAN2_STB; GESI - Boosterpack_GPIO2
UART1_
RTSN		 GPIO1_0 GPIO1_0/EQEP0_I
/MLB0_MLBDAT		 Output PD NA CP Board - PM I2C Mux seletion. ('0' - SOC_I2C2_SCL/SDA → PM1_SCL/SDA, '1' - SOC_I2C2_SCL/SDA → PM2_SCL/SDA)
GESI - Boosterpack_GPIO1
MCAN1_RX GPIO1_3 USBC_DIR Input PU NA USB Type C Cable Orientation. Type-C plug position 2 (H); Type-C plug position 1 (L)
ECAP0_IN_
APWM_
OUT		 GPIO1_11 GPIO1_11/MAIN_
I3C0_
SDAPULLEN		 Input PU Active High Display I/O expander Interrupt. ('0' - interrupt pending, '1' - no interrupt) (IOEXP4_INT#)
EXT_
REFCLK1		 GPIO1_12 GPIO1_12/MLB0_REFCLK Input PD NA CP Board Audio De-serializer UB926_GPIO1 (Tuner Unused GPIO)
MMC1_
SDWP		 GPIO1_22 ENET_EXP_INTB Input PU Active low Ethernet Expansion Interrupt. ('0' - interrupt pending, '1' - no interrupt)
I3C0_SCL GPIO1_5 H_I3C0_SCL I/O NA NA CP Board Audio De-serializer UB926_GPIO2
I3C0_SDA GPIO1_6 H_I3C0_SDA I/O NA NA CP Board Audio De-serializer UB926_GPIO3