SPRUIS4E March   2022  – January 2024

 

  1.   1
  2.   Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 REACH Compliance
    4. 1.4 EMC, EMI, and ESD Compliance
  5. 2J721E EVM Overview
    1. 2.1 J721E EVM Board Identification
    2. 2.2 J721E SOM Component Identification
    3. 2.3 Jacinto7 Common Processor Components Identification
    4. 2.4 Quad Ethernet Components Identification
  6. 3EVM User Setup/Configuration
    1. 3.1 Power Requirements
    2. 3.2 Power ON Switch and Power LEDs
      1. 3.2.1 Over Voltage and Under Voltage Protection Circuit
      2. 3.2.2 Power Regulators and Power Status LEDs
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM DIP Switches
      1. 3.4.1 EVM Configuration DIP Switch
      2. 3.4.2 SOM Configuration DIP Switch
      3. 3.4.3 Boot Modes
      4. 3.4.4 Other Selection Switches
    5. 3.5 EVM UART/COM Port Mapping
    6. 3.6 JTAG Emulation
  7. 4J721E EVM Hardware Architecture
    1. 4.1  J721E EVM Hardware Top level Diagram
    2. 4.2  J721E EVM Interface Mapping
    3. 4.3  I2C Address Mapping
    4. 4.4  GPIO Mapping
    5. 4.5  Power Supply
      1. 4.5.1 Power Sequencing
      2. 4.5.2 Voltage Supervisor
      3. 4.5.3 DDR I/O Voltage Selection
        1. 4.5.3.1 J721E SoC S2R Logic Flow Diagram
        2. 4.5.3.2 J721E SoC MCU Only Operation
        3. 4.5.3.3 Power Monitoring
    6. 4.6  Reset
    7. 4.7  Clock
      1. 4.7.1 Processor’s Primary Clock
      2. 4.7.2 Processor’s Secondary/SERDES Ref Clock
      3. 4.7.3 EVM Peripheral Ref Clock
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 OSPI Interface
      3. 4.8.3 UFS Interface
      4. 4.8.4 MMC Interface
        1. 4.8.4.1 MMC0 - eMMC Interface
        2. 4.8.4.2 MMC1 – Micro SD Interface
      5. 4.8.5 Board ID EEPROM Interface
      6. 4.8.6 Boot EEPROM Interface
    9. 4.9  MCU Ethernet Interface
      1. 4.9.1 Gigabit Ethernet PHY Default Configuration
    10. 4.10 QSGMII Ethernet Interface
    11. 4.11 PCIe Interface
      1. 4.11.1 X1 Lane PCIe Interface
      2. 4.11.2 X2 Lane PCIe Interface
      3. 4.11.3 M.2 PCIe Interface
    12. 4.12 USB Interface
      1. 4.12.1 USB 3.1 Interface
      2. 4.12.2 USB 2.0 Interface
      3. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port)
    13. 4.13 CAN Interface
    14. 4.14 FPD Interface (Audio Deserializer)
    15. 4.15 FPD Panel Interface (DSI Video Serializer)
    16. 4.16 Display Serial Interface (DSI) FPC
    17. 4.17 Audio Interface
    18. 4.18 Display Port Interface
    19. 4.19 MLB Interface
    20. 4.20 I3C Interface
    21. 4.21 ADC Interface
    22. 4.22 RTC Interface
    23. 4.23 Apple Authentication Header
    24. 4.24 EVM Expansion Connectors
    25. 4.25 ENET Expansion Connector
      1. 4.25.1 Power Requirements
      2. 4.25.2 Clock
        1. 4.25.2.1 Main Clock
        2. 4.25.2.2 Optional Clock
      3. 4.25.3 Reset Signals
      4. 4.25.4 Ethernet Interface
        1. 4.25.4.1 Quad Port SGMII PHY Default Configuration
      5. 4.25.5 Board ID EEPROM Interface
    26. 4.26 CSI Expansion Connector
  8. 5Revision History

4.5.3.3 Power Monitoring

INA226 power monitor devices are used to monitor current and voltage of various power rails of J721E processor. The device reports current, voltage and power to J721E processor through I2C interface. Four Terminal High Precision shunt resistors are provided, and the values are calculated based on load current.

Table 4-7 INA Devices I2C Slave Address
Power Source Supply Net I2C Bus Slave Address
(IN HEX)		 Value of the Shunt Connected to the Supply Rail
VDD_MCU_0V85_REG VDD_MCU_0V85 SOC_I2C2/PM1 0x40 0.01E
VDD_MCU_RAM_0V85_REG VDD_MCU_RAM_0V85 SOC_I2C2/PM1 0x41 0.01E
VDA_MCU_1V8_REG VDA_MCU_1V8 SOC_I2C2/PM1 0x42 0.01E
VDD_MCUIO_3V3_LS VDD_MCUIO_3V3 SOC_I2C2/PM1 0x43 0.01E
VDD_MCUIO_1V8_REG VDD_MCUIO_1V8 SOC_I2C2/PM1 0x44 0.01E
VDD_CORE_0V8_REG VDD_CORE_0V8 SOC_I2C2/PM1 0x45 0.01E
VDD_CORE_RAM_0V85_REG VDD_CORE_RAM_0V85 SOC_I2C2/PM1 0x46 0.01E
VDD_CPU_RAM_0V85_REG VDD_CPU_RAM_0V85 SOC_I2C2/PM1 0x47 0.01E
VDD_CPU_AVS_REG VDD_CPU_AVS SOC_I2C2/PM1 0x48 0.01E
V917_SMPS3_1V1 VDDR_BIAS_1V1 SOC_I2C2/PM1 0x49 0.01E
VDDR_IO_DV_SRC VDDR_IO_DV SOC_I2C2/PM1 0x4A 0.01E
VDD_CORE_0V8_REG VDD_PHYCORE_0V8 SOC_I2C2/PM1 0x4B 0.01E
VDA_PLL_1V8_REG VDA_PLL_1V8 SOC_I2C2/PM1 0x4C 0.01E
VDD_PHYIO_1V8_REG VDD_PHYIO_1V8 SOC_I2C2/PM1 0x4D 0.01E
VDA_USB_3V3_REG VDA_USB_3V3 SOC_I2C2/PM1 0x4E 0.01E
SPARE NA SOC_I2C2/PM1 0x4F NA
VDD_MCUIO_1V8_REG VDD_IO_1V8 SOC_I2C2/PM2 0x40 0.01E
VSYS_3V3 VDD_IO_3V3 SOC_I2C2/PM2 0x41 0.01E
VDD_SD_DV_REG VDD_SD_DV SOC_I2C2/PM2 0x42 0.01E
V917_LDO4_1V8 VDD1 SOC_I2C2/PM2 0x43 0.01E
V917_SMPS3_1V1 VDD2 SOC_I2C2/PM2 0x44 0.01E
VDDR_IO_DV_SRC VDDQ_LPDDR4_DV SOC_I2C2/PM2 0x45 0.01E
VDD_MCUIO_1V8_REG VSYS_MCUIO_1V8 SOC_I2C2/PM2 0x46 0.01E
VSYS_3V3 VSYS_MCUIO_3V3 SOC_I2C2/PM2 0x47 0.01E
VDD_MCUIO_1V8_REG VSYS_IO_1V8 SOC_I2C2/PM2 0x48 0.01E
VSYS_3V3 VSYS_IO_3V3 SOC_I2C2/PM2 0x49 0.01E
VCC_12V0 VCC_12V0 SOC_I2C2/PM2 0x4A 0.01E
VSYS_5V0 VSYS_5V0 SOC_I2C2/PM2 0x4B 0.01E
VSYS_3V3 VSYS_3V3 SOC_I2C2/PM2 0x4C 0.01E
VSYS_3V3 VSYS_3V3_SOM SOC_I2C2/PM2 0x4D 0.01E
VDD_EXTLDO1_0V8 VDDA_DLL_0V8 SOC_I2C2/PM2 0x4E 0.01E
EXP_3V3 EXP_3V3 SOC_I2C2/PM2 0x4F 0.01E

INA devices can be accessed from processor through Main I2C2 instance. Also, there is an option to Monitor the SoC and peripheral powers using external I2C Master.

Common processor has five-pin header (J12) with isolation circuit to interface the INA devices with external I2C Master. Buffer IC SN74CB3Q3125PWR (U69) is used to isolate the External I2C connections from the INA devices. The control of this buffer is provided from SYS_PWR_PG, which is enabled by default on power up.

External Power Monitor header details:

Mfr. Part# 68002-205HL (CON HDR 1X5 2.54MM PITCH ST TH)

Table 4-8 External Power Monitor Header Pinouts
Header (J12) Pin Number Signal Name
1 CON_PM1_SCL
2 CON_PM1_SDA
3 DGND
4 CON_PM2_SDA
5 CON_PM2_SCL

Test automation header on the Common processor board also can access these INA devices externally.