SPRUIS4E March   2022  – January 2024

 

  1.   1
  2.   Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 REACH Compliance
    4. 1.4 EMC, EMI, and ESD Compliance
  5. 2J721E EVM Overview
    1. 2.1 J721E EVM Board Identification
    2. 2.2 J721E SOM Component Identification
    3. 2.3 Jacinto7 Common Processor Components Identification
    4. 2.4 Quad Ethernet Components Identification
  6. 3EVM User Setup/Configuration
    1. 3.1 Power Requirements
    2. 3.2 Power ON Switch and Power LEDs
      1. 3.2.1 Over Voltage and Under Voltage Protection Circuit
      2. 3.2.2 Power Regulators and Power Status LEDs
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM DIP Switches
      1. 3.4.1 EVM Configuration DIP Switch
      2. 3.4.2 SOM Configuration DIP Switch
      3. 3.4.3 Boot Modes
      4. 3.4.4 Other Selection Switches
    5. 3.5 EVM UART/COM Port Mapping
    6. 3.6 JTAG Emulation
  7. 4J721E EVM Hardware Architecture
    1. 4.1  J721E EVM Hardware Top level Diagram
    2. 4.2  J721E EVM Interface Mapping
    3. 4.3  I2C Address Mapping
    4. 4.4  GPIO Mapping
    5. 4.5  Power Supply
      1. 4.5.1 Power Sequencing
      2. 4.5.2 Voltage Supervisor
      3. 4.5.3 DDR I/O Voltage Selection
        1. 4.5.3.1 J721E SoC S2R Logic Flow Diagram
        2. 4.5.3.2 J721E SoC MCU Only Operation
        3. 4.5.3.3 Power Monitoring
    6. 4.6  Reset
    7. 4.7  Clock
      1. 4.7.1 Processor’s Primary Clock
      2. 4.7.2 Processor’s Secondary/SERDES Ref Clock
      3. 4.7.3 EVM Peripheral Ref Clock
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 OSPI Interface
      3. 4.8.3 UFS Interface
      4. 4.8.4 MMC Interface
        1. 4.8.4.1 MMC0 - eMMC Interface
        2. 4.8.4.2 MMC1 – Micro SD Interface
      5. 4.8.5 Board ID EEPROM Interface
      6. 4.8.6 Boot EEPROM Interface
    9. 4.9  MCU Ethernet Interface
      1. 4.9.1 Gigabit Ethernet PHY Default Configuration
    10. 4.10 QSGMII Ethernet Interface
    11. 4.11 PCIe Interface
      1. 4.11.1 X1 Lane PCIe Interface
      2. 4.11.2 X2 Lane PCIe Interface
      3. 4.11.3 M.2 PCIe Interface
    12. 4.12 USB Interface
      1. 4.12.1 USB 3.1 Interface
      2. 4.12.2 USB 2.0 Interface
      3. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port)
    13. 4.13 CAN Interface
    14. 4.14 FPD Interface (Audio Deserializer)
    15. 4.15 FPD Panel Interface (DSI Video Serializer)
    16. 4.16 Display Serial Interface (DSI) FPC
    17. 4.17 Audio Interface
    18. 4.18 Display Port Interface
    19. 4.19 MLB Interface
    20. 4.20 I3C Interface
    21. 4.21 ADC Interface
    22. 4.22 RTC Interface
    23. 4.23 Apple Authentication Header
    24. 4.24 EVM Expansion Connectors
    25. 4.25 ENET Expansion Connector
      1. 4.25.1 Power Requirements
      2. 4.25.2 Clock
        1. 4.25.2.1 Main Clock
        2. 4.25.2.2 Optional Clock
      3. 4.25.3 Reset Signals
      4. 4.25.4 Ethernet Interface
        1. 4.25.4.1 Quad Port SGMII PHY Default Configuration
      5. 4.25.5 Board ID EEPROM Interface
    26. 4.26 CSI Expansion Connector
  8. 5Revision History

4.17 Audio Interface

Common Processor Board supports TI ‘s Audio Codec IC Mfr. Part# PCM3168APAP, to interface with J721E SoC McASP Port 10. A 1:3 De-Mux (Mfr. Part# SN74CBT16214CDGGR) Port B1 is used to interface McASP port 10 with codec. Port Selection is controlled by a I2C GPIO Expander and EVM Configuration switch. Table 4-21 shows the MUX table.

Table 4-21 MCASP/TRACE - 1:3 MUX: Truth Table
MUX_SEL2MUX_SEL1MUX_SEL0Function
HighHighLowA port = B1 port(default)
HighHighHighA port = B2 port
HighLowHighA port = B3 port
  • Port B1: McASP10
  • Port B2: TRACE
  • Port B3: GPMC

The Reference clock (SCKI) to the codec device is sourced from processor’s AUDIO_EXT_REFCLK2 using 1 to 2 Fan out clock buffer SN74LVC2G125DCUR, the secondary output clock from the fan out buffer is routed to EVM expansion connector to interface to Infotainment Audio Codec devices.

The MODE pin is held LOW to select I2C as control interface. Codec is configured over I2C3 interface. Default I2C address is set to 0x44. The device reset is controlled by the I2C GPIO expander using a I2C3 master port.

Line IN Port:

Single ended Stereo 1x Line Input signal from the Audio Jack J38 is converted to differential using “single ended to differential converter with Anti-aliasing low pass fiter” and interfaced with CODEC.

MIC Input Port:

Single ended Stereo 2x MIC Input signals from the stacked Audio Jack J39 is converted to differential using “single ended to differential converter with Anti-aliasing low pass fiter” and interfaced with CODEC. Pre-Amplifier circuit is provider inline to LPF circuit to amplify the external microphone inputs.

Microphone Input ports can be configured for Active and Passive microphones and also can be configured for Line Input. The configuration is set by the resistor option, as shown in Table 4-22.

Table 4-22 Config Table (1)
InstallRemove
PASSIVE-MIC
(default)		BIAS + PREAMPR2, R3, R5, R6R1, R4
ACTIVE-MICBIAS ONLYR1, R2, R4, R5R3, R6
LINE-INPUTNO BIAS/PREAMPR1, R4R2, R3, R5, R6
(1) The Reference Rx provided in this table denotes the text provided in the schematics.

Line Out Port:

2x digital Outputs from the CODEC is converted to single ended and terminated to stereo Audio jack J40 bottom port using “differential to single ended” converter Line out circuit.

Head Phone Port:

6x differential digital Outputs from the CODEC is converted to single ended and terminated to stereo Audio Jack J40 top port and stacked audio jack J41 with head phone circuit.

Port Mapping:

Common Processor board audio ports are mapped as below.

  • 3x Standard 3.5mm stacked Stereo Audio Jack Mfr. Part# STX-4235-3/3-N is provided for:
    • 2x – MIC IN, 1x – Line OUT and 3x – Head Phone OUT
  • 1x Standard 3.5mm Stereo Audio Jack Mfr. Part# SJ-3524-SMT-TR provided for:
    • 1x – Line IN interface
GUID-89450328-2DCB-4AED-B33D-2BE2038EAA52-low.gifFigure 4-37 Audio Port Interface Assignment