SPRUIS4E March   2022  – January 2024

 

  1.   1
  2.   Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 REACH Compliance
    4. 1.4 EMC, EMI, and ESD Compliance
  5. 2J721E EVM Overview
    1. 2.1 J721E EVM Board Identification
    2. 2.2 J721E SOM Component Identification
    3. 2.3 Jacinto7 Common Processor Components Identification
    4. 2.4 Quad Ethernet Components Identification
  6. 3EVM User Setup/Configuration
    1. 3.1 Power Requirements
    2. 3.2 Power ON Switch and Power LEDs
      1. 3.2.1 Over Voltage and Under Voltage Protection Circuit
      2. 3.2.2 Power Regulators and Power Status LEDs
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM DIP Switches
      1. 3.4.1 EVM Configuration DIP Switch
      2. 3.4.2 SOM Configuration DIP Switch
      3. 3.4.3 Boot Modes
      4. 3.4.4 Other Selection Switches
    5. 3.5 EVM UART/COM Port Mapping
    6. 3.6 JTAG Emulation
  7. 4J721E EVM Hardware Architecture
    1. 4.1  J721E EVM Hardware Top level Diagram
    2. 4.2  J721E EVM Interface Mapping
    3. 4.3  I2C Address Mapping
    4. 4.4  GPIO Mapping
    5. 4.5  Power Supply
      1. 4.5.1 Power Sequencing
      2. 4.5.2 Voltage Supervisor
      3. 4.5.3 DDR I/O Voltage Selection
        1. 4.5.3.1 J721E SoC S2R Logic Flow Diagram
        2. 4.5.3.2 J721E SoC MCU Only Operation
        3. 4.5.3.3 Power Monitoring
    6. 4.6  Reset
    7. 4.7  Clock
      1. 4.7.1 Processor’s Primary Clock
      2. 4.7.2 Processor’s Secondary/SERDES Ref Clock
      3. 4.7.3 EVM Peripheral Ref Clock
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 OSPI Interface
      3. 4.8.3 UFS Interface
      4. 4.8.4 MMC Interface
        1. 4.8.4.1 MMC0 - eMMC Interface
        2. 4.8.4.2 MMC1 – Micro SD Interface
      5. 4.8.5 Board ID EEPROM Interface
      6. 4.8.6 Boot EEPROM Interface
    9. 4.9  MCU Ethernet Interface
      1. 4.9.1 Gigabit Ethernet PHY Default Configuration
    10. 4.10 QSGMII Ethernet Interface
    11. 4.11 PCIe Interface
      1. 4.11.1 X1 Lane PCIe Interface
      2. 4.11.2 X2 Lane PCIe Interface
      3. 4.11.3 M.2 PCIe Interface
    12. 4.12 USB Interface
      1. 4.12.1 USB 3.1 Interface
      2. 4.12.2 USB 2.0 Interface
      3. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port)
    13. 4.13 CAN Interface
    14. 4.14 FPD Interface (Audio Deserializer)
    15. 4.15 FPD Panel Interface (DSI Video Serializer)
    16. 4.16 Display Serial Interface (DSI) FPC
    17. 4.17 Audio Interface
    18. 4.18 Display Port Interface
    19. 4.19 MLB Interface
    20. 4.20 I3C Interface
    21. 4.21 ADC Interface
    22. 4.22 RTC Interface
    23. 4.23 Apple Authentication Header
    24. 4.24 EVM Expansion Connectors
    25. 4.25 ENET Expansion Connector
      1. 4.25.1 Power Requirements
      2. 4.25.2 Clock
        1. 4.25.2.1 Main Clock
        2. 4.25.2.2 Optional Clock
      3. 4.25.3 Reset Signals
      4. 4.25.4 Ethernet Interface
        1. 4.25.4.1 Quad Port SGMII PHY Default Configuration
      5. 4.25.5 Board ID EEPROM Interface
    26. 4.26 CSI Expansion Connector
  8. 5Revision History

4.13 CAN Interface

The four CAN ports of J721E SoC (MCU_MCAN0, MCU_MCAN1, MCAN0, and MCAN2) is supported on the Common Processor board as explained below.

MCU CAN0

The MCU CAN0 port of J721E SoC is connected to the CAN transceiver with Wake function supported device TCAN1043-Q1. A 2-pin header J29 (68002-202HLF) is provided inline for user probe option.

The output of the CAN transceiver is terminated to a 4-pin header J30 (61300411121).

The signals MCU_MCAN0_H and MCU_MCAN0_L are routed as differential signals with 120E impedance with split termination. This Split termination improves the electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common-mode voltages at the start and end of message transmissions.

GUID-C8D5F088-74EB-4909-949E-CAFF59F8AE60-low.gifFigure 4-31 MCU CAN0 Interface

VSYS_MCU_5V0 to the CAN transceiver is generated using a Step-Up converter TPS61240DRV by giving VSYS_3V3 as input supply to the converter.

The STB signal is an active low signal held low with integrated pull down by default.

Hardware WAKEn input for the CAN interface is provided using a push-button SW12 available on the Common processor board bottom left corner. However, the MCU_CAN0 wake feature is disabled by default (resistor population). Only CAN wake-up supported is from MAIN domain.

MCU CAN1

The MCU CAN1 port of J721E SoC is connected to the CAN transceiver Mfr. Part# TCAN1042HGVD. A 2-pin header J34 (68002-202HLF) is provided inline for user probe option. This port does not support WAKE function. The signals MCU_MCAN1_H and MCU_MCAN1_L are terminated to a 3-pin header J31 (FCI: 68001-403HLF) with 120E split termination.

The STB signal is an active High signal held high with external pull up by default. The GPIO control from MCU domain provided to pull the line low.

MAIN CAN0 (Supports WAKE function)

The MAIN CAN0 port of J721E SoC is connected to the CAN transceiver with Wake function supported device TCAN1043-Q1. A 2-pin header J24 (68002-202HLF) is provided inline for user probe option.

The output of the CAN transceiver is terminated to a 4-pin header J27 (61300411121).

The signals MCAN0_H and MCAN0_L are routed as differential signals with 120E impedance with split termination. The STB signal is an active low signal held low with integrated pull down by default.

The VCC supply (5V) to the transceiver is derived from a Step-Up converter.

Hardware WAKEn input for the CAN interface is provided using a push-button SW12.

GUID-BE6CB50B-7EEB-4C49-8876-EE84D68E6534-low.gifFigure 4-32 CAN Wake Push Button

The CAN Wake signals of both MCU CAN0 and MAIN CAN0 transceivers are tied together and limited the voltage level to 1.8V using a Zener diode and terminated to SOM -CP B2B connector.

MAIN CAN2

The MAIN CAN2 port of J721E SoC is connected to the CAN transceiver Mfr. Part# TCAN1042HGVD. A 2-pin header J25 (68002-202HLF) is provided inline for user probe option. This port does not support WAKE function. The signals MCAN2_H and MCAN2_L are terminated to a 3-pin header J28 (68001-403HLF) with 120E split termination.

The STB signal is an active High signal held high with external pull up by default. The GPIO control from MAIN domain provided to pull the line low.

To interface these CAN signals to Test system, the below given custom converter to be prepared.

GUID-F9730FAD-036E-4145-B539-3F1CCDF33DC3-low.gifFigure 4-33 CAN Header Connections to DB9/Test Instrument