SPRUIT1B May   2020  – November 2020

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Key Features
  3. 2GESI Expansion Board Overview
    1. 2.1 GESI Expansion Board Identification
    2. 2.2 GESI Expansion Board Component Identification
  4. 3GESI Expansion Board - User Setup/Configuration
    1. 3.1 GESI Infotainment Expansion Board With CP Board
      1. 3.1.1 Board Assembly Procedures
    2. 3.2 Power Requirements
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM Configuration DIP Switch
  5. 4GESI Expansion Board Hardware Architecture
    1. 4.1  GESI Expansion Board Hardware Top Level Diagram
    2. 4.2  Expansion Connectors
    3. 4.3  Board ID EEPROM
    4. 4.4  Ethernet Interface
      1. 4.4.1 RGMII Clocking Scheme
      2. 4.4.2 Ethernet Port LED Indication
    5. 4.5  PROFI BUS / RS485
    6. 4.6  LIN Interface
    7. 4.7  MCAN
    8. 4.8  MUX Selection
      1. 4.8.1 MUX – PRGx_MDIO/MDC, CPSW9G_MDIO/MDC
      2. 4.8.2 MUX – PRG1_RGMII1/PRG1_PWM
      3. 4.8.3 MUX – PRG1_PWM/MCAN
      4. 4.8.4 MUX_MC/BP_SEL
    9. 4.9  GESI LaunchPad-Booster Pack Interface
    10. 4.10 Motor Control Interface
    11. 4.11 USS/IMU Header
    12. 4.12 Test Header
  6.   A Interface Mapping
  7.   B GESI Board GPIO Mapping
  8.   C I2C Address Mapping
  9.   D Revision History

4.4 Ethernet Interface

The Jacinto7 EVM – GESI Expansion board provides an option to the users to validate the Jacinto7 SoC’s RGMII and RMII controllers.

GESI supports 4 RGMII interfaces using Four DP83867 Gigabit Ethernet. It is connected to 2x stacked RJ45 connector J20A & J20B and J21A & J21B. Default Configurations of these PHYs can be determined by Resistor Straps on configuration pins of PHY.

Table 4-4 RGMII PHY Strap Configuration
Ports RGMII Port1 RGMII Port2 RGMII Port3 RGMII Port4
Connectors J21A J21B J20A J20B
PHY Address 00000 00011 01100 01111
Auto Negotiation Enabled Enabled Enabled Enabled
ANEGSel 10/100/1000 10/100/1000 10/100/1000 10/100/1000
RGMII Clock Skew TX 0 ns 0 ns 0 ns 0 ns
RGMII Clock Skew RX 2 ns 2 ns 2 ns 2 ns

On these RGMII PHYs either CPSWxG or Main domain RGMII interface of Jacinto7 processor can be validated by software configuration. It is specific to the processor.

GUID-6ABAD604-6143-40EB-93FA-E84FEA68223B-low.gif Figure 4-3 Ethernet Interface

Ethernet PHY management bus, MDIO-MDC is wired through 2:1 mux SN74CB3Q3257PWR. For Mux selection GPIO details, see Section B.

RMII connection of DP83822IRHBT provides a 10/100 Mbps port (J23).