The EST fetch RAM is read/writable in the CPSW configuration address space.
Each Ethernet transmit port has 128 locations in the global EST fetch RAM.
Ethernet port 1 has EST fetch RAM addresses 0x080-0x0FF, and so on.
One buffer operation: When CPSW_PN_EST_CONTROL_REG_k[0] EST_ONEBUF is set to 1h, the 128 port locations operate as one buffer. The EST_BUFACT bit in CPSW_PN_FIFO_STATUS_REG_k register is the upper address bit of the port’s fetch RAM address indicating whether operation is currently in the upper or lower 64 locations of the port’s fetch RAM.
Two buffer operation: When CPSW_PN_EST_CONTROL_REG_k[0] EST_ONEBUF is cleared there are two 64-location buffers with CPSW_PN_EST_CONTROL_REG_k[1] EST_BUFSEL selecting the buffer to be used. When the buffer is switched by changing the CPSW_PN_EST_CONTROL_REG_k[1] EST_BUFSEL value, the actual switch occurs on cycle start. The actual buffer being used is indicated by the EST_BUFACT bit in CPSW_PN_FIFO_STATUS_REG_k. Software should avoid writing the switched out buffer fetch RAM locations until it detects that the actual switch has occurred.
The first address location in the port’s fetch RAM space (location zero) is read at the beginning of each EST time interval (cycle start). Addresses are then read in ascending order for the duration of the interval. The port address zero is then read again at the beginning of the next cycle repeating the time interval packet operations.