SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The HyperBus module is a part of the device Flash Subsystem (FSS). For more information about FSS, see Section 12.3.1, Flash Subsystem (FSS).
The HyperBus module is a low pin count memory interface that provides high read/write performance. The HyperBus module connects to HyperBus memory (HyperFlash or HyperRAM) and uses simple HyperBus protocol for read and write transactions.
There is one HyperBus™ module inside the device. The HyperBus module includes one HyperBus Memory Controller (HBMC).
Table 12-4056 shows HyperBus allocation across device domains.
Instance | Domain | ||
---|---|---|---|
WKUP | MCU | MAIN | |
MCU_FSS0_HPB0 | - | ✓ | - |
Figure 12-2042 shows the HyperBus module overview.