Figure 12-2582 takes advantage of the synchronization feature between the ECAP modules. Here 4 independent PWM channels are required with different frequencies, but at integer multiples of each other to avoid "beat" frequencies. Hence one ECAP module is configured as the Master and the remaining 3 are Slaves all receiving their synch pulse (CTR = PRD) from the master. Note the Master is chosen to have the lower frequency (F1 = 1/20,000) requirement. Here Slave2 Freq = 2 × F1, Slave3 Freq = 4 × F1 and Slave4 Freq = 5 × F1. Note here values are in decimal notation. Also, only the APWM1 output waveform is shown.
Table 12-5012 ECAP1 Initialization for Multichannel PWM Generation with SynchronizationRegister | Bit | Value |
---|
CAP1 | CAP1 | 20000 |
CTRPHS | CTRPHS | 0 |
ECCTL2 | CAP_APWM | EC_APWM_MODE |
ECCTL2 | APWMPOL | EC_ACTV_HI |
ECCTL2 | SYNCI_EN | EC_DISABLE |
ECCTL2 | SYNCO_SEL | EC_CTR_PRD |
ECCTL2 | TSCTRSTOP | EC_RUN |
Table 12-5013 ECAP2 Initialization for Multichannel PWM Generation with SynchronizationRegister | Bit | Value |
---|
CAP1 | CAP1 | 10000 |
CTRPHS | CTRPHS | 0 |
ECCTL2 | CAP_APWM | EC_APWM_MODE |
ECCTL2 | APWMPOL | EC_ACTV_HI |
ECCTL2 | SYNCI_EN | EC_ENABLE |
ECCTL2 | SYNCO_SEL | EC_SYNCI |
ECCTL2 | TSCTRSTOP | EC_RUN |
Table 12-5014 ECAP3 Initialization for Multichannel PWM Generation with SynchronizationRegister | Bit | Value |
---|
CAP1 | CAP1 | 5000 |
CTRPHS | CTRPHS | 0 |
ECCTL2 | CAP_APWM | EC_APWM_MODE |
ECCTL2 | APWMPOL | EC_ACTV_HI |
ECCTL2 | SYNCI_EN | EC_ENABLE |
ECCTL2 | SYNCO_SEL | EC_SYNCI |
ECCTL2 | TSCTRSTOP | EC_RUN |
Table 12-5015 ECAP4 Initialization for Multichannel PWM Generation with SynchronizationRegister | Bit | Value |
---|
CAP1 | CAP1 | 4000 |
CTRPHS | CTRPHS | 0 |
ECCTL2 | CAP_APWM | EC_APWM_MODE |
ECCTL2 | APWMPOL | EC_ACTV_HI |
ECCTL2 | SYNCI_EN | EC_ENABLE |
ECCTL2 | SYNCO_SEL | EC_SYNCO_DIS |
ECCTL2 | TSCTRSTOP | EC_RUN |