SPRUIU1 User guide

Table 5-469 lists the memory-mapped registers for the MCU_CTRL_MMR0. All register offset addresses not listed in Table 5-469 should be considered as reserved locations and the register contents should not be modified.

Table 5-468 MCU_CTRL_MMR0 Instances

Instance	Base Address
MCU_CTRL_MMR0_CFG0	40F0 0000h

Table 5-469 MCU_CTRL_MMR0 Registers

Offset	Acronym	Register Name	MCU_CTRL_MMR0_CFG0 Physical Address
0h	CTRLMMR_MCU_PID	Peripheral Identification Register	40F0 0000h
8h	CTRLMMR_MCU_MMR_CFG1	Configuration register 1	40F0 0008h
100h	CTRLMMR_MCU_IPC_SET0	IPC Generation Register 0	40F0 0100h
104h	CTRLMMR_MCU_IPC_SET1	IPC Generation Register 1	40F0 0104h
120h	CTRLMMR_MCU_IPC_SET8	IPC Generation Register 8	40F0 0120h
180h	CTRLMMR_MCU_IPC_CLR0	IPC Acknowledge Register 0	40F0 0180h
184h	CTRLMMR_MCU_IPC_CLR1	IPC Acknowledge Register 1	40F0 0184h
1A0h	CTRLMMR_MCU_IPC_CLR8	IPC Acknowledge Register 8	40F0 01A0h
200h	CTRLMMR_MCU_MAC_ID0	MAC Address Lo register	40F0 0200h
204h	CTRLMMR_MCU_MAC_ID1	MAC Address Hi Register	40F0 0204h
1008h	CTRLMMR_MCU_LOCK0_KICK0	Partition 0 Lock Key 0 Register	40F0 1008h
100Ch	CTRLMMR_MCU_LOCK0_KICK1	Partition 0 Lock Key 1 Register	40F0 100Ch
1010h	CTRLMMR_MCU_INTR_RAW_STAT	Interrupt Raw Status Register	40F0 1010h
1014h	CTRLMMR_MCU_INTR_STAT_CLR	Interrupt Status and Clear Register	40F0 1014h
1018h	CTRLMMR_MCU_INTR_EN_SET	Interrupt Enable Set Register	40F0 1018h
101Ch	CTRLMMR_MCU_INTR_EN_CLR	Interrupt Enable Clear Register	40F0 101Ch
1020h	CTRLMMR_MCU_EOI	End of Interrupt Register	40F0 1020h
1024h	CTRLMMR_MCU_FAULT_ADDR	Fault Address Register	40F0 1024h
1028h	CTRLMMR_MCU_FAULT_TYPE	Fault Type Register	40F0 1028h
102Ch	CTRLMMR_MCU_FAULT_ATTR	Fault Attribute Register	40F0 102Ch
1030h	CTRLMMR_MCU_FAULT_CLR	Fault Clear Register	40F0 1030h
4030h	CTRLMMR_MCU_MSMC_CFG	MSMC Configuration Register	40F0 4030h
4040h	CTRLMMR_MCU_ENET_CTRL	MCU Ethernet Port1 Control Register	40F0 4040h
4060h	CTRLMMR_MCU_SPI1_CTRL	MCU SPI1 Connectivity Control Register	40F0 4060h
4070h	CTRLMMR_MCU_I3C0_CTRL0	MCU I3C0 Control Register 0	40F0 4070h
4074h	CTRLMMR_MCU_I3C0_CTRL1	MCU I3C0 Control Register 1	40F0 4074h
4080h	CTRLMMR_MCU_I2C0_CTRL	MCU I2C0 Control Register	40F0 4080h
4084h	CTRLMMR_MCU_I2C1_CTRL	MCU I2C1 Control Register	40F0 4084h
40A0h	CTRLMMR_MCU_FSS_CTRL	Flash Subsystem Control Register	40F0 40A0h
40B0h	CTRLMMR_MCU_ADC0_CTRL	MCU_ADC0 Control Register	40F0 40B0h
40C0h	CTRLMMR_MCU_ADC0_TRIM	MCU ADC0 Trim Register	40F0 40C0h
4200h	CTRLMMR_MCU_TIMER0_CTRL	MCU_TIMER0 Control Register	40F0 4200h
4204h	CTRLMMR_MCU_TIMER1_CTRL	MCU_TIMER1 Control Register	40F0 4204h
4208h	CTRLMMR_MCU_TIMER2_CTRL	MCU_TIMER2 Control Register	40F0 4208h
420Ch	CTRLMMR_MCU_TIMER3_CTRL	MCU_TIMER3 Control Register	40F0 420Ch
4210h	CTRLMMR_MCU_TIMER4_CTRL	MCU_TIMER4 Control Register	40F0 4210h
4214h	CTRLMMR_MCU_TIMER5_CTRL	MCU_TIMER5 Control Register	40F0 4214h
4218h	CTRLMMR_MCU_TIMER6_CTRL	MCU_TIMER6 Control Register	40F0 4218h
421Ch	CTRLMMR_MCU_TIMER7_CTRL	MCU_TIMER7 Control Register	40F0 421Ch
4220h	CTRLMMR_MCU_TIMER8_CTRL	MCU_TIMER8 Control Register	40F0 4220h
4224h	CTRLMMR_MCU_TIMER9_CTRL	MCU_TIMER9 Control Register	40F0 4224h
4280h	CTRLMMR_MCU_TIMERIO0_CTRL	MCU_TIMERIO0 Control Register	40F0 4280h
4284h	CTRLMMR_MCU_TIMERIO1_CTRL	MCU_TIMERIO1 Control Register	40F0 4284h
4288h	CTRLMMR_MCU_TIMERIO2_CTRL	MCU_TIMERIO2 Control Register	40F0 4288h
428Ch	CTRLMMR_MCU_TIMERIO3_CTRL	MCU_TIMERIO3 Control Register	40F0 428Ch
4290h	CTRLMMR_MCU_TIMERIO4_CTRL	MCU_TIMERIO4 Control Register	40F0 4290h
4294h	CTRLMMR_MCU_TIMERIO5_CTRL	MCU_TIMERIO5 Control Register	40F0 4294h
4298h	CTRLMMR_MCU_TIMERIO6_CTRL	MCU_TIMERIO6 Control Register	40F0 4298h
429Ch	CTRLMMR_MCU_TIMERIO7_CTRL	MCU_TIMERIO7 Control Register	40F0 429Ch
42A0h	CTRLMMR_MCU_TIMERIO8_CTRL	MCU_TIMERIO8 Control Register	40F0 42A0h
42A4h	CTRLMMR_MCU_TIMERIO9_CTRL	MCU_TIMERIO9 Control Register	40F0 42A4h
4300h	CTRLMMR_MCU_MTOG0_CTRL	MAIN to MCU Master Timeout Gasket Control	40F0 4300h
5008h	CTRLMMR_MCU_LOCK1_KICK0	Partition 1 Lock Key 0 Register	40F0 5008h
500Ch	CTRLMMR_MCU_LOCK1_KICK1	Partition 1 Lock Key 1 Register	40F0 500Ch
8010h	CTRLMMR_MCU_CLKOUT0_CTRL	MCU_CLKOUT0 Control Register	40F0 8010h
8018h	CTRLMMR_MCU_EFUSE_CLKSEL	MCU eFuse Controller Clock Select Register	40F0 8018h
8020h	CTRLMMR_MCU_MCAN0_CLKSEL	MCU_MCAN Clock Select Register	40F0 8020h
8024h	CTRLMMR_MCU_MCAN1_CLKSEL	MCU_MCAN Clock Select Register	40F0 8024h
8030h	CTRLMMR_MCU_OSPI0_CLKSEL	MCU_OSPI Clock Select Register	40F0 8030h
8040h	CTRLMMR_MCU_ADC0_CLKSEL	MCU_ADC Clock Select Register	40F0 8040h
8050h	CTRLMMR_MCU_ENET_CLKSEL	MCU Ethernet Port1 Clock Select Register	40F0 8050h
8080h	CTRLMMR_MCU_R5_CORE0_CLKSEL	MCU R5 Core 0 Clock Select Register	40F0 8080h
8100h	CTRLMMR_MCU_TIMER0_CLKSEL	MCU_TIMER0 Clock Select Register	40F0 8100h
8104h	CTRLMMR_MCU_TIMER1_CLKSEL	MCU_TIMER1 Clock Select Register	40F0 8104h
8108h	CTRLMMR_MCU_TIMER2_CLKSEL	MCU_TIMER2 Clock Select Register	40F0 8108h
810Ch	CTRLMMR_MCU_TIMER3_CLKSEL	MCU_TIMER3 Clock Select Register	40F0 810Ch
8110h	CTRLMMR_MCU_TIMER4_CLKSEL	MCU_TIMER4 Clock Select Register	40F0 8110h
8114h	CTRLMMR_MCU_TIMER5_CLKSEL	MCU_TIMER5 Clock Select Register	40F0 8114h
8118h	CTRLMMR_MCU_TIMER6_CLKSEL	MCU_TIMER6 Clock Select Register	40F0 8118h
811Ch	CTRLMMR_MCU_TIMER7_CLKSEL	MCU_TIMER7 Clock Select Register	40F0 811Ch
8120h	CTRLMMR_MCU_TIMER8_CLKSEL	MCU_TIMER8 Clock Select Register	40F0 8120h
8124h	CTRLMMR_MCU_TIMER9_CLKSEL	MCU_TIMER9 Clock Select Register	40F0 8124h
8180h	CTRLMMR_MCU_RTI0_CLKSEL	MCU_RTI[0:0] Clock Select Register	40F0 8180h
8184h	CTRLMMR_MCU_RTI1_CLKSEL	MCU_RTI[0:0] Clock Select Register	40F0 8184h
81C0h	CTRLMMR_MCU_USART_CLKSEL	MCU_USART0 Clock Select Register	40F0 81C0h
9008h	CTRLMMR_MCU_LOCK2_KICK0	Partition 2 Lock Key 0 Register	40F0 9008h
900Ch	CTRLMMR_MCU_LOCK2_KICK1	Partition 2 Lock Key 1 Register	40F0 900Ch
C000h	CTRLMMR_MCU_LBIST_CTRL	MCU_Pulsar Logic BIST Control Register	40F0 C000h
C004h	CTRLMMR_MCU_LBIST_PATCOUNT	MCU_Pulsar Logic BIST Pattern Count Register	40F0 C004h
C008h	CTRLMMR_MCU_LBIST_SEED0	MCU_Pulsar Logic BIST Seed0 Register	40F0 C008h
C00Ch	CTRLMMR_MCU_LBIST_SEED1	MCU_Pulsar Logic BIST Seed1 Register	40F0 C00Ch
C010h	CTRLMMR_MCU_LBIST_SPARE0	MCU_Pulsar Logic BIST Spare0 Register	40F0 C010h
C014h	CTRLMMR_MCU_LBIST_SPARE1	MCU_Pulsar Logic BIST Spare1 Register	40F0 C014h
C018h	CTRLMMR_MCU_LBIST_STAT	MCU_Pulsar Logic BIST Status Register	40F0 C018h
C01Ch	CTRLMMR_MCU_LBIST_MISR	MCU_Pulsar Logic BIST MISR Register	40F0 C01Ch
C280h	CTRLMMR_MCU_LBIST_SIG	MCU Pulsar Logic BIST MISR Signature Register	40F0 C280h
D008h	CTRLMMR_MCU_LOCK3_KICK0	Partition 3 Lock Key 0 Register	40F0 D008h
D00Ch	CTRLMMR_MCU_LOCK3_KICK1	Partition 3 Lock Key 1 Register	40F0 D00Ch
11008h	CTRLMMR_MCU_LOCK4_KICK0	Partition 4 Lock Key 0 Register	40F1 1008h
1100Ch	CTRLMMR_MCU_LOCK4_KICK1	Partition 4 Lock Key 1 Register	40F1 100Ch

1.2.4.1 CTRLMMR_MCU_PID Register ( Offset = 0h) [reset = 61800000h]

CTRLMMR_MCU_PID is shown in Figure 5-229 and described in Table 5-471.

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Peripheral release details.

Table 5-470 CTRLMMR_MCU_PID Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 0000h

Figure 5-229 CTRLMMR_MCU_PID Register

31	30	29	28	27	26	25	24
SCHEME		BU		FUNC
R-1h		R-2h		R-180h

23	22	21	20	19	18	17	16
FUNC
R-180h

15	14	13	12	11	10	9	8
R_RTL					X_MAJOR
R-0h					R-0h

7	6	5	4	3	2	1	0
CUSTOM		Y_MINOR
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-471 CTRLMMR_MCU_PID Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	SCHEME	R	1h	CTRLMMR_MCU_PID follows new scheme
29-28	BU	R	2h	Business unit - Processors
27-16	FUNC	R	180h	Module functional identifier - CTRL MMR
15-11	R_RTL	R	0h	RTL revision number
10-8	X_MAJOR	R	0h	Major revision number
7-6	CUSTOM	R	0h	Custom revision number
5-0	Y_MINOR	R	0h	Minor revision number

1.2.4.2 CTRLMMR_MCU_MMR_CFG1 Register ( Offset = 8h) [reset = 8000001Fh]

CTRLMMR_MCU_MMR_CFG1 is shown in Figure 5-230 and described in Table 5-473.

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Indicates the MMR configuration.

Table 5-472 CTRLMMR_MCU_MMR_CFG1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 0008h

Figure 5-230 CTRLMMR_MCU_MMR_CFG1 Register

31	30	29	28	27	26	25	24
RESERVED	RESERVED
R-1h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
PARTITIONS
R-1Fh

LEGEND: R = Read Only; -n = value after reset

Table 5-473 CTRLMMR_MCU_MMR_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	1h	Reserved
30-8	RESERVED	R	0h	Reserved
7-0	PARTITIONS	R	1Fh	Indicates present partitions

1.2.4.3 CTRLMMR_MCU_IPC_SET0 Register ( Offset = 100h) [reset = 0h]

CTRLMMR_MCU_IPC_SET0 is shown in Figure 5-231 and described in Table 5-475.

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Generate interprocessor communication interrupt to MCU R5 core0.

Table 5-474 CTRLMMR_MCU_IPC_SET0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 0100h

Figure 5-231 CTRLMMR_MCU_IPC_SET0 Register

31	30	29	28	27	26	25	24
IPC_SRC_SET
W1TS-0h

23	22	21	20	19	18	17	16
IPC_SRC_SET
W1TS-0h

15	14	13	12	11	10	9	8
IPC_SRC_SET
W1TS-0h

7	6	5	4	3	2	1	0
IPC_SRC_SET				RESERVED			IPC_SET
W1TS-0h				R-0h			W1TS-0h

LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset

Table 5-475 CTRLMMR_MCU_IPC_SET0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	IPC_SRC_SET	W1TS	0h	Read returns current value Write: 0h - No effect 1h - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register
3-1	RESERVED	R	0h	Reserved
0	IPC_SET	W1TS	0h	Read returns 0 Write: 0h - No effect 1h - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register

1.2.4.4 CTRLMMR_MCU_IPC_SET1 Register ( Offset = 104h) [reset = 0h]

CTRLMMR_MCU_IPC_SET1 is shown in Figure 5-232 and described in Table 5-477.

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Generate interprocessor communication interrupt to MCU R5 core1.

Table 5-476 CTRLMMR_MCU_IPC_SET1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 0104h

Figure 5-232 CTRLMMR_MCU_IPC_SET1 Register

31	30	29	28	27	26	25	24
IPC_SRC_SET
W1TS-0h

23	22	21	20	19	18	17	16
IPC_SRC_SET
W1TS-0h

15	14	13	12	11	10	9	8
IPC_SRC_SET
W1TS-0h

7	6	5	4	3	2	1	0
IPC_SRC_SET				RESERVED			IPC_SET
W1TS-0h				R-0h			W1TS-0h

LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset

Table 5-477 CTRLMMR_MCU_IPC_SET1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	IPC_SRC_SET	W1TS	0h	Read returns current value Write: 0h - No effect 1h - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register
3-1	RESERVED	R	0h	Reserved
0	IPC_SET	W1TS	0h	Read returns 0 Write: 0h - No effect 1h - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register

1.2.4.5 CTRLMMR_MCU_IPC_SET8 Register ( Offset = 120h) [reset = 0h]

CTRLMMR_MCU_IPC_SET8 is shown in Figure 5-233 and described in Table 5-479.

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Generate interprocessor communication interrupt to DMSC.

Table 5-478 CTRLMMR_MCU_IPC_SET8 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 0120h

Figure 5-233 CTRLMMR_MCU_IPC_SET8 Register

31	30	29	28	27	26	25	24
IPC_SRC_SET
W1TS-0h

23	22	21	20	19	18	17	16
IPC_SRC_SET
W1TS-0h

15	14	13	12	11	10	9	8
IPC_SRC_SET
W1TS-0h

7	6	5	4	3	2	1	0
IPC_SRC_SET				RESERVED			IPC_SET
W1TS-0h				R-0h			W1TS-0h

LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset

Table 5-479 CTRLMMR_MCU_IPC_SET8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	IPC_SRC_SET	W1TS	0h	Read returns current value Write: 0h - No effect 1h - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR register
3-1	RESERVED	R	0h	Reserved
0	IPC_SET	W1TS	0h	Read returns 0 Write: 0h - No effect 1h - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register

1.2.4.6 CTRLMMR_MCU_IPC_CLR0 Register ( Offset = 180h) [reset = 0h]

CTRLMMR_MCU_IPC_CLR0 is shown in Figure 5-234 and described in Table 5-481.

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Acknowledge interprocessor communication interrupt to MCU R5 core0.

Table 5-480 CTRLMMR_MCU_IPC_CLR0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 0180h

Figure 5-234 CTRLMMR_MCU_IPC_CLR0 Register

31	30	29	28	27	26	25	24
IPC_SRC_CLR
W1TC-0h

23	22	21	20	19	18	17	16
IPC_SRC_CLR
W1TC-0h

15	14	13	12	11	10	9	8
IPC_SRC_CLR
W1TC-0h

7	6	5	4	3	2	1	0
IPC_SRC_CLR				RESERVED			IPC_CLR
W1TC-0h				R-0h			W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-481 CTRLMMR_MCU_IPC_CLR0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	IPC_SRC_CLR	W1TC	0h	Read returns current value Write: 0h - No effect 1h - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register
3-1	RESERVED	R	0h	Reserved
0	IPC_CLR	W1TC	0h	Read returns current value Write: 0h - No effect 1h - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register

1.2.4.7 CTRLMMR_MCU_IPC_CLR1 Register ( Offset = 184h) [reset = 0h]

CTRLMMR_MCU_IPC_CLR1 is shown in Figure 5-235 and described in Table 5-483.

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Acknowledge interprocessor communication interrupt to MCU R5 core1.

Table 5-482 CTRLMMR_MCU_IPC_CLR1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 0184h

Figure 5-235 CTRLMMR_MCU_IPC_CLR1 Register

31	30	29	28	27	26	25	24
IPC_SRC_CLR
W1TC-0h

23	22	21	20	19	18	17	16
IPC_SRC_CLR
W1TC-0h

15	14	13	12	11	10	9	8
IPC_SRC_CLR
W1TC-0h

7	6	5	4	3	2	1	0
IPC_SRC_CLR				RESERVED			IPC_CLR
W1TC-0h				R-0h			W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-483 CTRLMMR_MCU_IPC_CLR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	IPC_SRC_CLR	W1TC	0h	Read returns current value Write: 0h - No effect 1h - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register
3-1	RESERVED	R	0h	Reserved
0	IPC_CLR	W1TC	0h	Read returns current value Write: 0h - No effect 1h - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register

1.2.4.8 CTRLMMR_MCU_IPC_CLR8 Register ( Offset = 1A0h) [reset = 0h]

CTRLMMR_MCU_IPC_CLR8 is shown in Figure 5-236 and described in Table 5-485.

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Acknowledge interprocessor communication interrupt to DMSC.

Table 5-484 CTRLMMR_MCU_IPC_CLR8 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 01A0h

Figure 5-236 CTRLMMR_MCU_IPC_CLR8 Register

31	30	29	28	27	26	25	24
IPC_SRC_CLR
W1TC-0h

23	22	21	20	19	18	17	16
IPC_SRC_CLR
W1TC-0h

15	14	13	12	11	10	9	8
IPC_SRC_CLR
W1TC-0h

7	6	5	4	3	2	1	0
IPC_SRC_CLR				RESERVED			IPC_CLR
W1TC-0h				R-0h			W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-485 CTRLMMR_MCU_IPC_CLR8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	IPC_SRC_CLR	W1TC	0h	Read returns current value Write: 0h - No effect 1h - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register
3-1	RESERVED	R	0h	Reserved
0	IPC_CLR	W1TC	0h	Read returns current value Write: 0h - No effect 1h - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register

1.2.4.9 CTRLMMR_MCU_MAC_ID0 Register ( Offset = 200h) [reset = X]

CTRLMMR_MCU_MAC_ID0 is shown in Figure 5-237 and described in Table 5-487.

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MCU Ethernet MAC address lower 32-bits.

Table 5-486 CTRLMMR_MCU_MAC_ID0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 0200h

Figure 5-237 CTRLMMR_MCU_MAC_ID0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MACID_LO
WOT-X

LEGEND: WOT = Write one time only (subsequent writes are ignored)-n = value after reset

Table 5-487 CTRLMMR_MCU_MAC_ID0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MACID_LO	WOT	X	32 lsbs of MAC address

1.2.4.10 CTRLMMR_MCU_MAC_ID1 Register ( Offset = 204h) [reset = X]

CTRLMMR_MCU_MAC_ID1 is shown in Figure 5-238 and described in Table 5-489.

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MCU Ethernet MAC address upper 16-bits.

Table 5-488 CTRLMMR_MCU_MAC_ID1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 0204h

Figure 5-238 CTRLMMR_MCU_MAC_ID1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																MACID_HI
R-0h																WOT-X

LEGEND: R = Read Only; WOT = Write one time only (subsequent writes are ignored)-n = value after reset

Table 5-489 CTRLMMR_MCU_MAC_ID1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	0h	Reserved
15-0	MACID_HI	WOT	X	16 msbs of MAC address

1.2.4.11 CTRLMMR_MCU_LOCK0_KICK0 Register ( Offset = 1008h) [reset = 0h]

CTRLMMR_MCU_LOCK0_KICK0 is shown in Figure 5-239 and described in Table 5-491.

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Lower 32-bits of Partition0 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_MCU_LOCK0_KICK1 with its key value before write-protected Partition 0 registers can be written.

Table 5-490 CTRLMMR_MCU_LOCK0_KICK0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 1008h

Figure 5-239 CTRLMMR_MCU_LOCK0_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-491 CTRLMMR_MCU_LOCK0_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.2.4.12 CTRLMMR_MCU_LOCK0_KICK1 Register ( Offset = 100Ch) [reset = 0h]

CTRLMMR_MCU_LOCK0_KICK1 is shown in Figure 5-240 and described in Table 5-493.

Return to Summary Table.

Upper 32-bits of Partition 0 write lock key. This register must be written with the designated key value after a write to CTRLMMR_MCU_LOCK0_KICK0 with its key value before write-protected Partition 0 registers can be written.

Table 5-492 CTRLMMR_MCU_LOCK0_KICK1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 100Ch

Figure 5-240 CTRLMMR_MCU_LOCK0_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-493 CTRLMMR_MCU_LOCK0_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers

1.2.4.13 CTRLMMR_MCU_INTR_RAW_STAT Register ( Offset = 1010h) [reset = 0h]

CTRLMMR_MCU_INTR_RAW_STAT is shown in Figure 5-241 and described in Table 5-495.

Return to Summary Table.

Shows the interrupt status (before enabling) and allows setting of the interrupt status (for test).

Table 5-494 CTRLMMR_MCU_INTR_RAW_STAT Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 1010h

Figure 5-241 CTRLMMR_MCU_INTR_RAW_STAT Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	LOCK_ERR	ADDR_ERR	PROT_ERR
R-0h				W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h

LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset

Table 5-495 CTRLMMR_MCU_INTR_RAW_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	RESERVED	W1TS	0h	Reserved
2	LOCK_ERR	W1TS	0h	Lock violation occurred (attempt to write a write-locked register with partition locked) Write 1 to set the status bit (for test) Writing 0 has no effect.
1	ADDR_ERR	W1TS	0h	Address violation occurred (attempt to read or write an invalid register address) Write 1 to set the status bit (for test) Writing 0 has no effect.
0	PROT_ERR	W1TS	0h	Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights) Write 1 to set the status bit (for test) Writing 0 has no effect.

1.2.4.14 CTRLMMR_MCU_INTR_STAT_CLR Register ( Offset = 1014h) [reset = 0h]

CTRLMMR_MCU_INTR_STAT_CLR is shown in Figure 5-242 and described in Table 5-497.

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Shows the enabled interrupt status and allows the interrupt to be cleared.

Table 5-496 CTRLMMR_MCU_INTR_STAT_CLR Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 1014h

Figure 5-242 CTRLMMR_MCU_INTR_STAT_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	EN_LOCK_ERR	EN_ADDR_ERR	EN_PROT_ERR
R-0h				W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-497 CTRLMMR_MCU_INTR_STAT_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	RESERVED	W1TC	0h	Reserved
2	EN_LOCK_ERR	W1TC	0h	Enabled lock interrupt event status Write 1 to clear the interrupt event Writing 0 has no effect.
1	EN_ADDR_ERR	W1TC	0h	Enabled address interrupt event status Write 1 to clear the interrupt event Writing 0 has no effect.
0	EN_PROT_ERR	W1TC	0h	Enabled protection interrupt event status Write 1 to clear the interrupt event Writing 0 has no effect.

1.2.4.15 CTRLMMR_MCU_INTR_EN_SET Register ( Offset = 1018h) [reset = 0h]

CTRLMMR_MCU_INTR_EN_SET is shown in Figure 5-243 and described in Table 5-499.

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Allows interrupt enables to be set.

Table 5-498 CTRLMMR_MCU_INTR_EN_SET Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 1018h

Figure 5-243 CTRLMMR_MCU_INTR_EN_SET Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	LOCK_ERR_EN_SET	ADDR_ERR_EN_SET	PROT_ERR_EN_SET
R-0h				W1TS-0h	W1TS-0h	W1TS-0h	W1TS-0h

LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset

Table 5-499 CTRLMMR_MCU_INTR_EN_SET Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	RESERVED	W1TS	0h	Reserved
2	LOCK_ERR_EN_SET	W1TS	0h	Lock interrupt enable Write 1 to enable lock interrupt events Writing 0 has no effect.
1	ADDR_ERR_EN_SET	W1TS	0h	Address interrupt enable Write 1 to enable address interrupt events Writing 0 has no effect.
0	PROT_ERR_EN_SET	W1TS	0h	Protection interrupt enable Write 1 to enable protection interrupt events Writing 0 has no effect.

1.2.4.16 CTRLMMR_MCU_INTR_EN_CLR Register ( Offset = 101Ch) [reset = 0h]

CTRLMMR_MCU_INTR_EN_CLR is shown in Figure 5-244 and described in Table 5-501.

Return to Summary Table.

Allows interrupt enables to be cleared.

Table 5-500 CTRLMMR_MCU_INTR_EN_CLR Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 101Ch

Figure 5-244 CTRLMMR_MCU_INTR_EN_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED	LOCK_ERR_EN_CLR	ADDR_ERR_EN_CLR	PROT_ERR_EN_CLR
R-0h				W1TC-0h	W1TC-0h	W1TC-0h	W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-501 CTRLMMR_MCU_INTR_EN_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R	0h	Reserved
3	RESERVED	W1TC	0h	Reserved
2	LOCK_ERR_EN_CLR	W1TC	0h	Lock interrupt disable Write 1 to disable lock interrupt events Writing 0 has no effect.
1	ADDR_ERR_EN_CLR	W1TC	0h	Address interrupt disable Write 1 to disable address interrupt events Writing 0 has no effect.
0	PROT_ERR_EN_CLR	W1TC	0h	Protection interrupt disable Write 1 to disable protection interrupt events Writing 0 has no effect.

1.2.4.17 CTRLMMR_MCU_EOI Register ( Offset = 1020h) [reset = 0h]

CTRLMMR_MCU_EOI is shown in Figure 5-245 and described in Table 5-503.

Return to Summary Table.

CTRLMMR_MCU_EOI Vector value This register should be written with interrupt distribution value required by the device architecture to indicate service completion of the MMR interrupt.

Table 5-502 CTRLMMR_MCU_EOI Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 1020h

Figure 5-245 CTRLMMR_MCU_EOI Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								VECTOR
R-0h																								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-503 CTRLMMR_MCU_EOI Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	0h	Reserved
7-0	VECTOR	R/W	0h	CTRLMMR_MCU_EOI vector value

1.2.4.18 CTRLMMR_MCU_FAULT_ADDR Register ( Offset = 1024h) [reset = 0h]

CTRLMMR_MCU_FAULT_ADDR is shown in Figure 5-246 and described in Table 5-505.

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Indicates the address of the first transfer that caused a fault to occur.

Table 5-504 CTRLMMR_MCU_FAULT_ADDR Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 1024h

Figure 5-246 CTRLMMR_MCU_FAULT_ADDR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDRESS
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-505 CTRLMMR_MCU_FAULT_ADDR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ADDRESS	R	0h	Address of the faulted access

1.2.4.19 CTRLMMR_MCU_FAULT_TYPE Register ( Offset = 1028h) [reset = 0h]

CTRLMMR_MCU_FAULT_TYPE is shown in Figure 5-247 and described in Table 5-507.

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Indicates the access type of the first transfer that caused a fault to occur.

Table 5-506 CTRLMMR_MCU_FAULT_TYPE Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 1028h

Figure 5-247 CTRLMMR_MCU_FAULT_TYPE Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																										TYPE
R-0h																										R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-507 CTRLMMR_MCU_FAULT_TYPE Register Field Descriptions

Bit

Field

Type

Reset

Description

31-6

RESERVED

R

0h

Reserved

5-0

TYPE

R

0h

Type of access which faulted

0h - No fault

1h - User execute access

2h - User write access

4h - User read access

8h - Supervisor execute access

10h - Supervisor write access

20h - Supervisor read access

1.2.4.20 CTRLMMR_MCU_FAULT_ATTR Register ( Offset = 102Ch) [reset = 0h]

CTRLMMR_MCU_FAULT_ATTR is shown in Figure 5-248 and described in Table 5-509.

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Indicates the attributes of the first transfer that caused a fault to occur.

Table 5-508 CTRLMMR_MCU_FAULT_ATTR Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 102Ch

Figure 5-248 CTRLMMR_MCU_FAULT_ATTR Register

31	30	29	28	27	26	25	24
XID
R-0h

23	22	21	20	19	18	17	16
XID				ROUTEID
R-0h				R-0h

15	14	13	12	11	10	9	8
ROUTEID
R-0h

7	6	5	4	3	2	1	0
PRIVID
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 5-509 CTRLMMR_MCU_FAULT_ATTR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	XID	R	0h	Transaction ID
19-8	ROUTEID	R	0h	Route ID
7-0	PRIVID	R	0h	Privilege ID

1.2.4.21 CTRLMMR_MCU_FAULT_CLR Register ( Offset = 1030h) [reset = 0h]

CTRLMMR_MCU_FAULT_CLR is shown in Figure 5-249 and described in Table 5-511.

Return to Summary Table.

Allows software to clear the current fault Clearing the current fault allows the CTRLMMR_MCU_FAULT_ADDR, CTRLMMR_MCU_FAULT_TYPE, and CTRLMMR_MCU_FAULT_ATTR registers to latch the attributes of the next fault that occurs. This does not affect the fault interrupt event itself. The interrupt must be cleared using the appropriate INTR_STATUS_CLR register bits.

Table 5-510 CTRLMMR_MCU_FAULT_CLR Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 1030h

Figure 5-249 CTRLMMR_MCU_FAULT_CLR Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLEAR
R-0h							W1TC-0h

LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset

Table 5-511 CTRLMMR_MCU_FAULT_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLEAR	W1TC	0h	Fault clear Write 1 to clear the current fault Writing 0 has no effect

1.2.4.22 CTRLMMR_MCU_MSMC_CFG Register ( Offset = 4030h) [reset = 400h]

CTRLMMR_MCU_MSMC_CFG is shown in Figure 5-250 and described in Table 5-513.

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Used to configure MSMC reset options.

Table 5-512 CTRLMMR_MCU_MSMC_CFG Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4030h

Figure 5-250 CTRLMMR_MCU_MSMC_CFG Register

31	30	29	28	27	26	25	24
DDR_ASSYM_EMIF_SEL	RESERVED	DDR_INTRLV_GRAN
R/W-0h	R-0h	R/W-0h

23	22	21	20	19	18	17	16
RESERVED		DDR_INTRLV_SIZE
R-0h		R/W-0h

15	14	13	12	11	10	9	8
RESERVED				MEM_SIZE
R-0h				R-4h

7	6	5	4	3	2	1	0
RESERVED			MEM_INIT_DIS	RESERVED
R-0h			R/W-0h	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-513 CTRLMMR_MCU_MSMC_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	DDR_ASSYM_EMIF_SEL	R/W	0h	In the asymmetric interleave, controls which EMIF controller implements the separated range of the memory window
30	RESERVED	R	0h	Reserved
29-24	DDR_INTRLV_GRAN	R/W	0h	Defines the size of each memory stripe for interleaved memory space
23-22	RESERVED	R	0h	Reserved
21-16	DDR_INTRLV_SIZE	R/W	0h	Defines the memory window size for the interleaved region starting at the bottom of the external memory address range. 0x00 - 0x13 - No Interleave region: 0x14 - 0x23 - 2^(ddr_intrlv_size) Region size
15-12	RESERVED	R	0h	Reserved
11-8	MEM_SIZE	R	4h	Indicates the size of MSMC shared SRAM/Cache 0h - 0.0 MB 1h - 0.25 MB 2h - 0.5 MB 3h - 0.75 MB 4h - 1.0 MB 5h - 1.25 MB 6h - 1.5 MB 7h - 1.75 MB 8h - 2.0 MB
7-5	RESERVED	R	0h	Reserved
4	MEM_INIT_DIS	R/W	0h	Disables MSMC SRAM initialization (Data, Cache Tags, and Snoop Filters). This is required for proper initial ECC initialization. 0h - Perform memory initialization 1h - Disable memory initialization
3-0	RESERVED	R	0h	Reserved

1.2.4.23 CTRLMMR_MCU_ENET_CTRL Register ( Offset = 4040h) [reset = 1h]

CTRLMMR_MCU_ENET_CTRL is shown in Figure 5-251 and described in Table 5-515.

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Controls MCU Ethernet Port1 operation.

Table 5-514 CTRLMMR_MCU_ENET_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4040h

Figure 5-251 CTRLMMR_MCU_ENET_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			RGMII_ID_MODE	RESERVED		MODE_SEL
R-0h			R/W-0h	R-0h		R/W-1h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-515 CTRLMMR_MCU_ENET_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	RGMII_ID_MODE	R/W	0h	Port1 RGMII internal transmit delay selection 0h - Internal transmit delay 1h - Reserved
3-2	RESERVED	R	0h	Reserved
1-0	MODE_SEL	R/W	1h	Selects Ethernet switch Port1 interface 0h - GMII/MII (not supported) 1h - RMII 2h - RGMII 3h - SGMII (not supported)

1.2.4.24 CTRLMMR_MCU_SPI1_CTRL Register ( Offset = 4060h) [reset = 0h]

CTRLMMR_MCU_SPI1_CTRL is shown in Figure 5-252 and described in Table 5-517.

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Controls if MCU_SPI1 is directly connected to SPI3 in the MAIN Domain (default) or if MCU_SPI1 and SPI3 are independently pinned out.

Table 5-516 CTRLMMR_MCU_SPI1_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4060h

Figure 5-252 CTRLMMR_MCU_SPI1_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							SPI1_LINKDIS
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-517 CTRLMMR_MCU_SPI1_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-1

RESERVED

R

0h

Reserved

0

SPI1_LINKDIS

R/W

0h

Disables direct connection of MCU_SPI1 to SPI3

0h - MCU_SPI1 is tied as a slave to SPI3. MCU_SPI1 CLK, DATA1 and CS0 are driven from SPI3, DATA OUT drives SPI3 DATA0

1h - MCU_SPI1 is NOT tied as a slave to SPI3. MCU_SPI1 CLK, DATA0, DATA1 and CS[3:0] are controlled through their respective MCU_SPI1 pins and SPI3 CLK, DATA0, DATA1, and CS[3:0] are controlled through their respective SPI3 pins.

1.2.4.25 CTRLMMR_MCU_I3C0_CTRL0 Register ( Offset = 4070h) [reset = 1020000h]

CTRLMMR_MCU_I3C0_CTRL0 is shown in Figure 5-253 and described in Table 5-519.

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Controls MCU I3C0 operation.

Table 5-518 CTRLMMR_MCU_I3C0_CTRL0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4070h

Figure 5-253 CTRLMMR_MCU_I3C0_CTRL0 Register

31	30	29	28	27	26	25	24
RESERVED	PID_MFR_ID
R-0h	R/W-102h

23	22	21	20	19	18	17	16
PID_MFR_ID
R/W-102h

15	14	13	12	11	10	9	8
RESERVED							ROLE
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED				PID_INSTANCE
R-0h				R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-519 CTRLMMR_MCU_I3C0_CTRL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	0h	Reserved
30-16	PID_MFR_ID	R/W	102h	Manufacturer ID This input corresponds to bits[47:33] of the Provisional ID to identify the manufacturer. Defaults to TI value.
15-9	RESERVED	R	0h	Reserved
8	ROLE	R/W	0h	Master Role 0h - Main master 1h - Secondary master
7-4	RESERVED	R	0h	Reserved
3-0	PID_INSTANCE	R/W	0h	Provisional ID Instance. This input corresponds to bits[15:12] of the Provisional ID. It is intended to provide a way of differentiating several I3C devices if there would be no other way to have each manufactured device have a unique Provisional ID

1.2.4.26 CTRLMMR_MCU_I3C0_CTRL1 Register ( Offset = 4074h) [reset = 0h]

CTRLMMR_MCU_I3C0_CTRL1 is shown in Figure 5-254 and described in Table 5-521.

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Controls MCU I3C0 operation.

Table 5-520 CTRLMMR_MCU_I3C0_CTRL1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4074h

Figure 5-254 CTRLMMR_MCU_I3C0_CTRL1 Register

31	30	29	28	27	26	25	24
BUS_AVAIL_TIME
R/W-0h

23	22	21	20	19	18	17	16
RESERVED						BUS_IDLE_TIME
R-0h						R/W-0h

15	14	13	12	11	10	9	8
BUS_IDLE_TIME
R/W-0h

7	6	5	4	3	2	1	0
BUS_IDLE_TIME
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-521 CTRLMMR_MCU_I3C0_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	BUS_AVAIL_TIME	R/W	0h	Indicates the number of pclk cycles in the Bus Available condition
23-18	RESERVED	R	0h	Reserved
17-0	BUS_IDLE_TIME	R/W	0h	Indicates the number of pclk cycles in the Bus Idle condition

1.2.4.27 CTRLMMR_MCU_I2C0_CTRL Register ( Offset = 4080h) [reset = 0h]

CTRLMMR_MCU_I2C0_CTRL is shown in Figure 5-255 and described in Table 5-523.

Return to Summary Table.

Controls MCU I2C0 operation.

Table 5-522 CTRLMMR_MCU_I2C0_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4080h

Figure 5-255 CTRLMMR_MCU_I2C0_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							HS_MCS_EN
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-523 CTRLMMR_MCU_I2C0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	HS_MCS_EN	R/W	0h	HS Mode master current source enable. When set, enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing.

1.2.4.28 CTRLMMR_MCU_I2C1_CTRL Register ( Offset = 4084h) [reset = 0h]

CTRLMMR_MCU_I2C1_CTRL is shown in Figure 5-256 and described in Table 5-525.

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Controls MCU I2C1 operation.

Table 5-524 CTRLMMR_MCU_I2C1_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4084h

Figure 5-256 CTRLMMR_MCU_I2C1_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							HS_MCS_EN
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-525 CTRLMMR_MCU_I2C1_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	HS_MCS_EN	R/W	0h	HS Mode master current source enable. When set, enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing.

1.2.4.29 CTRLMMR_MCU_FSS_CTRL Register ( Offset = 40A0h) [reset = 0h]

CTRLMMR_MCU_FSS_CTRL is shown in Figure 5-257 and described in Table 5-527.

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Controls Flash boot region size and placement.

Table 5-526 CTRLMMR_MCU_FSS_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 40A0h

Figure 5-257 CTRLMMR_MCU_FSS_CTRL Register

31	30	29	28	27	26	25	24
RESERVED							RESERVED
R-0h							R/W-0h

23	22	21	20	19	18	17	16
RESERVED		RESERVED
R-0h		R/W-0h

15	14	13	12	11	10	9	8
RESERVED							S0_BOOT_SIZE
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED		S0_BOOT_SEG
R-0h		R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-527 CTRLMMR_MCU_FSS_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	0h	Reserved
24	RESERVED	R/W	0h	Reserved
23-22	RESERVED	R	0h	Reserved
21-16	RESERVED	R/W	0h	Reserved
15-9	RESERVED	R	0h	Reserved
8	S0_BOOT_SIZE	R/W	0h	Selects the size of the boot block to be used for the S0 (OSPI0 or Hyperbus) flash interface 0h - S0 boot size is 64 MB 1h - S0 boot size is 128 MB
7-6	RESERVED	R	0h	Reserved
5-0	S0_BOOT_SEG	R/W	0h	Selects the boot block to be used for the S0 (OSPI0 or Hyperbus) flash interface. If the s0_boot_size is 128 MB then only bits [4:0] of this field are used. Care must be taken to account for the address translation as to not fall off or wrap the address of the flash. (e.g. if both ECC and authentication are enabled for 64 MB boot, the highest valid block number is 49, as sector 50 is only .2M Bytes in size.) 00h - Use block 0 01h - Use block 1 : 3Fh - Use block 63

1.2.4.30 CTRLMMR_MCU_ADC0_CTRL Register ( Offset = 40B0h) [reset = 0h]

CTRLMMR_MCU_ADC0_CTRL is shown in Figure 5-258 and described in Table 5-529.

Return to Summary Table.

Controls operation of MCU ADC0.

Table 5-528 CTRLMMR_MCU_ADC0_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 40B0h

Figure 5-258 CTRLMMR_MCU_ADC0_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED							GPI_MODE_EN
R-0h							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			TRIG_SEL
R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-529 CTRLMMR_MCU_ADC0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R	0h	Reserved
16	GPI_MODE_EN	R/W	0h	Enables MCU_ADC0 data pins to be used as general purpose inputs when set. This signal is tied to the en_dig_test input of MCU_ADC0
15-5	RESERVED	R	0h	Reserved
4-0	TRIG_SEL	R/W	0h	Selects the source of the ADC hardware event trigger 0h - MCU_ADC_EXT_TRIGGER0 pin 1h - MCU_ADC_EXT_TRIGGER1 pin 2h - eHRPWM SOCA event 3h - eHRPWM SOCB event 4h - MCU Timer0 PWM output 5h - MCU Timer1 PWM output 6h - MCU Timer2 PWM output 7h - MCU Timer3 PWM output 8h - Timer0 PWM output 9h - Timer1 PWM output Ah - Timer2 PWM output Bh - Timer3 PWM output Ch - Timer4 PWM output Dh - Timer5 PWM output Eh - Timer6 PWM output Fh - Timer7 PWM output 10h - Timer8 PWM output 11h - Timer9 PWM output 12h - Timer10 PWM output 13h - Timer11 PWM output 15h - Reserved (tied 0h) 16h - Reserved (tied 0h) 18h - MCU Timer4 PWM output 19h - MCU Timer5 PWM output 1Ah - MCU Timer6 PWM output 1Bh - MCU Timer7 PWM output 1Ch - MCU Timer8 PWM output 1Dh - MCU Timer9 PWM output 1Eh - Reserved (tied 0h) 1Fh - Reserved (tied 0h)

1.2.4.31 CTRLMMR_MCU_ADC0_TRIM Register ( Offset = 40C0h) [reset = X]

CTRLMMR_MCU_ADC0_TRIM is shown in Figure 5-259 and described in Table 5-531.

Return to Summary Table.

Trims ADC non-linearities.

Table 5-530 CTRLMMR_MCU_ADC0_TRIM Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 40C0h

Figure 5-259 CTRLMMR_MCU_ADC0_TRIM Register

31	30	29	28	27	26	25	24
RESERVED					TRIM5
R-0h					R/W-X

23	22	21	20	19	18	17	16
TRIM4			TRIM3			TRIM2
R/W-X			R/W-X			R/W-X

15	14	13	12	11	10	9	8
TRIM2		TRIM1				ENABLE_CALB
R/W-X		R/W-X				R/W-X

7	6	5	4	3	2	1	0
ENABLE_CALB			ENABLE_CAL
R/W-X			R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-531 CTRLMMR_MCU_ADC0_TRIM Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R	0h	Reserved
26-24	TRIM5	R/W	X	Refer to AFE specification
23-21	TRIM4	R/W	X	Refer to AFE specification
20-18	TRIM3	R/W	X	Refer to AFE specification
17-14	TRIM2	R/W	X	Refer to AFE specification
13-10	TRIM1	R/W	X	Refer to AFE specification
9-5	ENABLE_CALB	R/W	X	Refer to AFE specification
4-0	ENABLE_CAL	R/W	X	Refer to AFE specification

1.2.4.32 CTRLMMR_MCU_TIMER0_CTRL Register ( Offset = 4200h) [reset = 0h]

CTRLMMR_MCU_TIMER0_CTRL is shown in Figure 5-260 and described in Table 5-533.

Return to Summary Table.

Controls MCU Timer0 operation.

Table 5-532 CTRLMMR_MCU_TIMER0_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4200h

Figure 5-260 CTRLMMR_MCU_TIMER0_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CAP_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-533 CTRLMMR_MCU_TIMER0_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CAP_SEL

R/W

0h

Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER0 is configured for capture operation.

0h - Use MCU_TIMER_IO0 pin

1h - Use MCU_TIMER_IO1 pin

2h - Use MCU_TIMER_IO2 pin

3h - Use MCU_TIMER_IO3 pin

4h - Use MCU_TIMER_IO4 pin

5h - Use MCU_TIMER_IO5 pin

6h - Use MCU_TIMER_IO6 pin

7h - Use MCU_TIMER_IO7 pin

8h - Use MCU_TIMER_IO8 pin

9h - Use MCU_TIMER_IO9 pin

1.2.4.33 CTRLMMR_MCU_TIMER1_CTRL Register ( Offset = 4204h) [reset = 0h]

CTRLMMR_MCU_TIMER1_CTRL is shown in Figure 5-261 and described in Table 5-535.

Return to Summary Table.

Controls MCU Timer1 operation.

Table 5-534 CTRLMMR_MCU_TIMER1_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4204h

Figure 5-261 CTRLMMR_MCU_TIMER1_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED				CAP_SEL
R-0h				R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-535 CTRLMMR_MCU_TIMER1_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	When set, enables cascading of MCU_TIMER1 to MCU_TIMER0
7-4	RESERVED	R	0h	Reserved
3-0	CAP_SEL	R/W	0h	Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER1 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h - Use MCU_TIMER_IO4 pin 5h - Use MCU_TIMER_IO5 pin 6h - Use MCU_TIMER_IO6 pin 7h - Use MCU_TIMER_IO7 pin 8h - Use MCU_TIMER_IO8 pin 9h - Use MCU_TIMER_IO9 pin

1.2.4.34 CTRLMMR_MCU_TIMER2_CTRL Register ( Offset = 4208h) [reset = 0h]

CTRLMMR_MCU_TIMER2_CTRL is shown in Figure 5-262 and described in Table 5-537.

Return to Summary Table.

Controls MCU Timer2 operation.

Table 5-536 CTRLMMR_MCU_TIMER2_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4208h

Figure 5-262 CTRLMMR_MCU_TIMER2_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CAP_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-537 CTRLMMR_MCU_TIMER2_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CAP_SEL

R/W

0h

Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER2 is configured for capture operation.

0h - Use MCU_TIMER_IO0 pin

1h - Use MCU_TIMER_IO1 pin

2h - Use MCU_TIMER_IO2 pin

3h - Use MCU_TIMER_IO3 pin

4h - Use MCU_TIMER_IO4 pin

5h - Use MCU_TIMER_IO5 pin

6h - Use MCU_TIMER_IO6 pin

7h - Use MCU_TIMER_IO7 pin

8h - Use MCU_TIMER_IO8 pin

9h - Use MCU_TIMER_IO9 pin

1.2.4.35 CTRLMMR_MCU_TIMER3_CTRL Register ( Offset = 420Ch) [reset = 0h]

CTRLMMR_MCU_TIMER3_CTRL is shown in Figure 5-263 and described in Table 5-539.

Return to Summary Table.

Controls MCU Timer3 operation.

Table 5-538 CTRLMMR_MCU_TIMER3_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 420Ch

Figure 5-263 CTRLMMR_MCU_TIMER3_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED				CAP_SEL
R-0h				R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-539 CTRLMMR_MCU_TIMER3_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	When set, enables cascading of MCU_TIMER3 to MCU_TIMER2
7-4	RESERVED	R	0h	Reserved
3-0	CAP_SEL	R/W	0h	Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER3 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h - Use MCU_TIMER_IO4 pin 5h - Use MCU_TIMER_IO5 pin 6h - Use MCU_TIMER_IO6 pin 7h - Use MCU_TIMER_IO7 pin 8h - Use MCU_TIMER_IO8 pin 9h - Use MCU_TIMER_IO9 pin

1.2.4.36 CTRLMMR_MCU_TIMER4_CTRL Register ( Offset = 4210h) [reset = 0h]

CTRLMMR_MCU_TIMER4_CTRL is shown in Figure 5-264 and described in Table 5-541.

Return to Summary Table.

Controls MCU Timer4 operation.

Table 5-540 CTRLMMR_MCU_TIMER4_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4210h

Figure 5-264 CTRLMMR_MCU_TIMER4_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CAP_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-541 CTRLMMR_MCU_TIMER4_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CAP_SEL

R/W

0h

Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER4 is configured for capture operation.

0h - Use MCU_TIMER_IO0 pin

1h - Use MCU_TIMER_IO1 pin

2h - Use MCU_TIMER_IO2 pin

3h - Use MCU_TIMER_IO3 pin

4h - Use MCU_TIMER_IO4 pin

5h - Use MCU_TIMER_IO5 pin

6h - Use MCU_TIMER_IO6 pin

7h - Use MCU_TIMER_IO7 pin

8h - Use MCU_TIMER_IO8 pin

9h - Use MCU_TIMER_IO9 pin

1.2.4.37 CTRLMMR_MCU_TIMER5_CTRL Register ( Offset = 4214h) [reset = 0h]

CTRLMMR_MCU_TIMER5_CTRL is shown in Figure 5-265 and described in Table 5-543.

Return to Summary Table.

Controls MCU Timer5 operation.

Table 5-542 CTRLMMR_MCU_TIMER5_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4214h

Figure 5-265 CTRLMMR_MCU_TIMER5_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED				CAP_SEL
R-0h				R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-543 CTRLMMR_MCU_TIMER5_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	When set, enables cascading of MCU_TIMER5 to MCU_TIMER4
7-4	RESERVED	R	0h	Reserved
3-0	CAP_SEL	R/W	0h	Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER5 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h - Use MCU_TIMER_IO4 pin 5h - Use MCU_TIMER_IO5 pin 6h - Use MCU_TIMER_IO6 pin 7h - Use MCU_TIMER_IO7 pin 8h - Use MCU_TIMER_IO8 pin 9h - Use MCU_TIMER_IO9 pin

1.2.4.38 CTRLMMR_MCU_TIMER6_CTRL Register ( Offset = 4218h) [reset = 0h]

CTRLMMR_MCU_TIMER6_CTRL is shown in Figure 5-266 and described in Table 5-545.

Return to Summary Table.

Controls MCU Timer6 operation.

Table 5-544 CTRLMMR_MCU_TIMER6_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4218h

Figure 5-266 CTRLMMR_MCU_TIMER6_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CAP_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-545 CTRLMMR_MCU_TIMER6_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CAP_SEL

R/W

0h

Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER6 is configured for capture operation.

0h - Use MCU_TIMER_IO0 pin

1h - Use MCU_TIMER_IO1 pin

2h - Use MCU_TIMER_IO2 pin

3h - Use MCU_TIMER_IO3 pin

4h - Use MCU_TIMER_IO4 pin

5h - Use MCU_TIMER_IO5 pin

6h - Use MCU_TIMER_IO6 pin

7h - Use MCU_TIMER_IO7 pin

8h - Use MCU_TIMER_IO8 pin

9h - Use MCU_TIMER_IO9 pin

1.2.4.39 CTRLMMR_MCU_TIMER7_CTRL Register ( Offset = 421Ch) [reset = 0h]

CTRLMMR_MCU_TIMER7_CTRL is shown in Figure 5-267 and described in Table 5-547.

Return to Summary Table.

Controls MCU Timer7 operation.

Table 5-546 CTRLMMR_MCU_TIMER7_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 421Ch

Figure 5-267 CTRLMMR_MCU_TIMER7_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED				CAP_SEL
R-0h				R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-547 CTRLMMR_MCU_TIMER7_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	When set, enables cascading of MCU_TIMER7 to MCU_TIMER6
7-4	RESERVED	R	0h	Reserved
3-0	CAP_SEL	R/W	0h	Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER7 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h - Use MCU_TIMER_IO4 pin 5h - Use MCU_TIMER_IO5 pin 6h - Use MCU_TIMER_IO6 pin 7h - Use MCU_TIMER_IO7 pin 8h - Use MCU_TIMER_IO8 pin 9h - Use MCU_TIMER_IO9 pin

1.2.4.40 CTRLMMR_MCU_TIMER8_CTRL Register ( Offset = 4220h) [reset = 0h]

CTRLMMR_MCU_TIMER8_CTRL is shown in Figure 5-268 and described in Table 5-549.

Return to Summary Table.

Controls MCU Timer8 operation.

Table 5-548 CTRLMMR_MCU_TIMER8_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4220h

Figure 5-268 CTRLMMR_MCU_TIMER8_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												CAP_SEL
R-0h																												R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-549 CTRLMMR_MCU_TIMER8_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

CAP_SEL

R/W

0h

Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER8 is configured for capture operation.

0h - Use MCU_TIMER_IO0 pin

1h - Use MCU_TIMER_IO1 pin

2h - Use MCU_TIMER_IO2 pin

3h - Use MCU_TIMER_IO3 pin

4h - Use MCU_TIMER_IO4 pin

5h - Use MCU_TIMER_IO5 pin

6h - Use MCU_TIMER_IO6 pin

7h - Use MCU_TIMER_IO7 pin

8h - Use MCU_TIMER_IO8 pin

9h - Use MCU_TIMER_IO9 pin

1.2.4.41 CTRLMMR_MCU_TIMER9_CTRL Register ( Offset = 4224h) [reset = 0h]

CTRLMMR_MCU_TIMER9_CTRL is shown in Figure 5-269 and described in Table 5-551.

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Controls MCU Timer9 operation.

Table 5-550 CTRLMMR_MCU_TIMER9_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4224h

Figure 5-269 CTRLMMR_MCU_TIMER9_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED							CASCADE_EN
R-0h							R/W-0h

7	6	5	4	3	2	1	0
RESERVED				CAP_SEL
R-0h				R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-551 CTRLMMR_MCU_TIMER9_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R	0h	Reserved
8	CASCADE_EN	R/W	0h	When set, enables cascading of MCU_TIMER9 to MCU_TIMER8
7-4	RESERVED	R	0h	Reserved
3-0	CAP_SEL	R/W	0h	Selects the MCU_TIMERIO input pin for capture input signal. This control is only used when TIMER9 is configured for capture operation. 0h - Use MCU_TIMER_IO0 pin 1h - Use MCU_TIMER_IO1 pin 2h - Use MCU_TIMER_IO2 pin 3h - Use MCU_TIMER_IO3 pin 4h - Use MCU_TIMER_IO4 pin 5h - Use MCU_TIMER_IO5 pin 6h - Use MCU_TIMER_IO6 pin 7h - Use MCU_TIMER_IO7 pin 8h - Use MCU_TIMER_IO8 pin 9h - Use MCU_TIMER_IO9 pin

1.2.4.42 CTRLMMR_MCU_TIMERIO0_CTRL Register ( Offset = 4280h) [reset = Fh]

CTRLMMR_MCU_TIMERIO0_CTRL is shown in Figure 5-270 and described in Table 5-553.

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Controls MCU TimerIO muxing.

Table 5-552 CTRLMMR_MCU_TIMERIO0_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4280h

Figure 5-270 CTRLMMR_MCU_TIMERIO0_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												OUT_SEL
R-0h																												R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-553 CTRLMMR_MCU_TIMERIO0_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

OUT_SEL

R/W

Fh

Selects the source of the MCU_TIMERIO0 output

0h - MCU_TIMERIO0 is driven by MCU_TIMER0 output

1h - MCU_TIMERIO0 is driven by MCU_TIMER1 output

2h - MCU_TIMERIO0 is driven by MCU_TIMER2 output

3h - MCU_TIMERIO0 is driven by MCU_TIMER3 output

4h - MCU_TIMERIO0 is driven by MCU_TIMER4 output

5h - MCU_TIMERIO0 is driven by MCU_TIMER5 output

6h - MCU_TIMERIO0 is driven by MCU_TIMER6 output

7h - MCU_TIMERIO0 is driven by MCU_TIMER7 output

8h - MCU_TIMERIO0 is driven by MCU_TIMER8 output

9h - MCU_TIMERIO0 is driven by MCU_TIMER9 output

Ah - MCU_TIMERIO0 is driven low

Bh - MCU_TIMERIO0 is driven high

Ch - MCU_TIMERIO0 is driven low

Dh - MCU_TIMERIO0 is driven high

Eh - MCU_TIMERIO0 is driven low

Fh - MCU_TIMERIO0 is driven high

1.2.4.43 CTRLMMR_MCU_TIMERIO1_CTRL Register ( Offset = 4284h) [reset = Fh]

CTRLMMR_MCU_TIMERIO1_CTRL is shown in Figure 5-271 and described in Table 5-555.

Return to Summary Table.

Controls MCU TimerIO muxing.

Table 5-554 CTRLMMR_MCU_TIMERIO1_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4284h

Figure 5-271 CTRLMMR_MCU_TIMERIO1_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												OUT_SEL
R-0h																												R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-555 CTRLMMR_MCU_TIMERIO1_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

OUT_SEL

R/W

Fh

Selects the source of the MCU_TIMERIO1 output

0h - MCU_TIMERIO1 is driven by MCU_TIMER0 output

1h - MCU_TIMERIO1 is driven by MCU_TIMER1 output

2h - MCU_TIMERIO1 is driven by MCU_TIMER2 output

3h - MCU_TIMERIO1 is driven by MCU_TIMER3 output

4h - MCU_TIMERIO1 is driven by MCU_TIMER4 output

5h - MCU_TIMERIO1 is driven by MCU_TIMER5 output

6h - MCU_TIMERIO1 is driven by MCU_TIMER6 output

7h - MCU_TIMERIO1 is driven by MCU_TIMER7 output

8h - MCU_TIMERIO1 is driven by MCU_TIMER8 output

9h - MCU_TIMERIO1 is driven by MCU_TIMER9 output

Ah - MCU_TIMERIO1 is driven low

Bh - MCU_TIMERIO1 is driven high

Ch - MCU_TIMERIO1 is driven low

Dh - MCU_TIMERIO1 is driven high

Eh - MCU_TIMERIO1 is driven low

Fh - MCU_TIMERIO1 is driven high

1.2.4.44 CTRLMMR_MCU_TIMERIO2_CTRL Register ( Offset = 4288h) [reset = Fh]

CTRLMMR_MCU_TIMERIO2_CTRL is shown in Figure 5-272 and described in Table 5-557.

Return to Summary Table.

Controls MCU TimerIO muxing.

Table 5-556 CTRLMMR_MCU_TIMERIO2_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4288h

Figure 5-272 CTRLMMR_MCU_TIMERIO2_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												OUT_SEL
R-0h																												R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-557 CTRLMMR_MCU_TIMERIO2_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

OUT_SEL

R/W

Fh

Selects the source of the MCU_TIMERIO2 output

0h - MCU_TIMERIO2 is driven by MCU_TIMER0 output

1h - MCU_TIMERIO2 is driven by MCU_TIMER1 output

2h - MCU_TIMERIO2 is driven by MCU_TIMER2 output

3h - MCU_TIMERIO2 is driven by MCU_TIMER3 output

4h - MCU_TIMERIO2 is driven by MCU_TIMER4 output

5h - MCU_TIMERIO2 is driven by MCU_TIMER5 output

6h - MCU_TIMERIO2 is driven by MCU_TIMER6 output

7h - MCU_TIMERIO2 is driven by MCU_TIMER7 output

8h - MCU_TIMERIO2 is driven by MCU_TIMER8 output

9h - MCU_TIMERIO2 is driven by MCU_TIMER9 output

Ah - MCU_TIMERIO2 is driven low

Bh - MCU_TIMERIO2 is driven high

Ch - MCU_TIMERIO2 is driven low

Dh - MCU_TIMERIO2 is driven high

Eh - MCU_TIMERIO2 is driven low

Fh - MCU_TIMERIO2 is driven high

1.2.4.45 CTRLMMR_MCU_TIMERIO3_CTRL Register ( Offset = 428Ch) [reset = Fh]

CTRLMMR_MCU_TIMERIO3_CTRL is shown in Figure 5-273 and described in Table 5-559.

Return to Summary Table.

Controls MCU TimerIO muxing.

Table 5-558 CTRLMMR_MCU_TIMERIO3_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 428Ch

Figure 5-273 CTRLMMR_MCU_TIMERIO3_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												OUT_SEL
R-0h																												R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-559 CTRLMMR_MCU_TIMERIO3_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

OUT_SEL

R/W

Fh

Selects the source of the MCU_TIMERIO3 output

0h - MCU_TIMERIO3 is driven by MCU_TIMER0 output

1h - MCU_TIMERIO3 is driven by MCU_TIMER1 output

2h - MCU_TIMERIO3 is driven by MCU_TIMER2 output

3h - MCU_TIMERIO3 is driven by MCU_TIMER3 output

4h - MCU_TIMERIO3 is driven by MCU_TIMER4 output

5h - MCU_TIMERIO3 is driven by MCU_TIMER5 output

6h - MCU_TIMERIO3 is driven by MCU_TIMER6 output

7h - MCU_TIMERIO3 is driven by MCU_TIMER7 output

8h - MCU_TIMERIO3 is driven by MCU_TIMER8 output

9h - MCU_TIMERIO3 is driven by MCU_TIMER9 output

Ah - MCU_TIMERIO3 is driven low

Bh - MCU_TIMERIO3 is driven high

Ch - MCU_TIMERIO3 is driven low

Dh - MCU_TIMERIO3 is driven high

Eh - MCU_TIMERIO3 is driven low

Fh - MCU_TIMERIO3 is driven high

1.2.4.46 CTRLMMR_MCU_TIMERIO4_CTRL Register ( Offset = 4290h) [reset = Fh]

CTRLMMR_MCU_TIMERIO4_CTRL is shown in Figure 5-274 and described in Table 5-561.

Return to Summary Table.

Controls MCU TimerIO muxing.

Table 5-560 CTRLMMR_MCU_TIMERIO4_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4290h

Figure 5-274 CTRLMMR_MCU_TIMERIO4_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												OUT_SEL
R-0h																												R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-561 CTRLMMR_MCU_TIMERIO4_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

OUT_SEL

R/W

Fh

Selects the source of the MCU_TIMERIO4 output

0h - MCU_TIMERIO4 is driven by MCU_TIMER0 output

1h - MCU_TIMERIO4 is driven by MCU_TIMER1 output

2h - MCU_TIMERIO4 is driven by MCU_TIMER2 output

3h - MCU_TIMERIO4 is driven by MCU_TIMER3 output

4h - MCU_TIMERIO4 is driven by MCU_TIMER4 output

5h - MCU_TIMERIO4 is driven by MCU_TIMER5 output

6h - MCU_TIMERIO4 is driven by MCU_TIMER6 output

7h - MCU_TIMERIO4 is driven by MCU_TIMER7 output

8h - MCU_TIMERIO4 is driven by MCU_TIMER8 output

9h - MCU_TIMERIO4 is driven by MCU_TIMER9 output

Ah - MCU_TIMERIO4 is driven low

Bh - MCU_TIMERIO4 is driven high

Ch - MCU_TIMERIO4 is driven low

Dh - MCU_TIMERIO4 is driven high

Eh - MCU_TIMERIO4 is driven low

Fh - MCU_TIMERIO4 is driven high

1.2.4.47 CTRLMMR_MCU_TIMERIO5_CTRL Register ( Offset = 4294h) [reset = Fh]

CTRLMMR_MCU_TIMERIO5_CTRL is shown in Figure 5-275 and described in Table 5-563.

Return to Summary Table.

Controls MCU TimerIO muxing.

Table 5-562 CTRLMMR_MCU_TIMERIO5_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4294h

Figure 5-275 CTRLMMR_MCU_TIMERIO5_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												OUT_SEL
R-0h																												R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-563 CTRLMMR_MCU_TIMERIO5_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

OUT_SEL

R/W

Fh

Selects the source of the MCU_TIMERIO5 output

0h - MCU_TIMERIO5 is driven by MCU_TIMER0 output

1h - MCU_TIMERIO5 is driven by MCU_TIMER1 output

2h - MCU_TIMERIO5 is driven by MCU_TIMER2 output

3h - MCU_TIMERIO5 is driven by MCU_TIMER3 output

4h - MCU_TIMERIO5 is driven by MCU_TIMER4 output

5h - MCU_TIMERIO5 is driven by MCU_TIMER5 output

6h - MCU_TIMERIO5 is driven by MCU_TIMER6 output

7h - MCU_TIMERIO5 is driven by MCU_TIMER7 output

8h - MCU_TIMERIO5 is driven by MCU_TIMER8 output

9h - MCU_TIMERIO5 is driven by MCU_TIMER9 output

Ah - MCU_TIMERIO5 is driven low

Bh - MCU_TIMERIO5 is driven high

Ch - MCU_TIMERIO5 is driven low

Dh - MCU_TIMERIO5 is driven high

Eh - MCU_TIMERIO5 is driven low

Fh - MCU_TIMERIO5 is driven high

1.2.4.48 CTRLMMR_MCU_TIMERIO6_CTRL Register ( Offset = 4298h) [reset = Fh]

CTRLMMR_MCU_TIMERIO6_CTRL is shown in Figure 5-276 and described in Table 5-565.

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Controls MCU TimerIO muxing.

Table 5-564 CTRLMMR_MCU_TIMERIO6_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4298h

Figure 5-276 CTRLMMR_MCU_TIMERIO6_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												OUT_SEL
R-0h																												R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-565 CTRLMMR_MCU_TIMERIO6_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

OUT_SEL

R/W

Fh

Selects the source of the MCU_TIMERIO6 output

0h - MCU_TIMERIO6 is driven by MCU_TIMER0 output

1h - MCU_TIMERIO6 is driven by MCU_TIMER1 output

2h - MCU_TIMERIO6 is driven by MCU_TIMER2 output

3h - MCU_TIMERIO6 is driven by MCU_TIMER3 output

4h - MCU_TIMERIO6 is driven by MCU_TIMER4 output

5h - MCU_TIMERIO6 is driven by MCU_TIMER5 output

6h - MCU_TIMERIO6 is driven by MCU_TIMER6 output

7h - MCU_TIMERIO6 is driven by MCU_TIMER7 output

8h - MCU_TIMERIO6 is driven by MCU_TIMER8 output

9h - MCU_TIMERIO6 is driven by MCU_TIMER9 output

Ah - MCU_TIMERIO6 is driven low

Bh - MCU_TIMERIO6 is driven high

Ch - MCU_TIMERIO6 is driven low

Dh - MCU_TIMERIO6 is driven high

Eh - MCU_TIMERIO6 is driven low

Fh - MCU_TIMERIO6 is driven high

1.2.4.49 CTRLMMR_MCU_TIMERIO7_CTRL Register ( Offset = 429Ch) [reset = Fh]

CTRLMMR_MCU_TIMERIO7_CTRL is shown in Figure 5-277 and described in Table 5-567.

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Controls MCU TimerIO muxing.

Table 5-566 CTRLMMR_MCU_TIMERIO7_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 429Ch

Figure 5-277 CTRLMMR_MCU_TIMERIO7_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												OUT_SEL
R-0h																												R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-567 CTRLMMR_MCU_TIMERIO7_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

OUT_SEL

R/W

Fh

Selects the source of the MCU_TIMERIO7 output

0h - MCU_TIMERIO7 is driven by MCU_TIMER0 output

1h - MCU_TIMERIO7 is driven by MCU_TIMER1 output

2h - MCU_TIMERIO7 is driven by MCU_TIMER2 output

3h - MCU_TIMERIO7 is driven by MCU_TIMER3 output

4h - MCU_TIMERIO7 is driven by MCU_TIMER4 output

5h - MCU_TIMERIO7 is driven by MCU_TIMER5 output

6h - MCU_TIMERIO7 is driven by MCU_TIMER6 output

7h - MCU_TIMERIO7 is driven by MCU_TIMER7 output

8h - MCU_TIMERIO7 is driven by MCU_TIMER8 output

9h - MCU_TIMERIO7 is driven by MCU_TIMER9 output

Ah - MCU_TIMERIO7 is driven low

Bh - MCU_TIMERIO7 is driven high

Ch - MCU_TIMERIO7 is driven low

Dh - MCU_TIMERIO7 is driven high

Eh - MCU_TIMERIO7 is driven low

Fh - MCU_TIMERIO7 is driven high

1.2.4.50 CTRLMMR_MCU_TIMERIO8_CTRL Register ( Offset = 42A0h) [reset = Fh]

CTRLMMR_MCU_TIMERIO8_CTRL is shown in Figure 5-278 and described in Table 5-569.

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Controls MCU TimerIO muxing.

Table 5-568 CTRLMMR_MCU_TIMERIO8_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 42A0h

Figure 5-278 CTRLMMR_MCU_TIMERIO8_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												OUT_SEL
R-0h																												R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-569 CTRLMMR_MCU_TIMERIO8_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

OUT_SEL

R/W

Fh

Selects the source of the MCU_TIMERIO8 output

0h - MCU_TIMERIO8 is driven by MCU_TIMER0 output

1h - MCU_TIMERIO8 is driven by MCU_TIMER1 output

2h - MCU_TIMERIO8 is driven by MCU_TIMER2 output

3h - MCU_TIMERIO8 is driven by MCU_TIMER3 output

4h - MCU_TIMERIO8 is driven by MCU_TIMER4 output

5h - MCU_TIMERIO8 is driven by MCU_TIMER5 output

6h - MCU_TIMERIO8 is driven by MCU_TIMER6 output

7h - MCU_TIMERIO8 is driven by MCU_TIMER7 output

8h - MCU_TIMERIO8 is driven by MCU_TIMER8 output

9h - MCU_TIMERIO8 is driven by MCU_TIMER9 output

Ah - MCU_TIMERIO8 is driven low

Bh - MCU_TIMERIO8 is driven high

Ch - MCU_TIMERIO8 is driven low

Dh - MCU_TIMERIO8 is driven high

Eh - MCU_TIMERIO8 is driven low

Fh - MCU_TIMERIO8 is driven high

1.2.4.51 CTRLMMR_MCU_TIMERIO9_CTRL Register ( Offset = 42A4h) [reset = Fh]

CTRLMMR_MCU_TIMERIO9_CTRL is shown in Figure 5-279 and described in Table 5-571.

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Controls MCU TimerIO muxing.

Table 5-570 CTRLMMR_MCU_TIMERIO9_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 42A4h

Figure 5-279 CTRLMMR_MCU_TIMERIO9_CTRL Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												OUT_SEL
R-0h																												R/W-Fh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-571 CTRLMMR_MCU_TIMERIO9_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-4

RESERVED

R

0h

Reserved

3-0

OUT_SEL

R/W

Fh

Selects the source of the MCU_TIMERIO9 output

0h - MCU_TIMERIO9 is driven by MCU_TIMER0 output

1h - MCU_TIMERIO9 is driven by MCU_TIMER1 output

2h - MCU_TIMERIO9 is driven by MCU_TIMER2 output

3h - MCU_TIMERIO9 is driven by MCU_TIMER3 output

4h - MCU_TIMERIO9 is driven by MCU_TIMER4 output

5h - MCU_TIMERIO9 is driven by MCU_TIMER5 output

6h - MCU_TIMERIO9 is driven by MCU_TIMER6 output

7h - MCU_TIMERIO9 is driven by MCU_TIMER7 output

8h - MCU_TIMERIO9 is driven by MCU_TIMER8 output

9h - MCU_TIMERIO9 is driven by MCU_TIMER9 output

Ah - MCU_TIMERIO9 is driven low

Bh - MCU_TIMERIO9 is driven high

Ch - MCU_TIMERIO9 is driven low

Dh - MCU_TIMERIO9 is driven high

Eh - MCU_TIMERIO9 is driven low

Fh - MCU_TIMERIO9 is driven high

1.2.4.52 CTRLMMR_MCU_MTOG0_CTRL Register ( Offset = 4300h) [reset = X]

CTRLMMR_MCU_MTOG0_CTRL is shown in Figure 5-280 and described in Table 5-573.

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Controls timeout operation of transaction from MAIN domain to MCU peripheral data bus.

Table 5-572 CTRLMMR_MCU_MTOG0_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 4300h

Figure 5-280 CTRLMMR_MCU_MTOG0_CTRL Register

31	30	29	28	27	26	25	24
IDLE_STAT	RESERVED
R-X	R-0h

23	22	21	20	19	18	17	16
FORCE_TIMEOUT
R/W-0h

15	14	13	12	11	10	9	8
TIMEOUT_EN	RESERVED
R/W-0h	R-0h

7	6	5	4	3	2	1	0
RESERVED					TIMEOUT_VAL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-573 CTRLMMR_MCU_MTOG0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	IDLE_STAT	R	X	Idle status When high, indicates MTOG0 is idle.
30-24	RESERVED	R	0h	Reserved
23-16	FORCE_TIMEOUT	R/W	0h	Force Timeout Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket. 95h - Force a gasket timeout All others - Normal operation
15	TIMEOUT_EN	R/W	0h	Timeout Enable 0h - Disable the gasket. Clear the interrupt and reset the counter 1h - Enable the timeout gasket functions
14-3	RESERVED	R	0h	Reserved
2-0	TIMEOUT_VAL	R/W	0h	Gasket Timeout Value Selects the number of clock cycles before the interface is considered to have timed out 0h - 1024 clock cycles 1h - 4096 clock cycles 2h - 16,384 clock cycles 3h - 65,536 clock cycles 4h - 262,144 clock cycles 5h - 1,048,576 clock cycles 6h - 2,097,152 clock cycles 7h - 4,194,303 clock cycles

1.2.4.53 CTRLMMR_MCU_LOCK1_KICK0 Register ( Offset = 5008h) [reset = 0h]

CTRLMMR_MCU_LOCK1_KICK0 is shown in Figure 5-281 and described in Table 5-575.

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Lower 32-bits of Partition1 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_MCU_LOCK1_KICK1 with its key value before write-protected Partition 1 registers can be written.

Table 5-574 CTRLMMR_MCU_LOCK1_KICK0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 5008h

Figure 5-281 CTRLMMR_MCU_LOCK1_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-575 CTRLMMR_MCU_LOCK1_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.2.4.54 CTRLMMR_MCU_LOCK1_KICK1 Register ( Offset = 500Ch) [reset = 0h]

CTRLMMR_MCU_LOCK1_KICK1 is shown in Figure 5-282 and described in Table 5-577.

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Upper 32-bits of Partition 1 write lock key. This register must be written with the designated key value after a write to CTRLMMR_MCU_LOCK1_KICK0 with its key value before write-protected Partition 1 registers can be written.

Table 5-576 CTRLMMR_MCU_LOCK1_KICK1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 500Ch

Figure 5-282 CTRLMMR_MCU_LOCK1_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-577 CTRLMMR_MCU_LOCK1_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers

1.2.4.55 CTRLMMR_MCU_CLKOUT0_CTRL Register ( Offset = 8010h) [reset = 0h]

CTRLMMR_MCU_CLKOUT0_CTRL is shown in Figure 5-283 and described in Table 5-579.

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Enables and selects clock source of CPSW MCU_CLKOUT0 pin.

Table 5-578 CTRLMMR_MCU_CLKOUT0_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8010h

Figure 5-283 CTRLMMR_MCU_CLKOUT0_CTRL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			CLK_EN	RESERVED			CLK_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-579 CTRLMMR_MCU_CLKOUT0_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	CLK_EN	R/W	0h	When set, enables MCU_CLKOUT0 output
3-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects MCU_CLKOUT0 clock source 0h - RGMII_MHZ_50_CLK (50 MHz) 1h -RGMII_MHZ_50_CLK / 2 (25 MHz)

1.2.4.56 CTRLMMR_MCU_EFUSE_CLKSEL Register ( Offset = 8018h) [reset = 0h]

CTRLMMR_MCU_EFUSE_CLKSEL is shown in Figure 5-284 and described in Table 5-581.

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Selects the functional clock source for the MCU domain eFuse Controller.

Table 5-580 CTRLMMR_MCU_EFUSE_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8018h

Figure 5-284 CTRLMMR_MCU_EFUSE_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-581 CTRLMMR_MCU_EFUSE_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-1

RESERVED

R

0h

Reserved

0

CLK_SEL

R/W

0h

Selects the clock source

0h - EFUSE_CLK (HFOSC0_CLKOUT or CLK_12M_RC)

1h - MCU_SYSCLK0 / 8

1.2.4.57 CTRLMMR_MCU_MCAN0_CLKSEL Register ( Offset = 8020h) [reset = 0h]

CTRLMMR_MCU_MCAN0_CLKSEL is shown in Figure 5-285 and described in Table 5-583.

Return to Summary Table.

Controls the functional clock source for MCU_MCAN0.

Table 5-582 CTRLMMR_MCU_MCAN0_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8020h

Figure 5-285 CTRLMMR_MCU_MCAN0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-583 CTRLMMR_MCU_MCAN0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	CLK_SEL	R/W	0h	MCU_MCAN MCAN_CLK selection 0h - MCU_PLL2_HSDIV3_CLKOUT 1h - MCU_EXT_REFCLK0 2h - MCU_PLL1_HSDIV2_CLKOUT 3h - HFOSC0_CLKOUT

1.2.4.58 CTRLMMR_MCU_MCAN1_CLKSEL Register ( Offset = 8024h) [reset = 0h]

CTRLMMR_MCU_MCAN1_CLKSEL is shown in Figure 5-286 and described in Table 5-585.

Return to Summary Table.

Controls the functional clock source for MCU_MCAN1.

Table 5-584 CTRLMMR_MCU_MCAN1_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8024h

Figure 5-286 CTRLMMR_MCU_MCAN1_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-585 CTRLMMR_MCU_MCAN1_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	0h	Reserved
1-0	CLK_SEL	R/W	0h	MCU_MCAN MCAN_CLK selection 0h - MCU_PLL2_HSDIV3_CLKOUT 1h - MCU_EXT_REFCLK0 2h - MCU_PLL1_HSDIV2_CLKOUT 3h - HFOSC0_CLKOUT

1.2.4.59 CTRLMMR_MCU_OSPI0_CLKSEL Register ( Offset = 8030h) [reset = 0h]

CTRLMMR_MCU_OSPI0_CLKSEL is shown in Figure 5-287 and described in Table 5-587.

Return to Summary Table.

Controls the OSPI loopback clock source.

Table 5-586 CTRLMMR_MCU_OSPI0_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8030h

Figure 5-287 CTRLMMR_MCU_OSPI0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED			LOOPCLK_SEL	RESERVED			CLK_SEL
R-0h			R/W-0h	R-0h			R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-587 CTRLMMR_MCU_OSPI0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-5	RESERVED	R	0h	Reserved
4	LOOPCLK_SEL	R/W	0h	OBSPI0 Loopback clock source 0h - OSPI_DQS external pin (external) 1h - OSPI_LBCLKO output (internal)
3-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	OSPI0 reference clock selection 0h - MCU_PLL1_HSDIV4_CLKOUT 1h - MCU_PLL2_HSDIV4_CLKOUT

1.2.4.60 CTRLMMR_MCU_ADC0_CLKSEL Register ( Offset = 8040h) [reset = 0h]

CTRLMMR_MCU_ADC0_CLKSEL is shown in Figure 5-288 and described in Table 5-589.

Return to Summary Table.

Controls the functional clock source for the MCU_ADC0.

Table 5-588 CTRLMMR_MCU_ADC0_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8040h

Figure 5-288 CTRLMMR_MCU_ADC0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED						CLK_SEL
R-0h						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-589 CTRLMMR_MCU_ADC0_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-2

RESERVED

R

0h

Reserved

1-0

CLK_SEL

R/W

0h

Selects the sampling clock source for ADC0

0h - HFOSC0_CLKOUT

1h - MCU_PLL1_HSDIV1_CLKOUT1

2h - MCU_PLL0_HSDIV1_CLKOUT1

3h - MCU_EXT_REFCLK0

1.2.4.61 CTRLMMR_MCU_ENET_CLKSEL Register ( Offset = 8050h) [reset = F00h]

CTRLMMR_MCU_ENET_CLKSEL is shown in Figure 5-289 and described in Table 5-591.

Return to Summary Table.

Controls selectable clock sources for the MCU Ethernet Port1.

Table 5-590 CTRLMMR_MCU_ENET_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8050h

Figure 5-289 CTRLMMR_MCU_ENET_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED				CPTS_CLKSEL
R-0h				R/W-Fh

7	6	5	4	3	2	1	0
RESERVED							RMII_CLK_SEL
R-0h							R/W -0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-591 CTRLMMR_MCU_ENET_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	0h	Reserved
11-8	CPTS_CLKSEL	R/W	Fh	Selects the clock source for the CPSW2x Ethernet switch Common Platform Time Stamp module 0h - MAIN_PLL3_HSDIV1_CLKOUT 1h - MAIN_PLL0_HSDIV6_CLKOUT 2h - MCU_CPTS_REF_CLK (pin) 3h - CPTS_RFT_CLK (pin) 4h - MCU_EXT_REFCLK0 (pin) 5h - EXT_REFCLK1 (pin) 6h - SERDES0_IP2_LN0_TXMCLK 7h - SERDES0_IP2_LN1_TXMCLK 8h - SERDES0_IP2_LN2_TXMCLK 9h - SERDES0_IP2_LN3_TXMCLK Ah - SERDES4_IP2_LN0_TXMCLK Bh - SERDES4_IP2_LN1_TXMCLK Ch - SERDES4_IP2_LN2_TXMCLK Dh - SERDES4_IP2_LN3_TXMCLK Eh - MCU_PLL2_HSDIV1_CLKOUT Fh - MAIN_SYSCLK0 / 2
7-1	RESERVED	R	0h	Reserved
0	RMII_CLK_SEL	R/W	0h	Selects the rmii clock (rmii_mhz_50_clk) source. This defaults to the internal 50 MHz clock source for proper clockstop operation 0h - MCU_PLL2_HSDIV0_CLKOUT / 5 1h - MCU_RMII_REFCLK (pin)

1.2.4.62 CTRLMMR_MCU_R5_CORE0_CLKSEL Register ( Offset = 8080h) [reset = 0h]

CTRLMMR_MCU_R5_CORE0_CLKSEL is shown in Figure 5-290 and described in Table 5-593.

Return to Summary Table.

MCU Core 0 functional clock selection control.

Table 5-592 CTRLMMR_MCU_R5_CORE0_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8080h

Figure 5-290 CTRLMMR_MCU_R5_CORE0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-593 CTRLMMR_MCU_R5_CORE0_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	Selects the Core 0 functional clock and mcu/interface clock ratio. Note, this value must only be changed when the MCU R5 is powered off or in WFI 0h - Use MCU_SYSCLK0. MCU/interface is 3:1 clock ratio 1h - Use MCU_SYSCLK0/3. MCU/interface is 1:1 clock ratio

1.2.4.63 CTRLMMR_MCU_TIMER0_CLKSEL Register ( Offset = 8100h) [reset = 0h]

CTRLMMR_MCU_TIMER0_CLKSEL is shown in Figure 5-291 and described in Table 5-595.

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MCU Timer0 functional clock selection control.

Table 5-594 CTRLMMR_MCU_TIMER0_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8100h

Figure 5-291 CTRLMMR_MCU_TIMER0_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-595 CTRLMMR_MCU_TIMER0_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - MCU_SYSCLK0 / 4

2h - CLK_12M_RC

3h - MCU_PLL2_HSDIV2_CLKOUT

4h - MCU_EXT_REFCLK0

5h - LFXOSC_CLKOUT

6h - CPSW_GENF0

7h - CLK_32K

1.2.4.64 CTRLMMR_MCU_TIMER1_CLKSEL Register ( Offset = 8104h) [reset = 0h]

CTRLMMR_MCU_TIMER1_CLKSEL is shown in Figure 5-292 and described in Table 5-597.

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MCU Timer1 functional clock selection control.

Table 5-596 CTRLMMR_MCU_TIMER1_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8104h

Figure 5-292 CTRLMMR_MCU_TIMER1_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-597 CTRLMMR_MCU_TIMER1_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - MCU_SYSCLK0 / 4

2h - CLK_12M_RC

3h - MCU_PLL2_HSDIV2_CLKOUT

4h - MCU_EXT_REFCLK0

5h - LFXOSC_CLKOUT

6h - CPSW_GENF0

7h - CLK_32K

1.2.4.65 CTRLMMR_MCU_TIMER2_CLKSEL Register ( Offset = 8108h) [reset = 0h]

CTRLMMR_MCU_TIMER2_CLKSEL is shown in Figure 5-293 and described in Table 5-599.

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MCU Timer2 functional clock selection control.

Table 5-598 CTRLMMR_MCU_TIMER2_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8108h

Figure 5-293 CTRLMMR_MCU_TIMER2_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-599 CTRLMMR_MCU_TIMER2_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - MCU_SYSCLK0 / 4

2h - CLK_12M_RC

3h - MCU_PLL2_HSDIV2_CLKOUT

4h - MCU_EXT_REFCLK0

5h - LFXOSC_CLKOUT

6h - CPSW_GENF0

7h - CLK_32K

1.2.4.66 CTRLMMR_MCU_TIMER3_CLKSEL Register ( Offset = 810Ch) [reset = 0h]

CTRLMMR_MCU_TIMER3_CLKSEL is shown in Figure 5-294 and described in Table 5-601.

Return to Summary Table.

MCU Timer3 functional clock selection control.

Table 5-600 CTRLMMR_MCU_TIMER3_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 810Ch

Figure 5-294 CTRLMMR_MCU_TIMER3_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-601 CTRLMMR_MCU_TIMER3_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - MCU_SYSCLK0 / 4

2h - CLK_12M_RC

3h - MCU_PLL2_HSDIV2_CLKOUT

4h - MCU_EXT_REFCLK0

5h - LFXOSC_CLKOUT

6h - CPSW_GENF0

7h - CLK_32K

1.2.4.67 CTRLMMR_MCU_TIMER4_CLKSEL Register ( Offset = 8110h) [reset = 0h]

CTRLMMR_MCU_TIMER4_CLKSEL is shown in Figure 5-295 and described in Table 5-603.

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MCU Timer4 functional clock selection control.

Table 5-602 CTRLMMR_MCU_TIMER4_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8110h

Figure 5-295 CTRLMMR_MCU_TIMER4_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-603 CTRLMMR_MCU_TIMER4_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - MCU_SYSCLK0 / 4

2h - CLK_12M_RC

3h - MCU_PLL2_HSDIV2_CLKOUT

4h - MCU_EXT_REFCLK0

5h - LFXOSC_CLKOUT

6h - CPSW_GENF0

7h - CLK_32K

1.2.4.68 CTRLMMR_MCU_TIMER5_CLKSEL Register ( Offset = 8114h) [reset = 0h]

CTRLMMR_MCU_TIMER5_CLKSEL is shown in Figure 5-296 and described in Table 5-605.

Return to Summary Table.

MCU Timer5 functional clock selection control.

Table 5-604 CTRLMMR_MCU_TIMER5_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8114h

Figure 5-296 CTRLMMR_MCU_TIMER5_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-605 CTRLMMR_MCU_TIMER5_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - MCU_SYSCLK0 / 4

2h - CLK_12M_RC

3h - MCU_PLL2_HSDIV2_CLKOUT

4h - MCU_EXT_REFCLK0

5h - LFXOSC_CLKOUT

6h - CPSW_GENF0

7h - CLK_32K

1.2.4.69 CTRLMMR_MCU_TIMER6_CLKSEL Register ( Offset = 8118h) [reset = 0h]

CTRLMMR_MCU_TIMER6_CLKSEL is shown in Figure 5-297 and described in Table 5-607.

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MCU Timer6 functional clock selection control.

Table 5-606 CTRLMMR_MCU_TIMER6_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8118h

Figure 5-297 CTRLMMR_MCU_TIMER6_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-607 CTRLMMR_MCU_TIMER6_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - MCU_SYSCLK0 / 4

2h - CLK_12M_RC

3h - MCU_PLL2_HSDIV2_CLKOUT

4h - MCU_EXT_REFCLK0

5h - LFXOSC_CLKOUT

6h - CPSW_GENF0

7h - CLK_32K

1.2.4.70 CTRLMMR_MCU_TIMER7_CLKSEL Register ( Offset = 811Ch) [reset = 0h]

CTRLMMR_MCU_TIMER7_CLKSEL is shown in Figure 5-298 and described in Table 5-609.

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MCU Timer7 functional clock selection control.

Table 5-608 CTRLMMR_MCU_TIMER7_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 811Ch

Figure 5-298 CTRLMMR_MCU_TIMER7_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-609 CTRLMMR_MCU_TIMER7_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - MCU_SYSCLK0 / 4

2h - CLK_12M_RC

3h - MCU_PLL2_HSDIV2_CLKOUT

4h - MCU_EXT_REFCLK0

5h - LFXOSC_CLKOUT

6h - CPSW_GENF0

7h - CLK_32K

1.2.4.71 CTRLMMR_MCU_TIMER8_CLKSEL Register ( Offset = 8120h) [reset = 0h]

CTRLMMR_MCU_TIMER8_CLKSEL is shown in Figure 5-299 and described in Table 5-611.

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MCU Timer8 functional clock selection control.

Table 5-610 CTRLMMR_MCU_TIMER8_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8120h

Figure 5-299 CTRLMMR_MCU_TIMER8_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-611 CTRLMMR_MCU_TIMER8_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - MCU_SYSCLK0 / 4

2h - CLK_12M_RC

3h - MCU_PLL2_HSDIV2_CLKOUT

4h - MCU_EXT_REFCLK0

5h - LFXOSC_CLKOUT

6h - CPSW_GENF0

7h - CLK_32K

1.2.4.72 CTRLMMR_MCU_TIMER9_CLKSEL Register ( Offset = 8124h) [reset = 0h]

CTRLMMR_MCU_TIMER9_CLKSEL is shown in Figure 5-300 and described in Table 5-613.

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MCU Timer9 functional clock selection control.

Table 5-612 CTRLMMR_MCU_TIMER9_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8124h

Figure 5-300 CTRLMMR_MCU_TIMER9_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-613 CTRLMMR_MCU_TIMER9_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - MCU_SYSCLK0 / 4

2h - CLK_12M_RC

3h - MCU_PLL2_HSDIV2_CLKOUT

4h - MCU_EXT_REFCLK0

5h - LFXOSC_CLKOUT

6h - CPSW_GENF0

7h - CLK_32K

1.2.4.73 CTRLMMR_MCU_RTI0_CLKSEL Register ( Offset = 8180h) [reset = 0h]

CTRLMMR_MCU_RTI0_CLKSEL is shown in Figure 5-301 and described in Table 5-615.

Return to Summary Table.

MCU RTI0 functional clock selection control.

Table 5-614 CTRLMMR_MCU_RTI0_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8180h

Figure 5-301 CTRLMMR_MCU_RTI0_CLKSEL Register

31	30	29	28	27	26	25	24
WRTLOCK	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-615 CTRLMMR_MCU_RTI0_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31

WRTLOCK

R/W

0h

When set, locks further writes to CTRLMMR_MCU_RTI0_CLKSEL until the next module reset

30-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

RTI functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - LFXOSC_CLKOUT

2h - CLK_12M_RC

3h - CLK_32K

1.2.4.74 CTRLMMR_MCU_RTI1_CLKSEL Register ( Offset = 8184h) [reset = 0h]

CTRLMMR_MCU_RTI1_CLKSEL is shown in Figure 5-302 and described in Table 5-617.

Return to Summary Table.

MCU RTI1 functional clock selection control.

Table 5-616 CTRLMMR_MCU_RTI1_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 8184h

Figure 5-302 CTRLMMR_MCU_RTI1_CLKSEL Register

31	30	29	28	27	26	25	24
WRTLOCK	RESERVED
R/W-0h	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED					CLK_SEL
R-0h					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-617 CTRLMMR_MCU_RTI1_CLKSEL Register Field Descriptions

Bit

Field

Type

Reset

Description

31

WRTLOCK

R/W

0h

When set, locks further writes to CTRLMMR_MCU_RTI1_CLKSEL until the next module reset

30-3

RESERVED

R

0h

Reserved

2-0

CLK_SEL

R/W

0h

RTI functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - LFXOSC_CLKOUT

2h - CLK_12M_RC

3h - CLK_32K

1.2.4.75 CTRLMMR_MCU_USART_CLKSEL Register ( Offset = 81C0h) [reset = 0h]

CTRLMMR_MCU_USART_CLKSEL is shown in Figure 5-303 and described in Table 5-619.

Return to Summary Table.

Controls the functional clock source for MCU_USART0.

Table 5-618 CTRLMMR_MCU_USART_CLKSEL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 81C0h

Figure 5-303 CTRLMMR_MCU_USART_CLKSEL Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							CLK_SEL
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-619 CTRLMMR_MCU_USART_CLKSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	0h	Reserved
0	CLK_SEL	R/W	0h	MCU_USART0 FCLK selection 0h - MCU_PLL1_HSDIV3_CLKOUT 1h - MAIN_PLL1_HSDIV5_CLKOUT

1.2.4.76 CTRLMMR_MCU_LOCK2_KICK0 Register ( Offset = 9008h) [reset = 0h]

CTRLMMR_MCU_LOCK2_KICK0 is shown in Figure 5-304 and described in Table 5-621.

Return to Summary Table.

Lower 32-bits of Partition2 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_MCU_LOCK2_KICK1 with its key value before write-protected Partition 2 registers can be written.

Table 5-620 CTRLMMR_MCU_LOCK2_KICK0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 9008h

Figure 5-304 CTRLMMR_MCU_LOCK2_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-621 CTRLMMR_MCU_LOCK2_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.2.4.77 CTRLMMR_MCU_LOCK2_KICK1 Register ( Offset = 900Ch) [reset = 0h]

CTRLMMR_MCU_LOCK2_KICK1 is shown in Figure 5-305 and described in Table 5-623.

Return to Summary Table.

Upper 32-bits of Partition 2 write lock key. This register must be written with the designated key value after a write to CTRLMMR_MCU_LOCK2_KICK0 with its key value before write-protected Partition 2 registers can be written.

Table 5-622 CTRLMMR_MCU_LOCK2_KICK1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 900Ch

Figure 5-305 CTRLMMR_MCU_LOCK2_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-623 CTRLMMR_MCU_LOCK2_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers

1.2.4.78 CTRLMMR_MCU_LBIST_CTRL Register ( Offset = C000h) [reset = X]

CTRLMMR_MCU_LBIST_CTRL is shown in Figure 5-306 and described in Table 5-625.

Return to Summary Table.

Configures and enables LBIST operation.

Table 5-624 CTRLMMR_MCU_LBIST_CTRL Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 C000h

Figure 5-306 CTRLMMR_MCU_LBIST_CTRL Register

31	30	29	28	27	26	25	24
BIST_RESET	RESERVED			BIST_RUN
R/W-X	R-0h			R/W-X

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RUNBIST_MODE				RESERVED		DC_DEF
R/W-X				R-0h		R/W-X

7	6	5	4	3	2	1	0
LOAD_DIV	RESERVED		DIVIDE_RATIO
R/W-X	R-0h		R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-625 CTRLMMR_MCU_LBIST_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BIST_RESET	R/W	X	Reset LBIST macro
30-28	RESERVED	R	0h	Reserved
27-24	BIST_RUN	R/W	X	Starts LBIST if all bits are 1
23-16	RESERVED	R	0h	Reserved
15-12	RUNBIST_MODE	R/W	X	Runbist mode enable if all bits are 1
11-10	RESERVED	R	0h	Reserved
9-8	DC_DEF	R/W	X	Clock delay after scan_enable switching
7	LOAD_DIV	R/W	X	Loads LBIST clock divide ratio on transition from 0 to 1
6-5	RESERVED	R	0h	Reserved
4-0	DIVIDE_RATIO	R/W	X	LBIST clock divide ratio

1.2.4.79 CTRLMMR_MCU_LBIST_PATCOUNT Register ( Offset = C004h) [reset = X]

CTRLMMR_MCU_LBIST_PATCOUNT is shown in Figure 5-307 and described in Table 5-627.

Return to Summary Table.

Specifies the number of LBIST patterns to run.

Table 5-626 CTRLMMR_MCU_LBIST_PATCOUNT Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 C004h

Figure 5-307 CTRLMMR_MCU_LBIST_PATCOUNT Register

31	30	29	28	27	26	25	24
RESERVED		STATIC_PC_DEF
R-0h		R/W-X

23	22	21	20	19	18	17	16
STATIC_PC_DEF
R/W-X

15	14	13	12	11	10	9	8
RESERVED				SET_PC_DEF
R-0h				R/W-X

7	6	5	4	3	2	1	0
RESET_PC_DEF				SCAN_PC_DEF
R/W-X				R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-627 CTRLMMR_MCU_LBIST_PATCOUNT Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	0h	Reserved
29-16	STATIC_PC_DEF	R/W	X	Number of stuck-at patterns to run
15-12	RESERVED	R	0h	Reserved
11-8	SET_PC_DEF	R/W	X	Number of set patterns to run
7-4	RESET_PC_DEF	R/W	X	Number of reset patterns to run
3-0	SCAN_PC_DEF	R/W	X	Number of chain test patterns to run

1.2.4.80 CTRLMMR_MCU_LBIST_SEED0 Register ( Offset = C008h) [reset = X]

CTRLMMR_MCU_LBIST_SEED0 is shown in Figure 5-308 and described in Table 5-629.

Return to Summary Table.

Specifies the 32 LSBs of the PRPG seed.

Table 5-628 CTRLMMR_MCU_LBIST_SEED0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 C008h

Figure 5-308 CTRLMMR_MCU_LBIST_SEED0 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRPG_DEF
R/W-X

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-629 CTRLMMR_MCU_LBIST_SEED0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PRPG_DEF	R/W	X	Initial seed for PRPG (bits 31:0)

1.2.4.81 CTRLMMR_MCU_LBIST_SEED1 Register ( Offset = C00Ch) [reset = X]

CTRLMMR_MCU_LBIST_SEED1 is shown in Figure 5-309 and described in Table 5-631.

Return to Summary Table.

Specifies the 21 MSBs of the PRPG seed.

Table 5-630 CTRLMMR_MCU_LBIST_SEED1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 C00Ch

Figure 5-309 CTRLMMR_MCU_LBIST_SEED1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											PRPG_DEF
R-0h											R/W-X

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-631 CTRLMMR_MCU_LBIST_SEED1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-21	RESERVED	R	0h	Reserved
20-0	PRPG_DEF	R/W	X	Initial seed for PRPG (bits 52:32)

1.2.4.82 CTRLMMR_MCU_LBIST_SPARE0 Register ( Offset = C010h) [reset = 0h]

CTRLMMR_MCU_LBIST_SPARE0 is shown in Figure 5-310 and described in Table 5-633.

Return to Summary Table.

Spare LBIST control bits.

Table 5-632 CTRLMMR_MCU_LBIST_SPARE0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 C010h

Figure 5-310 CTRLMMR_MCU_LBIST_SPARE0 Register

31	30	29	28	27	26	25	24
SPARE0
R/W-0h

23	22	21	20	19	18	17	16
SPARE0
R/W-0h

15	14	13	12	11	10	9	8
SPARE0
R/W-0h

7	6	5	4	3	2	1	0
SPARE0						PBIST_SELFTEST_EN	LBIST_SELFTEST_EN
R/W-0h						R/W-0h	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-633 CTRLMMR_MCU_LBIST_SPARE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	SPARE0	R/W	0h	LBIST spare bits
1	PBIST_SELFTEST_EN	R/W	0h	PBIST isolation control
0	LBIST_SELFTEST_EN	R/W	0h	LBIST isolation control

1.2.4.83 CTRLMMR_MCU_LBIST_SPARE1 Register ( Offset = C014h) [reset = 0h]

CTRLMMR_MCU_LBIST_SPARE1 is shown in Figure 5-311 and described in Table 5-635.

Return to Summary Table.

Spare LBIST control bits.

Table 5-634 CTRLMMR_MCU_LBIST_SPARE1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 C014h

Figure 5-311 CTRLMMR_MCU_LBIST_SPARE1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SPARE1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-635 CTRLMMR_MCU_LBIST_SPARE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	SPARE1	R/W	0h	LBIST spare bits

1.2.4.84 CTRLMMR_MCU_LBIST_STAT Register ( Offset = C018h) [reset = X]

CTRLMMR_MCU_LBIST_STAT is shown in Figure 5-312 and described in Table 5-637.

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Indicates LBIST status and provides MISR selection control.

Table 5-636 CTRLMMR_MCU_LBIST_STAT Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 C018h

Figure 5-312 CTRLMMR_MCU_LBIST_STAT Register

31	30	29	28	27	26	25	24
BIST_DONE	RESERVED
R-X	R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
BIST_RUNNING	RESERVED					OUT_MUX_CTL
R-X	R-0h					R/W-0h

7	6	5	4	3	2	1	0
MISR_MUX_CTL
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-637 CTRLMMR_MCU_LBIST_STAT Register Field Descriptions

Bit	Field	Type	Reset	Description
31	BIST_DONE	R	X	LBIST is done
30-16	RESERVED	R	0h	Reserved
15	BIST_RUNNING	R	X	LBIST is running
14-10	RESERVED	R	0h	Reserved
9-8	OUT_MUX_CTL	R/W	0h	Selects source of LBIST output 0h - LBIST IP CTRLMMR_MCU_PID value 1h - LBIST CTRL ID value 2h or 3h - MISR value
7-0	MISR_MUX_CTL	R/W	0h	Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR.

1.2.4.85 CTRLMMR_MCU_LBIST_MISR Register ( Offset = C01Ch) [reset = X]

CTRLMMR_MCU_LBIST_MISR is shown in Figure 5-313 and described in Table 5-639.

Return to Summary Table.

Contains LBIST MISR output value.

Table 5-638 CTRLMMR_MCU_LBIST_MISR Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 C01Ch

Figure 5-313 CTRLMMR_MCU_LBIST_MISR Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISR_RESULT
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-639 CTRLMMR_MCU_LBIST_MISR Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MISR_RESULT	R	X	32-bits of MISR value selected by misr_mux_ctl

1.2.4.86 CTRLMMR_MCU_LBIST_SIG Register ( Offset = C280h) [reset = X]

CTRLMMR_MCU_LBIST_SIG is shown in Figure 5-314 and described in Table 5-641.

Return to Summary Table.

Contains expected MISR output value.

Table 5-640 CTRLMMR_MCU_LBIST_SIG Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 C280h

Figure 5-314 CTRLMMR_MCU_LBIST_SIG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISR_SIG
R-X

LEGEND: R = Read Only; -n = value after reset

Table 5-641 CTRLMMR_MCU_LBIST_SIG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MISR_SIG	R	X	MISR signature

1.2.4.87 CTRLMMR_MCU_LOCK3_KICK0 Register ( Offset = D008h) [reset = 0h]

CTRLMMR_MCU_LOCK3_KICK0 is shown in Figure 5-315 and described in Table 5-643.

Return to Summary Table.

Lower 32-bits of Partition3 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_MCU_LOCK3_KICK1 with its key value before write-protected Partition 3 registers can be written.

Table 5-642 CTRLMMR_MCU_LOCK3_KICK0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 D008h

Figure 5-315 CTRLMMR_MCU_LOCK3_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-643 CTRLMMR_MCU_LOCK3_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.2.4.88 CTRLMMR_MCU_LOCK3_KICK1 Register ( Offset = D00Ch) [reset = 0h]

CTRLMMR_MCU_LOCK3_KICK1 is shown in Figure 5-316 and described in Table 5-645.

Return to Summary Table.

Upper 32-bits of Partition 3 write lock key. This register must be written with the designated key value after a write to CTRLMMR_MCU_LOCK3_KICK0 with its key value before write-protected Partition 3 registers can be written.

Table 5-644 CTRLMMR_MCU_LOCK3_KICK1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F0 D00Ch

Figure 5-316 CTRLMMR_MCU_LOCK3_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-645 CTRLMMR_MCU_LOCK3_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers

1.2.4.89 CTRLMMR_MCU_LOCK4_KICK0 Register ( Offset = 11008h) [reset = 0h]

CTRLMMR_MCU_LOCK4_KICK0 is shown in Figure 5-317 and described in Table 5-647.

Return to Summary Table.

Lower 32-bits of Partition4 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_MCU_LOCK4_KICK1 with its key value before write-protected Partition 4 registers can be written.

Table 5-646 CTRLMMR_MCU_LOCK4_KICK0 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F1 1008h

Figure 5-317 CTRLMMR_MCU_LOCK4_KICK0 Register

31	30	29	28	27	26	25	24
KEY
R/W-0h

23	22	21	20	19	18	17	16
KEY
R/W-0h

15	14	13	12	11	10	9	8
KEY
R/W-0h

7	6	5	4	3	2	1	0
KEY							UNLOCKED
R/W-0h							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 5-647 CTRLMMR_MCU_LOCK4_KICK0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	KEY	R/W	0h	Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition4 registers
0	UNLOCKED	R	0h	Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.2.4.90 CTRLMMR_MCU_LOCK4_KICK1 Register ( Offset = 1100Ch) [reset = 0h]

CTRLMMR_MCU_LOCK4_KICK1 is shown in Figure 5-318 and described in Table 5-649.

Return to Summary Table.

Upper 32-bits of Partition 4 write lock key. This register must be written with the designated key value after a write to CTRLMMR_MCU_LOCK4_KICK0 with its key value before write-protected Partition 4 registers can be written.

Table 5-648 CTRLMMR_MCU_LOCK4_KICK1 Instances

Instance	Physical Address
MCU_CTRL_MMR0_CFG0	40F1 100Ch

Figure 5-318 CTRLMMR_MCU_LOCK4_KICK1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 5-649 CTRLMMR_MCU_LOCK4_KICK1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	KEY	R/W	0h	Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition4 registers

5.1.2.4 MCU_CTRL_MMR0 Registers

1.2.4.1 CTRLMMR_MCU_PID Register ( Offset = 0h) [reset = 61800000h]

1.2.4.2 CTRLMMR_MCU_MMR_CFG1 Register ( Offset = 8h) [reset = 8000001Fh]

1.2.4.3 CTRLMMR_MCU_IPC_SET0 Register ( Offset = 100h) [reset = 0h]

1.2.4.4 CTRLMMR_MCU_IPC_SET1 Register ( Offset = 104h) [reset = 0h]

1.2.4.5 CTRLMMR_MCU_IPC_SET8 Register ( Offset = 120h) [reset = 0h]

1.2.4.6 CTRLMMR_MCU_IPC_CLR0 Register ( Offset = 180h) [reset = 0h]

1.2.4.7 CTRLMMR_MCU_IPC_CLR1 Register ( Offset = 184h) [reset = 0h]

1.2.4.8 CTRLMMR_MCU_IPC_CLR8 Register ( Offset = 1A0h) [reset = 0h]

1.2.4.9 CTRLMMR_MCU_MAC_ID0 Register ( Offset = 200h) [reset = X]

1.2.4.10 CTRLMMR_MCU_MAC_ID1 Register ( Offset = 204h) [reset = X]

1.2.4.11 CTRLMMR_MCU_LOCK0_KICK0 Register ( Offset = 1008h) [reset = 0h]

1.2.4.12 CTRLMMR_MCU_LOCK0_KICK1 Register ( Offset = 100Ch) [reset = 0h]

1.2.4.13 CTRLMMR_MCU_INTR_RAW_STAT Register ( Offset = 1010h) [reset = 0h]

1.2.4.14 CTRLMMR_MCU_INTR_STAT_CLR Register ( Offset = 1014h) [reset = 0h]

1.2.4.15 CTRLMMR_MCU_INTR_EN_SET Register ( Offset = 1018h) [reset = 0h]

1.2.4.16 CTRLMMR_MCU_INTR_EN_CLR Register ( Offset = 101Ch) [reset = 0h]

1.2.4.17 CTRLMMR_MCU_EOI Register ( Offset = 1020h) [reset = 0h]

1.2.4.18 CTRLMMR_MCU_FAULT_ADDR Register ( Offset = 1024h) [reset = 0h]

1.2.4.19 CTRLMMR_MCU_FAULT_TYPE Register ( Offset = 1028h) [reset = 0h]

1.2.4.20 CTRLMMR_MCU_FAULT_ATTR Register ( Offset = 102Ch) [reset = 0h]

1.2.4.21 CTRLMMR_MCU_FAULT_CLR Register ( Offset = 1030h) [reset = 0h]

1.2.4.22 CTRLMMR_MCU_MSMC_CFG Register ( Offset = 4030h) [reset = 400h]

1.2.4.23 CTRLMMR_MCU_ENET_CTRL Register ( Offset = 4040h) [reset = 1h]

1.2.4.24 CTRLMMR_MCU_SPI1_CTRL Register ( Offset = 4060h) [reset = 0h]

1.2.4.25 CTRLMMR_MCU_I3C0_CTRL0 Register ( Offset = 4070h) [reset = 1020000h]

1.2.4.26 CTRLMMR_MCU_I3C0_CTRL1 Register ( Offset = 4074h) [reset = 0h]

1.2.4.27 CTRLMMR_MCU_I2C0_CTRL Register ( Offset = 4080h) [reset = 0h]

1.2.4.28 CTRLMMR_MCU_I2C1_CTRL Register ( Offset = 4084h) [reset = 0h]

1.2.4.29 CTRLMMR_MCU_FSS_CTRL Register ( Offset = 40A0h) [reset = 0h]

1.2.4.30 CTRLMMR_MCU_ADC0_CTRL Register ( Offset = 40B0h) [reset = 0h]

1.2.4.31 CTRLMMR_MCU_ADC0_TRIM Register ( Offset = 40C0h) [reset = X]

1.2.4.32 CTRLMMR_MCU_TIMER0_CTRL Register ( Offset = 4200h) [reset = 0h]

1.2.4.33 CTRLMMR_MCU_TIMER1_CTRL Register ( Offset = 4204h) [reset = 0h]

1.2.4.34 CTRLMMR_MCU_TIMER2_CTRL Register ( Offset = 4208h) [reset = 0h]

1.2.4.35 CTRLMMR_MCU_TIMER3_CTRL Register ( Offset = 420Ch) [reset = 0h]

1.2.4.36 CTRLMMR_MCU_TIMER4_CTRL Register ( Offset = 4210h) [reset = 0h]

1.2.4.37 CTRLMMR_MCU_TIMER5_CTRL Register ( Offset = 4214h) [reset = 0h]

1.2.4.38 CTRLMMR_MCU_TIMER6_CTRL Register ( Offset = 4218h) [reset = 0h]

1.2.4.39 CTRLMMR_MCU_TIMER7_CTRL Register ( Offset = 421Ch) [reset = 0h]

1.2.4.40 CTRLMMR_MCU_TIMER8_CTRL Register ( Offset = 4220h) [reset = 0h]

1.2.4.41 CTRLMMR_MCU_TIMER9_CTRL Register ( Offset = 4224h) [reset = 0h]

1.2.4.42 CTRLMMR_MCU_TIMERIO0_CTRL Register ( Offset = 4280h) [reset = Fh]

1.2.4.43 CTRLMMR_MCU_TIMERIO1_CTRL Register ( Offset = 4284h) [reset = Fh]

1.2.4.44 CTRLMMR_MCU_TIMERIO2_CTRL Register ( Offset = 4288h) [reset = Fh]

1.2.4.45 CTRLMMR_MCU_TIMERIO3_CTRL Register ( Offset = 428Ch) [reset = Fh]

1.2.4.46 CTRLMMR_MCU_TIMERIO4_CTRL Register ( Offset = 4290h) [reset = Fh]

1.2.4.47 CTRLMMR_MCU_TIMERIO5_CTRL Register ( Offset = 4294h) [reset = Fh]

1.2.4.48 CTRLMMR_MCU_TIMERIO6_CTRL Register ( Offset = 4298h) [reset = Fh]

1.2.4.49 CTRLMMR_MCU_TIMERIO7_CTRL Register ( Offset = 429Ch) [reset = Fh]

1.2.4.50 CTRLMMR_MCU_TIMERIO8_CTRL Register ( Offset = 42A0h) [reset = Fh]

1.2.4.51 CTRLMMR_MCU_TIMERIO9_CTRL Register ( Offset = 42A4h) [reset = Fh]

1.2.4.52 CTRLMMR_MCU_MTOG0_CTRL Register ( Offset = 4300h) [reset = X]

1.2.4.53 CTRLMMR_MCU_LOCK1_KICK0 Register ( Offset = 5008h) [reset = 0h]

1.2.4.54 CTRLMMR_MCU_LOCK1_KICK1 Register ( Offset = 500Ch) [reset = 0h]

1.2.4.55 CTRLMMR_MCU_CLKOUT0_CTRL Register ( Offset = 8010h) [reset = 0h]

1.2.4.56 CTRLMMR_MCU_EFUSE_CLKSEL Register ( Offset = 8018h) [reset = 0h]

1.2.4.57 CTRLMMR_MCU_MCAN0_CLKSEL Register ( Offset = 8020h) [reset = 0h]

1.2.4.58 CTRLMMR_MCU_MCAN1_CLKSEL Register ( Offset = 8024h) [reset = 0h]

1.2.4.59 CTRLMMR_MCU_OSPI0_CLKSEL Register ( Offset = 8030h) [reset = 0h]

1.2.4.60 CTRLMMR_MCU_ADC0_CLKSEL Register ( Offset = 8040h) [reset = 0h]

1.2.4.61 CTRLMMR_MCU_ENET_CLKSEL Register ( Offset = 8050h) [reset = F00h]

1.2.4.62 CTRLMMR_MCU_R5_CORE0_CLKSEL Register ( Offset = 8080h) [reset = 0h]

1.2.4.63 CTRLMMR_MCU_TIMER0_CLKSEL Register ( Offset = 8100h) [reset = 0h]

1.2.4.64 CTRLMMR_MCU_TIMER1_CLKSEL Register ( Offset = 8104h) [reset = 0h]

1.2.4.65 CTRLMMR_MCU_TIMER2_CLKSEL Register ( Offset = 8108h) [reset = 0h]

1.2.4.66 CTRLMMR_MCU_TIMER3_CLKSEL Register ( Offset = 810Ch) [reset = 0h]

1.2.4.67 CTRLMMR_MCU_TIMER4_CLKSEL Register ( Offset = 8110h) [reset = 0h]

1.2.4.68 CTRLMMR_MCU_TIMER5_CLKSEL Register ( Offset = 8114h) [reset = 0h]

1.2.4.69 CTRLMMR_MCU_TIMER6_CLKSEL Register ( Offset = 8118h) [reset = 0h]

1.2.4.70 CTRLMMR_MCU_TIMER7_CLKSEL Register ( Offset = 811Ch) [reset = 0h]

1.2.4.71 CTRLMMR_MCU_TIMER8_CLKSEL Register ( Offset = 8120h) [reset = 0h]

1.2.4.72 CTRLMMR_MCU_TIMER9_CLKSEL Register ( Offset = 8124h) [reset = 0h]

1.2.4.73 CTRLMMR_MCU_RTI0_CLKSEL Register ( Offset = 8180h) [reset = 0h]

1.2.4.74 CTRLMMR_MCU_RTI1_CLKSEL Register ( Offset = 8184h) [reset = 0h]

1.2.4.75 CTRLMMR_MCU_USART_CLKSEL Register ( Offset = 81C0h) [reset = 0h]

1.2.4.76 CTRLMMR_MCU_LOCK2_KICK0 Register ( Offset = 9008h) [reset = 0h]

1.2.4.77 CTRLMMR_MCU_LOCK2_KICK1 Register ( Offset = 900Ch) [reset = 0h]

1.2.4.78 CTRLMMR_MCU_LBIST_CTRL Register ( Offset = C000h) [reset = X]

1.2.4.79 CTRLMMR_MCU_LBIST_PATCOUNT Register ( Offset = C004h) [reset = X]