SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-123 lists the memory-mapped registers for the GPIO registers. All register offset addresses not listed in Table 12-123 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
GPIO0 | 0060 0000h |
GPIO2 | 0061 0000h |
GPIO4 | 0062 0000h |
GPIO6 | 0063 0000h |
WKUP_GPIO1 | 4210 0000h |
WKUP_GPIO0 | 4211 0000h |
Offset | Acronym | Register Name | GPIO0 Physical Address | GPIO2 Physical Address |
---|---|---|---|---|
0h | GPIO_PID | 0060 0000h | 0061 0000h | |
4h | GPIO_PCR | 0060 0004h | 0061 0004h | |
8h | GPIO_BINTEN | 0060 0008h | 0061 0008h | |
10h | GPIO_DIR01 | 0060 0010h | 0061 0010h | |
14h | GPIO_OUT_DATA01 | 0060 0014h | 0061 0014h | |
18h | GPIO_SET_DATA01 | 0060 0018h | 0061 0018h | |
1Ch | GPIO_CLR_DATA01 | 0060 001Ch | 0061 001Ch | |
20h | GPIO_IN_DATA01 | 0060 0020h | 0061 0020h | |
24h | GPIO_SET_RIS_TRIG01 | 0060 0024h | 0061 0024h | |
28h | GPIO_CLR_RIS_TRIG01 | 0060 0028h | 0061 0028h | |
2Ch | GPIO_SET_FAL_TRIG01 | 0060 002Ch | 0061 002Ch | |
30h | GPIO_CLR_FAL_TRIG01 | 0060 0030h | 0061 0030h | |
34h | GPIO_INTSTAT01 | 0060 0034h | 0061 0034h | |
38h | GPIO_DIR23 | 0060 0038h | 0061 0038h | |
3Ch | GPIO_OUT_DATA23 | 0060 003Ch | 0061 003Ch | |
40h | GPIO_SET_DATA23 | 0060 0040h | 0061 0040h | |
44h | GPIO_CLR_DATA23 | 0060 0044h | 0061 0044h | |
48h | GPIO_IN_DATA23 | 0060 0048h | 0061 0048h | |
4Ch | GPIO_SET_RIS_TRIG23 | 0060 004Ch | 0061 004Ch | |
50h | GPIO_CLR_RIS_TRIG23 | 0060 0050h | 0061 0050h | |
54h | GPIO_SET_FAL_TRIG23 | 0060 0054h | 0061 0054h | |
58h | GPIO_CLR_FAL_TRIG23 | 0060 0058h | 0061 0058h | |
5Ch | GPIO_INTSTAT23 | 0060 005Ch | 0061 005Ch | |
60h | GPIO_DIR45 | 0060 0060h | 0061 0060h | |
64h | GPIO_OUT_DATA45 | 0060 0064h | 0061 0064h | |
68h | GPIO_SET_DATA45 | 0060 0068h | 0061 0068h | |
6Ch | GPIO_CLR_DATA45 | 0060 006Ch | 0061 006Ch | |
70h | GPIO_IN_DATA45 | 0060 0070h | 0061 0070h | |
74h | GPIO_SET_RIS_TRIG45 | 0060 0074h | 0061 0074h | |
78h | GPIO_CLR_RIS_TRIG45 | 0060 0078h | 0061 0078h | |
7Ch | GPIO_SET_FAL_TRIG45 | 0060 007Ch | 0061 007Ch | |
80h | GPIO_CLR_FAL_TRIG45 | 0060 0080h | 0061 0080h | |
84h | GPIO_INTSTAT45 | 0060 0084h | 0061 0084h | |
88h | GPIO_DIR67 | 0060 0088h | 0061 0088h | |
8Ch | GPIO_OUT_DATA67 | 0060 008Ch | 0061 008Ch | |
90h | GPIO_SET_DATA67 | 0060 0090h | 0061 0090h | |
94h | GPIO_CLR_DATA67 | 0060 0094h | 0061 0094h | |
98h | GPIO_IN_DATA67 | 0060 0098h | 0061 0098h | |
9Ch | GPIO_SET_RIS_TRIG67 | 0060 009Ch | 0061 009Ch | |
A0h | GPIO_CLR_RIS_TRIG67 | 0060 00A0h | 0061 00A0h | |
A4h | GPIO_SET_FAL_TRIG67 | 0060 00A4h | 0061 00A4h | |
A8h | GPIO_CLR_FAL_TRIG67 | 0060 00A8h | 0061 00A8h | |
ACh | GPIO_INTSTAT67 | 0060 00ACh | 0061 00ACh | |
B0h | GPIO_DIR8 | 0060 00B0h | 0061 00B0h | |
B4h | GPIO_OUT_DATA8 | 0060 00B4h | 0061 00B4h | |
B8h | GPIO_SET_DATA8 | 0060 00B8h | 0061 00B8h | |
BCh | GPIO_CLR_DATA8 | 0060 00BCh | 0061 00BCh | |
C0h | GPIO_IN_DATA8 | 0060 00C0h | 0061 00C0h | |
C4h | GPIO_SET_RIS_TRIG8 | 0060 00C4h | 0061 00C4h | |
C8h | GPIO_CLR_RIS_TRIG8 | 0060 00C8h | 0061 00C8h | |
CCh | GPIO_SET_FAL_TRIG8 | 0060 00CCh | 0061 00CCh | |
D0h | GPIO_CLR_FAL_TRIG8 | 0060 00D0h | 0061 00D0h | |
D4h | GPIO_INTSTAT8 | 0060 00D4h | 0061 00D4h |
Offset | Acronym | Register Name | GPIO4 Physical Address | GPIO6 Physical Address |
---|---|---|---|---|
0h | GPIO_PID | 0062 0000h | 0063 0000h | |
4h | GPIO_PCR | 0062 0004h | 0063 0004h | |
8h | GPIO_BINTEN | 0062 0008h | 0063 0008h | |
10h | GPIO_DIR01 | 0062 0010h | 0063 0010h | |
14h | GPIO_OUT_DATA01 | 0062 0014h | 0063 0014h | |
18h | GPIO_SET_DATA01 | 0062 0018h | 0063 0018h | |
1Ch | GPIO_CLR_DATA01 | 0062 001Ch | 0063 001Ch | |
20h | GPIO_IN_DATA01 | 0062 0020h | 0063 0020h | |
24h | GPIO_SET_RIS_TRIG01 | 0062 0024h | 0063 0024h | |
28h | GPIO_CLR_RIS_TRIG01 | 0062 0028h | 0063 0028h | |
2Ch | GPIO_SET_FAL_TRIG01 | 0062 002Ch | 0063 002Ch | |
30h | GPIO_CLR_FAL_TRIG01 | 0062 0030h | 0063 0030h | |
34h | GPIO_INTSTAT01 | 0062 0034h | 0063 0034h | |
38h | GPIO_DIR23 | 0062 0038h | 0063 0038h | |
3Ch | GPIO_OUT_DATA23 | 0062 003Ch | 0063 003Ch | |
40h | GPIO_SET_DATA23 | 0062 0040h | 0063 0040h | |
44h | GPIO_CLR_DATA23 | 0062 0044h | 0063 0044h | |
48h | GPIO_IN_DATA23 | 0062 0048h | 0063 0048h | |
4Ch | GPIO_SET_RIS_TRIG23 | 0062 004Ch | 0063 004Ch | |
50h | GPIO_CLR_RIS_TRIG23 | 0062 0050h | 0063 0050h | |
54h | GPIO_SET_FAL_TRIG23 | 0062 0054h | 0063 0054h | |
58h | GPIO_CLR_FAL_TRIG23 | 0062 0058h | 0063 0058h | |
5Ch | GPIO_INTSTAT23 | 0062 005Ch | 0063 005Ch | |
60h | GPIO_DIR45 | 0062 0060h | 0063 0060h | |
64h | GPIO_OUT_DATA45 | 0062 0064h | 0063 0064h | |
68h | GPIO_SET_DATA45 | 0062 0068h | 0063 0068h | |
6Ch | GPIO_CLR_DATA45 | 0062 006Ch | 0063 006Ch | |
70h | GPIO_IN_DATA45 | 0062 0070h | 0063 0070h | |
74h | GPIO_SET_RIS_TRIG45 | 0062 0074h | 0063 0074h | |
78h | GPIO_CLR_RIS_TRIG45 | 0062 0078h | 0063 0078h | |
7Ch | GPIO_SET_FAL_TRIG45 | 0062 007Ch | 0063 007Ch | |
80h | GPIO_CLR_FAL_TRIG45 | 0062 0080h | 0063 0080h | |
84h | GPIO_INTSTAT45 | 0062 0084h | 0063 0084h | |
88h | GPIO_DIR67 | 0062 0088h | 0063 0088h | |
8Ch | GPIO_OUT_DATA67 | 0062 008Ch | 0063 008Ch | |
90h | GPIO_SET_DATA67 | 0062 0090h | 0063 0090h | |
94h | GPIO_CLR_DATA67 | 0062 0094h | 0063 0094h | |
98h | GPIO_IN_DATA67 | 0062 0098h | 0063 0098h | |
9Ch | GPIO_SET_RIS_TRIG67 | 0062 009Ch | 0063 009Ch | |
A0h | GPIO_CLR_RIS_TRIG67 | 0062 00A0h | 0063 00A0h | |
A4h | GPIO_SET_FAL_TRIG67 | 0062 00A4h | 0063 00A4h | |
A8h | GPIO_CLR_FAL_TRIG67 | 0062 00A8h | 0063 00A8h | |
ACh | GPIO_INTSTAT67 | 0062 00ACh | 0063 00ACh | |
B0h | GPIO_DIR8 | 0062 00B0h | 0063 00B0h | |
B4h | GPIO_OUT_DATA8 | 0062 00B4h | 0063 00B4h | |
B8h | GPIO_SET_DATA8 | 0062 00B8h | 0063 00B8h | |
BCh | GPIO_CLR_DATA8 | 0062 00BCh | 0063 00BCh | |
C0h | GPIO_IN_DATA8 | 0062 00C0h | 0063 00C0h | |
C4h | GPIO_SET_RIS_TRIG8 | 0062 00C4h | 0063 00C4h | |
C8h | GPIO_CLR_RIS_TRIG8 | 0062 00C8h | 0063 00C8h | |
CCh | GPIO_SET_FAL_TRIG8 | 0062 00CCh | 0063 00CCh | |
D0h | GPIO_CLR_FAL_TRIG8 | 0062 00D0h | 0063 00D0h | |
D4h | GPIO_INTSTAT8 | 0062 00D4h | 0063 00D4h |
Offset | Acronym | Register Name | WKUP_GPIO0 Physical Address | WKUP_GPIO1 Physical Address |
---|---|---|---|---|
0h | GPIO_PID | 4211 0000h | 4210 0000h | |
4h | GPIO_PCR | 4211 0004h | 4210 0004h | |
8h | GPIO_BINTEN | 4211 0008h | 4210 0008h | |
10h | GPIO_DIR01 | 4211 0010h | 4210 0010h | |
14h | GPIO_OUT_DATA01 | 4211 0014h | 4210 0014h | |
18h | GPIO_SET_DATA01 | 4211 0018h | 4210 0018h | |
1Ch | GPIO_CLR_DATA01 | 4211 001Ch | 4210 001Ch | |
20h | GPIO_IN_DATA01 | 4211 0020h | 4210 0020h | |
24h | GPIO_SET_RIS_TRIG01 | 4211 0024h | 4210 0024h | |
28h | GPIO_CLR_RIS_TRIG01 | 4211 0028h | 4210 0028h | |
2Ch | GPIO_SET_FAL_TRIG01 | 4211 002Ch | 4210 002Ch | |
30h | GPIO_CLR_FAL_TRIG01 | 4211 0030h | 4210 0030h | |
34h | GPIO_INTSTAT01 | 4211 0034h | 4210 0034h | |
38h | GPIO_DIR23 | 4211 0038h | 4210 0038h | |
3Ch | GPIO_OUT_DATA23 | 4211 003Ch | 4210 003Ch | |
40h | GPIO_SET_DATA23 | 4211 0040h | 4210 0040h | |
44h | GPIO_CLR_DATA23 | 4211 0044h | 4210 0044h | |
48h | GPIO_IN_DATA23 | 4211 0048h | 4210 0048h | |
4Ch | GPIO_SET_RIS_TRIG23 | 4211 004Ch | 4210 004Ch | |
50h | GPIO_CLR_RIS_TRIG23 | 4211 0050h | 4210 0050h | |
54h | GPIO_SET_FAL_TRIG23 | 4211 0054h | 4210 0054h | |
58h | GPIO_CLR_FAL_TRIG23 | 4211 0058h | 4210 0058h | |
5Ch | GPIO_INTSTAT23 | 4211 005Ch | 4210 005Ch | |
60h | GPIO_DIR45 | 4211 0060h | 4210 0060h | |
64h | GPIO_OUT_DATA45 | 4211 0064h | 4210 0064h | |
68h | GPIO_SET_DATA45 | 4211 0068h | 4210 0068h | |
6Ch | GPIO_CLR_DATA45 | 4211 006Ch | 4210 006Ch | |
70h | GPIO_IN_DATA45 | 4211 0070h | 4210 0070h | |
74h | GPIO_SET_RIS_TRIG45 | 4211 0074h | 4210 0074h | |
78h | GPIO_CLR_RIS_TRIG45 | 4211 0078h | 4210 0078h | |
7Ch | GPIO_SET_FAL_TRIG45 | 4211 007Ch | 4210 007Ch | |
80h | GPIO_CLR_FAL_TRIG45 | 4211 0080h | 4210 0080h | |
84h | GPIO_INTSTAT45 | 4211 0084h | 4210 0084h | |
88h | GPIO_DIR67 | 4211 0088h | 4210 0088h | |
8Ch | GPIO_OUT_DATA67 | 4211 008Ch | 4210 008Ch | |
90h | GPIO_SET_DATA67 | 4211 0090h | 4210 0090h | |
94h | GPIO_CLR_DATA67 | 4211 0094h | 4210 0094h | |
98h | GPIO_IN_DATA67 | 4211 0098h | 4210 0098h | |
9Ch | GPIO_SET_RIS_TRIG67 | 4211 009Ch | 4210 009Ch | |
A0h | GPIO_CLR_RIS_TRIG67 | 4211 00A0h | 4210 00A0h | |
A4h | GPIO_SET_FAL_TRIG67 | 4211 00A4h | 4210 00A4h | |
A8h | GPIO_CLR_FAL_TRIG67 | 4211 00A8h | 4210 00A8h | |
ACh | GPIO_INTSTAT67 | 4211 00ACh | 4210 00ACh | |
B0h | GPIO_DIR8 | 4211 00B0h | 4210 00B0h | |
B4h | GPIO_OUT_DATA8 | 4211 00B4h | 4210 00B4h | |
B8h | GPIO_SET_DATA8 | 4211 00B8h | 4210 00B8h | |
BCh | GPIO_CLR_DATA8 | 4211 00BCh | 4210 00BCh | |
C0h | GPIO_IN_DATA8 | 4211 00C0h | 4210 00C0h | |
C4h | GPIO_SET_RIS_TRIG8 | 4211 00C4h | 4210 00C4h | |
C8h | GPIO_CLR_RIS_TRIG8 | 4211 00C8h | 4210 00C8h | |
CCh | GPIO_SET_FAL_TRIG8 | 4211 00CCh | 4210 00CCh | |
D0h | GPIO_CLR_FAL_TRIG8 | 4211 00D0h | 4210 00D0h | |
D4h | GPIO_INTSTAT8 | 4211 00D4h | 4210 00D4h |
GPIO_PID is shown in Figure 12-61 and described in Table 12-127.
Return to Summary Table.
GPIO Periperal ID Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0000h |
GPIO2 | 0061 0000h |
GPIO4 | 0062 0000h |
GPIO6 | 0063 0000h |
WKUP_GPIO1 | 4210 0000h |
WKUP_GPIO0 | 4211 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SCHEME | RESERVED | FUNC | |||||
R-1h | R-0h | R-483h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FUNC | |||||||
R-483h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RTL | MAJOR | ||||||
R-5h | R-1h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM | MINOR | ||||||
R-0h | R-5h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Current scheme |
29-28 | RESERVED | R | 0h | RESERVED |
27-16 | FUNC | R | 483h | Function code assigned to TCP3 |
15-11 | RTL | R | 5h | RTL Version R code |
10-8 | MAJOR | R | 1h | Major revision X code |
7-6 | CUSTOM | R | 0h | Custom version code |
5-0 | MINOR | R | 5h | Minor revision Y code |
GPIO_PCR is shown in Figure 12-62 and described in Table 12-129.
Return to Summary Table.
Peripheral Control Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0004h |
GPIO2 | 0061 0004h |
GPIO4 | 0062 0004h |
GPIO6 | 0063 0004h |
WKUP_GPIO1 | 4210 0004h |
WKUP_GPIO0 | 4211 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT | FREE | |||||
R-X | R-0h | R-1h | |||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | X | |
1 | SOFT | R | 0h | Used in conjunction with FREE bit to determine the emulation suspend mode |
0 | FREE | R | 1h | For GPIO, the FREE bit is fixed at 1, which means GPIO runs free in emulation suspend |
GPIO_BINTEN is shown in Figure 12-63 and described in Table 12-131.
Return to Summary Table.
Bit Interrupt Enable Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0008h |
GPIO2 | 0061 0008h |
GPIO4 | 0062 0008h |
GPIO6 | 0063 0008h |
WKUP_GPIO1 | 4210 0008h |
WKUP_GPIO0 | 4211 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EN | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | RESERVED |
15-0 | EN | R/W | 0h | Per bank interrupt enable |
GPIO_DIR01 is shown in Figure 12-64 and described in Table 12-133.
Return to Summary Table.
Direction Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0010h |
GPIO2 | 0061 0010h |
GPIO4 | 0062 0010h |
GPIO6 | 0063 0010h |
WKUP_GPIO1 | 4210 0010h |
WKUP_GPIO0 | 4211 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIR1 | DIR0 | ||||||||||||||||||||||||||||||
R/W-FFFFh | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | DIR1 | R/W | FFFFh | Direction of GPIO bank 1 bits, |
15-0 | DIR0 | R/W | FFFFh | Direction of GPIO bank 0 bits, |
GPIO_OUT_DATA01 is shown in Figure 12-65 and described in Table 12-135.
Return to Summary Table.
Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0014h |
GPIO2 | 0061 0014h |
GPIO4 | 0062 0014h |
GPIO6 | 0063 0014h |
WKUP_GPIO1 | 4210 0014h |
WKUP_GPIO0 | 4211 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUT1 | OUT0 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | OUT1 | R/W | 0h | Output drive state of GPIO bank 1 bits, does not affect operation when it is configured as input Reading it returns the output drive state |
15-0 | OUT0 | R/W | 0h | Output drive state of GPIO bank 0 bits, does not affect operation when it is configured as input Reading it returns the output drive state |
GPIO_SET_DATA01 is shown in Figure 12-66 and described in Table 12-137.
Return to Summary Table.
Set Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0018h |
GPIO2 | 0061 0018h |
GPIO4 | 0062 0018h |
GPIO6 | 0063 0018h |
WKUP_GPIO1 | 4210 0018h |
WKUP_GPIO0 | 4211 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET1 | SET0 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SET1 | R/W1S | 0h | Writing 1 sets the output drive state of GPIO bank 1 bits Reading it returns the output drive state |
15-0 | SET0 | R/W1S | 0h | Writing 1 sets the output drive state of GPIO bank 0 bits Reading it returns the output drive state |
GPIO_CLR_DATA01 is shown in Figure 12-67 and described in Table 12-139.
Return to Summary Table.
Clear Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 001Ch |
GPIO2 | 0061 001Ch |
GPIO4 | 0062 001Ch |
GPIO6 | 0063 001Ch |
WKUP_GPIO1 | 4210 001Ch |
WKUP_GPIO0 | 4211 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR1 | CLR0 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLR1 | R/W1C | 0h | Writing 1 clears the output drive state of GPIO Reading it returns the output drive state |
15-0 | CLR0 | R/W1C | 0h | Writing 1 clears the output drive state of GPIO Reading it returns the output drive state |
GPIO_IN_DATA01 is shown in Figure 12-68 and described in Table 12-141.
Return to Summary Table.
Bank Status Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0020h |
GPIO2 | 0061 0020h |
GPIO4 | 0062 0020h |
GPIO6 | 0063 0020h |
WKUP_GPIO1 | 4210 0020h |
WKUP_GPIO0 | 4211 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN1 | IN0 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | IN1 | R | 0h | Status of GPIO bank 1 bits |
15-0 | IN0 | R | 0h | Status of GPIO bank 0 bits |
GPIO_SET_RIS_TRIG01 is shown in Figure 12-69 and described in Table 12-143.
Return to Summary Table.
Set Rising Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0024h |
GPIO2 | 0061 0024h |
GPIO4 | 0062 0024h |
GPIO6 | 0063 0024h |
WKUP_GPIO1 | 4210 0024h |
WKUP_GPIO0 | 4211 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETRIS1 | SETRIS0 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SETRIS1 | R/W1S | 0h | Writing 1 enables rising edge detection for GPIO bank 1 bits |
15-0 | SETRIS0 | R/W1S | 0h | Writing 1 enables rising edge detection for GPIO bank 0 bits |
GPIO_CLR_RIS_TRIG01 is shown in Figure 12-70 and described in Table 12-145.
Return to Summary Table.
Clear Rising Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0028h |
GPIO2 | 0061 0028h |
GPIO4 | 0062 0028h |
GPIO6 | 0063 0028h |
WKUP_GPIO1 | 4210 0028h |
WKUP_GPIO0 | 4211 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRRIS1 | CLRRIS0 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLRRIS1 | R/W1C | 0h | Writing 1 clears rising edge detection for GPIO bank 1 bits |
15-0 | CLRRIS0 | R/W1C | 0h | Writing 1 clears rising edge detection for GPIO bank 0 bits |
GPIO_SET_FAL_TRIG01 is shown in Figure 12-71 and described in Table 12-147.
Return to Summary Table.
Set Falling Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 002Ch |
GPIO2 | 0061 002Ch |
GPIO4 | 0062 002Ch |
GPIO6 | 0063 002Ch |
WKUP_GPIO1 | 4210 002Ch |
WKUP_GPIO0 | 4211 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETFAL1 | SETFAL0 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SETFAL1 | R/W1S | 0h | Writing 1 enables falling edge detection for for GPIO bank 1 bits |
15-0 | SETFAL0 | R/W1S | 0h | Writing 1 enables falling edge detection for for GPIO bank 0 bits |
GPIO_CLR_FAL_TRIG01 is shown in Figure 12-72 and described in Table 12-149.
Return to Summary Table.
Clear Falling Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0030h |
GPIO2 | 0061 0030h |
GPIO4 | 0062 0030h |
GPIO6 | 0063 0030h |
WKUP_GPIO1 | 4210 0030h |
WKUP_GPIO0 | 4211 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRFAL1 | CLRFAL0 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLRFAL1 | R/W1C | 0h | Writing 1 clears falling edge detection for for GPIO bank 1 bits |
15-0 | CLRFAL0 | R/W1C | 0h | Writing 1 clears falling edge detection for for GPIO bank 0 bits |
GPIO_INTSTAT01 is shown in Figure 12-73 and described in Table 12-151.
Return to Summary Table.
Bank Interrupt Status Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0034h |
GPIO2 | 0061 0034h |
GPIO4 | 0062 0034h |
GPIO6 | 0063 0034h |
WKUP_GPIO1 | 4210 0034h |
WKUP_GPIO0 | 4211 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STAT1 | STAT0 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | STAT1 | R/W1C | 0h | Status of GPIO bank 0 bits interrupt Reading back |
15-0 | STAT0 | R/W1C | 0h | Status of GPIO bank 0 bits interrupt Reading back |
GPIO_DIR23 is shown in Figure 12-74 and described in Table 12-153.
Return to Summary Table.
Direction Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0038h |
GPIO2 | 0061 0038h |
GPIO4 | 0062 0038h |
GPIO6 | 0063 0038h |
WKUP_GPIO1 | 4210 0038h |
WKUP_GPIO0 | 4211 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIR3 | DIR2 | ||||||||||||||||||||||||||||||
R/W-FFFFh | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | DIR3 | R/W | FFFFh | Direction of GPIO bank 3 bits, |
15-0 | DIR2 | R/W | FFFFh | Direction of GPIO bank 2 bits, |
GPIO_OUT_DATA23 is shown in Figure 12-75 and described in Table 12-155.
Return to Summary Table.
Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 003Ch |
GPIO2 | 0061 003Ch |
GPIO4 | 0062 003Ch |
GPIO6 | 0063 003Ch |
WKUP_GPIO1 | 4210 003Ch |
WKUP_GPIO0 | 4211 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUT3 | OUT2 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | OUT3 | R/W | 0h | Output drive state of GPIO bank 3 bits, does not affect operation when it is configured as input Reading it returns the output drive state |
15-0 | OUT2 | R/W | 0h | Output drive state of GPIO bank 2 bits, does not affect operation when it is configured as input Reading it returns the output drive state |
GPIO_SET_DATA23 is shown in Figure 12-76 and described in Table 12-157.
Return to Summary Table.
Set Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0040h |
GPIO2 | 0061 0040h |
GPIO4 | 0062 0040h |
GPIO6 | 0063 0040h |
WKUP_GPIO1 | 4210 0040h |
WKUP_GPIO0 | 4211 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET3 | SET2 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SET3 | R/W1S | 0h | Writing 1 sets the output drive state of GPIO bank 3 bits Reading it returns the output drive state |
15-0 | SET2 | R/W1S | 0h | Writing 1 sets the output drive state of GPIO bank 2 bits Reading it returns the output drive state |
GPIO_CLR_DATA23 is shown in Figure 12-77 and described in Table 12-159.
Return to Summary Table.
Clear Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0044h |
GPIO2 | 0061 0044h |
GPIO4 | 0062 0044h |
GPIO6 | 0063 0044h |
WKUP_GPIO1 | 4210 0044h |
WKUP_GPIO0 | 4211 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR3 | CLR2 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLR3 | R/W1C | 0h | Writing 1 clears the output drive state of GPIO Reading it returns the output drive state |
15-0 | CLR2 | R/W1C | 0h | Writing 1 clears the output drive state of GPIO Reading it returns the output drive state |
GPIO_IN_DATA23 is shown in Figure 12-78 and described in Table 12-161.
Return to Summary Table.
Bank Status Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0048h |
GPIO2 | 0061 0048h |
GPIO4 | 0062 0048h |
GPIO6 | 0063 0048h |
WKUP_GPIO1 | 4210 0048h |
WKUP_GPIO0 | 4211 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN3 | IN2 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | IN3 | R | 0h | Status of GPIO bank 3 bits |
15-0 | IN2 | R | 0h | Status of GPIO bank 2 bits |
GPIO_SET_RIS_TRIG23 is shown in Figure 12-79 and described in Table 12-163.
Return to Summary Table.
Set Rising Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 004Ch |
GPIO2 | 0061 004Ch |
GPIO4 | 0062 004Ch |
GPIO6 | 0063 004Ch |
WKUP_GPIO1 | 4210 004Ch |
WKUP_GPIO0 | 4211 004Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETRIS3 | SETRIS2 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SETRIS3 | R/W1S | 0h | Writing 1 enables rising edge detection for GPIO bank 3 bits |
15-0 | SETRIS2 | R/W1S | 0h | Writing 1 enables rising edge detection for GPIO bank 2 bits |
GPIO_CLR_RIS_TRIG23 is shown in Figure 12-80 and described in Table 12-165.
Return to Summary Table.
Clear Rising Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0050h |
GPIO2 | 0061 0050h |
GPIO4 | 0062 0050h |
GPIO6 | 0063 0050h |
WKUP_GPIO1 | 4210 0050h |
WKUP_GPIO0 | 4211 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRRIS3 | CLRRIS2 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLRRIS3 | R/W1C | 0h | Writing 1 clears rising edge detection for GPIO bank 3 bits |
15-0 | CLRRIS2 | R/W1C | 0h | Writing 1 clears rising edge detection for GPIO bank 2 bits |
GPIO_SET_FAL_TRIG23 is shown in Figure 12-81 and described in Table 12-167.
Return to Summary Table.
Set Falling Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0054h |
GPIO2 | 0061 0054h |
GPIO4 | 0062 0054h |
GPIO6 | 0063 0054h |
WKUP_GPIO1 | 4210 0054h |
WKUP_GPIO0 | 4211 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETFAL3 | SETFAL2 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SETFAL3 | R/W1S | 0h | Writing 1 enables falling edge detection for for GPIO bank 3 bits |
15-0 | SETFAL2 | R/W1S | 0h | Writing 1 enables falling edge detection for for GPIO bank 2 bits |
GPIO_CLR_FAL_TRIG23 is shown in Figure 12-82 and described in Table 12-169.
Return to Summary Table.
Clear Falling Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0058h |
GPIO2 | 0061 0058h |
GPIO4 | 0062 0058h |
GPIO6 | 0063 0058h |
WKUP_GPIO1 | 4210 0058h |
WKUP_GPIO0 | 4211 0058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRFAL3 | CLRFAL2 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLRFAL3 | R/W1C | 0h | Writing 1 clears falling edge detection for for GPIO bank 3 bits |
15-0 | CLRFAL2 | R/W1C | 0h | Writing 1 clears falling edge detection for for GPIO bank 2 bits |
GPIO_INTSTAT23 is shown in Figure 12-83 and described in Table 12-171.
Return to Summary Table.
Bank Interrupt Status Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 005Ch |
GPIO2 | 0061 005Ch |
GPIO4 | 0062 005Ch |
GPIO6 | 0063 005Ch |
WKUP_GPIO1 | 4210 005Ch |
WKUP_GPIO0 | 4211 005Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STAT3 | STAT2 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | STAT3 | R/W1C | 0h | Status of GPIO bank 2 bits interrupt Reading back |
15-0 | STAT2 | R/W1C | 0h | Status of GPIO bank 2 bits interrupt Reading back |
GPIO_DIR45 is shown in Figure 12-84 and described in Table 12-173.
Return to Summary Table.
Direction Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0060h |
GPIO2 | 0061 0060h |
GPIO4 | 0062 0060h |
GPIO6 | 0063 0060h |
WKUP_GPIO1 | 4210 0060h |
WKUP_GPIO0 | 4211 0060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIR5 | DIR4 | ||||||||||||||||||||||||||||||
R/W-FFFFh | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | DIR5 | R/W | FFFFh | Direction of GPIO bank 5 bits, |
15-0 | DIR4 | R/W | FFFFh | Direction of GPIO bank 4 bits, |
GPIO_OUT_DATA45 is shown in Figure 12-85 and described in Table 12-175.
Return to Summary Table.
Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0064h |
GPIO2 | 0061 0064h |
GPIO4 | 0062 0064h |
GPIO6 | 0063 0064h |
WKUP_GPIO1 | 4210 0064h |
WKUP_GPIO0 | 4211 0064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUT5 | OUT4 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | OUT5 | R/W | 0h | Output drive state of GPIO bank 5 bits, does not affect operation when it is configured as input Reading it returns the output drive state |
15-0 | OUT4 | R/W | 0h | Output drive state of GPIO bank 4 bits, does not affect operation when it is configured as input Reading it returns the output drive state |
GPIO_SET_DATA45 is shown in Figure 12-86 and described in Table 12-177.
Return to Summary Table.
Set Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0068h |
GPIO2 | 0061 0068h |
GPIO4 | 0062 0068h |
GPIO6 | 0063 0068h |
WKUP_GPIO1 | 4210 0068h |
WKUP_GPIO0 | 4211 0068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET5 | SET4 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SET5 | R/W1S | 0h | Writing 1 sets the output drive state of GPIO bank 5 bits Reading it returns the output drive state |
15-0 | SET4 | R/W1S | 0h | Writing 1 sets the output drive state of GPIO bank 4 bits Reading it returns the output drive state |
GPIO_CLR_DATA45 is shown in Figure 12-87 and described in Table 12-179.
Return to Summary Table.
Clear Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 006Ch |
GPIO2 | 0061 006Ch |
GPIO4 | 0062 006Ch |
GPIO6 | 0063 006Ch |
WKUP_GPIO1 | 4210 006Ch |
WKUP_GPIO0 | 4211 006Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR5 | CLR4 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLR5 | R/W1C | 0h | Writing 1 clears the output drive state of GPIO Reading it returns the output drive state |
15-0 | CLR4 | R/W1C | 0h | Writing 1 clears the output drive state of GPIO Reading it returns the output drive state |
GPIO_IN_DATA45 is shown in Figure 12-88 and described in Table 12-181.
Return to Summary Table.
Bank Status Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0070h |
GPIO2 | 0061 0070h |
GPIO4 | 0062 0070h |
GPIO6 | 0063 0070h |
WKUP_GPIO1 | 4210 0070h |
WKUP_GPIO0 | 4211 0070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN5 | IN4 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | IN5 | R | 0h | Status of GPIO bank 5 bits |
15-0 | IN4 | R | 0h | Status of GPIO bank 4 bits |
GPIO_SET_RIS_TRIG45 is shown in Figure 12-89 and described in Table 12-183.
Return to Summary Table.
Set Rising Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0074h |
GPIO2 | 0061 0074h |
GPIO4 | 0062 0074h |
GPIO6 | 0063 0074h |
WKUP_GPIO1 | 4210 0074h |
WKUP_GPIO0 | 4211 0074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETRIS5 | SETRIS4 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SETRIS5 | R/W1S | 0h | Writing 1 enables rising edge detection for GPIO bank 5 bits |
15-0 | SETRIS4 | R/W1S | 0h | Writing 1 enables rising edge detection for GPIO bank 4 bits |
GPIO_CLR_RIS_TRIG45 is shown in Figure 12-90 and described in Table 12-185.
Return to Summary Table.
Clear Rising Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0078h |
GPIO2 | 0061 0078h |
GPIO4 | 0062 0078h |
GPIO6 | 0063 0078h |
WKUP_GPIO1 | 4210 0078h |
WKUP_GPIO0 | 4211 0078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRRIS5 | CLRRIS4 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLRRIS5 | R/W1C | 0h | Writing 1 clears rising edge detection for GPIO bank 5 bits |
15-0 | CLRRIS4 | R/W1C | 0h | Writing 1 clears rising edge detection for GPIO bank 4 bits |
GPIO_SET_FAL_TRIG45 is shown in Figure 12-91 and described in Table 12-187.
Return to Summary Table.
Set Falling Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 007Ch |
GPIO2 | 0061 007Ch |
GPIO4 | 0062 007Ch |
GPIO6 | 0063 007Ch |
WKUP_GPIO1 | 4210 007Ch |
WKUP_GPIO0 | 4211 007Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETFAL5 | SETFAL4 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SETFAL5 | R/W1S | 0h | Writing 1 enables falling edge detection for for GPIO bank 5 bits |
15-0 | SETFAL4 | R/W1S | 0h | Writing 1 enables falling edge detection for for GPIO bank 4 bits |
GPIO_CLR_FAL_TRIG45 is shown in Figure 12-92 and described in Table 12-189.
Return to Summary Table.
Clear Falling Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0080h |
GPIO2 | 0061 0080h |
GPIO4 | 0062 0080h |
GPIO6 | 0063 0080h |
WKUP_GPIO1 | 4210 0080h |
WKUP_GPIO0 | 4211 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRFAL5 | CLRFAL4 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLRFAL5 | R/W1C | 0h | Writing 1 clears falling edge detection for for GPIO bank 5 bits |
15-0 | CLRFAL4 | R/W1C | 0h | Writing 1 clears falling edge detection for for GPIO bank 4 bits |
GPIO_INTSTAT45 is shown in Figure 12-93 and described in Table 12-191.
Return to Summary Table.
Bank Interrupt Status Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0084h |
GPIO2 | 0061 0084h |
GPIO4 | 0062 0084h |
GPIO6 | 0063 0084h |
WKUP_GPIO1 | 4210 0084h |
WKUP_GPIO0 | 4211 0084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STAT5 | STAT4 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | STAT5 | R/W1C | 0h | Status of GPIO bank 4 bits interrupt Reading back |
15-0 | STAT4 | R/W1C | 0h | Status of GPIO bank 4 bits interrupt Reading back |
GPIO_DIR67 is shown in Figure 12-94 and described in Table 12-193.
Return to Summary Table.
Direction Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0088h |
GPIO2 | 0061 0088h |
GPIO4 | 0062 0088h |
GPIO6 | 0063 0088h |
WKUP_GPIO1 | 4210 0088h |
WKUP_GPIO0 | 4211 0088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIR7 | DIR6 | ||||||||||||||||||||||||||||||
R/W-FFFFh | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | DIR7 | R/W | FFFFh | Direction of GPIO bank 7 bits, |
15-0 | DIR6 | R/W | FFFFh | Direction of GPIO bank 6 bits, |
GPIO_OUT_DATA67 is shown in Figure 12-95 and described in Table 12-195.
Return to Summary Table.
Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 008Ch |
GPIO2 | 0061 008Ch |
GPIO4 | 0062 008Ch |
GPIO6 | 0063 008Ch |
WKUP_GPIO1 | 4210 008Ch |
WKUP_GPIO0 | 4211 008Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OUT7 | OUT6 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | OUT7 | R/W | 0h | Output drive state of GPIO bank 7 bits, does not affect operation when it is configured as input Reading it returns the output drive state |
15-0 | OUT6 | R/W | 0h | Output drive state of GPIO bank 6 bits, does not affect operation when it is configured as input Reading it returns the output drive state |
GPIO_SET_DATA67 is shown in Figure 12-96 and described in Table 12-197.
Return to Summary Table.
Set Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0090h |
GPIO2 | 0061 0090h |
GPIO4 | 0062 0090h |
GPIO6 | 0063 0090h |
WKUP_GPIO1 | 4210 0090h |
WKUP_GPIO0 | 4211 0090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SET7 | SET6 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SET7 | R/W1S | 0h | Writing 1 sets the output drive state of GPIO bank 7 bits Reading it returns the output drive state |
15-0 | SET6 | R/W1S | 0h | Writing 1 sets the output drive state of GPIO bank 6 bits Reading it returns the output drive state |
GPIO_CLR_DATA67 is shown in Figure 12-97 and described in Table 12-199.
Return to Summary Table.
Clear Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0094h |
GPIO2 | 0061 0094h |
GPIO4 | 0062 0094h |
GPIO6 | 0063 0094h |
WKUP_GPIO1 | 4210 0094h |
WKUP_GPIO0 | 4211 0094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLR7 | CLR6 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLR7 | R/W1C | 0h | Writing 1 clears the output drive state of GPIO Reading it returns the output drive state |
15-0 | CLR6 | R/W1C | 0h | Writing 1 clears the output drive state of GPIO Reading it returns the output drive state |
GPIO_IN_DATA67 is shown in Figure 12-98 and described in Table 12-201.
Return to Summary Table.
Bank Status Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 0098h |
GPIO2 | 0061 0098h |
GPIO4 | 0062 0098h |
GPIO6 | 0063 0098h |
WKUP_GPIO1 | 4210 0098h |
WKUP_GPIO0 | 4211 0098h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IN7 | IN6 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | IN7 | R | 0h | Status of GPIO bank 7 bits |
15-0 | IN6 | R | 0h | Status of GPIO bank 6 bits |
GPIO_SET_RIS_TRIG67 is shown in Figure 12-99 and described in Table 12-203.
Return to Summary Table.
Set Rising Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 009Ch |
GPIO2 | 0061 009Ch |
GPIO4 | 0062 009Ch |
GPIO6 | 0063 009Ch |
WKUP_GPIO1 | 4210 009Ch |
WKUP_GPIO0 | 4211 009Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETRIS7 | SETRIS6 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SETRIS7 | R/W1S | 0h | Writing 1 enables rising edge detection for GPIO bank 7 bits |
15-0 | SETRIS6 | R/W1S | 0h | Writing 1 enables rising edge detection for GPIO bank 6 bits |
GPIO_CLR_RIS_TRIG67 is shown in Figure 12-100 and described in Table 12-205.
Return to Summary Table.
Clear Rising Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00A0h |
GPIO2 | 0061 00A0h |
GPIO4 | 0062 00A0h |
GPIO6 | 0063 00A0h |
WKUP_GPIO1 | 4210 00A0h |
WKUP_GPIO0 | 4211 00A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRRIS7 | CLRRIS6 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLRRIS7 | R/W1C | 0h | Writing 1 clears rising edge detection for GPIO bank 7 bits |
15-0 | CLRRIS6 | R/W1C | 0h | Writing 1 clears rising edge detection for GPIO bank 6 bits |
GPIO_SET_FAL_TRIG67 is shown in Figure 12-101 and described in Table 12-207.
Return to Summary Table.
Set Falling Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00A4h |
GPIO2 | 0061 00A4h |
GPIO4 | 0062 00A4h |
GPIO6 | 0063 00A4h |
WKUP_GPIO1 | 4210 00A4h |
WKUP_GPIO0 | 4211 00A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SETFAL7 | SETFAL6 | ||||||||||||||||||||||||||||||
R/W1S-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | SETFAL7 | R/W1S | 0h | Writing 1 enables falling edge detection for for GPIO bank 7 bits |
15-0 | SETFAL6 | R/W1S | 0h | Writing 1 enables falling edge detection for for GPIO bank 6 bits |
GPIO_CLR_FAL_TRIG67 is shown in Figure 12-102 and described in Table 12-209.
Return to Summary Table.
Clear Falling Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00A8h |
GPIO2 | 0061 00A8h |
GPIO4 | 0062 00A8h |
GPIO6 | 0063 00A8h |
WKUP_GPIO1 | 4210 00A8h |
WKUP_GPIO0 | 4211 00A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLRFAL7 | CLRFAL6 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | CLRFAL7 | R/W1C | 0h | Writing 1 clears falling edge detection for for GPIO bank 7 bits |
15-0 | CLRFAL6 | R/W1C | 0h | Writing 1 clears falling edge detection for for GPIO bank 6 bits |
GPIO_INTSTAT67 is shown in Figure 12-103 and described in Table 12-211.
Return to Summary Table.
Bank Interrupt Status Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00ACh |
GPIO2 | 0061 00ACh |
GPIO4 | 0062 00ACh |
GPIO6 | 0063 00ACh |
WKUP_GPIO1 | 4210 00ACh |
WKUP_GPIO0 | 4211 00ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STAT7 | STAT6 | ||||||||||||||||||||||||||||||
R/W1C-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | STAT7 | R/W1C | 0h | Status of GPIO bank 6 bits interrupt Reading back |
15-0 | STAT6 | R/W1C | 0h | Status of GPIO bank 6 bits interrupt Reading back |
GPIO_DIR8 is shown in Figure 12-104 and described in Table 12-213.
Return to Summary Table.
Direction Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00B0h |
GPIO2 | 0061 00B0h |
GPIO4 | 0062 00B0h |
GPIO6 | 0063 00B0h |
WKUP_GPIO1 | 4210 00B0h |
WKUP_GPIO0 | 4211 00B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DIR8 | ||||||||||||||||||||||||||||||
R-FFFFh | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | FFFFh | RESERVED |
15-0 | DIR8 | R/W | FFFFh | Direction of GPIO bank 8 bits, |
GPIO_OUT_DATA8 is shown in Figure 12-105 and described in Table 12-215.
Return to Summary Table.
Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00B4h |
GPIO2 | 0061 00B4h |
GPIO4 | 0062 00B4h |
GPIO6 | 0063 00B4h |
WKUP_GPIO1 | 4210 00B4h |
WKUP_GPIO0 | 4211 00B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OUT8 | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | RESERVED |
15-0 | OUT8 | R/W | 0h | Output drive state of GPIO bank 8 bits, does not affect operation when it is configured as input Reading it returns the output drive state |
GPIO_SET_DATA8 is shown in Figure 12-106 and described in Table 12-217.
Return to Summary Table.
Set Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00B8h |
GPIO2 | 0061 00B8h |
GPIO4 | 0062 00B8h |
GPIO6 | 0063 00B8h |
WKUP_GPIO1 | 4210 00B8h |
WKUP_GPIO0 | 4211 00B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SET8 | ||||||||||||||||||||||||||||||
R-0h | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | RESERVED |
15-0 | SET8 | R/W1S | 0h | Writing 1 sets the output drive state of GPIO bank 8 bits Reading it returns the output drive state |
GPIO_CLR_DATA8 is shown in Figure 12-107 and described in Table 12-219.
Return to Summary Table.
Clear Output Drive State Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00BCh |
GPIO2 | 0061 00BCh |
GPIO4 | 0062 00BCh |
GPIO6 | 0063 00BCh |
WKUP_GPIO1 | 4210 00BCh |
WKUP_GPIO0 | 4211 00BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLR8 | ||||||||||||||||||||||||||||||
R-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | RESERVED |
15-0 | CLR8 | R/W1C | 0h | Writing 1 clears the output drive state of GPIO Reading it returns the output drive state |
GPIO_IN_DATA8 is shown in Figure 12-108 and described in Table 12-221.
Return to Summary Table.
Bank Status Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00C0h |
GPIO2 | 0061 00C0h |
GPIO4 | 0062 00C0h |
GPIO6 | 0063 00C0h |
WKUP_GPIO1 | 4210 00C0h |
WKUP_GPIO0 | 4211 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IN8 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | RESERVED |
15-0 | IN8 | R | 0h | Status of GPIO bank 8 bits |
GPIO_SET_RIS_TRIG8 is shown in Figure 12-109 and described in Table 12-223.
Return to Summary Table.
Set Rising Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00C4h |
GPIO2 | 0061 00C4h |
GPIO4 | 0062 00C4h |
GPIO6 | 0063 00C4h |
WKUP_GPIO1 | 4210 00C4h |
WKUP_GPIO0 | 4211 00C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SETRIS8 | ||||||||||||||||||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | SETRIS8 | R/W1S | 0h | Writing 1 enables rising edge detection for GPIO bank 8 bits |
GPIO_CLR_RIS_TRIG8 is shown in Figure 12-110 and described in Table 12-225.
Return to Summary Table.
Clear Rising Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00C8h |
GPIO2 | 0061 00C8h |
GPIO4 | 0062 00C8h |
GPIO6 | 0063 00C8h |
WKUP_GPIO1 | 4210 00C8h |
WKUP_GPIO0 | 4211 00C8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLRRIS8 | ||||||||||||||||||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | CLRRIS8 | R/W1C | 0h | Writing 1 clears rising edge detection for GPIO bank 8 bits |
GPIO_SET_FAL_TRIG8 is shown in Figure 12-111 and described in Table 12-227.
Return to Summary Table.
Set Falling Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00CCh |
GPIO2 | 0061 00CCh |
GPIO4 | 0062 00CCh |
GPIO6 | 0063 00CCh |
WKUP_GPIO1 | 4210 00CCh |
WKUP_GPIO0 | 4211 00CCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SETFAL8 | ||||||||||||||||||||||||||||||
R/W-X | R/W1S-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | SETFAL8 | R/W1S | 0h | Writing 1 enables falling edge detection for for GPIO bank 8 bits |
GPIO_CLR_FAL_TRIG8 is shown in Figure 12-112 and described in Table 12-229.
Return to Summary Table.
Clear Falling Edge Detection Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00D0h |
GPIO2 | 0061 00D0h |
GPIO4 | 0062 00D0h |
GPIO6 | 0063 00D0h |
WKUP_GPIO1 | 4210 00D0h |
WKUP_GPIO0 | 4211 00D0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLRFAL8 | ||||||||||||||||||||||||||||||
R/W-X | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | CLRFAL8 | R/W1C | 0h | Writing 1 clears falling edge detection for for GPIO bank 8 bits |
GPIO_INTSTAT8 is shown in Figure 12-113 and described in Table 12-231.
Return to Summary Table.
Bank Interrupt Status Register
Instance | Physical Address |
---|---|
GPIO0 | 0060 00D4h |
GPIO2 | 0061 00D4h |
GPIO4 | 0062 00D4h |
GPIO6 | 0063 00D4h |
WKUP_GPIO1 | 4210 00D4h |
WKUP_GPIO0 | 4211 00D4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STAT8 | ||||||||||||||||||||||||||||||
R-0h | R/W1C-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | RESERVED |
15-0 | STAT8 | R/W1C | 0h | Status of GPIO bank 8 bits interrupt Reading back |