SPRUIU1 User guide

SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1

12.2.2.3 CPSW0 Integration

Figure 12-893 shows the integration of the CPSW0 module in the device.

Figure 12-893 CPSW0 Integration

The following CPSW0 control registers are located in CTRL_MMR0 module: CTRLMMR_ENET1_CTRL to CTRLMMR_ENET4_CTRL, CTRLMMR_CPSW_CLKSEL.

Table 12-1722 through Table 12-1724 summarize the integration of the CPSW0 module in the device.

Table 12-1722 CPSW0 Integration Attributes

Module Instance		Attributes
Module Instance	Power Sleep Controller	Power Domain	Module Domain	Interconnect
CPSW0	PSC0	PD4	LPSC63	CBASS0

Table 12-1723 CPSW0 Clocks and Resets

Clocks
Module Instance	Module Clock Input	Source Clock Signal	Source	Description
CPSW0	CPPI_ICLK	MAIN_PLL1_HSDIV1_CLKOUT	PLL1 (HSDIV1 of PER0 PLL)	CPPI packet streaming interface clock (320-MHz). Main clock for CPSW0.
	GMII_RFT_CLK	MAIN_PLL3_HSDIV0_CLKOUT/2	PLL3 (HSDIV0 of CPSW0 PLL)	125-MHz GMII Gigabit mode clock.
	RGMII_MHZ_5_CLK	MAIN_PLL3_HSDIV0_CLKOUT/50	PLL3 (HSDIV0 of CPSW0 PLL)	5-MHz RGMII reference clock.
	RGMII_MHZ_50_CLK	MAIN_PLL3_HSDIV0_CLKOUT/5	PLL3 (HSDIV0 of CPSW0 PLL)	50-MHz RGMII reference clock.
	RGMII_MHZ_250_CLK	MAIN_PLL3_HSDIV0_CLKOUT	PLL3 (HSDIV0 of CPSW0 PLL)	250-MHz RGMII reference clock.
	RMII_MHZ_50_CLK	RMII_REF_CLK	RMII_REF_CLK pad	50-MHz RMII reference clock. This clock is derived from the RMII_REF_CLK pad.
	CPTS_RFT_CLK	MAIN_PLL3_HSDIV1_CLKOUT	HSDIV1 of CPSW0 PLL Controller, selected through CPTS Multiplexer (200 or 250-MHz clock)	CPTS IEEE 1588 clock. Selected through the CTRLMMR_CPSW_CLKSEL register.
		MAIN_PLL0_HSDIV6_CLKOUT	HSDIV6 of MAIN PLL Controller, selected through CPTS Multiplexer (200 or 250-MHz clock)
		MCU_CPTS_RFT_CLK pad	MCU_CPTS_RFT_CLK pad, selected through CPTS Multiplexer (200-MHz clock)
		CPTS_RFT_CLK pad	CPTS_RFT_CLK pad, selected through CPTS Multiplexer (200-MHz clock)
		MCU_EXT_REFCLK0 pad	MCU_EXT_REFCLK0 pad, selected through CPTS Multiplexer (100-MHz clock)
		EXT_REFCLK1 pad	EXT_REFCLK1 pad, selected through CPTS Multiplexer (100-MHz clock)
		SERDES0_IP2_LN0_TXMCLK	SERDES0 Lane0 (500-MHz clock)
		SERDES0_IP2_LN1_TXMCLK	SERDES0 Lane1 (500-MHz clock)
		SERDES0_IP2_LN2_TXMCLK	SERDES0 Lane2 (500-MHz clock)
		SERDES0_IP2_LN3_TXMCLK	SERDES0 Lane3 (500-MHz clock)
		MCU_PLL2_HSDIV1_CLKOUT	HSDIV1 of MCU_CPSW0 PLL Controller, selected through CPTS Multiplexer (500-MHz clock)
		MAIN_SYSCLK0	PLLCTRL (500-MHz clock)
	GMII1_MT_CLK	RGMII_MHZ_250_CLK/10	RGMII_MHZ_250_CLK
	GMII2_MT_CLK
	GMII3_MT_CLK
	GMII4_MT_CLK
	GMII1_MR_CLK	RGMII_MHZ_250_CLK/10	RGMII_MHZ_250_CLK
	GMII2_MR_CLK
	GMII3_MR_CLK
	GMII4_MR_CLK
	RGMII1_RXC_I	RGMII1_RXC	RGMII1_RXC pad	RGMII1 reference clock that provides the timing reference for receive operations.
	RGMII2_RXC_I	RGMII2_RXC	RGMII2_RXC pad	RGMII2 reference clock that provides the timing reference for receive operations.
	RGMII3_RXC_I	RGMII3_RXC	RGMII3_RXC pad	RGMII3 reference clock that provides the timing reference for receive operations.
	RGMII4_RXC_I	RGMII4_RXC	RGMII4_RXC pad	RGMII4 reference clock that provides the timing reference for receive operations.
	RGMII1_TXC_O	RGMII1_TXC	RGMII1_TXC pad	RGMII1 transmit reference clock.
	RGMII2_TXC_O	RGMII2_TXC	RGMII2_TXC pad	RGMII2 transmit reference clock.
	RGMII3_TXC_O	RGMII3_TXC	RGMII3_TXC pad	RGMII3 transmit reference clock.
	RGMII4_TXC_O	RGMII4_TXC	RGMII4_TXC pad	RGMII4 transmit reference clock.
	MDIO_MCLK	MDIO_MCLK	MDIO0_MDC pad	Management data clock (MDIO_MCLK). The MDIO data clock is sourced by the MDIO module on the system. It is used to synchronize MDIO data access operations done on the MDIO pin.
Resets
Module Instance	Module Reset Input	Source Reset Signal	Source	Description
CPSW0	CPSW0_RST	MOD_G_RST	LPSC63	Module Reset

Table 12-1724 CPSW0 Hardware Requests

Interrupt Requests
Module Instance	Module Interrupt Signal	Destination Interrupt Input	Destination	Description	Type
CPSW0	CPSW0_STAT_PEND_0	R5FSS0_CORE0_INTR_IN_96	R5FSS0_CORE0	CPSW0 statistic pending interrupt 0	Level
		R5FSS0_CORE1_INTR_IN_96	R5FSS0_CORE1
		GIC500_SPI_IN_46	GIC500
		MAIN2MCU_LVL_INTRTR0_IN_221	MAIN2MCU_LVL_INTRTR0
	CPSW0_MDIO_PEND_0	R5FSS0_CORE0_INTR_IN_97	R5FSS0_CORE0	CPSW0 MDIO interrupt	Level
		R5FSS0_CORE1_INTR_IN_97	R5FSS0_CORE1
		GIC500_SPI_IN_47	GIC500
		MAIN2MCU_LVL_INTRTR0_IN_222	MAIN2MCU_LVL_INTRTR0
	CPSW0_EVNT_PEND_0	R5FSS0_CORE0_INTR_IN_98	R5FSS0_CORE0	CPSW0 event pending interrupt	Level
		R5FSS0_CORE1_INTR_IN_98	R5FSS0_CORE1
		GIC500_SPI_IN_48	GIC500
		MAIN2MCU_LVL_INTRTR0_IN_223	MAIN2MCU_LVL_INTRTR0
	CPSW0_ECC_SEC_PEND_0	ESM0_LVL_IN_306	ESM0	CPSW0 SEC ECC error interrupt	Level
	CPSW0_ECC_DED_PEND_0	ESM0_LVL_IN_307	ESM0	CPSW0 DED ECC error interrupt	Level
Time Sync and Compare Events
Module Instance	Module Event	Destination Event Input	Destination	Description	Type
CPSW0	CPSW0_CPTS_COMP_0	CMPEVENT_INTRTR0_IN_9	CMPEVT_INTRTR0	CPSW0 compare event interrupt	Edge
	CPSW0_CPTS_GENF0_0	TIMESYNC_INTRTR0_IN_14	TYMESYNC_INTRTR0	CPSW0 CPTS generator function event interrupt 0	Edge
	CPSW0_CPTS_GENF1_0	TIMESYNC_INTRTR0_IN_15	TYMESYNC_INTRTR0	CPSW0 CPTS generator function event interrupt 1	Edge
	CPSW0_CPTS_SYNC_0	TIMESYNC_INTRTR0_IN_37	TYMESYNC_INTRTR0	CPSW0 CPTS sync event interrupt	Edge