SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-492 lists the memory-mapped registers for the NAVSS0_PROXY_TARGET0_DATA. All register offset addresses not listed in Table 10-492 should be considered as reserved locations and the register contents should not be modified.
Proxy Datapath Region for Target 0.
Instance | Base Address |
---|---|
NAVSS0_PROXY_TARGET0_DATA | 3300 0000h |
MCU_NAVSS0_PROXY0_TARGET0_DATA | 2A50 0000h |
Offset | Acronym | Register Name | NAVSS0_PROXY_TARGET0_DATA Physical Address | MCU_NAVSS0_PROXY0_TARGET0_DATA Physical Address |
---|---|---|---|---|
0h + formula | PROXY_CTL_j | Proxy Control Register | 3300 0000h + formula | 2A50 0000h + formula |
4h + formula | PROXY_STATUS_j | Proxy Status Register | 3300 0004h + formula | 2A50 0004h + formula |
200h + formula | PROXY_DATA_j_y | Proxy Data Register | 3300 0200h + formula | 2A50 0200h + formula |
PROXY_CTL_j is shown in Figure 10-182 and described in Table 10-494.
Return to Summary Table.
The Proxy Control for the proxy. NOTE: This register must be written only via 32-bit accesses. 64-bit writes are not supported and may result in data loss.
Offset = 0h + (j * 1000h); where j = 0h to 3Fh
Instance | Physical Address |
---|---|
NAVSS0_PROXY_TARGET0_DATA | 3300 0000h + formula |
MCU_NAVSS0_PROXY0_TARGET0_DATA | 2A50 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ELSIZE | RESERVED | MODE | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUEUE | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R/W | X | |
26-24 | ELSIZE | R/W | 0h | Queue element size. This field is encoded as follows: 0 = 4 bytes 1 = 8 bytes 2 = 16 bytes 3 = 32 bytes 4 = 64 bytes 5 = 128 bytes 6 = 256 bytes 7 = 512 bytes |
23-18 | RESERVED | R/W | X | |
17-16 | MODE | R/W | 0h | Proxy Queue Mode that determines how to access the queue. 0h = access the head of the queue 1h = access the tail of the queue 2h = peek access the head of the queue 3h = peek access the tail of the queue. NOT SUPPORTED |
15-0 | QUEUE | R/W | 0h | Proxy Queue |
PROXY_STATUS_j is shown in Figure 10-183 and described in Table 10-496.
Return to Summary Table.
The Proxy Status for the proxy. NOTE: This register must be written only via 32-bit accesses. 64-bit writes are not supported and may result in data loss.
Offset = 4h + (j * 1000h); where j = 0h to 3Fh
Instance | Physical Address |
---|---|
NAVSS0_PROXY_TARGET0_DATA | 3300 0004h + formula |
MCU_NAVSS0_PROXY0_TARGET0_DATA | 2A50 0004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ERROR | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-X | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ERROR | R/W | 0h | Proxy Error status |
30-0 | RESERVED | R/W | X |
PROXY_DATA_j_y is shown in Figure 10-184 and described in Table 10-498.
Return to Summary Table.
The Proxy Data for the proxy, target and channel
Offset = 200h + (j * 1000h) + (y * 4h); where j = 0h to 3Fh, y = 0h to 7Fh
Instance | Physical Address |
---|---|
NAVSS0_PROXY_TARGET0_DATA | 3300 0200h + formula |
MCU_NAVSS0_PROXY0_TARGET0_DATA | 2A50 0200h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Proxy Data |