SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There are two WKUP_GPIO modules integrated in the device WKUP domain - WKUP_GPIO0 and WKUP_GPIO1. Figure 12-56 shows the integration of WKUP_GPIO[0-1].
Table 12-110 through Table 12-112 summarize the integration of WKUP_GPIO[0-1] in the device WKUP domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
WKUP_GPIO0 | WKUP_PSC0 | PD0 | LPSC3 | WKUP_CBASS0 |
WKUP_GPIO1 | WKUP_PSC0 | PD0 | LPSC3 | WKUP_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
WKUP_GPIO0 | WKUP_GPIO0_VBUS_CLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | WKUP_GPIO0 Functional and Interface clock. Output of multiplexer, see Figure 12-56 , WKUP_GPIO0 Integration. Multiplexers control is provided via Figure 12-56 [1-0] WAKE_CLK_SEL bit field in Control Module (CTRL_MMR). |
CLK_32K_RC | WKUP_RC_OSC_12M | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
WKUP_GPIO1 | WKUP_GPIO1_VBUS_CLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | WKUP_GPIO1 Functional and Interface clock. Output of multiplexer, see Figure 12-56 , WKUP_GPIO0 Integration. Multiplexers control is provided via Figure 12-56 [1-0] WAKE_CLK_SEL bit field in Control Module (CTRL_MMR). |
CLK_32K_RC | WKUP_RC_OSC_12M | |||
CLK_12M_RC | WKUP_RC_OSC_12M | |||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
WKUP_GPIO0 | WKUP_GPIO0_RST | MOD_G_RST | LPSC3 | WKUP_GPIO0 reset |
WKUP_GPIO1 | WKUP_GPIO1_RST | MOD_G_RST | LPSC3 | WKUP_GPIO1 reset |
Interrupt Requests | ||||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type | |
WKUP_GPIO0 | WKUP_GPIO0_GPIO_LVL_0 | WKUP_DMSC0_INTR_IN_28 | WKUP_DMSC0 | WKUP_GPIO0 interrupt request | Level | |
WKUP_GPIO0_GPIO_[0:31] | WKUP_GPIO0_VIRT_IN0_[0:31] | WKUP_GPIO0_VIRT | WKUP_GPIO0 pins [0:31] interrupt requests | Pulse | ||
WKUP_GPIO0_GPIO_[43:81] | WKUP_GPIO0_VIRT_IN0_[43:81] | WKUP_GPIO0_VIRT | WKUP_GPIO0 pins [43:81] interrupt requests | Pulse | ||
WKUP_GPIO0_GPIO_84 | WKUP_GPIO0_VIRT_IN0_84 | WKUP_GPIO0_VIRT | WKUP_GPIO0 pin 84 interrupt request | Pulse | ||
WKUP_GPIO0_GPIO_BANK_0 | WKUP_GPIOMUX_INTRTR0_IN_103 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO0 bank0 interrupt request | Pulse | ||
WKUP_GPIO0_GPIO_BANK_1 | WKUP_GPIOMUX_INTRTR0_IN_104 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO0 bank1 interrupt request | Pulse | ||
WKUP_GPIO0_GPIO_BANK_2 | WKUP_GPIOMUX_INTRTR0_IN_105 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO0 bank2 interrupt request | Pulse | ||
WKUP_GPIO0_GPIO_BANK_3 | WKUP_GPIOMUX_INTRTR0_IN_106 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO0 bank3 interrupt request | Pulse | ||
WKUP_GPIO0_GPIO_BANK_4 | WKUP_GPIOMUX_INTRTR0_IN_107 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO0 bank4 interrupt request | Pulse | ||
WKUP_GPIO0_GPIO_BANK_5 | WKUP_GPIOMUX_INTRTR0_IN_108 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO0 bank5 interrupt request | Pulse | ||
WKUP_GPIO1 | WKUP_GPIO1_GPIO_LVL_0 | WKUP_DMSC0_INTR_IN_29 | WKUP_DMSC0 | WKUP_GPIO1 interrupt request | Level | |
WKUP_GPIO1_GPIO_[0:31] | WKUP_GPIO1_VIRT_IN1_[0:31] | WKUP_GPIO0_VIRT | WKUP_GPIO1 pins [0:31] interrupt requests | Pulse | ||
WKUP_GPIO1_GPIO_[43:81] | WKUP_GPIO1_VIRT_IN1_[43:81] | WKUP_GPIO0_VIRT | WKUP_GPIO1 pins [43:81] interrupt requests | Pulse | ||
WKUP_GPIO1_GPIO_84 | WKUP_GPIO1_VIRT_IN1_84 | WKUP_GPIO0_VIRT | WKUP_GPIO1 pin 84 interrupt request | Pulse | ||
WKUP_GPIO1_GPIO_BANK_0 | WKUP_GPIOMUX_INTRTR0_IN_112 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO1 bank0 interrupt request | Pulse | ||
WKUP_GPIO1_GPIO_BANK_1 | WKUP_GPIOMUX_INTRTR0_IN_113 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO1 bank1 interrupt request | Pulse | ||
WKUP_GPIO1_GPIO_BANK_2 | WKUP_GPIOMUX_INTRTR0_IN_114 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO1 bank2 interrupt request | Pulse | ||
WKUP_GPIO1_GPIO_BANK_3 | WKUP_GPIOMUX_INTRTR0_IN_115 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO1 bank3 interrupt request | Pulse | ||
WKUP_GPIO1_GPIO_BANK_4 | WKUP_GPIOMUX_INTRTR0_IN_116 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO1 bank4 interrupt request | Pulse | ||
WKUP_GPIO1_GPIO_BANK_5 | WKUP_GPIOMUX_INTRTR0_IN_117 | WKUP_GPIOMUX_INTRTR0 | WKUP_GPIO1 bank5 interrupt request | Pulse |