SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 6-278 lists the memory-mapped registers for the R5FSS_VIM module. All register offset addresses not listed in Table 6-278 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | MCU_ARMSS_VIC_CFG Physical Address |
---|---|---|---|
0h | R5FSS_VIM_PID | Revision register | 40F8 0000h |
4h | R5FSS_VIM_INFO | Info register | 40F8 0004h |
8h | R5FSS_VIM_PRIIRQ | Prioritized IRQ register | 40F8 0008h |
Ch | R5FSS_VIM_PRIFIQ | Prioritized FIQ register | 40F8 000Ch |
10h | R5FSS_VIM_IRQGSTS | IRQ group status register | 40F8 0010h |
14h | R5FSS_VIM_FIQGSTS | FIQ group status register | 40F8 0014h |
18h | R5FSS_VIM_IRQVEC | IRQ vector address register | 40F8 0018h |
1Ch | R5FSS_VIM_FIQVEC | FIQ vector address register | 40F8 001Ch |
20h | R5FSS_VIM_ACTIRQ | Active IRQ register | 40F8 0020h |
24h | R5FSS_VIM_ACTFIQ | Active FIQ register | 40F8 0024h |
30h | R5FSS_VIM_DEDVEC | DED vector address register | 40F8 0030h |
400h + formula | R5FSS_VIM_RAW_j | Raw status/set register | 40F8 0400h + formula |
404h + formula | R5FSS_VIM_STS_j | Interrupt enable status/clear register | 40F8 0404h + formula |
408h + formula | R5FSS_VIM_INTR_EN_SET_j | Interrupt enable set register | 40F8 0408h + formula |
40Ch + formula | R5FSS_VIM_INTR_EN_CLR_j | Interrupt enabled clear register | 40F8 040Ch + formula |
410h + formula | R5FSS_VIM_IRQSTS_j | IRQ interrupt enable status/clear register | 40F8 0410h + formula |
414h + formula | R5FSS_VIM_FIQSTS_j | FIQ interrupt enable status/clear register | 40F8 0414h + formula |
418h + formula | R5FSS_VIM_INTMAP_j | Interrupt map register | 40F8 0418h + formula |
41Ch + formula | R5FSS_VIM_INTTYPE_j | Interrupt type register | 40F8 041Ch + formula |
1000h + formula | R5FSS_VIM_PRI_INT_j | Interrupt priority register | 40F8 1000h + formula |
2000h + formula | R5FSS_VIM_VEC_INT_j | Interrupt vector register | 40F8 2000h + formula |
Offset | Acronym | Register Name | ARMSS_VIC_CFG Physical Address |
---|---|---|---|
0h | R5FSS_VIM_PID | Revision register | 0FF8 0000h |
4h | R5FSS_VIM_INFO | Info register | 0FF8 0004h |
8h | R5FSS_VIM_PRIIRQ | Prioritized IRQ register | 0FF8 0008h |
Ch | R5FSS_VIM_PRIFIQ | Prioritized FIQ register | 0FF8 000Ch |
10h | R5FSS_VIM_IRQGSTS | IRQ group status register | 0FF8 0010h |
14h | R5FSS_VIM_FIQGSTS | FIQ group status register | 0FF8 0014h |
18h | R5FSS_VIM_IRQVEC | IRQ vector address register | 0FF8 0018h |
1Ch | R5FSS_VIM_FIQVEC | FIQ vector address register | 0FF8 001Ch |
20h | R5FSS_VIM_ACTIRQ | Active IRQ register | 0FF8 0020h |
24h | R5FSS_VIM_ACTFIQ | Active FIQ register | 0FF8 0024h |
30h | R5FSS_VIM_DEDVEC | DED vector address register | 0FF8 0030h |
400h + formula | R5FSS_VIM_RAW_j | Raw status/set register | 0FF8 0400h + formula |
404h + formula | R5FSS_VIM_STS_j | Interrupt enable status/clear register | 0FF8 0404h + formula |
408h + formula | R5FSS_VIM_INTR_EN_SET_j | Interrupt enable set register | 0FF8 0408h + formula |
40Ch + formula | R5FSS_VIM_INTR_EN_CLR_j | Interrupt enabled clear register | 0FF8 040Ch + formula |
410h + formula | R5FSS_VIM_IRQSTS_j | IRQ interrupt enable status/clear register | 0FF8 0410h + formula |
414h + formula | R5FSS_VIM_FIQSTS_j | FIQ interrupt enable status/clear register | 0FF8 0414h + formula |
418h + formula | R5FSS_VIM_INTMAP_j | Interrupt map register | 0FF8 0418h + formula |
41Ch + formula | R5FSS_VIM_INTTYPE_j | Interrupt type register | 0FF8 041Ch + formula |
1000h + formula | R5FSS_VIM_PRI_INT_j | Interrupt priority register | 0FF8 1000h + formula |
2000h + formula | R5FSS_VIM_VEC_INT_j | Interrupt vector register | 0FF8 2000h + formula |
R5FSS_VIM_PID is shown in Figure 6-120 and described in Table 6-281.
Return to Summary Table.
This register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0000h |
ARMSS_VIC_CFG | 0FF8 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-60900001h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 60900001h | TI internal data. Identifies revision of peripheral. |
R5FSS_VIM_INFO is shown in Figure 6-121 and described in Table 6-283.
Return to Summary Table.
This contains information about the configuration of the R5FSS_VIM.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0004h |
ARMSS_VIC_CFG | 0FF8 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTERRUPTS | ||||||||||||||||||||||||||||||
R-0h | R-200h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
10-0 | INTERRUPTS | R | 200h | Indicates the number of interrupts supported by the VIM. |
R5FSS_VIM_PRIIRQ is shown in Figure 6-122 and described in Table 6-285.
Return to Summary Table.
This register contains the number of the highest priority pending IRQ.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0008h |
ARMSS_VIC_CFG | 0FF8 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
VALID | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | NUM | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NUM | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | VALID | R | 0h | This field indicates if the NUM field of this register is valid. |
30-20 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
19-16 | PRI | R | 0h | This field indicates the priority of the pending IRQ interrupt. |
15-10 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
9-0 | NUM | R | 0h | This field indicates the interrupt number of the pending IRQ interrupt with the highest priority. |
R5FSS_VIM_PRIFIQ is shown in Figure 6-123 and described in Table 6-287.
Return to Summary Table.
This register contains the number of the highest priority pending FIQ.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 000Ch |
ARMSS_VIC_CFG | 0FF8 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
VALID | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | NUM | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NUM | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | VALID | R | 0h | This field indicates if the NUM field of this register is valid. |
30-20 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
19-16 | PRI | R | 0h | This field indicates the priority of the pending FIQ interrupt. |
15-10 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
9-0 | NUM | R | 0h | This field indicates the interrupt number of the pending FIQ interrupt with the highest priority. |
R5FSS_VIM_IRQGSTS is shown in Figure 6-124 and described in Table 6-289.
Return to Summary Table.
This register indicates which groups of interrupts have pending, unmasked IRQ interrupts.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0010h |
ARMSS_VIC_CFG | 0FF8 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | STS | R | 0h | This field indicates that one or more interrupts in group M are mapped to IRQ, unmasked, and pending. Bit 0 corresponds to group 0, bit 1 corresponds to group 1, etc. The interrupts associated with each group are [(M*32)+31:M*32] |
R5FSS_VIM_FIQGSTS is shown in Figure 6-125 and described in Table 6-291.
Return to Summary Table.
This register indicates which groups of interrupts have pending, unmasked FIQ interrupts.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0014h |
ARMSS_VIC_CFG | 0FF8 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | STS | R | 0h | This field indicates that one or more interrupts in group M are mapped to FIQ, unmasked, and pending. Bit 0 corresponds to group 0, bit 1 corresponds to group 1, etc. The interrupts associated with each group are [(M*32)+31:M*32] |
R5FSS_VIM_IRQVEC is shown in Figure 6-126 and described in Table 6-293.
Return to Summary Table.
This register contains the 32-bit interrupt vector address of the currently pending IRQ.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0018h |
ARMSS_VIC_CFG | 0FF8 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR | RESERVED | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | ADDR | R | 0h | This field contains the upper 30 bits of the
32-bit interrupt vector address (addresses must be
32-bit aligned) of the currently pending highest
priority IRQ (as indicated by the
R5FSS_VIM_PRIIRQ[9-0] NUM field). |
1-0 | RESERVED | R | 0h | Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.) |
R5FSS_VIM_FIQVEC is shown in Figure 6-127 and described in Table 6-295.
Return to Summary Table.
This register contains the 32-bit interrupt vector address of the currently pending FIQ.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 001Ch |
ARMSS_VIC_CFG | 0FF8 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR | RESERVED | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | ADDR | R | 0h | This field contains the upper 30 bits of the
32-bit interrupt vector address (addresses must be
32-bit aligned) of the currently pending highest
priority FIQ (as indicated by the
R5FSS_VIM_PRIFIQ[9-0] NUM field). |
1-0 | RESERVED | R | 0h | Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.) |
R5FSS_VIM_ACTIRQ is shown in Figure 6-128 and described in Table 6-297.
Return to Summary Table.
This register contains the number of the active IRQ.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0020h |
ARMSS_VIC_CFG | 0FF8 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
VALID | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | NUM | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NUM | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | VALID | R | 0h | This field indicates if the NUM field of this
register is valid. |
30-20 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
19-16 | PRI | R | 0h | This field indicates the priority of the active IRQ interrupt. |
15-10 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
9-0 | NUM | R | 0h | This field indicates the interrupt number of the
active IRQ interrupt. |
R5FSS_VIM_ACTFIQ is shown in Figure 6-129 and described in Table 6-299.
Return to Summary Table.
This register contains the number of the active FIQ.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0024h |
ARMSS_VIC_CFG | 0FF8 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
VALID | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | NUM | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NUM | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | VALID | R | 0h | This field indicates if the NUM field of this
register is valid. |
30-20 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
19-16 | PRI | R | 0h | This field indicates the priority of the active FIQ interrupt. |
15-10 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
9-0 | NUM | R | 0h | This field indicates the interrupt number of the
active FIQ interrupt. |
R5FSS_VIM_DEDVEC is shown in Figure 6-130 and described in Table 6-301.
Return to Summary Table.
This register contains the 32-bit interrupt vector address to be used as a default in case of a DED error in any of the vectors.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0030h |
ARMSS_VIC_CFG | 0FF8 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADDR | RESERVED | ||||||||||||||||||||||||||||||
R/W-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | ADDR | R/W | 0h | This field contains the upper 30 bits of the
32-bit interrupt vector address (the address must
be 32-bit aligned) of an interrupt to be used if
an uncorrectable double-bit error (DED) is
detected in any of the interrupt vector
addresses. |
1-0 | RESERVED | R | 0h | Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.) |
R5FSS_VIM_RAW_j is shown in Figure 6-131 and described in Table 6-303.
Return to Summary Table.
This register indicates the raw status of the events in group M.
Offset = 400h + (j * 20h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0400h + formula |
ARMSS_VIC_CFG | 0FF8 0400h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STS | |||||||||||||||||||||||||||||||
R/W1S-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | STS | R/W1S | 0h | This is the raw status of the events in group M. Each bit corresponds to event Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_STS_j is shown in Figure 6-132 and described in Table 6-305.
Return to Summary Table.
This register indicates the masked status of the events in group M.
Offset = 404h + (j * 20h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0404h + formula |
ARMSS_VIC_CFG | 0FF8 0404h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W1C-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W1C | 0h | This is the masked status of the events in group M. Each bit corresponds to event Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_INTR_EN_SET_j is shown in Figure 6-133 and described in Table 6-307.
Return to Summary Table.
This register is used to enable the mask for the events in group M.
Offset = 408h + (j * 20h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0408h + formula |
ARMSS_VIC_CFG | 0FF8 0408h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W1S-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W1S | 0h | This field is used to enable the mask of events in group M. Each bit corresponds to event Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_INTR_EN_CLR_j is shown in Figure 6-134 and described in Table 6-309.
Return to Summary Table.
This register is used to disable the mask for the events in group M.
Offset = 40Ch + (j * 20h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 040Ch + formula |
ARMSS_VIC_CFG | 0FF8 040Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W1C-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W1C | 0h | This field is used to disable the mask of events in group M. Each bit corresponds to event Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_IRQSTS_j is shown in Figure 6-135 and described in Table 6-311.
Return to Summary Table.
This register indicates the masked status of the events in Group M that are also mapped as IRQs.
Offset = 410h + (j * 20h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0410h + formula |
ARMSS_VIC_CFG | 0FF8 0410h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W1C-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W1C | 0h | This is the masked status of the events in group M that are mapped to IRQ. Each bit corresponds to event Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_FIQSTS_j is shown in Figure 6-136 and described in Table 6-313.
Return to Summary Table.
This register indicates the masked status of the events in group M that are also mapped as FIQs.
Offset = 414h + (j * 20h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0414h + formula |
ARMSS_VIC_CFG | 0FF8 0414h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W1C-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W1C | 0h | This is the masked status of the events in group M that are mapped to FIQ. Each bit corresponds to event Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_INTMAP_j is shown in Figure 6-137 and described in Table 6-315.
Return to Summary Table.
This register is used to map interrupts as IRQ or FIQ.
Offset = 418h + (j * 20h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 0418h + formula |
ARMSS_VIC_CFG | 0FF8 0418h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W | 0h | This field is used to indicate which interrupt the corresponding event influences (if enabled) for event group M. Each bit corresponds to event Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_INTTYPE_j is shown in Figure 6-138 and described in Table 6-317.
Return to Summary Table.
This register indicates whether an interrupt is a pulse or level source.
Offset = 41Ch + (j * 20h); where j = 0h to Fh.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 041Ch + formula |
ARMSS_VIC_CFG | 0FF8 041Ch + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSK | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSK | R/W | 0h | This field is used to indicate whether the source of an interrupt is a level (default) or a pulse for event group M. Each bit corresponds to event Q, where Q = M*32+bit (example: bit 0 is event M*32+0, bit 1 is M*32+1, etc). |
R5FSS_VIM_PRI_INT_j is shown in Figure 6-139 and described in Table 6-319.
Return to Summary Table.
This register is used to set the priority of interrupt Q.
Offset = 1000h + (j * 4h); where j = 0h to 1FFh.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 1000h + formula |
ARMSS_VIC_CFG | 0FF8 1000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL | ||||||||||||||||||||||||||||||
R-0h | R/W-Fh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved. Reads return 0. Writes have no effect. |
3-0 | VAL | R/W | Fh | This is the priority for interrupt Q. If two interrupts have the same priority, then whichever interrupt has the lower number Q wins arbitration. |
R5FSS_VIM_VEC_INT_j is shown in Figure 6-140 and described in Table 6-321.
Return to Summary Table.
This register contains the vector address associated with interrupt Q.
Offset = 2000h + (j * 4h); where j = 0h to 1FFh.
Instance | Physical Address |
---|---|
MCU_ARMSS_VIC_CFG | 40F8 2000h + formula |
ARMSS_VIC_CFG | 0FF8 2000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VAL | RESERVED | ||||||||||||||||||||||||||||||
R/W-0h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | VAL | R/W | 0h | These are the upper 30 bits of the 32-bit vector
address associated with interrupt Q. It is the
address that will be reflected in the
R5FSS_VIM_IRQVEC or R5FSS_VIM_FIQVEC and the
VECADDR output when interrupt Q is the active
interrupt. |
1-0 | RESERVED | R | 0h | Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. (Vector addresses must be 32-bit aligned.) |