SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
When the write leveling algorithm has completed, the final write DQS delay settings can be found in the following fields:
After write leveling is complete, the following fields can be checked to obtain the leveling status:
After write leveling is complete, software can always override the results by writing directly to the following fields:
If the clock path to the SDRAM is longer than the DQS path to the SDRAM, the leveling result from the first SDRAM along the memory clock path always returns a small value greater than zero because the DQS signal needs to be moved slightly to the right to line up with the memory clock. If the clock path to the SDRAM is shorter than the DQS path to the SDRAM, the DQS signal may need to be moved close to a cycle before it lines up with the memory clock. The leveling result indicates to the slice that the DQS needs to be delayed almost a cycle. This would then result in the write data being a cycle later than expected by the SDRAM based on when the write command is received. In reality, the DQS needs to be negatively delayed to align to the memory clock in the proper cycle. To create this “negative” delay, the command bus needs to be delayed one cycle so that when the DQS is delayed almost one cycle, the DQS appears “early” with respect to the write command. For example, if the memory clock path for slice 0 is expected to be about 1/16th cycle shorter than the DQS path, a write leveling result of 0x1E0 would be expected. The DDRSS_PHY_131[25-16] PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 field enables the data slice 0 to understand if this is an expected delay or if this is a “negative” delay condition. When the result contained in DDRSS_PHY_120[25-16] PHY_CLK_WRDQS_SLAVE_DELAY_0 field is greater than the DDRSS_PHY_131[25-16] PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 field, the command bus is delayed by one cycle.Table 8-90 shows examples of programming this field for various expected delays. The following fields are associated with the other data slices:
| Expected Delay | PHY_WRLVL_DELAY_EARLY_THRESHOLD_x x = 0, 1, 2, 3 | Command Bus Impact |
|---|---|---|
| 0.25 cycle | 0x200 (off) | None |
| 1.00 cycle | 0x200 (off) | None |
| 0.00 cycles | 0x1E0 | 1 cycle delay if result is > 0x1E0 |
The DDRSS_PHY_132[16] PHY_WRLVL_EARLY_FORCE_ZERO_0 bit works with the DDRSS_PHY_131[25-16] PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 field for slice 0. The following fields are associated with the other slices:
When the write leveling result satisfies the early threshold condition, the DQS is ideally aligned to clock but there is a cycle of latency added to the command path. Setting the PHY_WRLVL_EARLY_FORCE_ZERO_x bit to 0x1 forces the PHY_CLK_WRDQS_SLAVE_DELAY_x value to 0x0 so there is no command latency impact.
The PHY_WRLVL_THRESHOLD_ADJUST_x fields contain the results of the PHY_WRLVL_DELAY_PERIOD_THRESHOLD_x and PHY_WRLVL_DELAY_EARLY_THRESHOLD_x calculations from the write leveling process. This allows for direct observation of the leveling results. It also allows to rewrite leveling results if desired. This can be useful in case leveling is performed once and the same results are used in the future. The PHY_WRLVL_DELAY_EARLY_THRESHOLD_x and PHY_WRLVL_DELAY_PERIOD_THRESHOLD_x results can be applied through the PHY_WRLVL_THRESHOLD_ADJUST_x fields without having to go through the leveling process again.
The previously mentioned PHY_WRLVL_DELAY_PERIOD_THRESHOLD_x fields are accessed through the following registers: