SPRUIU1 User guide

SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1

12.2.2.4.6.2.1 Priority Mapping and Transmit VLAN Priority

There are three priorities that are used inside the Gigabit Ethernet Switch: packet priority, header packet priority, and switch priority. The header packet priority is used as the outgoing VLAN priority if the packet is egressing from the switch with a VLAN tag. The switch priority determines which of the 8 FIFO priority queues the packet uses during egress.

Figure 12-896 below, as well as the corresponding explanation that follows, explains each of the priorities, how they are determined, and how they are used. A number in parentheses in the figure indicates a process (Ethernet port ingress, host port egress, etc.). Each bullet in the text following the diagram explains one of the 5 processes pointed out in the figure.

Figure 12-896 Gigabit Ethernet Switch Priority Mapping and Transmit VLAN Processing

From Figure 12-896 above:

(1) is the ingress process that occurs at the external Ethernet ports
- The incoming packet is assigned a packet priority based on either its VLAN priority, IPv4 or IPv6 DSCP value, or the ingress port’s priority. This packet priority is then mapped to a header packet priority using the CPSW_PN_RX_PRI_MAP_REG_k register where N is the port where the packet entered the switch. This process is explained in further detail in Section 12.2.2.4.6.2.
(2) is the egress process that occurs at the external Ethernet ports
- If the switch is in VLAN Aware mode then the VLAN header may be added, replaced, or removed during the egress process. If the VLAN header is to be added or replaced, the VLAN priority will come from the header packet priority that was determined in process (1) or (5). Transmit VLAN processing is the same for both the host port and the external Ethernet ports and is described in Section 12.2.2.4.6.4.1.
(3) is the process by which it is decided which priority TX queue to place the packet on in the Port N TX FIFO during egress
- Each Port’s TX FIFO has 8 queues that each correspond to a priority that is used when determining which packet will egress from the switch next at that port. The header packet priority (Ethernet port ingress, process (1)) or the receive packet thread (host port 0 ingress, process (5)) gets mapped through the CPSW_PN_RX_PRI_MAP_REG_k register (where N is the egress port number) to determine the switch priority of the packet. The switch priority determines which TX FIFO queue to place the packet in. The FIFO architecture is described in Section 12.2.2.4.6.10.11. The header packet priority to switch priority mapping is discussed in Section 12.2.2.4.6.2.
(4) is the egress process that occurs at Host Port 0 toward the transmit streaming interface (TXST)
- The TXST has 8 egress threads for each external Ethernet port (32 threads in a 5-port switch). The TX thread that is selected for a packet is determined by the Ethernet port of ingress and the switch priority of the packet that was determined in process (3).
- If the switch is in VLAN Aware mode then the VLAN header may be added, replaced, or removed during the egress process. If the VLAN header is to be added or replaced, the VLAN priority will come from the header packet priority that was determined in process (1). Transmit VLAN processing is the same for both the host port and the external Ethernet ports and is described in Section 12.2.2.4.6.4.1.
(5) is the ingress process that occurs at Host Port 0
- The incoming packet is assigned a packet priority based on either its VLAN priority, IPv4 or IPv6 DSCP value, or the host port’s priority. This packet priority is then mapped to a header packet priority using the CPSW_PN_RX_PRI_MAP_REG_k register.
- Host port 0 also has a received packet thread. The receive packet thread is based on either the packet’s VLAN priority, IPv4 or IPv6 DSCP value, or the streaming interface (RXST) thread that the packet entered host port 0 on. This is discussed in .