Note: For validated set of parameters that can be programmed to PLLs, please refer to the device-specific Datasheet.
Initially, the device powers up in PLL bypass mode. The bypass mux is a glitch free mux and is located outside the PLL module. PLL_EXTBYPASS bit controls the bypass mux section. During Power-up, the bypass mux defaults to select FREF clock (PLL clock bypass mode).
During boot, WKUP_DMSC0 ROM programs the MCU_PLL0 to a valid frequency based on the crystal frequency and BOOTMODE pin settings. WKUP_DMSC0 then waits for PLL to be locked by checking the PLL LOCK status bit. WKUP_DMSC0 ROM programs PLL_EXTBYPASS bit to ‘0’ to disable the bypass mode to propagate MCU_PLL0 clock to WKUP_PLLCTRL0. At this point WKUP_DMSC0 brings MCU_R5FSS out of reset to complete the reset of the boot process. R5FSS software configures the remaining PLLs and bring them out of bypass mode.
The following shows the PLL initialization sequence.
- Wait until supplies are stable and PORz is de-asserted. By this time the reference clock source must be up and running.
- Default controls settings:
- By default PLLEN signal is Low provided by <PLL_name>_CTRL register default state. This signal behaves like a reset control to the PLL.
- By default PLL_INTBYPASS signal is low provided by <PLL_name>_CTRL register default state.
- By default PLL_EXTBYPASS signal is high provided by PLL MMR CTRL default state. PLL clock will be bypassed externally by a glitch free mux. The output of the mux will be the reference clock FREF.
- LOCK output of PLL will be Low.
- Program the PLL to a valid setting that runs the VCO within the specified range. The following bits/bitfields must be programmed appropriately by software: DSMEN, DACEN, FOUTPOSTDIVEN, FOUT4PHASEEN, REFDIV[5-0], FBDIV[11-0], FRAC[23-0], POSTDIV1[2-0], POSTDIV2[2-0].
- Wait for 1 µs to allow the PLL internal reset to complete (PLL powerdown switch pulls the loop filter voltage from rail-to-rail, which ensures the PLL will be completely powered down from any state).
- Assert PLLEN to a High (by writing a '1' into PLLEN bit in <PLL_name>_CTRL register).
- Wait for PLL Lock output to go high. Software can read the LOCK bit in <PLL_name>_STATS register to check if PLL has locked.
- De-assert PLL_EXTBYPASS signal to a Low by writing 0 into BYPASS_EN bit in <PLL_name>_CTRL register.
- Glitch free mux safely switches to the PLL clock output.
Changing PLL setting: During normal operation, before changing PLL settings, the PLL clock must be bypassed by setting PLL_EXTBYPASS control to a high. Then follow steps 2 to 8 from the above sequence.