SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-580 lists the memory-mapped registers for the UDMASS_INTA0_CFG_INTR. All register offset addresses not listed in Table 10-580 should be considered as reserved locations and the register contents should not be modified.
The Interupt Control / Status Registers region is accessed by setting the cfg_rsel signal to 2 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG_INTR | 33D0 0000h |
MCU_NAVSS0_UDMASS_INTA0_CFG_INTR | 2A70 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_INTA0_CFG_INTR Physical Address | MCU_NAVSS0_UDMASS_INTA0_CFG_INTR Physical Address |
---|---|---|---|---|
0h + formula | UDMA_INTA_ENABLE_SET_j | Interrupt Enable Set Register | 33D0 0000h + formula | 2A70 0000h + formula |
8h + formula | UDMA_INTA_ENABLE_CLEAR_j | Interrupt Enable Clear Register | 33D0 0008h + formula | 2A70 0008h + formula |
10h + formula | UDMA_INTA_STATUS_SET_j | Interrupt Status Set Register | 33D0 0010h + formula | 2A70 0010h + formula |
18h + formula | UDMA_INTA_STATUS_CLEAR_j | Interrupt Status Clear Register | 33D0 0018h + formula | 2A70 0018h + formula |
20h + formula | UDMA_INTA_STATUSM_j | Interrupt Masked Status Register | 33D0 0020h + formula | 2A70 0020h + formula |
UDMA_INTA_ENABLE_SET_j is shown in Figure 10-214 and described in Table 10-582.
Return to Summary Table.
The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output.
Offset = 0h + (j * 1000h); where j = 0h to FFh
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG_INTR | 33D0 0000h + formula |
MCU_NAVSS0_UDMASS_INTA0_CFG_INTR | 2A70 0000h + formula |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
ENABLE | |||||||||||||||||||||||||||||||
R/W1S-X | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE | |||||||||||||||||||||||||||||||
R/W1S-X | |||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63-0 | ENABLE | R/W1S | X | Interrupt enable set value. On writes, set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register. |
UDMA_INTA_ENABLE_CLEAR_j is shown in Figure 10-215 and described in Table 10-584.
Return to Summary Table.
The Interrupt Enable Clear register is written by software to disable (i.e. mask) specified bits to disallow their current status from be considered in the generation of the corresponding level sensitive virtual interrupt output.
Offset = 8h + (j * 1000h); where j = 0h to FFh
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG_INTR | 33D0 0008h + formula |
MCU_NAVSS0_UDMASS_INTA0_CFG_INTR | 2A70 0008h + formula |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
ENABLE | |||||||||||||||||||||||||||||||
R/W1C-X | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ENABLE | |||||||||||||||||||||||||||||||
R/W1C-X | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63-0 | ENABLE | R/W1C | X | Interrupt enable clear value. On writes, set bits will cause corresponding bits in the internal interrupt enable register to be cleared. Reads will reflect back the current status of the internal interrupt enable register. |
UDMA_INTA_STATUS_SET_j is shown in Figure 10-216 and described in Table 10-586.
Return to Summary Table.
The Interrupt Status register is read by software to determine the cause of an interrupt.
Offset = 10h + (j * 1000h); where j = 0h to FFh
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG_INTR | 33D0 0010h + formula |
MCU_NAVSS0_UDMASS_INTA0_CFG_INTR | 2A70 0010h + formula |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
STATUS | |||||||||||||||||||||||||||||||
R/W1S-X | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATUS | |||||||||||||||||||||||||||||||
R/W1S-X | |||||||||||||||||||||||||||||||
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63-0 | STATUS | R/W1S | X | Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be set |
UDMA_INTA_STATUS_CLEAR_j is shown in Figure 10-217 and described in Table 10-588.
Return to Summary Table.
The Interrupt Status register is read by software to determine the cause of an interrupt.
Offset = 18h + (j * 1000h); where j = 0h to FFh
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG_INTR | 33D0 0018h + formula |
MCU_NAVSS0_UDMASS_INTA0_CFG_INTR | 2A70 0018h + formula |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
STATUS | |||||||||||||||||||||||||||||||
R/W1C-X | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATUS | |||||||||||||||||||||||||||||||
R/W1C-X | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63-0 | STATUS | R/W1C | X | Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared |
UDMA_INTA_STATUSM_j is shown in Figure 10-218 and described in Table 10-590.
Return to Summary Table.
The Interrupt Masked Status register can be read by software to determine the cause of an interrupt.
Offset = 20h + (j * 1000h); where j = 0h to FFh
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_INTA0_CFG_INTR | 33D0 0020h + formula |
MCU_NAVSS0_UDMASS_INTA0_CFG_INTR | 2A70 0020h + formula |
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
STATUS | |||||||||||||||||||||||||||||||
R-X | |||||||||||||||||||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATUS | |||||||||||||||||||||||||||||||
R-X | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
63-0 | STATUS | R | X | Masked state of bits in internal interrupt status register. This value is the result of bitwise ANDing the interrupt enable and status registers |