SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
To generate high-frequency clocks, the device supports multiple on-chip PLLs controlled directly by the Top-level Clocking. They are the following types: Standard fractional PLL (PLLTS16FFCLAFRAC2) and Fractional PLL with Calibration (PLLTS16FFCLAFRACF).
This chapter discusses only the PLLs that are directly controlled by the Top-level Clocking. The other PLLs embedded in and managed by other subsystems are described in their respective subsystems.