SPRUIU1C July   2020  – February 2024 DRA821U , DRA821U-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation From Texas Instruments
    3.     Support Resources
    4.     Glossary
    5.     Export Control Notice
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Device Overview
    2. 1.2 Device Block Diagram
    3. 1.3 Device Main Domain
      1. 1.3.1  Arm Cortex-A72 Subsystem
      2. 1.3.2  Arm Cortex-R5F Processor
      3. 1.3.3  Navigator Subsystem
      4. 1.3.4  Region-based Address Translation Module
      5. 1.3.5  Multicore Shared Memory Controller
      6. 1.3.6  DDR Subsystem
      7. 1.3.7  General Purpose Input/Output Interface
      8. 1.3.8  Inter-Integrated Circuit Interface
      9. 1.3.9  Improved Inter-Integrated Circuit Interface
      10. 1.3.10 Multi-channel Serial Peripheral Interface
      11. 1.3.11 Universal Asynchronous Receiver/Transmitter
      12. 1.3.12 Gigabit Ethernet Switch
      13. 1.3.13 Peripheral Component Interconnect Express Subsystem
      14. 1.3.14 Universal Serial Bus (USB) Subsystem
      15. 1.3.15 SerDes
      16. 1.3.16 General Purpose Memory Controller with Error Location Module
      17. 1.3.17 Multimedia Card/Secure Digital Interface
      18. 1.3.18 Enhanced Capture Module
      19. 1.3.19 Enhanced Pulse-Width Modulation Module
      20. 1.3.20 Enhanced Quadrature Encoder Pulse Module
      21. 1.3.21 Controller Area Network
      22. 1.3.22 Audio Tracking Logic
      23. 1.3.23 Multi-channel Audio Serial Port
      24. 1.3.24 Timers
      25. 1.3.25 Internal Diagnostics Modules
    4. 1.4 Device MCU Domain
      1. 1.4.1  MCU Arm Cortex-R5F Processor
      2. 1.4.2  MCU Region-based Address Translation Module
      3. 1.4.3  MCU Navigator Subsystem
      4. 1.4.4  MCU Analog-to-Digital Converter
      5. 1.4.5  MCU Inter-Integrated Circuit Interface
      6. 1.4.6  MCU Improved Inter-Integrated Circuit Interface
      7. 1.4.7  MCU Multi-channel Serial Peripheral Interface
      8. 1.4.8  MCU Universal Asynchronous Receiver/Transmitter
      9. 1.4.9  MCU Gigabit Ethernet Switch
      10. 1.4.10 MCU Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
      11. 1.4.11 MCU Controller Area Network
      12. 1.4.12 MCU Timers
      13. 1.4.13 MCU Internal Diagnostics Modules
    5. 1.5 Device WKUP Domain
      1. 1.5.1 WKUP Device Management and Security Controller
      2. 1.5.2 WKUP General Purpose Input/Output Interface
      3. 1.5.3 WKUP Inter-Integrated Circuit Interface
      4. 1.5.4 WKUP Universal Asynchronous Receiver/Transmitter
      5. 1.5.5 WKUP Internal Diagnostics Modules
    6. 1.6 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 WKUP Domain Memory Map
    4. 2.4 Processors View Memory Map
    5. 2.5 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 System Interconnect Overview
    2. 3.2 System Interconnect Integration
      1. 3.2.1 Interconnect Integration in WKUP Domain
      2. 3.2.2 Interconnect Integration in MCU Domain
      3. 3.2.3 Interconnect Integration in MAIN Domain
    3. 3.3 System Interconnect Functional Description
      1. 3.3.1 Master-Slave Connections
      2. 3.3.2 Quality of Service (QoS)
      3. 3.3.3 Route ID
      4. 3.3.4 Initiator-Side Security Controls and Firewalls
        1. 3.3.4.1 Initiator-Side Security Controls (ISC)
          1. 3.3.4.1.1 Special System Level Priv-ID
          2. 3.3.4.1.2 Priv ID and ISC Assignment
        2. 3.3.4.2 Firewalls (FW)
          1. 3.3.4.2.1 Peripheral Firewalls (FW)
          2. 3.3.4.2.2 Memory or Region-based Firewalls
            1. 3.3.4.2.2.1 Region Based Firewall Functional Description
          3. 3.3.4.2.3 Channelized Firewalls
            1. 3.3.4.2.3.1 Channelized Firewall Functional Description
      5. 3.3.5 Null Error Reporting
      6. 3.3.6 VBUSM_TIMEOUT_GASKET (MCU_TIMEOUT_64B2)
        1. 3.3.6.1 Overview and Feature List
          1. 3.3.6.1.1 Features Supported
          2. 3.3.6.1.2 Features Not Supported
        2. 3.3.6.2 Functional Description
          1. 3.3.6.2.1 Functional Operation
            1. 3.3.6.2.1.1  Overview
            2. 3.3.6.2.1.2  FIFOs
            3. 3.3.6.2.1.3  ID Allocator
            4. 3.3.6.2.1.4  Timer
            5. 3.3.6.2.1.5  Timeout Queue
            6. 3.3.6.2.1.6  Write Scoreboard
            7. 3.3.6.2.1.7  Read Scoreboard
            8. 3.3.6.2.1.8  Flush Mode
            9. 3.3.6.2.1.9  Flushing
            10. 3.3.6.2.1.10 Timeout Error Reporting
            11. 3.3.6.2.1.11 Command Timeout Error Reporting
            12. 3.3.6.2.1.12 Unexpected Response Reporting
            13. 3.3.6.2.1.13 Latency and Stalls
            14. 3.3.6.2.1.14 Bypass
            15. 3.3.6.2.1.15 Safety
        3. 3.3.6.3 Interrupt Conditions
          1. 3.3.6.3.1 Transaction Error Interrupt
            1. 3.3.6.3.1.1 Transaction Timeout
            2. 3.3.6.3.1.2 Unexpected Response
            3. 3.3.6.3.1.3 Command Timeout
        4. 3.3.6.4 Memory Map
          1. 3.3.6.4.1  Revision Register (Base Address + 0x00)
          2. 3.3.6.4.2  Configuration Register (Base Address + 0x04)
          3. 3.3.6.4.3  Info Register (Base Address + 0x08)
          4. 3.3.6.4.4  Enable Register (Base Address + 0x0C)
          5. 3.3.6.4.5  Flush Register (Base Address + 0x10)
          6. 3.3.6.4.6  Timeout Value Register (Base Address + 0x14)
          7. 3.3.6.4.7  Timer Register (Base Address + 0x18)
          8. 3.3.6.4.8  Error Interrupt Raw Status/Set Register (Base Address + 0x20)
          9. 3.3.6.4.9  Error Interrupt Enabled Status/Clear Register (Base Address + 0x24)
          10. 3.3.6.4.10 Error Interrupt Mask Set Register (Base Address + 0x28)
          11. 3.3.6.4.11 Error Interrupt Mask Clear Register (Base Address + 0x2C)
          12. 3.3.6.4.12 Timeout Error Info Register (Base Address + 0x30)
          13. 3.3.6.4.13 Unexpected Response Info Register (Base Address + 0x34)
          14. 3.3.6.4.14 Error Transaction Valid/Dir/RouteID Register (Base Address + 0x38)
          15. 3.3.6.4.15 Error Transaction Tag/CommandID Register (Base Address + 0x3C)
          16. 3.3.6.4.16 Error Transaction Bytecnt Register (Base Address + 0x40)
          17. 3.3.6.4.17 Error Transaction Upper Address Register (Base Address + 0x44)
          18. 3.3.6.4.18 Error Transaction Lower Address Register (Base Address + 0x48)
        5. 3.3.6.5 Integration Overview
          1. 3.3.6.5.1 Parameterization Requirements
        6. 3.3.6.6 I/O Description
          1. 3.3.6.6.1 Clockstop Idle
          2. 3.3.6.6.2 Flush
          3. 3.3.6.6.3 Module I/O
        7. 3.3.6.7 User’s Guide
          1. 3.3.6.7.1 Programmer’s Guide
            1. 3.3.6.7.1.1 Initialization
            2. 3.3.6.7.1.2 Software Flush
      7. 3.3.7 Timeout Gasket (TOG)
    4. 3.4 System Interconnect Registers
      1. 3.4.1 QoS Registers
      2. 3.4.2 Firewall Exception Registers
      3. 3.4.3 Firewall Region Registers
      4. 3.4.4 Null Error Reporting Registers
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Terminology
    2. 4.2 Boot Process
      1. 4.2.1 MCU ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
      4. 4.2.4 MCU Only vs Normal Boot
    3. 4.3 Boot Mode Pins
      1. 4.3.1  MCU_BOOTMODE Pin Mapping
      2. 4.3.2  BOOTMODE Pin Mapping
        1. 4.3.2.1 Primary Boot Mode Selection
        2. 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0
        3. 4.3.2.3 Primary Boot Mode Configuration
        4. 4.3.2.4 Backup Boot Mode Configuration
      3. 4.3.3  No-boot/Dev-boot Configuration
      4. 4.3.4  Hyperflash Boot Device Configuration
      5. 4.3.5  OSPI Boot Device Configuration
      6. 4.3.6  QSPI Boot Device Configuration
      7. 4.3.7  SPI Boot Device Configuration
      8. 4.3.8  xSPI Boot Device Configuration
      9. 4.3.9  I2C Boot Device Configuration
      10. 4.3.10 MMC/SD Card Boot Device Configuration
      11. 4.3.11 eMMC Boot Device Configuration
      12. 4.3.12 Ethernet Boot Device Configuration
      13. 4.3.13 USB Boot Device Configuration
      14. 4.3.14 PCIe Boot Device Configuration
      15. 4.3.15 UART Boot Device Configuration
      16. 4.3.16 PLL Configuration
        1. 4.3.16.1 MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
        2. 4.3.16.2 MCU_PLL1
        3. 4.3.16.3 Main PLL1
        4. 4.3.16.4 Main PLL2
        5. 4.3.16.5 HSDIV Values
        6. 4.3.16.6 190
    4. 4.4 Boot Parameter Tables
      1. 4.4.1  Common Header
      2. 4.4.2  PLL Setup
      3. 4.4.3  PCIe Boot Parameter Table
      4. 4.4.4  I2C Boot Parameter Table
      5. 4.4.5  OSPI/QSPI/SPI Boot Parameter Table
      6. 4.4.6  Ethernet Boot Parameter Table
      7. 4.4.7  USB Boot Parameter Table
      8. 4.4.8  MMCSD Boot Parameter Table
      9. 4.4.9  UART Boot Parameter Table
      10. 4.4.10 Hyperflash Boot Parameter Table
    5. 4.5 Boot Image Format
      1. 4.5.1 Overall Structure
      2. 4.5.2 X.509 Certificate
      3. 4.5.3 Organizational Identifier (OID)
      4. 4.5.4 X.509 Extensions Specific to Boot
        1. 4.5.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.5.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.5.5 Extended Boot Info Extension
        1. 4.5.5.1 Impact on HS Device
        2. 4.5.5.2 Extended Boot Info Details
        3. 4.5.5.3 Certificate / Component Types
        4. 4.5.5.4 Extended Boot Encryption Info
        5. 4.5.5.5 Component Ordering
        6. 4.5.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.5.5.7 Device Type and Extended Boot Extension
      6. 4.5.6 Generating X.509 Certificates
        1. 4.5.6.1 Key Generation
          1. 4.5.6.1.1 Degenerate RSA Keys
        2. 4.5.6.2 Configuration Script
      7. 4.5.7 Image Data
    6. 4.6 Boot Modes
      1. 4.6.1 I2C Bootloader Operation
        1. 4.6.1.1 I2C Initialization Process
          1. 4.6.1.1.1 Block Size
          2. 4.6.1.1.2 226
        2. 4.6.1.2 I2C Loading Process
          1. 4.6.1.2.1 Loading a Boot Image From EEPROM
      2. 4.6.2 SPI Bootloader Operation
        1. 4.6.2.1 SPI Initialization Process
        2. 4.6.2.2 SPI Loading Process
      3. 4.6.3 QSPI Bootloader Operation
        1. 4.6.3.1 QSPI Initialization Process
        2. 4.6.3.2 QSPI Loading Process
      4. 4.6.4 OSPI Bootloader Operation
        1. 4.6.4.1 OSPI Initialization Process
        2. 4.6.4.2 OSPI Loading Process
      5. 4.6.5 PCIe Bootloader Operation
        1. 4.6.5.1 PCIe Initialization Process
        2. 4.6.5.2 PCIe Loading Process
      6. 4.6.6 Ethernet Bootloader Operation
        1. 4.6.6.1 Ethernet Initialization Process
        2. 4.6.6.2 Ethernet Loading Process
          1. 4.6.6.2.1 Ethernet Boot Data Formats
            1. 4.6.6.2.1.1 Limitations
            2. 4.6.6.2.1.2 BOOTP Request
              1. 4.6.6.2.1.2.1 MAC Header (DIX)
              2. 4.6.6.2.1.2.2 IPv4 Header
              3. 4.6.6.2.1.2.3 UDP Header
              4. 4.6.6.2.1.2.4 BOOTP Payload
              5. 4.6.6.2.1.2.5 TFTP
        3. 4.6.6.3 Ethernet Hand Over Process
      7. 4.6.7 USB Bootloader Operation
        1. 4.6.7.1 USB-Specific Attributes
          1. 4.6.7.1.1 DFU Device Mode
      8. 4.6.8 MMCSD Bootloader Operation
      9. 4.6.9 UART Bootloader Operation
        1. 4.6.9.1 Initialization Process
        2. 4.6.9.2 UART Loading Process
          1. 4.6.9.2.1 UART XMODEM
        3. 4.6.9.3 UART Hand-Over Process
    7. 4.7 Boot Memory Maps
      1. 4.7.1 Memory Layout/MPU
      2. 4.7.2 Global Memory Addresses Used by ROM Code
      3. 4.7.3 Memory Reserved by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 WKUP_CTRL_MMR0
        1. 5.1.1.1 WKUP_CTRL_MMR0 Overview
        2. 5.1.1.2 WKUP_CTRL_MMR0 Integration
        3. 5.1.1.3 WKUP_CTRL_MMR0 Functional Description
          1. 5.1.1.3.1 Description for WKUP_CTRL_MMR0 Register Types
            1. 5.1.1.3.1.1  Pad Configuration Registers
            2. 5.1.1.3.1.2  Kick Protection Registers
            3. 5.1.1.3.1.3  WKUP_CTRL_MMR0 Module Interrupts
            4. 5.1.1.3.1.4  Clock Selection Registers
            5. 5.1.1.3.1.5  Device Feature Registers
            6. 5.1.1.3.1.6  POK Module Registers
            7. 5.1.1.3.1.7  Power and Reset Related Registers
            8. 5.1.1.3.1.8  PRG Related Registers
            9. 5.1.1.3.1.9  Voltage Glitch Detect Control and Status Registers
            10. 5.1.1.3.1.10 I/O Debounce Control Registers
        4. 5.1.1.4 WKUP_CTRL_MMR0 Registers
      2. 5.1.2 MCU_CTRL_MMR0
        1. 5.1.2.1 MCU_CTRL_MMR0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 Register Types
            1. 5.1.2.3.1.1 Kick Protection Registers
            2. 5.1.2.3.1.2 MCU_CTRL_MMR0 Module Interrupts
            3. 5.1.2.3.1.3 Inter-processor Communication Registers
            4. 5.1.2.3.1.4 Timer I/O Muxing Control Registers
            5. 5.1.2.3.1.5 Clock Muxing and Division Registers
            6. 5.1.2.3.1.6 MCU_CPSW0 MAC Address Registers
        4. 5.1.2.4 MCU_CTRL_MMR0 Registers
        5. 5.1.2.5 MCU_SEC_MMR0_DBG_CTRL Registers
        6. 5.1.2.6 MCU_SEC_MMR0_BOOT_CTRL Registers
      3. 5.1.3 CTRL_MMR0
        1. 5.1.3.1 CTRL_MMR0 Overview
        2. 5.1.3.2 CTRL_MMR0 Integration
        3. 5.1.3.3 CTRL_MMR0 Functional Description
          1. 5.1.3.3.1 Description for CTRL_MMR0 Register Types
            1. 5.1.3.3.1.1  Pad Configuration Registers
            2. 5.1.3.3.1.2  Kick Protection Registers
            3. 5.1.3.3.1.3  CTRL_MMR0 Module Interrupts
            4. 5.1.3.3.1.4  Inter-processor Communication Registers
            5. 5.1.3.3.1.5  Timer I/O Muxing Control Registers
            6. 5.1.3.3.1.6  EHRPWM/EQEP Control and Status Registers
            7. 5.1.3.3.1.7  Clock Muxing and Division Registers
            8. 5.1.3.3.1.8  Ethernet Port Operation Control Registers
            9. 5.1.3.3.1.9  SERDES Lane Function Control Registers
            10. 5.1.3.3.1.10 DDRSS Dynamic Frequency Change Registers
        4. 5.1.3.4 CTRL_MMR0 Registers
        5. 5.1.3.5 SEC_MMR0_DBG_CTRL Registers
        6. 5.1.3.6 SEC_MMR0_BOOT_CTRL Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power Subsystems Overview
          1. 5.2.2.1.1 POK Overview
          2. 5.2.2.1.2 PRG / PRG_PP Overview
          3. 5.2.2.1.3 POR Overview
          4. 5.2.2.1.4 POK / PRG(_PP) /POR Overview
          5. 5.2.2.1.5 Timing
          6. 5.2.2.1.6 Restrictions
        2. 5.2.2.2 Power System Modules
          1. 5.2.2.2.1 Power OK (POK) Modules
            1. 5.2.2.2.1.1 POK Programming Model
              1. 5.2.2.2.1.1.1 POK Threshold Setting Programming Sequence
          2. 5.2.2.2.2 Power on Reset (POR) Module
            1. 5.2.2.2.2.1 POR Overview
            2. 5.2.2.2.2.2 POR Integration
            3. 5.2.2.2.2.3 POR Programming Model
          3. 5.2.2.2.3 PoR/Reset Generator (PRG_PP) Modules
            1. 5.2.2.2.3.1 PRG_PP Overview
            2. 5.2.2.2.3.2 PRG_PP Integration
            3. 5.2.2.2.3.3 PRG_PP Programming Model
          4. 5.2.2.2.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.2.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.2.5.1 VTM Overview
              1. 5.2.2.2.5.1.1 VTM Features
              2. 5.2.2.2.5.1.2 VTM Not Supported Features
            2. 5.2.2.2.5.2 VTM Integration
            3. 5.2.2.2.5.3 VTM Functional Description
              1. 5.2.2.2.5.3.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.2.5.3.1.1 10-bit Temperature Values Versus Temperature
              2. 5.2.2.2.5.3.2 VTM Temperature Driven Alerts and Interrupts
              3. 5.2.2.2.5.3.3 VTM VID Voltage Domains
              4. 5.2.2.2.5.3.4 VTM Clocking
              5. 5.2.2.2.5.3.5 VTM Retention Interface
              6. 5.2.2.2.5.3.6 VTM ECC Aggregator
              7. 5.2.2.2.5.3.7 VTM Programming Model
                1. 5.2.2.2.5.3.7.1 VTM Maximum Temperature Outrange Alert
                2. 5.2.2.2.5.3.7.2 Temperature Monitor during Low Power Modes
                3. 5.2.2.2.5.3.7.3 Sensors Programming Sequences
              8. 5.2.2.2.5.3.8 AVS-Class0
          6. 5.2.2.2.6 Distributed Power Clock and Reset Controller (DPCR)
        3. 5.2.2.3 Power Control Modules
          1. 5.2.2.3.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.3.1.1 PSC Terminology
            2. 5.2.2.3.1.2 PSC Features
            3. 5.2.2.3.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.3.1.3.1 WKUP_PSC0 Device-Specific Information
              2. 5.2.2.3.1.3.2 PSC0 Device-Specific Information
              3. 5.2.2.3.1.3.3 LPSC Dependences Overview
            4. 5.2.2.3.1.4 PSC: Power Domain and Module States
              1. 5.2.2.3.1.4.1 Power Domain States
              2. 5.2.2.3.1.4.2 Module States
              3. 5.2.2.3.1.4.3 Local Reset
            5. 5.2.2.3.1.5 PSC: Executing State Transitions
              1. 5.2.2.3.1.5.1 Power Domain State Transitions
              2. 5.2.2.3.1.5.2 Module State Transitions
              3. 5.2.2.3.1.5.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.3.1.5.4 Recommendations for Power Domain/Module Sequencing
            6. 5.2.2.3.1.6 PSC: Emulation Support in the PSC
            7. 5.2.2.3.1.7 PSC: A72SS, MSMC, MCU Cortex-R5F, C71SS0, and C66SS Subsystem Power-Up and Power-Down Sequences
              1. 5.2.2.3.1.7.1 ARMi_COREn Power State Transition
              2. 5.2.2.3.1.7.2 A72SS Power State Transition
              3. 5.2.2.3.1.7.3 GIC0 Sequencing to Support A72SS Power Management
              4. 5.2.2.3.1.7.4 MSMC0 Clkstop/Powerdown/Disconnect Sequencing
              5. 5.2.2.3.1.7.5 MCU Cortex-R5F Power Modes
          2. 5.2.2.3.2 Integrated Power Management (DMSC)
            1. 5.2.2.3.2.1 DMSC Power Management Overview
              1. 5.2.2.3.2.1.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Voltage Domains
        3. 5.2.3.3 Power Domains
        4. 5.2.3.4 Clock Sources States
        5. 5.2.3.5 Wake-up Sources
        6. 5.2.3.6 Device Power States and Transitions
          1. 5.2.3.6.1 LPM Entry Sequences
          2. 5.2.3.6.2 LPM Exit Sequences
          3. 5.2.3.6.3 IO Retention
          4. 5.2.3.6.4 DDRSS Self-Refresh
      4. 5.2.4 Dynamic Power Management
        1. 5.2.4.1 AVS Support
        2. 5.2.4.2 Dynamic Frequency Scaling (DFS) Operations
      5. 5.2.5 Thermal Management
      6. 5.2.6 Registers
        1. 5.2.6.1 WKUP_VTM0 Registers
        2. 5.2.6.2 PSC Registers
    3. 5.3 Reset
      1. 5.3.1 Reset Overview
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
      4. 5.3.4 Reset Control
      5. 5.3.5 BOOTMODE Pins
      6. 5.3.6 Reset Sequences
        1. 5.3.6.1 MCU_PORz Overview
        2. 5.3.6.2 MCU_PORz Sequence
        3. 5.3.6.3 MCU_RESETz Sequence
        4. 5.3.6.4 PORz Sequence
        5. 5.3.6.5 RESET_REQz Sequence
      7. 5.3.7 PLL Behavior on Reset
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 424
          3. 5.4.3.1.3 OBSCLK0, OBSCLK1, and OBSCLK2 Pins
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillators with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 WKUP and MCU Domains PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRAC2 Type Output Clocks
              2. 5.4.5.4.1.2.2 PLLTS16FFCLAFRACF Type Output Clocks
              3. 5.4.5.4.1.2.3 PLL Lock
              4. 5.4.5.4.1.2.4 HSDIVIDER
              5. 5.4.5.4.1.2.5 ICG Module
              6. 5.4.5.4.1.2.6 PLL Power Down
              7. 5.4.5.4.1.2.7 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
      6. 5.4.6 Registers
        1. 5.4.6.1 MCU_PLL0_CFG Registers
        2. 5.4.6.2 PLL0_CFG Registers
        3. 5.4.6.3 PLLCTRL0 Registers
  8. 6 Processors and Accelerators
    1. 6.1 Compute Cluster
      1. 6.1.1 Compute Cluster Overview
      2. 6.1.2 Compute Cluster Functional Description
        1. 6.1.2.1 Compute Cluster Memory Regions
        2. 6.1.2.2 Compute Cluster Firewalls
        3. 6.1.2.3 Compute Cluster ECC Aggregators
      3. 6.1.3 Compute Cluster Registers
    2. 6.2 Dual-A72 MPU Subsystem
      1. 6.2.1 A72SS Overview
        1. 6.2.1.1 A72SS Introduction
        2. 6.2.1.2 A72SS Features
      2. 6.2.2 A72SS Integration
      3. 6.2.3 A72SS Functional Description
        1. 6.2.3.1  A72SS Block Diagram
        2. 6.2.3.2  A72SS A72 Cluster
        3. 6.2.3.3  A72SS Interfaces and Async Bridges
        4. 6.2.3.4  A72SS Interrupts
          1. 6.2.3.4.1 A72SS Interrupt Inputs
          2. 6.2.3.4.2 A72SS Interrupt Outputs
        5. 6.2.3.5  A72SS Power Management, Clocking and Reset
          1. 6.2.3.5.1 A72SS Power Management
          2. 6.2.3.5.2 A72SS Clocking
        6. 6.2.3.6  A72SS Debug Support
        7. 6.2.3.7  A72SS Timestamps
        8. 6.2.3.8  A72SS Watchdog
        9. 6.2.3.9  A72SS Internal Diagnostics
          1. 6.2.3.9.1 A72SS ECC Aggregators During Low Power States
          2. 6.2.3.9.2 A72SS CBASS Diagnostics
          3. 6.2.3.9.3 A72SS SRAM Diagnostics
          4. 6.2.3.9.4 A72SS SRAM ECC Aggregator Configurations
        10. 6.2.3.10 A72SS Cache Pre-Warming
        11. 6.2.3.11 A72SS Boot
        12. 6.2.3.12 A72SS IPC with Other CPUs
      4. 6.2.4 A72SS Registers
        1. 6.2.4.1 Arm A72 Cluster Registers
        2. 6.2.4.2 A72SS ECC Aggregator Registers
          1. 6.2.4.2.1 A72SS CLUSTER ECC Registers
          2. 6.2.4.2.2 A72SS CORE0 ECC Registers
          3. 6.2.4.2.3 A72SS CORE1 ECC Registers
    3. 6.3 Dual-R5F MCU Subsystem
      1. 6.3.1 R5FSS Overview
        1. 6.3.1.1 R5FSS Features
        2. 6.3.1.2 R5FSS Not Supported Features
      2. 6.3.2 R5FSS Integration
        1. 6.3.2.1 R5FSS Integration in MCU Domain
        2. 6.3.2.2 R5FSS Integration in MAIN Domain
      3. 6.3.3 R5FSS Functional Description
        1. 6.3.3.1  R5FSS Block Diagram
        2. 6.3.3.2  R5FSS Cortex-R5F Core
          1. 6.3.3.2.1 L1 Caches
          2. 6.3.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.3.3.2.3 R5FSS Special Signals
        3. 6.3.3.3  R5FSS Interfaces
          1. 6.3.3.3.1 R5FSS Master Interfaces
          2. 6.3.3.3.2 R5FSS Slave Interfaces
        4. 6.3.3.4  R5FSS Power, Clocking and Reset
          1. 6.3.3.4.1 R5FSS Power
          2. 6.3.3.4.2 R5FSS Clocking
            1. 6.3.3.4.2.1 Changing MCU_R5FSS0 CPU Clock Frequency
          3. 6.3.3.4.3 R5FSS Reset
        5. 6.3.3.5  R5FSS Lockstep Error Detection Logic
          1. 6.3.3.5.1 CPU Output Compare Block
            1. 6.3.3.5.1.1 Operating Modes
            2. 6.3.3.5.1.2 Compare Block Active Mode
            3. 6.3.3.5.1.3 Self Test Mode
            4. 6.3.3.5.1.4 Compare Match Test
            5. 6.3.3.5.1.5 Compare Mismatch Test
            6. 6.3.3.5.1.6 Error Forcing Mode
            7. 6.3.3.5.1.7 Self Test Error Forcing Mode
          2. 6.3.3.5.2 Inactivity Monitor Block
            1. 6.3.3.5.2.1 Operating Modes
            2. 6.3.3.5.2.2 Compare Block Active Mode
            3. 6.3.3.5.2.3 Self Test Mode
            4. 6.3.3.5.2.4 Compare Match Test
            5. 6.3.3.5.2.5 Compare Mismatch Test
            6. 6.3.3.5.2.6 Error Forcing Mode
            7. 6.3.3.5.2.7 Self Test Error Forcing Mode
          3. 6.3.3.5.3 Polarity Inversion Logic
        6. 6.3.3.6  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.3.3.6.1 VIM Overview
          2. 6.3.3.6.2 VIM Interrupt Inputs
          3. 6.3.3.6.3 VIM Interrupt Outputs
          4. 6.3.3.6.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.3.3.6.5 VIM Interrupt Prioritization
          6. 6.3.3.6.6 VIM ECC Support
          7. 6.3.3.6.7 VIM Lockstep Mode
          8. 6.3.3.6.8 VIM IDLE State
          9. 6.3.3.6.9 VIM Interrupt Handling
            1. 6.3.3.6.9.1 Servicing IRQ Through Vector Interface
            2. 6.3.3.6.9.2 Servicing IRQ Through MMR Interface
            3. 6.3.3.6.9.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.3.3.6.9.4 Servicing FIQ
            5. 6.3.3.6.9.5 Servicing FIQ (Alternative)
        7. 6.3.3.7  R5FSS Region Address Translation (RAT)
          1. 6.3.3.7.1 RAT Overview
          2. 6.3.3.7.2 RAT Operation
          3. 6.3.3.7.3 RAT Error Logging
          4. 6.3.3.7.4 RAT Protection
        8. 6.3.3.8  R5FSS ECC Support
        9. 6.3.3.9  R5FSS Memory View
        10. 6.3.3.10 R5FSS Debug and Trace
        11. 6.3.3.11 R5FSS Boot Options
        12. 6.3.3.12 R5FSS Core Memory ECC Events
      4. 6.3.4 R5FSS Registers
        1. 6.3.4.1 R5FSS_CCMR5 Registers
        2. 6.3.4.2 R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
        3. 6.3.4.3 R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
        4. 6.3.4.4 R5FSS_VIM Registers
        5. 6.3.4.5 R5FSS_RAT Registers
        6. 6.3.4.6 R5FSS_EVNT_BUS_VBUSP_MMRS Registers
  9. 7 Interprocessor Communication
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 Multicore Shared Memory Controller (MSMC)
      1. 8.1.1 MSMC Overview
        1. 8.1.1.1 MSMC Not Supported Features
      2. 8.1.2 MSMC Integration
        1. 8.1.2.1 MSMC Integration in MAIN Domain
        2. 8.1.2.2 639
      3. 8.1.3 MSMC Functional Description
        1. 8.1.3.1  MSMC Block Diagram
        2. 8.1.3.2  MSMC On-Chip Memory Banking
        3. 8.1.3.3  MSMC Snoop Filter and Data Cache
          1. 8.1.3.3.1 Way Partitioning
          2. 8.1.3.3.2 Cache Size Configuration and Associativity
        4. 8.1.3.4  MSMC Access Protection Checks
        5. 8.1.3.5  MSMC Null Slave
        6. 8.1.3.6  MSMC Resource Arbitration
        7. 8.1.3.7  MSMC Error Detection and Correction
          1. 8.1.3.7.1 On-chip SRAM and Pipeline Data Protection
          2. 8.1.3.7.2 On-chip SRAM L3 Cache Tag and Snoop Filter Protection
          3. 8.1.3.7.3 On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
          4. 8.1.3.7.4 Background Parity Refresh (Scrubbing)
        8. 8.1.3.8  MSMC Interrupts
          1. 8.1.3.8.1 Raw Interrupt Registers
          2. 8.1.3.8.2 Interrupt Enable Registers
          3. 8.1.3.8.3 Triggered and Enabled Interrupts
        9. 8.1.3.9  MSMC Memory Regions
        10. 8.1.3.10 MSMC Hardware Coherence
          1. 8.1.3.10.1 Snoop Filter Broadcast Mode
        11. 8.1.3.11 MSMC Quality-of-Service
        12. 8.1.3.12 MSMC Memory Regions Protection
        13. 8.1.3.13 MSMC Cache Tag View
      4. 8.1.4 MSMC Registers
    2. 8.2 DDR Subsystem (DDRSS)
      1. 8.2.1 DDRSS Overview
        1. 8.2.1.1 DDRSS Not Supported Features
      2. 8.2.2 DDRSS Environment
      3. 8.2.3 DDRSS Integration
        1. 8.2.3.1 DDRSS Integration in MAIN Domain
      4. 8.2.4 DDRSS Functional Description
        1. 8.2.4.1 DDRSS MSMC2DDR Bridge
          1. 8.2.4.1.1 VBUSM.C Threads
          2. 8.2.4.1.2 Class of Service (CoS)
          3. 8.2.4.1.3 AXI Write Data All-Strobes
          4. 8.2.4.1.4 Inline ECC for SDRAM Data
            1. 8.2.4.1.4.1 ECC Cache
            2. 8.2.4.1.4.2 ECC Statistics
          5. 8.2.4.1.5 Opcode Checking
          6. 8.2.4.1.6 Address Alias Prevention
          7. 8.2.4.1.7 Data Error Detection and Correction
          8. 8.2.4.1.8 AXI Bus Timeout
        2. 8.2.4.2 DDRSS Interrupts
        3. 8.2.4.3 DDRSS Memory Regions
        4. 8.2.4.4 DDRSS ECC Support
        5. 8.2.4.5 DDRSS Dynamic Frequency Change Interface
        6. 8.2.4.6 DDR Controller Functional Description
          1. 8.2.4.6.1  DDR PHY Interface (DFI)
          2. 8.2.4.6.2  Command Queue
            1. 8.2.4.6.2.1 Placement Logic
            2. 8.2.4.6.2.2 Command Selection Logic
          3. 8.2.4.6.3  Low Power Control
          4. 8.2.4.6.4  Transaction Processing
          5. 8.2.4.6.5  BIST Engine
          6. 8.2.4.6.6  ECC Engine
          7. 8.2.4.6.7  Address Mapping
          8. 8.2.4.6.8  Paging Policy
          9. 8.2.4.6.9  DDR Controller Initialization
          10. 8.2.4.6.10 Programming LPDDR4 Memories
            1. 8.2.4.6.10.1 Frequency Set Point (FSP)
              1. 8.2.4.6.10.1.1 FSP Mode Register Programming During Initialization
              2. 8.2.4.6.10.1.2 FSP Mode Register Programming During Normal Operation
              3. 8.2.4.6.10.1.3 FSP Mode Register Programming During Dynamic Frequency Scaling
            2. 8.2.4.6.10.2 Data Bus Inversion (DBI)
            3. 8.2.4.6.10.3 On-Die Termination
              1. 8.2.4.6.10.3.1 LPDDR4 DQ ODT
              2. 8.2.4.6.10.3.2 LPDDR4 CA ODT
            4. 8.2.4.6.10.4 Byte Lane Swapping
            5. 8.2.4.6.10.5 DQS Interval Oscillator
              1. 8.2.4.6.10.5.1 Oscillator State Machine
            6. 8.2.4.6.10.6 Per-Bank Refresh (PBR)
              1. 8.2.4.6.10.6.1 Normal Operation
              2. 8.2.4.6.10.6.2 Continuous Refresh Request Mode
        7. 8.2.4.7 DDR PHY Functional Description
          1. 8.2.4.7.1  Data Slice
          2. 8.2.4.7.2  Address Slice
            1. 8.2.4.7.2.1 Address Swapping
          3. 8.2.4.7.3  Address/Control Slice
          4. 8.2.4.7.4  Clock Slice
          5. 8.2.4.7.5  DDR PHY Initialization
          6. 8.2.4.7.6  DDR PHY Dynamic Frequency Scaling (DFS)
          7. 8.2.4.7.7  Chip Select and Frequency Based Register Settings
          8. 8.2.4.7.8  Low-Power Modes
          9. 8.2.4.7.9  Training Support
            1. 8.2.4.7.9.1 Write Leveling
            2. 8.2.4.7.9.2 Read Gate Training
            3. 8.2.4.7.9.3 Read Data Eye Training
            4. 8.2.4.7.9.4 Write DQ Training
            5. 8.2.4.7.9.5 CA Training
            6. 8.2.4.7.9.6 CS Training
          10. 8.2.4.7.10 Data Bus Inversion (DBI)
          11. 8.2.4.7.11 I/O Pad Calibration
          12. 8.2.4.7.12 DQS Error
        8. 8.2.4.8 PI Functional Description
          1. 8.2.4.8.1 PI Initialization
      5. 8.2.5 DDRSS Registers
        1. 8.2.5.1 DDR Subsystem Registers
        2. 8.2.5.2 DDR Controller Registers
        3. 8.2.5.3 PI Registers
        4. 8.2.5.4 DDR PHY Registers
        5. 8.2.5.5 DDRSS0_ECC_AGGR_CTL Registers
        6. 8.2.5.6 DDRSS0_ECC_AGGR_VBUS Registers
        7. 8.2.5.7 DDRSS0_ECC_AGGR_CFG Registers
    3. 8.3 Peripheral Virtualization Unit (PVU)
      1. 8.3.1 PVU Overview
        1. 8.3.1.1 PVU Features
        2. 8.3.1.2 PVU Parameters
        3. 8.3.1.3 PVU Not Supported Features
      2. 8.3.2 PVU Integration
      3. 8.3.3 PVU Functional Description
        1. 8.3.3.1  Functional Operation Overview
        2. 8.3.3.2  PVU Channels
        3. 8.3.3.3  TLB
        4. 8.3.3.4  TLB Entry
        5. 8.3.3.5  TLB Selection
        6. 8.3.3.6  DMA Classes
        7. 8.3.3.7  General virtIDs
        8. 8.3.3.8  TLB Lookup
        9. 8.3.3.9  TLB Miss
        10. 8.3.3.10 Multiple Matching Entries
        11. 8.3.3.11 TLB Disable
        12. 8.3.3.12 TLB Chaining
        13. 8.3.3.13 TLB Permissions
        14. 8.3.3.14 Translation
        15. 8.3.3.15 Memory Attributes
        16. 8.3.3.16 Faulted Transactions
        17. 8.3.3.17 Non-Virtual Transactions
        18. 8.3.3.18 Allowed virtIDs
        19. 8.3.3.19 Software Control
        20. 8.3.3.20 Fault Logging
        21. 8.3.3.21 Alignment Restrictions
      4. 8.3.4 PVU Registers
        1. 8.3.4.1 NAVSS_PVU_CFG Registers
        2. 8.3.4.2 NAVSS0_PVU_CFG_TLBIF Registers
    4. 8.4 Region-based Address Translation (RAT) Module
      1. 8.4.1 RAT Functional Description
        1. 8.4.1.1 RAT Availability
        2. 8.4.1.2 RAT Operation
        3. 8.4.1.3 RAT Error Logging
      2. 8.4.2 RAT Registers
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GIC)
        1. 9.2.1.1 GIC Overview
          1. 9.2.1.1.1 GIC Features
          2. 9.2.1.1.2 GIC Not Supported Features
        2. 9.2.1.2 GIC Integration
        3. 9.2.1.3 GIC Functional Description
          1. 9.2.1.3.1 GIC Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GIC Interrupt Types
          4. 9.2.1.3.4 GIC Interfaces
          5. 9.2.1.3.5 GIC Interrupt Outputs
          6. 9.2.1.3.6 GIC ECC Support
          7. 9.2.1.3.7 GIC AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GIC Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GIC_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 WKUP_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
        3. 9.3.2.3 MAIN2MCU_LVL_INTRTR0 Integration
        4. 9.3.2.4 MAIN2MCU_PLS_INTRTR0 Integration
      3. 9.3.3 INTRTR Registers
        1. 9.3.3.1 WKUP_GPIOMUX_INTRTR0 Registers
        2. 9.3.3.2 GPIOMUX_INTRTR0 Registers
        3. 9.3.3.3 MAIN2MCU_LVL_INTRTR0 Registers
        4. 9.3.3.4 MAIN2MCU_PLS_INTRTR0 Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1 WKUP Domain Interrupt Maps
        1. 9.4.1.1 WKUP_DMSC0 Interrupt Map
        2. 9.4.1.2 WKUP_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.1.3 WKUP_GPIO0_VIRT Interrupt Map
        4. 9.4.1.4 WKUP_ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_R5FSS0_CORE0 Interrupt Map
        2. 9.4.2.2 MCU_R5FSS0_CORE1 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
      3. 9.4.3 MAIN Domain Interrupt Maps
        1. 9.4.3.1 COMPUTE_CLUSTER0 Interrupt Map
          1. 9.4.3.1.1 GIC500 PPI Interrupt Map
          2. 9.4.3.1.2 GIC500 SPI Interrupt Map
          3. 9.4.3.1.3 SoC Event Output Interrupt Map
        2. 9.4.3.2 R5FSS0_CORE0 Interrupt Map
        3. 9.4.3.3 R5FSS0_CORE1 Interrupt Map
        4. 9.4.3.4 MAIN2MCU_LVL_INTRTR0 Interrupt Map
        5. 9.4.3.5 MAIN2MCU_PLS_INTRTR0 Interrupt Map
        6. 9.4.3.6 GPIOMUX_INTRTR0 Interrupt Map
        7. 9.4.3.7 GPIO0_VIRT Interrupt Map
        8. 9.4.3.8 ESM0 Interrupt Map
  12. 10Data Movement Architecture (DMA)
    1. 10.1 DMA Architecture
      1. 10.1.1 Overview
        1. 10.1.1.1  Navigator Subsystem
        2. 10.1.1.2  Ring Accelerator (RA)
        3. 10.1.1.3  Proxy
        4. 10.1.1.4  Secure Proxy
        5. 10.1.1.5  Interrupt Aggregator (INTA)
        6. 10.1.1.6  Interrupt Router (IR)
        7. 10.1.1.7  Unified DMA – Third Party Channel Controller (UDMA-C)
        8. 10.1.1.8  Unified Transfer Controller (UTC)
        9. 10.1.1.9  Data Routing Unit (DRU)
        10. 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
          1. 10.1.1.10.1 Channel Classes
        11. 10.1.1.11 Peripheral DMA (PDMA)
        12. 10.1.1.12 Embedded DMA
        13. 10.1.1.13 Definition of Terms
      2. 10.1.2 UDMA Hardware/Software Interface
        1. 10.1.2.1 Data Buffers
        2. 10.1.2.2 Descriptors
          1. 10.1.2.2.1 Host Packet Descriptor
          2. 10.1.2.2.2 Host Buffer Descriptor
          3. 10.1.2.2.3 Monolithic Packet Descriptor
          4. 10.1.2.2.4 Transfer Request Descriptor
        3. 10.1.2.3 Transfer Request Record
          1. 10.1.2.3.1 Overview
          2. 10.1.2.3.2 Addressing Algorithm
            1. 10.1.2.3.2.1 Linear Addressing (Forward)
          3. 10.1.2.3.3 Transfer Request Formats
          4. 10.1.2.3.4 Flags Field Definition
            1. 10.1.2.3.4.1 Type: TR Type Field
            2. 10.1.2.3.4.2 STATIC: Static Field Definition
            3. 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
            4. 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
            5. 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
            6. 10.1.2.3.4.6 TRIGGERX: Trigger Selection
            7. 10.1.2.3.4.7 CMD ID: Command ID Field Definition
            8. 10.1.2.3.4.8 Configuration Specific Flags Definition
          5. 10.1.2.3.5 TR Address and Size Attributes
            1. 10.1.2.3.5.1  ICNT0
            2. 10.1.2.3.5.2  ICNT1
            3. 10.1.2.3.5.3  ADDR
            4. 10.1.2.3.5.4  DIM1
            5. 10.1.2.3.5.5  ICNT2
            6. 10.1.2.3.5.6  ICNT3
            7. 10.1.2.3.5.7  DIM2
            8. 10.1.2.3.5.8  DIM3
            9. 10.1.2.3.5.9  DDIM1
            10. 10.1.2.3.5.10 DADDR
            11. 10.1.2.3.5.11 DDIM2
            12. 10.1.2.3.5.12 DDIM3
            13. 10.1.2.3.5.13 DICNT0
            14. 10.1.2.3.5.14 DICNT1
            15. 10.1.2.3.5.15 DICNT2
            16. 10.1.2.3.5.16 DICNT3
          6. 10.1.2.3.6 FMTFLAGS
            1. 10.1.2.3.6.1 AMODE: Addressing Mode Definition
              1. 10.1.2.3.6.1.1 Linear Addressing
              2. 10.1.2.3.6.1.2 Circular Addressing
            2. 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
            3. 10.1.2.3.6.3 ELTYPE: Element Type Definition
            4. 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
            5. 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
              1. 10.1.2.3.6.5.1 Secondary TR Formats
              2. 10.1.2.3.6.5.2 Secondary TR FLAGS
                1. 10.1.2.3.6.5.2.1 SEC_TR_TYPE: Secondary TR Type Field
                2. 10.1.2.3.6.5.2.2 Multiple Buffer Interleave
            6. 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
              1. 10.1.2.3.6.6.1 Circular Address Mode Specific Flags
                1. 10.1.2.3.6.6.1.1 CBK0 and CBK1: Circular Block Size Selection
                2. 10.1.2.3.6.6.1.2 Amx: Addressing Mode Selection
            7. 10.1.2.3.6.7 Cache Flags
        4. 10.1.2.4 Transfer Response Record
          1. 10.1.2.4.1 STATUS Field Definition
            1. 10.1.2.4.1.1 STATUS_TYPE Definition
              1. 10.1.2.4.1.1.1 Transfer Error
              2. 10.1.2.4.1.1.2 Aborted Error
              3. 10.1.2.4.1.1.3 Submission Error
              4. 10.1.2.4.1.1.4 Unsupported Feature
              5. 10.1.2.4.1.1.5 Transfer Exception
              6. 10.1.2.4.1.1.6 Teardown Flush
        5. 10.1.2.5 Queues
          1. 10.1.2.5.1 Queue Types
            1. 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
            2. 10.1.2.5.1.2 Transmit Queues (Pass By Value)
            3. 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
            4. 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
            5. 10.1.2.5.1.5 Receive Queues
            6. 10.1.2.5.1.6 Free Descriptor Queues
            7. 10.1.2.5.1.7 Free Descriptor/Buffer Queues
          2. 10.1.2.5.2 Ring Accelerator Queues Implementation
      3. 10.1.3 Operational Description
        1. 10.1.3.1  Resource Allocation
        2. 10.1.3.2  Ring Accelerator Operation
          1. 10.1.3.2.1 Queue Initialization
          2. 10.1.3.2.2 Queuing packets (Exposed Ring Mode)
          3. 10.1.3.2.3 De-queuing packets (Exposed Ring Mode)
          4. 10.1.3.2.4 Queuing packets (Queue Mode)
          5. 10.1.3.2.5 De-queuing packets (Queue Mode)
        3. 10.1.3.3  UDMA Internal Transmit Channel Setup (All Packet Types)
        4. 10.1.3.4  UDMA Internal Transmit Channel Teardown (All Packet Types)
        5. 10.1.3.5  UDMA External Transmit Channel Setup
        6. 10.1.3.6  UDMA Transmit External Channel Teardown
        7. 10.1.3.7  UDMA-P Transmit Channel Pause
        8. 10.1.3.8  UDMA-P Transmit Operation (Host Packet Type)
        9. 10.1.3.9  UDMA-P Transmit Operation (Monolithic Packet)
        10. 10.1.3.10 UDMA Transmit Operation (TR Packet)
        11. 10.1.3.11 UDMA Transmit Operation (Direct TR)
        12. 10.1.3.12 UDMA Transmit Error/Exception Handling
          1. 10.1.3.12.1 Null Icnt0 Error
          2. 10.1.3.12.2 Unsupported TR Type
          3. 10.1.3.12.3 Bus Errors
        13. 10.1.3.13 UDMA Receive Channel Setup (All Packet Types)
        14. 10.1.3.14 UDMA Receive Channel Teardown
        15. 10.1.3.15 UDMA-P Receive Channel Pause
        16. 10.1.3.16 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
        17. 10.1.3.17 UDMA-P Receive FlowID Firewall Operation
        18. 10.1.3.18 UDMA-P Receive Operation (Host Packet)
        19. 10.1.3.19 UDMA-P Receive Operation (Monolithic Packet)
        20. 10.1.3.20 UDMA Receive Operation (TR Packet)
        21. 10.1.3.21 UDMA Receive Operation (Direct TR)
        22. 10.1.3.22 UDMA Receive Error/Exception Handling
          1. 10.1.3.22.1 Error Conditions
            1. 10.1.3.22.1.1 Bus Errors
            2. 10.1.3.22.1.2 Null Icnt0 Error
            3. 10.1.3.22.1.3 Unsupported TR Type
          2. 10.1.3.22.2 Exception Conditions Exception Conditions
            1. 10.1.3.22.2.1 Descriptor Starvation
            2. 10.1.3.22.2.2 Protocol Errors
            3. 10.1.3.22.2.3 Dropped Packets
            4. 10.1.3.22.2.4 Reception of EOL Delimiter
            5. 10.1.3.22.2.5 EOP Asserted Prematurely (Short Packet)
            6. 10.1.3.22.2.6 EOP Asserted Late (Long Packets)
        23. 10.1.3.23 UTC Operation
        24. 10.1.3.24 UTC Receive Error/Exception Handling
          1. 10.1.3.24.1 Error Handling
            1. 10.1.3.24.1.1 Null Icnt0 Error
            2. 10.1.3.24.1.2 Unsupported TR Type
          2. 10.1.3.24.2 Exception Conditions
            1. 10.1.3.24.2.1 Reception of EOL Delimiter
            2. 10.1.3.24.2.2 EOP Asserted Prematurely (Short Packet)
            3. 10.1.3.24.2.3 EOP Asserted Late (Long Packets)
    2. 10.2 Navigator Subsystem (NAVSS)
      1. 10.2.1  Main Navigator Subsystem (NAVSS)
        1. 10.2.1.1 NAVSS Overview
        2. 10.2.1.2 NAVSS Integration
          1. 10.2.1.2.1 NAVSS Interrupt Router Configuration
          2. 10.2.1.2.2 Global Event Map
          3. 10.2.1.2.3 PSI-L System Thread Map (All NAVSS)
          4. 10.2.1.2.4 NAVSS VBUSM Route ID Table
        3. 10.2.1.3 NAVSS Functional Description
        4. 10.2.1.4 NAVSS Interrupt Configuration
          1. 10.2.1.4.1 NAVSS Event and Interrupt Flow
            1. 10.2.1.4.1.1 NAVSS Interrupts Description
            2. 10.2.1.4.1.2 Application Example
        5. 10.2.1.5 NAVSS Top-level Registers
          1. 10.2.1.5.1 NAVSS0_CFG Registers
          2. 10.2.1.5.2 INTR0_INTR_ROUTER_CFG Registers
          3. 10.2.1.5.3 VIRTID_CFG_MMRS Registers
      2. 10.2.2  MCU Navigator Subsystem (MCU NAVSS)
        1. 10.2.2.1 MCU NAVSS Overview
        2. 10.2.2.2 MCU NAVSS Integration
          1. 10.2.2.2.1  MCU NAVSS Interrupt Router Configuration
          2. 10.2.2.2.2  MCU NAVSS UDMASS Interrupt Aggregator Configuration
          3. 10.2.2.2.3  MCU NAVSS UDMA Configuration
          4. 10.2.2.2.4  MCU NAVSS Ring Accelerator Configuration
          5. 10.2.2.2.5  MCU NAVSS Proxy Configuration
          6. 10.2.2.2.6  MCU NAVSS Secure Proxy Configuration
          7. 10.2.2.2.7  Global Event Map
          8. 10.2.2.2.8  PSI-L System Thread Map (All NAVSS)
          9. 10.2.2.2.9  MCU NAVSS VBUSM Route ID Table
          10. 10.2.2.2.10 1006
        3. 10.2.2.3 MCU NAVSS Functional Description
        4. 10.2.2.4 MCU NAVSS Top-Level Registers
          1. 10.2.2.4.1 MCU_NAVSS0_CFG Registers
          2. 10.2.2.4.2 MCU_NAVSS0_UDMASS_ECCAGGR0 Registers
      3. 10.2.3  Unified DMA Controller (UDMA)
        1. 10.2.3.1 UDMA Overview
          1. 10.2.3.1.1 UDMA Features
          2. 10.2.3.1.2 UDMA Parameters
        2. 10.2.3.2 UDMA Integration
        3. 10.2.3.3 UDMA Functional Description
          1. 10.2.3.3.1 Block Diagram
          2. 10.2.3.3.2 General Functionality
            1. 10.2.3.3.2.1  Operational States
            2. 10.2.3.3.2.2  Tx Channel Allocation
            3. 10.2.3.3.2.3  Rx Channel Allocation
            4. 10.2.3.3.2.4  Tx Teardown
            5. 10.2.3.3.2.5  Rx Teardown
            6. 10.2.3.3.2.6  Tx Clock Stop
            7. 10.2.3.3.2.7  Rx Clock Stop
            8. 10.2.3.3.2.8  Rx Thread Enables
            9. 10.2.3.3.2.9  Events
              1. 10.2.3.3.2.9.1 Local Event Inputs
              2. 10.2.3.3.2.9.2 Inbound Tx PSI-L Events
              3. 10.2.3.3.2.9.3 Outbound Rx PSI-L Events
            10. 10.2.3.3.2.10 Emulation Control
          3. 10.2.3.3.3 Packet Oriented Transmit Operation
            1. 10.2.3.3.3.1 Packet Mode VBUSM Master Interface Command ID Selection
          4. 10.2.3.3.4 Packet Oriented Receive Operation
            1. 10.2.3.3.4.1 Rx Packet Drop
            2. 10.2.3.3.4.2 Rx Starvation and the Starvation Timer
          5. 10.2.3.3.5 Third Party Mode Operation
            1. 10.2.3.3.5.1 Events and Flow Control
              1. 10.2.3.3.5.1.1 Channel Triggering
              2. 10.2.3.3.5.1.2 Internal TR Completion Events
            2. 10.2.3.3.5.2 Transmit Operation
              1. 10.2.3.3.5.2.1 Transfer Request
              2. 10.2.3.3.5.2.2 Transfer Response
              3. 10.2.3.3.5.2.3 Data Transfer
              4. 10.2.3.3.5.2.4 Memory Interface Transactions
              5. 10.2.3.3.5.2.5 Error Handling
            3. 10.2.3.3.5.3 Receive Operation
              1. 10.2.3.3.5.3.1 Transfer Request
              2. 10.2.3.3.5.3.2 Transfer Response
              3. 10.2.3.3.5.3.3 Error Handling
            4. 10.2.3.3.5.4 Data Transfer
              1. 10.2.3.3.5.4.1 Memory Interface Transactions
              2. 10.2.3.3.5.4.2 Rx Packet Drop
        4. 10.2.3.4 UDMA Registers
          1. 10.2.3.4.1 UDMASS_UDMAP0_CFG Registers
          2. 10.2.3.4.2 UDMASS_UDMAP0_CFG_TCHAN Registers
          3. 10.2.3.4.3 UDMASS_UDMAP0_CFG_RCHAN Registers
          4. 10.2.3.4.4 UDMASS_UDMAP0_CFG_RFLOW Registers
          5. 10.2.3.4.5 UDMASS_UDMAP0_CFG_RCHANRT Registers
          6. 10.2.3.4.6 UDMASS_UDMAP0_CFG_TCHANRT Registers
      4. 10.2.4  Ring Accelerator (RINGACC)
        1. 10.2.4.1 RINGACC Overview
          1. 10.2.4.1.1 RINGACC Features
          2. 10.2.4.1.2 RINGACC Not Supported Features
          3. 10.2.4.1.3 RINGACC Parameters
        2. 10.2.4.2 RINGACC Integration
        3. 10.2.4.3 RINGACC Functional Description
          1. 10.2.4.3.1 Block Diagram
            1. 10.2.4.3.1.1  Configuration Registers
            2. 10.2.4.3.1.2  Source Command FIFO
            3. 10.2.4.3.1.3  Source Write Data FIFO
            4. 10.2.4.3.1.4  Source Read Data FIFO
            5. 10.2.4.3.1.5  Source Write Status FIFO
            6. 10.2.4.3.1.6  Main State Machine
            7. 10.2.4.3.1.7  Destination Command FIFO
            8. 10.2.4.3.1.8  Destination Write Data FIFO
            9. 10.2.4.3.1.9  Destination Read Data FIFO
            10. 10.2.4.3.1.10 Destination Write Status FIFO
          2. 10.2.4.3.2 RINGACC Functional Operation
            1. 10.2.4.3.2.1 Queue Modes
              1. 10.2.4.3.2.1.1 Ring Mode
              2. 10.2.4.3.2.1.2 Messaging Mode
              3. 10.2.4.3.2.1.3 Credentials Mode
              4. 10.2.4.3.2.1.4 Queue Manager Mode
              5. 10.2.4.3.2.1.5 Peek Support
              6. 10.2.4.3.2.1.6 Index Register Operation
            2. 10.2.4.3.2.2 VBUSM Slave Ring Operations
            3. 10.2.4.3.2.3 VBUSM Master Interface Command ID Selection
            4. 10.2.4.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 10.2.4.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 10.2.4.3.2.6 Host Doorbell Access
            7. 10.2.4.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 10.2.4.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 10.2.4.3.2.9 Mismatched Element Size Handling
          3. 10.2.4.3.3 Events
          4. 10.2.4.3.4 Bus Error Handling
          5. 10.2.4.3.5 Monitors
            1. 10.2.4.3.5.1 Threshold Monitor
            2. 10.2.4.3.5.2 Watermark Monitor
            3. 10.2.4.3.5.3 Starvation Monitor
            4. 10.2.4.3.5.4 Statistics Monitor
            5. 10.2.4.3.5.5 Overflow
            6. 10.2.4.3.5.6 Ring Update Port
            7. 10.2.4.3.5.7 Tracing
        4. 10.2.4.4 RINGACC Registers
          1. 10.2.4.4.1 NAVSS0_UDMASS_RINGACC0_CFG Registers
          2. 10.2.4.4.2 NAVSS0_UDMASS_RINGACC0_GCFG Registers
          3. 10.2.4.4.3 NAVSS0_UDMASS_RINGACC0_CFG_MON Registers
          4. 10.2.4.4.4 NAVSS0_UDMASS_RINGACC0_CFG_RT Registers
          5. 10.2.4.4.5 NAVSS0_UDMASS_RINGACC0_SRC_FIFOS Registers
      5. 10.2.5  Proxy
        1. 10.2.5.1 Proxy Overview
          1. 10.2.5.1.1 Proxy Features
          2. 10.2.5.1.2 Proxy Parameters
          3. 10.2.5.1.3 Proxy Not Supported Features
        2. 10.2.5.2 Proxy Integration
        3. 10.2.5.3 Proxy Functional Description
          1. 10.2.5.3.1  Targets
            1. 10.2.5.3.1.1 Ring Accelerator
          2. 10.2.5.3.2  Proxy Sizes
          3. 10.2.5.3.3  Proxy Interleaving
          4. 10.2.5.3.4  Proxy Host States
          5. 10.2.5.3.5  Proxy Host Channel Selection
          6. 10.2.5.3.6  Proxy Host Access
            1. 10.2.5.3.6.1 Proxy Host Writes
            2. 10.2.5.3.6.2 Proxy Host Reads
          7. 10.2.5.3.7  Permission Inheritance
          8. 10.2.5.3.8  Buffer Size
          9. 10.2.5.3.9  Error Events
          10. 10.2.5.3.10 Debug Reads
        4. 10.2.5.4 Proxy Registers
          1. 10.2.5.4.1 NAVSS0_PROXY0_CFG_BUF_CFG Registers
          2. 10.2.5.4.2 NAVSS0_PROXY0_BUF_CFG Registers
          3. 10.2.5.4.3 NAVSS0_PROXY_BUF Registers
          4. 10.2.5.4.4 NAVSS0_PROXY_TARGET0_DATA Registers
      6. 10.2.6  Secure Proxy
        1. 10.2.6.1 Secure Proxy Overview
          1. 10.2.6.1.1 Secure Proxy Features
          2. 10.2.6.1.2 Secure Proxy Parameters
          3. 10.2.6.1.3 Secure Proxy Not Supported Features
        2. 10.2.6.2 Secure Proxy Integration
        3. 10.2.6.3 Secure Proxy Functional Description
          1. 10.2.6.3.1  Targets
            1. 10.2.6.3.1.1 Ring Accelerator
          2. 10.2.6.3.2  Buffers
            1. 10.2.6.3.2.1 Proxy Credits
            2. 10.2.6.3.2.2 Proxy Private Word
            3. 10.2.6.3.2.3 Completion Byte
          3. 10.2.6.3.3  Proxy Thread Sizes
          4. 10.2.6.3.4  Proxy Thread Interleaving
          5. 10.2.6.3.5  Proxy States
          6. 10.2.6.3.6  Proxy Host Access
            1. 10.2.6.3.6.1 Proxy Host Writes
            2. 10.2.6.3.6.2 Proxy Host Reads
            3. 10.2.6.3.6.3 Buffer Accesses
            4. 10.2.6.3.6.4 Target Access
            5. 10.2.6.3.6.5 Error State
          7. 10.2.6.3.7  Permission Inheritance
          8. 10.2.6.3.8  Resource Association
          9. 10.2.6.3.9  Direction
          10. 10.2.6.3.10 Threshold Events
          11. 10.2.6.3.11 Error Events
          12. 10.2.6.3.12 Bus Errors and Credits
          13. 10.2.6.3.13 Debug
        4. 10.2.6.4 Secure Proxy Registers
          1. 10.2.6.4.1 NAVSS0_SEC_PROXY0_CFG_MMRS Registers
          2. 10.2.6.4.2 NAVSS0_SEC_PROXY0_CFG_RT Registers
          3. 10.2.6.4.3 NAVSS0_SEC_PROXY0_CFG_SCFG Registers
          4. 10.2.6.4.4 NAVSS0_SEC_PROXY0_SRC_TARGET_DATA Registers
      7. 10.2.7  Interrupt Aggregator (INTR_AGGR)
        1. 10.2.7.1 INTR_AGGR Overview
          1. 10.2.7.1.1 INTR_AGGR Features
          2. 10.2.7.1.2 INTR_AGGR Parameters
        2. 10.2.7.2 INTR_AGGR Integration
        3. 10.2.7.3 INTR_AGGR Functional Description
          1. 10.2.7.3.1 Submodule Descriptions
            1. 10.2.7.3.1.1 Status/Mask Registers
            2. 10.2.7.3.1.2 Interrupt Mapping Block
            3. 10.2.7.3.1.3 Global Event Input (GEVI) Counters
            4. 10.2.7.3.1.4 Local Event Input (LEVI) to Global Event Conversion
            5. 10.2.7.3.1.5 Global Event Multicast
          2. 10.2.7.3.2 General Functionality
            1. 10.2.7.3.2.1 Event to Interrupt Bit Steering
            2. 10.2.7.3.2.2 Interrupt Status
            3. 10.2.7.3.2.3 Interrupt Masked Status
            4. 10.2.7.3.2.4 Enabling/Disabling Individual Interrupt Source Bits
            5. 10.2.7.3.2.5 Interrupt Output Generation
            6. 10.2.7.3.2.6 Global Event Counting
            7. 10.2.7.3.2.7 Local Event to Global Event Conversion
            8. 10.2.7.3.2.8 Global Event Multicast
        4. 10.2.7.4 INTR_AGGR Registers
          1. 10.2.7.4.1  MODSS_INTA_CFG Registers
          2. 10.2.7.4.2  MODSS_INTA_CFG_IMAP Registers
          3. 10.2.7.4.3  MODSS_INTA_CFG_INTR Registers
          4. 10.2.7.4.4  UDMASS_INTA0_CFG Registers
          5. 10.2.7.4.5  UDMASS_INTA0_CFG_INTR Registers
          6. 10.2.7.4.6  UDMASS_INTA0_CFG_IMAP Registers
          7. 10.2.7.4.7  UDMASS_INTA0_CFG_L2G Registers
          8. 10.2.7.4.8  UDMASS_INTA0_CFG_MCAST Registers
          9. 10.2.7.4.9  UDMASS_INTA0_CFG_GCNTCFG Registers
          10. 10.2.7.4.10 UDMASS_INTA0_CFG_GCNTRTI Registers
      8. 10.2.8  Packet Streaming Interface Link (PSI-L)
        1. 10.2.8.1 PSI-L Overview
        2. 10.2.8.2 PSI-L Functional Description
          1. 10.2.8.2.1 PSI-L Introduction
          2. 10.2.8.2.2 PSI-L Operation
            1. 10.2.8.2.2.1 Event Transport
            2. 10.2.8.2.2.2 Threads
            3. 10.2.8.2.2.3 Arbitration Protocol
            4. 10.2.8.2.2.4 Thread Configuration
              1. 10.2.8.2.2.4.1 Thread Pairing
                1. 10.2.8.2.2.4.1.1 Configuration Transaction Pairing
              2. 10.2.8.2.2.4.2 Configuration Registers Region
        3. 10.2.8.3 PSI-L Configuration Registers
        4. 10.2.8.4 PSI-L CFG_PROXY Registers
      9. 10.2.9  PSIL Subsystem (PSILSS)
        1. 10.2.9.1 PSILSS Overview
          1. 10.2.9.1.1 PSILSS Features
        2. 10.2.9.2 PSILSS Functional Description
          1. 10.2.9.2.1 PSILSS Basic Operation
          2. 10.2.9.2.2 PSILSS Event Routing
          3. 10.2.9.2.3 PSILSS Link Down Detection
          4. 10.2.9.2.4 PSILSS Configuration
        3. 10.2.9.3 PSILSS Registers
          1. 10.2.9.3.1 PDMA_USART_PSILSS0 Registers
          2. 10.2.9.3.2 PDMA_SPI_PSILSS0 Registers
      10. 10.2.10 NAVSS North Bridge (NB)
        1. 10.2.10.1 NB Overview
          1. 10.2.10.1.1 Features Supported
          2. 10.2.10.1.2 NB Parameters
            1. 10.2.10.1.2.1 Compliance to Standards
            2. 10.2.10.1.2.2 Features Not Supported
        2. 10.2.10.2 NB Functional Description
          1. 10.2.10.2.1  VBUSM Slave Interfaces
          2. 10.2.10.2.2  VBUSM Master Interface
          3. 10.2.10.2.3  VBUSM.C Interfaces
            1. 10.2.10.2.3.1 Multi-Threading
            2. 10.2.10.2.3.2 Write Command Crediting
            3. 10.2.10.2.3.3 Early Credit Response
            4. 10.2.10.2.3.4 Priority Escalation
          4. 10.2.10.2.4  Source M2M Bridges
          5. 10.2.10.2.5  Destination M2M Bridge
          6. 10.2.10.2.6  M2C Bridge
          7. 10.2.10.2.7  Memory Attribute Tables
          8. 10.2.10.2.8  Outstanding Read Data Limiter
          9. 10.2.10.2.9  Ordering
          10. 10.2.10.2.10 Quality of Service
          11. 10.2.10.2.11 IDLE Behavior
          12. 10.2.10.2.12 Clock Power Management
        3. 10.2.10.3 NB Registers
          1. 10.2.10.3.1 NAVSS0_NBSS_CFG_REGS0_MMRS Registers
          2. 10.2.10.3.2 NAVSS0_NBSS_NB_CFG_MMRS Registers
    3. 10.3 Peripheral DMA (PDMA)
      1. 10.3.1 PDMA Controller
        1. 10.3.1.1 PDMA Overview
          1. 10.3.1.1.1 PDMA Features
            1. 10.3.1.1.1.1  MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
            2. 10.3.1.1.1.2  MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
            3. 10.3.1.1.1.3  MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
            4. 10.3.1.1.1.4  MCU_PDMA3 (MCU_PDMA_ADC) Features
            5. 10.3.1.1.1.5  PDMA2 (PDMA_DEBUG_CCMCU) Features
            6. 10.3.1.1.1.6  PDMA5 (PDMA_MCAN) Features
            7. 10.3.1.1.1.7  PDMA6 (PDMA_MCASP_G0) Features
            8. 10.3.1.1.1.8  PDMA9 (PDMA_SPI_G0) Features
            9. 10.3.1.1.1.9  PDMA10 (PDMA_SPI_G1) Features
            10. 10.3.1.1.1.10 PDMA13 (PDMA_USART_G0) Features
            11. 10.3.1.1.1.11 PDMA14 (PDMA_USART_G1) Features
            12. 10.3.1.1.1.12 PDMA15 (PDMA_USART_G2) Features
        2. 10.3.1.2 PDMA Integration
          1. 10.3.1.2.1 PDMA Integration in MCU Domain
          2. 10.3.1.2.2 PDMA Integration in MAIN Domain
        3. 10.3.1.3 PDMA Functional Description
          1. 10.3.1.3.1 PDMA Functional Blocks
            1. 10.3.1.3.1.1 Scheduler
            2. 10.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 10.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 10.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 10.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 10.3.1.3.2 PDMA General Functionality
            1. 10.3.1.3.2.1 Operational States
            2. 10.3.1.3.2.2 Clock Stop
            3. 10.3.1.3.2.3 Emulation Control
          3. 10.3.1.3.3 PDMA Events and Flow Control
            1. 10.3.1.3.3.1 Channel Types
              1. 10.3.1.3.3.1.1 X-Y FIFO Mode
              2. 10.3.1.3.3.1.2 MCAN Mode
              3. 10.3.1.3.3.1.3 AASRC Mode
              4. 10.3.1.3.3.1.4 1288
            2. 10.3.1.3.3.2 Channel Triggering
            3. 10.3.1.3.3.3 Completion Events
          4. 10.3.1.3.4 PDMA Transmit Operation
            1. 10.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 10.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 10.3.1.3.4.3 Destination Channel Initialization
              1. 10.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 10.3.1.3.4.3.2 Static Transfer Request Setup
              3. 10.3.1.3.4.3.3 1297
              4. 10.3.1.3.4.3.4 PSI-L Destination Thread Enables
            4. 10.3.1.3.4.4 Data Transfer
              1. 10.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 10.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 10.3.1.3.4.4.2 MCAN Mode Channel
                1. 10.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 10.3.1.3.4.4.3 AASRC Mode Channel
            5. 10.3.1.3.4.5 Tx Pause
            6. 10.3.1.3.4.6 Tx Teardown
            7. 10.3.1.3.4.7 Tx Channel Reset
            8. 10.3.1.3.4.8 Tx Debug/State Registers
          5. 10.3.1.3.5 PDMA Receive Operation
            1. 10.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 10.3.1.3.5.2 Source Channel Initialization
              1. 10.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 10.3.1.3.5.2.2 Static Transfer Request Setup
              3. 10.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 10.3.1.3.5.3 Data Transfer
              1. 10.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 10.3.1.3.5.3.2 MCAN Mode Channel
                1. 10.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 10.3.1.3.5.3.3 AASRC Mode Channel
            4. 10.3.1.3.5.4 Rx Pause
            5. 10.3.1.3.5.5 Rx Teardown
            6. 10.3.1.3.5.6 Rx Channel Reset
            7. 10.3.1.3.5.7 Rx Debug/State Register
          6. 10.3.1.3.6 PDMA ECC Support
        4. 10.3.1.4 PDMA Registers
          1. 10.3.1.4.1 PDMA5 ECC Registers
          2. 10.3.1.4.2 PDMA9 ECC Registers
          3. 10.3.1.4.3 PDMA10 ECC Registers
          4. 10.3.1.4.4 PDMA PSI-L TX Configuration Registers
          5. 10.3.1.4.5 PDMA PSI-L RX Configuration Registers
      2. 10.3.2 PDMA Sources
        1. 10.3.2.1 MCU Domain PDMA Event Maps
          1. 10.3.2.1.1 MCU_PDMA_MISC_G0 Event Map
          2. 10.3.2.1.2 MCU_PDMA_MISC_G1 Event Map
          3. 10.3.2.1.3 MCU_PDMA_MISC_G2 Event Map
          4. 10.3.2.1.4 MCU_PDMA_ADC Event Map
        2. 10.3.2.2 MAIN Domain PDMA Event Maps
          1. 10.3.2.2.1 PDMA_DEBUG_CCMCU Event Map
          2. 10.3.2.2.2 PDMA_MCAN Event Map
          3. 10.3.2.2.3 PDMA_MCASP_G0 Event Map
          4. 10.3.2.2.4 PDMA_SPI_G0 Event Map
          5. 10.3.2.2.5 PDMA_SPI_G1 Event Map
          6. 10.3.2.2.6 PDMA_USART_G0 Event Map
          7. 10.3.2.2.7 PDMA_USART_G1 Event Map
          8. 10.3.2.2.8 PDMA_USART_G2 Event Map
  13. 11Time Sync
    1. 11.1 Time Sync Module (CPTS)
      1. 11.1.1 CPTS Overview
        1. 11.1.1.1 CPTS Features
        2. 11.1.1.2 CPTS Not Supported Features
      2. 11.1.2 CPTS Integration
      3. 11.1.3 CPTS Functional Description
        1. 11.1.3.1  CPTS Architecture
        2. 11.1.3.2  CPTS Initialization
        3. 11.1.3.3  32-bit Time Stamp Value
        4. 11.1.3.4  64-bit Time Stamp Value
          1. 11.1.3.4.1 64-Bit Timestamp Nudge
          2. 11.1.3.4.2 64-bit Timestamp PPM
        5. 11.1.3.5  Event FIFO
        6. 11.1.3.6  Timestamp Compare Output
          1. 11.1.3.6.1 Non-Toggle Mode
          2. 11.1.3.6.2 Toggle Mode
        7. 11.1.3.7  Timestamp Sync Output
        8. 11.1.3.8  Timestamp GENF Output
          1. 11.1.3.8.1 GENFn Nudge
          2. 11.1.3.8.2 GENFn PPM
        9. 11.1.3.9  Time Sync Events
          1. 11.1.3.9.1 Time Stamp Push Event
          2. 11.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 11.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 11.1.3.9.4 Hardware Time Stamp Push Event
        10. 11.1.3.10 Timestamp Compare Event
        11. 11.1.3.11 CPTS Interrupt Handling
      4. 11.1.4 CPTS Registers
    2. 11.2 Timer Manager
      1. 11.2.1 Timer Manager Overview
        1. 11.2.1.1 Timer Manager Features
        2. 11.2.1.2 Timer Manager Not Supported Features
      2. 11.2.2 Timer Manager Integration
      3. 11.2.3 Timer Manager Functional Description
        1. 11.2.3.1 Timer Manager Function Overview
        2. 11.2.3.2 Timer Counter
          1. 11.2.3.2.1 Timer Counter Rollover
        3. 11.2.3.3 Timer Control Module (FSM)
        4. 11.2.3.4 Timer Reprogramming
          1. 11.2.3.4.1 Periodic Hardware Timers
        5. 11.2.3.5 Event FIFO
        6. 11.2.3.6 Output Event Lookup (OES RAM)
      4. 11.2.4 Timer Manager Programming Guide
        1. 11.2.4.1 Timer Manager Low-level Programming Models
          1. 11.2.4.1.1 Surrounding Modules Global Initialization
          2. 11.2.4.1.2 Initialization Sequence
          3. 11.2.4.1.3 Real-time Operating Requirements
            1. 11.2.4.1.3.1 Timer Touch
            2. 11.2.4.1.3.2 Timer Disable
            3. 11.2.4.1.3.3 Timer Enable
          4. 11.2.4.1.4 Power Up/Power Down Sequence
      5. 11.2.5 Timer Manager Registers
        1. 11.2.5.1 TIMERMGR_CFG_CFG Registers
        2. 11.2.5.2 TIMERMGR_CFG_OES Registers
        3. 11.2.5.3 TIMERMGR_CFG_TIMERS Registers
    3. 11.3 Time Sync and Compare Events
      1. 11.3.1 Time Sync Architecture
        1. 11.3.1.1 Time Sync Architecture Overview
      2. 11.3.2 Time Sync Routers
        1. 11.3.2.1 Time Sync Routers Overview
        2. 11.3.2.2 Time Sync Routers Integration
          1. 11.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 11.3.2.2.2 CMPEVT_INTRTR0 Integration
        3. 11.3.2.3 Time Sync Routers Registers
          1. 11.3.2.3.1 TIMESYNC_INTRTR0 Registers
          2. 11.3.2.3.2 CMPEVT_INTRTR0 Registers
      3. 11.3.3 Time Sync Event Sources
        1. 11.3.3.1 CMPEVT_INTRTR0 Event Map
        2. 11.3.3.2 TIMESYNC_INTRTR0 Event Map
        3. 11.3.3.3 DMSS0 Sync Event Map
        4. 11.3.3.4 PCIE1 Sync Event Map
        5. 11.3.3.5 MCU_CPSW0 Sync Event Map
        6. 11.3.3.6 CPSW0 Sync Event Map
        7. 11.3.3.7 I/O Sync Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MCU Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
        6. 12.1.1.6 ADC Registers
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in WKUP Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO DeepSleep Mode
          6. 12.1.2.4.6 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
        6. 12.1.2.6 GPIO Registers
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 1501
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in WKUP Domain
          2. 12.1.3.3.2 I2C Integration in MCU Domain
          3. 12.1.3.3.3 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
        6. 12.1.3.6 I2C Registers
      4. 12.1.4 Improved Inter-Integrated Circuit (I3C) Interface
        1. 12.1.4.1 I3C Overview
          1. 12.1.4.1.1 I3C Features
          2. 12.1.4.1.2 I3C Not Supported Features
        2. 12.1.4.2 I3C Environment
          1. 12.1.4.2.1 I3C Typical Application
            1. 12.1.4.2.1.1 I3C Pins for Typical Connections
            2. 12.1.4.2.1.2 I3C Interface Typical Connections
            3. 12.1.4.2.1.3 1555
        3. 12.1.4.3 I3C Integration
          1. 12.1.4.3.1 I3C Integration in MCU Domain
          2. 12.1.4.3.2 I3C Integration in MAIN Domain
        4. 12.1.4.4 I3C Functional Description
          1. 12.1.4.4.1  I3C Block Diagram
          2. 12.1.4.4.2  I3C Clock Configuration
            1. 12.1.4.4.2.1 Setting Base Frequencies
            2. 12.1.4.4.2.2 Asymmetric Push-Pull SCL Timing
            3. 12.1.4.4.2.3 Open-Drain SCL Timing
            4. 12.1.4.4.2.4 Changing Programmed Frequencies
          3. 12.1.4.4.3  I3C Interrupt Requests
          4. 12.1.4.4.4  I3C Power Configuration
          5. 12.1.4.4.5  I3C Dynamic Address Management
          6. 12.1.4.4.6  I3C Retaining Registers Space
          7. 12.1.4.4.7  I3C Dynamic Address Assignment Procedure
          8. 12.1.4.4.8  I3C Sending CCC Messages
          9. 12.1.4.4.9  I3C In-Band Interrupt
            1. 12.1.4.4.9.1 Regular I3C Slave In-Band Interrupt
            2. 12.1.4.4.9.2 Current Master Takeover In-Band Interrupt
          10. 12.1.4.4.10 I3C Hot-Join Request
          11. 12.1.4.4.11 I3C Immediate Commands
          12. 12.1.4.4.12 I3C Host Commands
          13. 12.1.4.4.13 I3C Sending Private Data in SDR Messages
            1. 12.1.4.4.13.1 SDR Private Write Message
            2. 12.1.4.4.13.2 SDR Private Read Message
            3. 12.1.4.4.13.3 SDR Payload Length Adjustment
        5. 12.1.4.5 I3C Programming Guide
          1. 12.1.4.5.1 I3C Power-On Programming Model
          2. 12.1.4.5.2 I3C Static Devices Programming
          3. 12.1.4.5.3 I3C DAA Procedure Initiation
          4. 12.1.4.5.4 I3C SDR Write Message Programming Model
          5. 12.1.4.5.5 I3C SDR Read Message Programming Model
          6. 12.1.4.5.6 I3C DDR Write Message Programming Model
          7. 12.1.4.5.7 I3C DDR Read Message Programming Model
        6. 12.1.4.6 I3C Registers
      5. 12.1.5 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.5.1 MCSPI Overview
          1. 12.1.5.1.1 SPI Features
          2. 12.1.5.1.2 MCSPI Not Supported Features
        2. 12.1.5.2 MCSPI Environment
          1. 12.1.5.2.1 Basic MCSPI Pins for Master Mode
          2. 12.1.5.2.2 Basic MCSPI Pins for Slave Mode
          3. 12.1.5.2.3 MCSPI Internal Connectivity
          4. 12.1.5.2.4 MCSPI Protocol and Data Format
            1. 12.1.5.2.4.1 Transfer Format
          5. 12.1.5.2.5 MCSPI in Controller Mode
          6. 12.1.5.2.6 MCSPI in Peripheral Mode
        3. 12.1.5.3 MCSPI Integration
          1. 12.1.5.3.1 MCSPI Integration in MCU Domain
          2. 12.1.5.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.5.4 MCSPI Functional Description
          1. 12.1.5.4.1 SPI Block Diagram
          2. 12.1.5.4.2 MCSPI Reset
          3. 12.1.5.4.3 MCSPI Controller Mode
            1. 12.1.5.4.3.1 Controller Mode Features
            2. 12.1.5.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.5.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.5.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.5.4.3.5 Single-Channel Controller Mode
              1. 12.1.5.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.5.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.5.4.3.5.3 Turbo Mode
            6. 12.1.5.4.3.6 Start-Bit Mode
            7. 12.1.5.4.3.7 Chip-Select Timing Control
            8. 12.1.5.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.5.4.3.8.1 Clock Ratio Granularity
          4. 12.1.5.4.4 MCSPI Peripheral Mode
            1. 12.1.5.4.4.1 Dedicated Resources
            2. 12.1.5.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.5.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.5.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.5.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.5.4.6 MCSPI FIFO Buffer Management
            1. 12.1.5.4.6.1 Buffer Almost Full
            2. 12.1.5.4.6.2 Buffer Almost Empty
            3. 12.1.5.4.6.3 End of Transfer Management
            4. 12.1.5.4.6.4 Multiple MCSPI Word Access
            5. 12.1.5.4.6.5 First MCSPI Word Delay
          7. 12.1.5.4.7 MCSPI Interrupts
            1. 12.1.5.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.5.4.7.1.1 TXx_EMPTY
              2. 12.1.5.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.1.3 RXx_ FULL
              4. 12.1.5.4.7.1.4 End Of Word Count
            2. 12.1.5.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.5.4.7.2.1 TXx_EMPTY
              2. 12.1.5.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.2.3 RXx_FULL
              4. 12.1.5.4.7.2.4 RX0_OVERFLOW
              5. 12.1.5.4.7.2.5 End Of Word Count
            3. 12.1.5.4.7.3 Interrupt-Driven Operation
            4. 12.1.5.4.7.4 Polling
          8. 12.1.5.4.8 MCSPI DMA Requests
          9. 12.1.5.4.9 MCSPI Power Saving Management
            1. 12.1.5.4.9.1 Normal Mode
            2. 12.1.5.4.9.2 Idle Mode
              1. 12.1.5.4.9.2.1 Force-Idle Mode
        5. 12.1.5.5 MCSPI Programming Guide
          1. 12.1.5.5.1 MCSPI Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 MCSPI Global Initialization
              1. 12.1.5.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.5.5.2 MCSPI Operational Mode Configuration
            1. 12.1.5.5.2.1 MCSPI Operational Modes
              1. 12.1.5.5.2.1.1 Common Transfer Sequence
              2. 12.1.5.5.2.1.2 End of Transfer Sequences
              3. 12.1.5.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.5.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.5.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.5.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.5.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.5.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.5.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.5.5.2.1.7 Peripheral Receive-Only
              8. 12.1.5.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.5.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.5.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.5.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.5.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.5.5.2.1.8.5 Transmit-Only
                6. 12.1.5.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.5.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.5.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.5.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.5.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.5.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.5.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
        6. 12.1.5.6 MCSPI Registers
      6. 12.1.6 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.6.1 UART Overview
          1. 12.1.6.1.1 UART Features
          2. 12.1.6.1.2 IrDA Features
          3. 12.1.6.1.3 CIR Features
          4. 12.1.6.1.4 UART Not Supported Features
        2. 12.1.6.2 UART Environment
          1. 12.1.6.2.1 UART Functional Interfaces
            1. 12.1.6.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.6.2.1.2 UART Interface Description
            3. 12.1.6.2.1.3 UART Protocol and Data Format
            4. 12.1.6.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.6.2.2 RS-485 Functional Interfaces
            1. 12.1.6.2.2.1 System Using RS-485 Communication
            2. 12.1.6.2.2.2 RS-485 Interface Description
          3. 12.1.6.2.3 IrDA Functional Interfaces
            1. 12.1.6.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.6.2.3.2 IrDA Interface Description
            3. 12.1.6.2.3.3 IrDA Protocol and Data Format
              1. 12.1.6.2.3.3.1 SIR Mode
                1. 12.1.6.2.3.3.1.1 Frame Format
                2. 12.1.6.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.6.2.3.3.1.3 Abort Sequence
                4. 12.1.6.2.3.3.1.4 Pulse Shaping
                5. 12.1.6.2.3.3.1.5 Encoder
                6. 12.1.6.2.3.3.1.6 Decoder
                7. 12.1.6.2.3.3.1.7 IR Address Checking
              2. 12.1.6.2.3.3.2 SIR Free-Format Mode
              3. 12.1.6.2.3.3.3 MIR Mode
                1. 12.1.6.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.6.2.3.3.3.2 SIP Generation
              4. 12.1.6.2.3.3.4 FIR Mode
          4. 12.1.6.2.4 CIR Functional Interfaces
            1. 12.1.6.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.6.2.4.2 CIR Interface Description
            3. 12.1.6.2.4.3 CIR Protocol and Data Format
              1. 12.1.6.2.4.3.1 Carrier Modulation
              2. 12.1.6.2.4.3.2 Pulse Duty Cycle
              3. 12.1.6.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.6.3 UART Integration
          1. 12.1.6.3.1 UART Integration in WKUP Domain
          2. 12.1.6.3.2 UART Integration in MCU Domain
          3. 12.1.6.3.3 UART Integration in MAIN Domain
        4. 12.1.6.4 UART Functional Description
          1. 12.1.6.4.1 UART Block Diagram
          2. 12.1.6.4.2 UART Clock Configuration
          3. 12.1.6.4.3 UART Software Reset
            1. 12.1.6.4.3.1 Independent TX/RX
          4. 12.1.6.4.4 UART Power Management
            1. 12.1.6.4.4.1 UART Mode Power Management
              1. 12.1.6.4.4.1.1 Module Power Saving
              2. 12.1.6.4.4.1.2 System Power Saving
            2. 12.1.6.4.4.2 IrDA Mode Power Management
              1. 12.1.6.4.4.2.1 Module Power Saving
              2. 12.1.6.4.4.2.2 System Power Saving
            3. 12.1.6.4.4.3 CIR Mode Power Management
              1. 12.1.6.4.4.3.1 Module Power Saving
              2. 12.1.6.4.4.3.2 System Power Saving
            4. 12.1.6.4.4.4 Local Power Management
          5. 12.1.6.4.5 UART Interrupt Requests
            1. 12.1.6.4.5.1 UART Mode Interrupt Management
              1. 12.1.6.4.5.1.1 UART Interrupts
              2. 12.1.6.4.5.1.2 Wake-Up Interrupt
            2. 12.1.6.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.6.4.5.2.1 IrDA Interrupts
              2. 12.1.6.4.5.2.2 Wake-Up Interrupts
            3. 12.1.6.4.5.3 CIR Mode Interrupt Management
              1. 12.1.6.4.5.3.1 CIR Interrupts
              2. 12.1.6.4.5.3.2 Wake-Up Interrupts
          6. 12.1.6.4.6 UART FIFO Management
            1. 12.1.6.4.6.1 FIFO Trigger
              1. 12.1.6.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.6.4.6.1.2 Receive FIFO Trigger
            2. 12.1.6.4.6.2 FIFO Interrupt Mode
            3. 12.1.6.4.6.3 FIFO Polled Mode Operation
            4. 12.1.6.4.6.4 FIFO DMA Mode Operation
              1. 12.1.6.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.6.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.6.4.6.4.3 DMA Transmission
              4. 12.1.6.4.6.4.4 DMA Reception
          7. 12.1.6.4.7 UART Mode Selection
            1. 12.1.6.4.7.1 Register Access Modes
              1. 12.1.6.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.6.4.7.1.2 Register Access Submode
              3. 12.1.6.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.6.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.6.4.7.2.1 Registers Available for the UART Function
              2. 12.1.6.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.6.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.6.4.8 UART Protocol Formatting
            1. 12.1.6.4.8.1 UART Mode
              1. 12.1.6.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.6.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.1.3 UART Data Formatting
                1. 12.1.6.4.8.1.3.1 Frame Formatting
                2. 12.1.6.4.8.1.3.2 Hardware Flow Control
                3. 12.1.6.4.8.1.3.3 Software Flow Control
                  1. 1.6.4.8.1.3.3.1 Receive (RX)
                  2. 1.6.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.6.4.8.1.3.4 Autobauding Modes
                5. 12.1.6.4.8.1.3.5 Error Detection
                6. 12.1.6.4.8.1.3.6 Overrun During Receive
                7. 12.1.6.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.6.4.8.1.3.7.1 Time-Out Counter
                  2. 1.6.4.8.1.3.7.2 Break Condition
            2. 12.1.6.4.8.2 RS-485 Mode
              1. 12.1.6.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.6.4.8.3 IrDA Mode
              1. 12.1.6.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.6.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.3.3 IrDA Data Formatting
                1. 12.1.6.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.6.4.8.3.3.2  IrDA Reception Control
                3. 12.1.6.4.8.3.3.3  IR Address Checking
                4. 12.1.6.4.8.3.3.4  Frame Closing
                5. 12.1.6.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.6.4.8.3.3.6  Error Detection
                7. 12.1.6.4.8.3.3.7  Underrun During Transmission
                8. 12.1.6.4.8.3.3.8  Overrun During Receive
                9. 12.1.6.4.8.3.3.9  Status FIFO
                10. 12.1.6.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.6.4.8.3.3.11 Time-guard
              4. 12.1.6.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.6.4.8.3.4.1 Abort Sequence
                2. 12.1.6.4.8.3.4.2 Pulse Shaping
                3. 12.1.6.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.6.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.6.4.8.4 CIR Mode
              1. 12.1.6.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.6.4.8.4.2 CIR Data Formatting
                1. 12.1.6.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.6.4.8.4.2.2 CIR Transmission
                3. 12.1.6.4.8.4.2.3 CIR Reception
        5. 12.1.6.5 UART Programming Guide
          1. 12.1.6.5.1 UART Global Initialization
            1. 12.1.6.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.6.5.1.2 UART Module Global Initialization
          2. 12.1.6.5.2 UART Mode selection
          3. 12.1.6.5.3 UART Submode selection
          4. 12.1.6.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.6.5.4.1 DMA mode Settings
            2. 12.1.6.5.4.2 FIFO Trigger Settings
          5. 12.1.6.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.6.5.5.1 Baud rate settings
            2. 12.1.6.5.5.2 Interrupt settings
            3. 12.1.6.5.5.3 Protocol settings
            4. 12.1.6.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.6.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.6.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.6.5.6.1 Hardware Flow Control Configuration
            2. 12.1.6.5.6.2 Software Flow Control Configuration
          7. 12.1.6.5.7 IrDA Programming Model
            1. 12.1.6.5.7.1 SIR mode
              1. 12.1.6.5.7.1.1 Receive
              2. 12.1.6.5.7.1.2 Transmit
            2. 12.1.6.5.7.2 MIR mode
              1. 12.1.6.5.7.2.1 Receive
              2. 12.1.6.5.7.2.2 Transmit
            3. 12.1.6.5.7.3 FIR mode
              1. 12.1.6.5.7.3.1 Receive
              2. 12.1.6.5.7.3.2 Transmit
        6. 12.1.6.6 UART Registers
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet MAC (MCU_CPSW0)
        1. 12.2.1.1 MCU_CPSW0 Overview
          1. 12.2.1.1.1 MCU_CPSW0 Features
          2. 12.2.1.1.2 MCU_CPSW0 Not Supported Features
          3. 12.2.1.1.3 Terminology
        2. 12.2.1.2 MCU_CPSW0 Environment
          1. 12.2.1.2.1 MCU_CPSW0 RMII Interface
          2. 12.2.1.2.2 MCU_CPSW0 RGMII Interface
        3. 12.2.1.3 MCU_CPSW0 Integration
        4. 12.2.1.4 MCU_CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_2G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 2-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1 Free Table Entry
                2. 12.2.1.4.6.1.9.2 Multicast Address Table Entry
                3. 12.2.1.4.6.1.9.3 VLAN/Multicast Address Table Entry
                4. 12.2.1.4.6.1.9.4 Unicast Address Table Entry
                5. 12.2.1.4.6.1.9.5 OUI Unicast Address Table Entry
                6. 12.2.1.4.6.1.9.6 VLAN/Unicast Address Table Entry
                7. 12.2.1.4.6.1.9.7 VLAN Table Entry
              10. 12.2.1.4.6.1.10 ALE Policing and Classification
                1. 12.2.1.4.6.1.10.1 ALE Classification
                  1. 2.1.4.6.1.10.1.1 Classifier to CPPI Transmit Flow ID Mapping
              11. 12.2.1.4.6.1.11 DSCP
              12. 12.2.1.4.6.1.12 Packet Forwarding Processes
                1. 12.2.1.4.6.1.12.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.12.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.12.3 Egress Process
                4. 12.2.1.4.6.1.12.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.12.4.1 Learning Process
                  2. 2.1.4.6.1.12.4.2 Updating Process
                  3. 2.1.4.6.1.12.4.3 Touching Process
              13. 12.2.1.4.6.1.13 VLAN Aware Mode
              14. 12.2.1.4.6.1.14 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 1945
                1. 12.2.1.4.6.10.1.1 1946
                  1. 2.1.4.6.10.1.1.1 CRC Insertion
                  2. 2.1.4.6.10.1.1.2 MTXER
                  3. 2.1.4.6.10.1.1.3 Adaptive Performance Optimization (APO)
                  4. 2.1.4.6.10.1.1.4 Inter-Packet-Gap Enforcement
                  5. 2.1.4.6.10.1.1.5 Back Off
                  6. 2.1.4.6.10.1.1.6 Programmable Transmit Inter-Packet Gap
                  7. 2.1.4.6.10.1.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A20Ch - Port 1)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A214h - Port 1)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A21Ch - Port 1)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A25Ch - Port 1)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
              8. 12.2.1.4.6.18.8  Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.8.1  Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
                2. 12.2.1.4.6.18.8.2  Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
                3. 12.2.1.4.6.18.8.3  Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
                4. 12.2.1.4.6.18.8.4  Pause Tx Frames (Offset = 3A240h - Port 1)
                5. 12.2.1.4.6.18.8.5  Deferred Tx Frames (Offset = 3A244h - Port 1)
                6. 12.2.1.4.6.18.8.6  Collisions (Offset = 3A248h - Port 1)
                7. 12.2.1.4.6.18.8.7  Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
                8. 12.2.1.4.6.18.8.8  Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
                9. 12.2.1.4.6.18.8.9  Excessive Collisions (Offset = 3A254h - Port 1)
                10. 12.2.1.4.6.18.8.10 Late Collisions (Offset = 3A258h - Port 1)
                11. 12.2.1.4.6.18.8.11 Carrier Sense Errors (Offset = 3A260h - Port 1)
                12. 12.2.1.4.6.18.8.12 Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
                13. 12.2.1.4.6.18.8.13 Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
                14. 12.2.1.4.6.18.8.14 Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
                15. 12.2.1.4.6.18.8.15 Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
                16. 12.2.1.4.6.18.8.16 IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
                17. 12.2.1.4.6.18.8.17 IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
              9. 12.2.1.4.6.18.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
                2. 12.2.1.4.6.18.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
                3. 12.2.1.4.6.18.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
                4. 12.2.1.4.6.18.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
                5. 12.2.1.4.6.18.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
                6. 12.2.1.4.6.18.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
                7. 12.2.1.4.6.18.9.7 Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
              10. 12.2.1.4.6.18.10 2045
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  MCU_CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 2073
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_2G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_2G Ingress)
            3. 12.2.1.4.8.3 CPPI Checksum Offload
              1. 12.2.1.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.3.1.1 IPV4 UDP
                2. 12.2.1.4.8.3.1.2 IPV4 TCP
                3. 12.2.1.4.8.3.1.3 IPV6 UDP
                4. 12.2.1.4.8.3.1.4 IPV6 TCP
            4. 12.2.1.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.1.4.8.5 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 MCU_CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
        6. 12.2.1.6 MCU_CPSW0 Registers
          1. 12.2.1.6.1  MCU_CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.1.6.2  MCU_CPSW0_SGMII Registers
          3. 12.2.1.6.3  MCU_CPSW0_MDIO Registers
          4. 12.2.1.6.4  MCU_CPSW0_CPTS Registers
          5. 12.2.1.6.5  MCU_CPSW0_CONTROL Registers
          6. 12.2.1.6.6  MCU_CPSW0_CPINT Registers
          7. 12.2.1.6.7  MCU_CPSW0_RAM Registers
          8. 12.2.1.6.8  MCU_CPSW0_STAT0 Registers
          9. 12.2.1.6.9  MCU_CPSW0_STAT1 Registers
          10. 12.2.1.6.10 MCU_CPSW0_ALE Registers
          11. 12.2.1.6.11 MCU_CPSW0_ECC Registers
      2. 12.2.2 Gigabit Ethernet Switch (CPSW0)
        1. 12.2.2.1 CPSW0 Overview
          1. 12.2.2.1.1 CPSW0 Features
          2. 12.2.2.1.2 CPSW0 Not Supported Features
          3. 12.2.2.1.3 Terminology
        2. 12.2.2.2 CPSW0 Environment
          1. 12.2.2.2.1 CPSW0 RMII Interface
          2. 12.2.2.2.2 CPSW0 RGMII Interface
        3. 12.2.2.3 CPSW0 Integration
        4. 12.2.2.4 CPSW0 Functional Description
          1. 12.2.2.4.1 Functional Block Diagram
          2. 12.2.2.4.2 CPSW Ports
            1. 12.2.2.4.2.1 Interface Mode Selection
          3. 12.2.2.4.3 Clocking
            1. 12.2.2.4.3.1 Subsystem Clocking
            2. 12.2.2.4.3.2 Interface Clocking
              1. 12.2.2.4.3.2.1 RGMII Interface Clocking
              2. 12.2.2.4.3.2.2 RMII Interface Clocking
              3. 12.2.2.4.3.2.3 MDIO Clocking
          4. 12.2.2.4.4 Software IDLE
          5. 12.2.2.4.5 Interrupt Functionality
            1. 12.2.2.4.5.1 EVNT_PEND Interrupt
            2. 12.2.2.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.2.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.2.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.2.4.5.5 MDIO Interrupts
          6. 12.2.2.4.6 CPSW_5X
            1. 12.2.2.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.2.4.6.1.1  Error Handling
              2. 12.2.2.4.6.1.2  Bypass Operations
              3. 12.2.2.4.6.1.3  OUI Deny or Accept
              4. 12.2.2.4.6.1.4  Statistics Counting
              5. 12.2.2.4.6.1.5  Automotive Security Features
              6. 12.2.2.4.6.1.6  CPSW Switching Solutions
                1. 12.2.2.4.6.1.6.1 Basics of 5-port Switch Type
              7. 12.2.2.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.2.4.6.1.7.1 InterVLAN Routing
                2. 12.2.2.4.6.1.7.2 OAM Operations
              8. 12.2.2.4.6.1.8  Supervisory packets
              9. 12.2.2.4.6.1.9  Address Table Entry
                1. 12.2.2.4.6.1.9.1  Free Table Entry
                2. 12.2.2.4.6.1.9.2  Multicast Address Table Entry (Bit 40 == 0)
                3. 12.2.2.4.6.1.9.3  Multicast Address Table Entry (Bit 40 == 1)
                4. 12.2.2.4.6.1.9.4  VLAN Unicast Address Table Entry (Bit 40 == 0)
                5. 12.2.2.4.6.1.9.5  OUI Unicast Address Table Entry
                6. 12.2.2.4.6.1.9.6  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                7. 12.2.2.4.6.1.9.7  VLAN/ Multicast Address Table Entry (Bit 40 == 1)
                8. 12.2.2.4.6.1.9.8  Inner VLAN Table Entry
                9. 12.2.2.4.6.1.9.9  Outer VLAN Table Entry
                10. 12.2.2.4.6.1.9.10 EtherType Table Entry
                11. 12.2.2.4.6.1.9.11 IPv4 Table Entry
                12. 12.2.2.4.6.1.9.12 IPv6 Table Entry High
                13. 12.2.2.4.6.1.9.13 IPv6 Table Entry Low
              10. 12.2.2.4.6.1.10 Multicast Address
                1. 12.2.2.4.6.1.10.1 Multicast Ranges
              11. 12.2.2.4.6.1.11 Supervisory Packets
              12. 12.2.2.4.6.1.12 Aging and Auto Aging
              13. 12.2.2.4.6.1.13 ALE Policing and Classification
                1. 12.2.2.4.6.1.13.1 ALE Policing
                2. 12.2.2.4.6.1.13.2 Classifier to Host Thread Mapping
                3. 12.2.2.4.6.1.13.3 ALE Classification
                  1. 2.2.4.6.1.13.3.1 Classifier to CPPI Transmit Flow ID Mapping
              14. 12.2.2.4.6.1.14 Mirroring
              15. 12.2.2.4.6.1.15 Trunking
              16. 12.2.2.4.6.1.16 DSCP
              17. 12.2.2.4.6.1.17 Packet Forwarding Processes
                1. 12.2.2.4.6.1.17.1 Ingress Filtering Process
                2. 12.2.2.4.6.1.17.2 VLAN_Aware Lookup Process
                3. 12.2.2.4.6.1.17.3 Egress Process
                4. 12.2.2.4.6.1.17.4 Learning/Updating/Touching Processes
                  1. 2.2.4.6.1.17.4.1 Learning Process
                  2. 2.2.4.6.1.17.4.2 Updating Process
                  3. 2.2.4.6.1.17.4.3 Touching Process
              18. 12.2.2.4.6.1.18 VLAN Aware Mode
              19. 12.2.2.4.6.1.19 VLAN Unaware Mode
            2. 12.2.2.4.6.2  Packet Priority Handling
              1. 12.2.2.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.2.4.6.3  CPPI Port Ingress
            4. 12.2.2.4.6.4  Packet CRC Handling
              1. 12.2.2.4.6.4.1 Transmit VLAN Processing
                1. 12.2.2.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.2.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.2.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.2.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.2.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.2.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.2.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.2.4.6.5  FIFO Memory Control
            6. 12.2.2.4.6.6  FIFO Transmit Queue Control
              1. 12.2.2.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.2.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.2.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.2.4.6.7.1 IET Configuration
            8. 12.2.2.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.2.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.2.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.2.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.2.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.2.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.2.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 12.2.2.4.6.9  Audio Video Bridging
              1. 12.2.2.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.2.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.2.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.2.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.2.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.2.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.2.4.6.10 Ethernet MAC Sliver
              1. 12.2.2.4.6.10.1  CRC Insertion
              2. 12.2.2.4.6.10.2  MTXER
              3. 12.2.2.4.6.10.3  Adaptive Performance Optimization (APO)
              4. 12.2.2.4.6.10.4  Inter-Packet-Gap Enforcement
              5. 12.2.2.4.6.10.5  Back Off
              6. 12.2.2.4.6.10.6  Programmable Transmit Inter-Packet Gap
              7. 12.2.2.4.6.10.7  Speed, Duplex and Pause Frame Support Negotiation
              8. 12.2.2.4.6.10.8  RMII Interface
                1. 12.2.2.4.6.10.8.1 Features
                2. 12.2.2.4.6.10.8.2 RMII Receive (RX)
                3. 12.2.2.4.6.10.8.3 RMII Transmit (TX)
              9. 12.2.2.4.6.10.9  RGMII Interface
                1. 12.2.2.4.6.10.9.1 Features
                2. 12.2.2.4.6.10.9.2 RGMII Receive (RX)
                3. 12.2.2.4.6.10.9.3 In-Band Mode of Operation
                4. 12.2.2.4.6.10.9.4 Forced Mode of Operation
                5. 12.2.2.4.6.10.9.5 RGMII Transmit (TX)
              10. 12.2.2.4.6.10.10 Frame Classification
              11. 12.2.2.4.6.10.11 Receive FIFO Architecture
            11. 12.2.2.4.6.11 Embedded Memories
            12. 12.2.2.4.6.12 Memory Error Detection and Correction
              1. 12.2.2.4.6.12.1 Packet Header ECC
              2. 12.2.2.4.6.12.2 Packet Protect CRC
              3. 12.2.2.4.6.12.3 Aggregator RAM Control
            13. 12.2.2.4.6.13 Ethernet Port Flow Control
              1. 12.2.2.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.2.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.2.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.2.4.6.13.2 Qbb (10/100/1G/10G) Receive Priority Based Flow Control (PFC)
              3. 12.2.2.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.2.4.6.14 PFC Trigger Rules
              1. 12.2.2.4.6.14.1 Destination Based Rule
              2. 12.2.2.4.6.14.2 Sum of Outflows Rule
              3. 12.2.2.4.6.14.3 Sum of Blocks Per Port Rule
              4. 12.2.2.4.6.14.4 Sum of Blocks Total Rule
              5. 12.2.2.4.6.14.5 Top of Receive FIFO Rule
            15. 12.2.2.4.6.15 Energy Efficient Ethernet Support (802.3az)
            16. 12.2.2.4.6.16 Ethernet Switch Latency
            17. 12.2.2.4.6.17 MAC Emulation Control
            18. 12.2.2.4.6.18 MAC Command IDLE
            19. 12.2.2.4.6.19 CPSW Network Statistics
              1. 12.2.2.4.6.19.1  Rx-only Statistics Descriptions
                1. 12.2.2.4.6.19.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.2.4.6.19.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.2.4.6.19.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.2.4.6.19.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.2.4.6.19.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.2.4.6.19.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.2.4.6.19.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.2.4.6.19.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.2.4.6.19.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.2.4.6.19.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.2.4.6.19.1.11 RX IPG Error
                12. 12.2.2.4.6.19.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.2.4.6.19.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.2.4.6.19.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.2.4.6.19.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.2.4.6.19.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.2.4.6.19.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.2.4.6.19.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.2.4.6.19.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.2.4.6.19.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.2.4.6.19.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.2.4.6.19.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.2.4.6.19.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.2.4.6.19.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.2.4.6.19.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.2.4.6.19.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.2.4.6.19.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.2.4.6.19.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.2.4.6.19.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.2.4.6.19.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.2.4.6.19.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.2.4.6.19.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.2.4.6.19.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.2.4.6.19.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.2.4.6.19.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.2.4.6.19.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.2.4.6.19.8  Tx-only Statistics Descriptions
                1. 12.2.2.4.6.19.8.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.2.4.6.19.8.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.2.4.6.19.8.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.2.4.6.19.8.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.2.4.6.19.8.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.2.4.6.19.8.6  Collisions (Offset = 3A048h)
                7. 12.2.2.4.6.19.8.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.2.4.6.19.8.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.2.4.6.19.8.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.2.4.6.19.8.10 Late Collisions (Offset = 3A058h)
                11. 12.2.2.4.6.19.8.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.2.4.6.19.8.12 Tx Octets (Offset = 3A064h)
                13. 12.2.2.4.6.19.8.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.2.4.6.19.8.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
                15. 12.2.2.4.6.19.8.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.2.4.6.19.8.16 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                17. 12.2.2.4.6.19.8.17 IET Transmit Merge Hold Count (Offset = 3A150h)
              9. 12.2.2.4.6.19.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.2.4.6.19.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.2.4.6.19.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.2.4.6.19.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.2.4.6.19.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.2.4.6.19.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.2.4.6.19.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.2.4.6.19.9.7 Net Octets (Offset = 3A080h)
              10. 12.2.2.4.6.19.10 2324
          7. 12.2.2.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.2.4.7.1  CPSW0 CPTS Integration
            2. 12.2.2.4.7.2  CPTS Architecture
            3. 12.2.2.4.7.3  CPTS Initialization
            4. 12.2.2.4.7.4  32-bit Time Stamp Value
            5. 12.2.2.4.7.5  64-bit Time Stamp Value
            6. 12.2.2.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.2.4.7.7  64-bit Timestamp PPM
            8. 12.2.2.4.7.8  Event FIFO
            9. 12.2.2.4.7.9  Timestamp Compare Output
              1. 12.2.2.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.2.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.2.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.2.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.2.4.7.10 Timestamp Sync Output
            11. 12.2.2.4.7.11 Timestamp GENFn Output
              1. 12.2.2.4.7.11.1 GENFn Nudge
              2. 12.2.2.4.7.11.2 GENFn PPM
            12. 12.2.2.4.7.12 Timestamp ESTFn
            13. 12.2.2.4.7.13 Time Sync Events
              1. 12.2.2.4.7.13.1 Time Stamp Push Event
              2. 12.2.2.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.2.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.2.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.2.4.7.13.5 Ethernet Port Events
                1. 12.2.2.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.2.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.2.4.7.13.5.3 2352
            14. 12.2.2.4.7.14 Timestamp Compare Event
              1. 12.2.2.4.7.14.1 32-Bit Mode
              2. 12.2.2.4.7.14.2 64-Bit Mode
            15. 12.2.2.4.7.15 Host Transmit Event
            16. 12.2.2.4.7.16 CPTS Interrupt Handling
          8. 12.2.2.4.8 CPPI Streaming Packet Interface
            1. 12.2.2.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_5X Egress)
            2. 12.2.2.4.8.2 CPPI Receive Packet Streaming Interface (CPSW Ingress)
            3. 12.2.2.4.8.3 CPPI Checksum Offload
              1. 12.2.2.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.2.4.8.3.1.1 IPV4 UDP
                2. 12.2.2.4.8.3.1.2 IPV4 TCP
                3. 12.2.2.4.8.3.1.3 IPV6 UDP
                4. 12.2.2.4.8.3.1.4 IPV6 TCP
            4. 12.2.2.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.2.4.8.5 Egress Packet Operations
          9. 12.2.2.4.9 MII Management Interface (MDIO)
            1. 12.2.2.4.9.1 MDIO Frame Formats
            2. 12.2.2.4.9.2 MDIO Functional Description
        5. 12.2.2.5 CPSW0 Programming Guide
          1. 12.2.2.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.2.5.2 Ethernet MAC Reset or XGMII/GMII Mode Change Configuration
          3. 12.2.2.5.3 MDIO Software Interface
            1. 12.2.2.5.3.1 Initializing the MDIO Module
            2. 12.2.2.5.3.2 Writing Data To a PHY Register
            3. 12.2.2.5.3.3 Reading Data From a PHY Register
        6. 12.2.2.6 CPSW0 Registers
          1. 12.2.2.6.1  CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.2.6.2  CPSW0_SGMII Registers
          3. 12.2.2.6.3  CPSW0_MDIO Registers
          4. 12.2.2.6.4  CPSW0_CPTS Registers
          5. 12.2.2.6.5  CPSW0_CONTROL Registers
          6. 12.2.2.6.6  CPSW0_CPINT Registers
          7. 12.2.2.6.7  CPSW0_RAM Registers
          8. 12.2.2.6.8  CPSW0_STAT Registers
          9. 12.2.2.6.9  CPSW0_ALE Registers
          10. 12.2.2.6.10 CPSW0_PCSR Registers
          11. 12.2.2.6.11 CPSW0_ECC Registers
      3. 12.2.3 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.3.1 PCIe Subsystem Overview
          1. 12.2.3.1.1 PCIe Subsystem Features
          2. 12.2.3.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.3.2 PCIe Subsystem Environment
        3. 12.2.3.3 PCIe Subsystem Integration
        4. 12.2.3.4 PCIe Subsystem Functional Description
          1. 12.2.3.4.1  PCIe Subsystem Block Diagram
            1. 12.2.3.4.1.1 PCIe Core Module
            2. 12.2.3.4.1.2 PCIe PHY Interface
            3. 12.2.3.4.1.3 CBA Infrastructure
            4. 12.2.3.4.1.4 VBUSM to AXI Bridges
            5. 12.2.3.4.1.5 AXI to VBUSM Bridges
            6. 12.2.3.4.1.6 VBUSP to APB Bridge
            7. 12.2.3.4.1.7 Custom Logic
          2. 12.2.3.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.3.4.2.1 PCIe Conventional Reset
            2. 12.2.3.4.2.2 PCIe Function Level Reset
            3. 12.2.3.4.2.3 PCIe Reset Isolation
              1. 12.2.3.4.2.3.1 Root Port Reset with Device Not Reset
              2. 12.2.3.4.2.3.2 Device Reset with Root Port Not Reset
              3. 12.2.3.4.2.3.3 End Point Device Reset with Root Port Not Reset
              4. 12.2.3.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.3.4.2.4 PCIe Reset Limitations
            5. 12.2.3.4.2.5 PCIe Reset Requirements
          3. 12.2.3.4.3  PCIe Subsystem Power Management
            1. 12.2.3.4.3.1 CBA Power Management
          4. 12.2.3.4.4  PCIe Subsystem Interrupts
            1. 12.2.3.4.4.1 Interrupts Aggregation
            2. 12.2.3.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.3.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.3.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.3.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.3.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.3.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.3.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.3.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.3.4.4.3.5 PTM Valid Interrupt
            4. 12.2.3.4.4.4 Interrupt Generation in RP Mode
            5. 12.2.3.4.4.5 Interrupt Reception in RP Mode
              1. 12.2.3.4.4.5.1 PCIe Legacy Interrupt Reception in RP Mode
              2. 12.2.3.4.4.5.2 MSI/MSI-X Interrupt Reception in RP Mode
              3. 12.2.3.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.3.4.4.6 Common Interrupt Reception in RP and EP Modes
              1. 12.2.3.4.4.6.1 PCIe Local Interrupt
              2. 12.2.3.4.4.6.2 PHY Interrupt
              3. 12.2.3.4.4.6.3 Link down Interrupt
              4. 12.2.3.4.4.6.4 Transaction Error Interrupts
              5. 12.2.3.4.4.6.5 Power Management Event Interrupt
              6. 12.2.3.4.4.6.6 Active Internal Diagnostics Interrupts
            7. 12.2.3.4.4.7 ECC Aggregator Interrupts
            8. 12.2.3.4.4.8 CPTS Interrupt
          5. 12.2.3.4.5  PCIe Subsystem DMA Support
            1. 12.2.3.4.5.1 PCIe DMA Support in RP Mode
            2. 12.2.3.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.3.4.6  PCIe Subsystem Transactions
            1. 12.2.3.4.6.1 PCIe Supported Transactions
            2. 12.2.3.4.6.2 PCIe Transaction Limitations
          7. 12.2.3.4.7  PCIe Subsystem Address Translation
            1. 12.2.3.4.7.1 PCIe Inbound Address Translation
              1. 12.2.3.4.7.1.1 Root Port Inbound PCIe to AXI Address Translation
              2. 12.2.3.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.3.4.7.2 PCIe Outbound Address Translation
              1. 12.2.3.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.3.4.8  PCIe Subsystem Virtualization Support
            1. 12.2.3.4.8.1 End Point SR-IOV Support
            2. 12.2.3.4.8.2 Root Port ATS Support
            3. 12.2.3.4.8.3 VirtID Mapping
          9. 12.2.3.4.9  PCIe Subsystem Quality-of-Service (QoS)
          10. 12.2.3.4.10 PCIe Subsystem Precision Time Measurement (PTM)
          11. 12.2.3.4.11 PCIe Subsystem Loopback
            1. 12.2.3.4.11.1 PCIe PIPE Loopback
              1. 12.2.3.4.11.1.1 PIPE Loopback Master Mode
              2. 12.2.3.4.11.1.2 PIPE Loopback Slave Mode
          12. 12.2.3.4.12 PCIe Subsystem Error Handling
            1. 12.2.3.4.12.1 PCIe AXI to/from VBUSM Bus Error Mapping
          13. 12.2.3.4.13 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.3.4.13.1 PCIe Parity
            2. 12.2.3.4.13.2 ECC Aggregators
            3. 12.2.3.4.13.3 RAM ECC Inversion
          14. 12.2.3.4.14 LTSSM State Encoding
        5. 12.2.3.5 PCIe Subsystem Registers
          1. 12.2.3.5.1  PCIE_CORE_EP_PF Registers
          2. 12.2.3.5.2  PCIE_CORE_EP_VF Registers
          3. 12.2.3.5.3  PCIE_CORE_RP Registers
          4. 12.2.3.5.4  PCIE_CORE_LM Registers
          5. 12.2.3.5.5  PCIE_CORE_AXI Registers
          6. 12.2.3.5.6  PCIE_INTD Registers
          7. 12.2.3.5.7  PCIE_VMAP Registers
          8. 12.2.3.5.8  PCIE_CPTS Registers
          9. 12.2.3.5.9  PCIE_USER_CFG Registers
          10. 12.2.3.5.10 PCIE_ECC_AGGR0 Registers
          11. 12.2.3.5.11 PCIE_ECC_AGGR1 Registers
          12. 12.2.3.5.12 PCIE_DAT0 Registers
          13. 12.2.3.5.13 PCIE_DAT1 Registers
      4. 12.2.4 Universal Serial Bus (USB) Subsystem
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
        3. 12.2.4.3 USB Integration
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Type-C Connector Support
          2. 12.2.4.4.2 USB Controller Reset
          3. 12.2.4.4.3 Overcurrent Detection
          4. 12.2.4.4.4 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
          1. 12.2.4.5.1 USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
          2. 12.2.4.5.2 USB_ECC_AGGR_CFG Registers
          3. 12.2.4.5.3 USB_RAMS_INJ_CFG Registers
      5. 12.2.5 Serializer/Deserializer (SerDes)
        1. 12.2.5.1 SerDes Overview
          1. 12.2.5.1.1 SerDes Features
          2. 12.2.5.1.2 Industry Standards Compatibility
        2. 12.2.5.2 SerDes Environment
          1. 12.2.5.2.1 SerDes I/Os
        3. 12.2.5.3 SerDes Integration
          1. 12.2.5.3.1 WIZ Settings
            1. 12.2.5.3.1.1 Interface Selection
            2. 12.2.5.3.1.2 Reference Clock Distribution
            3. 12.2.5.3.1.3 Internal Reference Clock Selection
        4. 12.2.5.4 SerDes Functional Description
          1. 12.2.5.4.1 SerDes Block Diagram
          2. 12.2.5.4.2 SerDes Programming Guide
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        2. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        3. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MCU Domain
        4. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS ECC Support
            1. 12.3.1.4.2.1 FSS ECC Calculation
          3. 12.3.1.4.3 FSS Modes of Operation
          4. 12.3.1.4.4 FSS Regions
            1. 12.3.1.4.4.1 FSS Regions Boot Size Configuration
          5. 12.3.1.4.5 FSS Memory Regions
        5. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Real-Time Operation
          3. 12.3.1.5.3 FSS Power Up/Down Sequence
        6. 12.3.1.6 FSS Registers
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MCU Domain
        4. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
            2. 12.3.2.4.2.2 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
            2. 12.3.2.4.11.2 2576
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        5. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
        6. 12.3.2.6 OSPI Registers
      3. 12.3.3 HyperBus Interface
        1. 12.3.3.1 HyperBus Overview
          1. 12.3.3.1.1 HyperBus Features
          2. 12.3.3.1.2 HyperBus Not Supported Features
        2. 12.3.3.2 HyperBus Environment
        3. 12.3.3.3 HyperBus Integration
          1. 12.3.3.3.1 HyperBus Integration in MCU Domain
        4. 12.3.3.4 HyperBus Functional Description
          1. 12.3.3.4.1 HyperBus Interrupts
          2. 12.3.3.4.2 HyperBus ECC Support
            1. 12.3.3.4.2.1 ECC Aggregator
          3. 12.3.3.4.3 HyperBus Internal FIFOs
          4. 12.3.3.4.4 HyperBus Data Regions
          5. 12.3.3.4.5 HyperBus True Continuous Read (TCR) Mode
        5. 12.3.3.5 HyperBus Programming Guide
          1. 12.3.3.5.1 HyperBus Initialization Sequence
            1. 12.3.3.5.1.1 HyperFlash Access
            2. 12.3.3.5.1.2 HyperRAM Access
          2. 12.3.3.5.2 HyperBus Real-time Operating Requirements
          3. 12.3.3.5.3 HyperBus Power Up/Down Sequence
        6. 12.3.3.6 HyperBus Registers
      4. 12.3.4 General-Purpose Memory Controller (GPMC)
        1. 12.3.4.1 GPMC Overview
          1. 12.3.4.1.1 GPMC Features
          2. 12.3.4.1.2 GPMC Not Supported Features
        2. 12.3.4.2 GPMC Environment
          1. 12.3.4.2.1 GPMC Modes
          2. 12.3.4.2.2 GPMC I/O Signals
        3. 12.3.4.3 GPMC Integration
          1. 12.3.4.3.1 GPMC Integration in MAIN Domain
        4. 12.3.4.4 GPMC Functional Description
          1. 12.3.4.4.1  GPMC Block Diagram
          2. 12.3.4.4.2  GPMC Clock Configuration
          3. 12.3.4.4.3  GPMC Power Management
          4. 12.3.4.4.4  GPMC Interrupt Requests
          5. 12.3.4.4.5  GPMC Interconnect Port Interface
          6. 12.3.4.4.6  GPMC Address and Data Bus
            1. 12.3.4.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.4.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.4.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.4.4.7.2 Access Protocol
              1. 12.3.4.4.7.2.1 Supported Devices
              2. 12.3.4.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.4.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.4.4.7.3 External Signals
              1. 12.3.4.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.4.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.4.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.4.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.4.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.4.4.7.3.1.5 Wait With NAND Device
                6. 12.3.4.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.4.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.4.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.4.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.4.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.4.4.7.3.2 DIR Pin
              3. 12.3.4.4.7.3.3 Reset
              4. 12.3.4.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.4.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.4.4.7.4 Error Handling
          8. 12.3.4.4.8  GPMC Timing Setting
            1. 12.3.4.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.4.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.4.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.4.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.4.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.4.4.8.6  GPMC_CLKOUT
            7. 12.3.4.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.4.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.4.4.8.8.1 Access Time on Read Access
              2. 12.3.4.4.8.8.2 Access Time on Write Access
            9. 12.3.4.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.4.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.4.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.4.4.8.10 Bus Keeping Support
          9. 12.3.4.4.9  GPMC NOR Access Description
            1. 12.3.4.4.9.1 Asynchronous Access Description
              1. 12.3.4.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.4.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.4.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.4.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.4.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.4.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.4.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.4.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.4.4.9.2 Synchronous Access Description
              1. 12.3.4.4.9.2.1 Synchronous Single Read
              2. 12.3.4.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.4.4.9.2.3 Synchronous Single Write
              4. 12.3.4.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.4.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.4.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.4.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.4.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.4.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.4.4.9.4 Page and Burst Support
            5. 12.3.4.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.4.4.10 GPMC pSRAM Access Specificities
          11. 12.3.4.4.11 GPMC NAND Access Description
            1. 12.3.4.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.4.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.4.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.4.4.11.1.3 Command Latch Cycle
              4. 12.3.4.4.11.1.4 Address Latch Cycle
              5. 12.3.4.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.4.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.4.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.4.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.4.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.4.4.11.2 NAND Device-Ready Pin
              1. 12.3.4.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.4.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.4.4.11.3 ECC Calculator
              1. 12.3.4.4.11.3.1 Hamming Code
                1. 12.3.4.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.4.4.11.3.1.2 ECC Enabling
                3. 12.3.4.4.11.3.1.3 ECC Computation
                4. 12.3.4.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.4.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.4.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.4.4.11.3.2 BCH Code
                1. 12.3.4.4.11.3.2.1 Requirements
                2. 12.3.4.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.4.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.4.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.4.4.11.3.2.2.3 Wrapping Modes
                    1. 4.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 4.4.11.3.2.2.3.2  Mode 0x1
                    3. 4.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 4.4.11.3.2.2.3.4  Mode 0x2
                    5. 4.4.11.3.2.2.3.5  Mode 0x3
                    6. 4.4.11.3.2.2.3.6  Mode 0x7
                    7. 4.4.11.3.2.2.3.7  Mode 0x8
                    8. 4.4.11.3.2.2.3.8  Mode 0x4
                    9. 4.4.11.3.2.2.3.9  Mode 0x9
                    10. 4.4.11.3.2.2.3.10 Mode 0x5
                    11. 4.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 4.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.4.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.4.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.4.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.4.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.4.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.4.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.4.4.11.4.2 Prefetch Mode
              3. 12.3.4.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.4.4.11.4.4 Write-Posting Mode
              5. 12.3.4.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.4.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.4.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.4.4.12 GPMC Use Cases and Tips
            1. 12.3.4.4.12.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.4.4.12.1.1 External Memory Attached to the GPMC Module
              2. 12.3.4.4.12.1.2 Typical GPMC Setup
                1. 12.3.4.4.12.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.4.4.12.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.4.4.12.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.4.4.12.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.4.4.12.2.1 Supported Memories or Devices
                1. 12.3.4.4.12.2.1.1 Memory Pin Multiplexing
                2. 12.3.4.4.12.2.1.2 NAND Interface Protocol
                3. 12.3.4.4.12.2.1.3 NOR Interface Protocol
                4. 12.3.4.4.12.2.1.4 Other Technologies
        5. 12.3.4.5 GPMC Basic Programming Model
          1. 12.3.4.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.4.5.2 GPMC Initialization
          3. 12.3.4.5.3 GPMC Configuration in NOR Mode
          4. 12.3.4.5.4 GPMC Configuration in NAND Mode
          5. 12.3.4.5.5 Set Memory Access
          6. 12.3.4.5.6 GPMC Timing Parameters
            1. 12.3.4.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
        6. 12.3.4.6 GPMC Registers
      5. 12.3.5 Error Location Module (ELM)
        1. 12.3.5.1 ELM Overview
          1. 12.3.5.1.1 ELM Features
          2. 12.3.5.1.2 ELM Not Supported Features
        2. 12.3.5.2 ELM Integration
          1. 12.3.5.2.1 ELM Integration in MAIN Domain
        3. 12.3.5.3 ELM Functional Description
          1. 12.3.5.3.1 ELM Software Reset
          2. 12.3.5.3.2 ELM Power Management
          3. 12.3.5.3.3 ELM Interrupt Requests
          4. 12.3.5.3.4 ELM Processing Initialization
          5. 12.3.5.3.5 ELM Processing Sequence
          6. 12.3.5.3.6 ELM Processing Completion
        4. 12.3.5.4 ELM Basic Programming Model
          1. 12.3.5.4.1 ELM Low-Level Programming Model
            1. 12.3.5.4.1.1 Processing Initialization
            2. 12.3.5.4.1.2 Read Results
            3. 12.3.5.4.1.3 2786
          2. 12.3.5.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.5.4.3 Use Case: ELM Used in Page Mode
        5. 12.3.5.5 ELM Registers
      6. 12.3.6 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.6.1 MMCSD Overview
          1. 12.3.6.1.1 MMCSD Features
          2. 12.3.6.1.2 MMCSD Not Supported Features
        2. 12.3.6.2 MMCSD Environment
          1. 12.3.6.2.1 Protocol and Data Format
            1. 12.3.6.2.1.1 Protocol
            2. 12.3.6.2.1.2 Data Format
              1. 12.3.6.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.6.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.6.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.6.3 MMCSD Integration
          1. 12.3.6.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.6.4 MMCSD Functional Description
          1. 12.3.6.4.1 Block Diagram
          2. 12.3.6.4.2 Memory Regions
          3. 12.3.6.4.3 Interrupt Requests
          4. 12.3.6.4.4 ECC Support
            1. 12.3.6.4.4.1 ECC Aggregator
          5. 12.3.6.4.5 Advanced DMA
          6. 12.3.6.4.6 eMMC PHY BIST
            1. 12.3.6.4.6.1 BIST Overview
            2. 12.3.6.4.6.2 BIST Modes
              1. 12.3.6.4.6.2.1 DS Mode
              2. 12.3.6.4.6.2.2 HS Mode with TXDLY using DLL
              3. 12.3.6.4.6.2.3 HS Mode with TXDLY using Delay Chain
              4. 12.3.6.4.6.2.4 DDR50 Mode with TXDLY using DLL
              5. 12.3.6.4.6.2.5 DDR50 Mode with TXDLY using Delay Chain
              6. 12.3.6.4.6.2.6 HS200 Mode with TX/RXDLY using DLL
              7. 12.3.6.4.6.2.7 HS200 Mode with TX/RXDLY using Delay Chain
              8. 12.3.6.4.6.2.8 HS400 Mode
            3. 12.3.6.4.6.3 BIST Functionality
            4. 12.3.6.4.6.4 Signal Interface
            5. 12.3.6.4.6.5 Programming Flow
              1. 12.3.6.4.6.5.1 DS Mode
                1. 12.3.6.4.6.5.1.1 Configuration
                2. 12.3.6.4.6.5.1.2 BIST Programming
              2. 12.3.6.4.6.5.2 HS Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.2.1 Configuration
                2. 12.3.6.4.6.5.2.2 BIST Programming
              3. 12.3.6.4.6.5.3 HS Mode with DLL
                1. 12.3.6.4.6.5.3.1 Configuration
                2. 12.3.6.4.6.5.3.2 BIST Programming
              4. 12.3.6.4.6.5.4 DDR52 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.4.1 Configuration
                2. 12.3.6.4.6.5.4.2 BIST Programming
              5. 12.3.6.4.6.5.5 DDR52 Mode with DLL
                1. 12.3.6.4.6.5.5.1 Configuration
                2. 12.3.6.4.6.5.5.2 BIST Programming
              6. 12.3.6.4.6.5.6 HS200 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.6.1 Configuration
                2. 12.3.6.4.6.5.6.2 BIST Programming
              7. 12.3.6.4.6.5.7 HS200 Mode with DLL
                1. 12.3.6.4.6.5.7.1 Configuration
                2. 12.3.6.4.6.5.7.2 BIST Programming
              8. 12.3.6.4.6.5.8 HS400 Mode with DLL
                1. 12.3.6.4.6.5.8.1 Configuration
                2. 12.3.6.4.6.5.8.2 BIST Programming
            6. 12.3.6.4.6.6 HS200 BIST Result Check Procedure
        5. 12.3.6.5 MMCSD Programming Guide
          1. 12.3.6.5.1 Sequences
            1. 12.3.6.5.1.1  SD Card Detection
            2. 12.3.6.5.1.2  SD Clock Control
              1. 12.3.6.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.6.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.6.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.6.5.1.3  SD Bus Power Control
            4. 12.3.6.5.1.4  Changing Bus Width
            5. 12.3.6.5.1.5  Timeout Setting on DAT Line
            6. 12.3.6.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.6.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.6.5.1.7  SD Transaction Generation
              1. 12.3.6.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.6.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.6.5.1.7.1.3 2865
              2. 12.3.6.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.2.1 Not using DMA
                2. 12.3.6.5.1.7.2.2 Using SDMA
                3. 12.3.6.5.1.7.2.3 Using ADMA
            8. 12.3.6.5.1.8  Abort Transaction
              1. 12.3.6.5.1.8.1 Asynchronous Abort
              2. 12.3.6.5.1.8.2 Synchronous Abort
            9. 12.3.6.5.1.9  Changing Bus Speed Mode
            10. 12.3.6.5.1.10 Error Recovery
              1. 12.3.6.5.1.10.1 Error Interrupt Recovery
              2. 12.3.6.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.6.5.1.11 Wakeup Control (Optional)
            12. 12.3.6.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.6.5.1.12.1 Suspend Sequence
              2. 12.3.6.5.1.12.2 Resume Sequence
              3. 12.3.6.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.6.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.6.5.2 Driver Flow Sequence
            1. 12.3.6.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.6.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.6.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.6.5.2.2 Boot Operation
              1. 12.3.6.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.6.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.6.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.6.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.6.5.2.3.1 Sampling Clock Tuning
              2. 12.3.6.5.2.3.2 Tuning Modes
              3. 12.3.6.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.6.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.6.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.6.5.2.4.2 Task Issuance Sequence
              3. 12.3.6.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.6.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.6.5.2.4.5 Error Detect and Recovery when CQ is enabled
        6. 12.3.6.6 MMCSD Registers
          1. 12.3.6.6.1 MMCSD0 Subsystem Registers
          2. 12.3.6.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 12.3.6.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 12.3.6.6.4 MMCSD0 Host Controller Registers
          5. 12.3.6.6.5 MMCSD1 Subsystem Registers
          6. 12.3.6.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 12.3.6.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 12.3.6.6.8 MMCSD1 Host Controller Registers
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Enhanced Capture (ECAP) Module
        1. 12.4.1.1 ECAP Overview
          1. 12.4.1.1.1 ECAP Features
        2. 12.4.1.2 ECAP Environment
          1. 12.4.1.2.1 ECAP I/O Interface
        3. 12.4.1.3 ECAP Integration
          1. 12.4.1.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.1.4 ECAP Functional Description
          1. 12.4.1.4.1 Capture and APWM Operating Modes
            1. 12.4.1.4.1.1 ECAP Capture Mode Description
              1. 12.4.1.4.1.1.1 ECAP Event Prescaler
              2. 12.4.1.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.1.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.1.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.1.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.1.4.1.1.6 ECAP Interrupt Control
              7. 12.4.1.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.1.4.1.2 ECAP APWM Mode Operation
          2. 12.4.1.4.2 Summary of ECAP Functional Registers
        5. 12.4.1.5 ECAP Use Cases
          1. 12.4.1.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.1.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.1.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.1.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.1.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.1.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.1.5.5 Application of the APWM Mode
            1. 12.4.1.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.1.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.1.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.1.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.1.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.1.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        6. 12.4.1.6 ECAP Registers
      2. 12.4.2 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.2.1 EPWM Overview
          1. 12.4.2.1.1 EPWM Features
          2. 12.4.2.1.2 EPWM Not Supported Features
          3. 12.4.2.1.3 2951
        2. 12.4.2.2 EPWM Environment
          1. 12.4.2.2.1 EPWM I/O Interface
        3. 12.4.2.3 EPWM Integration
          1. 12.4.2.3.1 Device Specific EPWM Features
          2. 12.4.2.3.2 Daisy-Chain Connectivity between EPWM Modules
          3. 12.4.2.3.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
          4. 12.4.2.3.4 EPWM Modules Time Base Clock Gating
        4. 12.4.2.4 EPWM Functional Description
          1. 12.4.2.4.1  EPWM Submodule Features
            1. 12.4.2.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.2.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.2.4.2.1 Overview
            2. 12.4.2.4.2.2 2964
            3. 12.4.2.4.2.3 Controlling and Monitoring the EPWM Time-Base Submodule
            4. 12.4.2.4.2.4 Calculating PWM Period and Frequency
              1. 12.4.2.4.2.4.1 EPWM Time-Base Period Shadow Register
              2. 12.4.2.4.2.4.2 EPWM Time-Base Counter Synchronization
            5. 12.4.2.4.2.5 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            6. 12.4.2.4.2.6 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.2.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.2.4.3.1 Overview
            2. 12.4.2.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.2.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.2.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.2.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.2.4.4.1 Overview
            2. 12.4.2.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.2.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.2.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.2.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.2.4.5.1 Overview
            2. 12.4.2.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.2.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.2.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.2.4.6.1 Overview
            2. 12.4.2.4.6.2 2987
            3. 12.4.2.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.2.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.2.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.2.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.2.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.2.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.2.4.7.1 Overview
            2. 12.4.2.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.2.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.2.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.2.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.2.4.8.1 Overview
            2. 12.4.2.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.2.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.2.4.8.4 3002
          9. 12.4.2.4.9  EPWM High Resolution (HRPWM) Submodule
            1. 12.4.2.4.9.1 Overview
            2. 12.4.2.4.9.2 Architecture of the High-Resolution PWM Submodule
            3. 12.4.2.4.9.3 Controlling and Monitoring the High-Resolution PWM Submodule
            4. 12.4.2.4.9.4 Configuring the High-Resolution PWM Submodule
            5. 12.4.2.4.9.5 Operational Highlights for the High-Resolution PWM Submodule
              1. 12.4.2.4.9.5.1 HRPWM Edge Positioning
              2. 12.4.2.4.9.5.2 HRPWM Scaling Considerations
              3. 12.4.2.4.9.5.3 HRPWM Duty Cycle Range Limitation
          10. 12.4.2.4.10 EPWM / HRPWM Functional Register Groups
          11. 12.4.2.4.11 Proper EPWM Interrupt Initialization Procedure
        5. 12.4.2.5 EPWM Registers
      3. 12.4.3 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.3.1 EQEP Overview
          1. 12.4.3.1.1 EQEP Features
          2. 12.4.3.1.2 EQEP Not Supported Features
        2. 12.4.3.2 EQEP Environment
          1. 12.4.3.2.1 EQEP I/O Interface
        3. 12.4.3.3 EQEP Integration
          1. 12.4.3.3.1 Device Specific EQEP Features
        4. 12.4.3.4 EQEP Functional Description
          1. 12.4.3.4.1 EQEP Inputs
          2. 12.4.3.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.3.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.3.4.2.1.1 Quadrature Count Mode
              2. 12.4.3.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.3.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.3.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.3.4.2.2 EQEP Input Polarity Selection
            3. 12.4.3.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.3.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.3.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.3.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.3.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.3.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.3.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.3.4.3.2 EQEP Position Counter Latch
              1. 12.4.3.4.3.2.1 Index Event Latch
              2. 12.4.3.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.3.4.3.3 EQEP Position Counter Initialization
            4. 12.4.3.4.3.4 EQEP Position-Compare Unit
          4. 12.4.3.4.4 EQEP Edge Capture Unit
          5. 12.4.3.4.5 EQEP Watchdog
          6. 12.4.3.4.6 Unit Timer Base
          7. 12.4.3.4.7 EQEP Interrupt Structure
          8. 12.4.3.4.8 Summary of EQEP Functional Registers
        5. 12.4.3.5 EQEP Registers
      4. 12.4.4 Controller Area Network (MCAN)
        1. 12.4.4.1 MCAN Overview
          1. 12.4.4.1.1 MCAN Features
          2. 12.4.4.1.2 MCAN Not Supported Features
        2. 12.4.4.2 MCAN Environment
          1. 12.4.4.2.1 CAN Network Basics
        3. 12.4.4.3 MCAN Integration
          1. 12.4.4.3.1 MCAN Integration in MCU Domain
          2. 12.4.4.3.2 MCAN Integration in MAIN Domain
        4. 12.4.4.4 MCAN Functional Description
          1. 12.4.4.4.1  Module Clocking Requirements
          2. 12.4.4.4.2  Interrupt and DMA Requests
            1. 12.4.4.4.2.1 Interrupt Requests
            2. 12.4.4.4.2.2 DMA Requests
            3. 12.4.4.4.2.3 3064
          3. 12.4.4.4.3  Operating Modes
            1. 12.4.4.4.3.1 Software Initialization
            2. 12.4.4.4.3.2 Normal Operation
            3. 12.4.4.4.3.3 CAN FD Operation
            4. 12.4.4.4.3.4 Transmitter Delay Compensation
              1. 12.4.4.4.3.4.1 Description
              2. 12.4.4.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.4.4.3.5 Restricted Operation Mode
            6. 12.4.4.4.3.6 Bus Monitoring Mode
            7. 12.4.4.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.4.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.4.4.3.8 Power Down (Sleep Mode)
              1. 12.4.4.4.3.8.1 External Clock Stop Mode
              2. 12.4.4.4.3.8.2 Suspend Mode
              3. 12.4.4.4.3.8.3 Wakeup request
            9. 12.4.4.4.3.9 Test Modes
              1. 12.4.4.4.3.9.1 Internal Loopback Mode
          4. 12.4.4.4.4  Timestamp Generation
            1. 12.4.4.4.4.1 External Timestamp Counter
          5. 12.4.4.4.5  Timeout Counter
          6. 12.4.4.4.6  ECC Support
            1. 12.4.4.4.6.1 ECC Wrapper
            2. 12.4.4.4.6.2 ECC Aggregator
          7. 12.4.4.4.7  Rx Handling
            1. 12.4.4.4.7.1 Acceptance Filtering
              1. 12.4.4.4.7.1.1 Range Filter
              2. 12.4.4.4.7.1.2 Filter for specific IDs
              3. 12.4.4.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.4.4.7.1.4 Standard Message ID Filtering
              5. 12.4.4.4.7.1.5 Extended Message ID Filtering
            2. 12.4.4.4.7.2 Rx FIFOs
              1. 12.4.4.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.4.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.4.4.7.3 Dedicated Rx Buffers
              1. 12.4.4.4.7.3.1 Rx Buffer Handling
            4. 12.4.4.4.7.4 Debug on CAN Support
          8. 12.4.4.4.8  Tx Handling
            1. 12.4.4.4.8.1 Transmit Pause
            2. 12.4.4.4.8.2 Dedicated Tx Buffers
            3. 12.4.4.4.8.3 Tx FIFO
            4. 12.4.4.4.8.4 Tx Queue
            5. 12.4.4.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.4.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.4.4.8.7 Transmit Cancellation
            8. 12.4.4.4.8.8 Tx Event Handling
          9. 12.4.4.4.9  FIFO Acknowledge Handling
          10. 12.4.4.4.10 Message RAM
            1. 12.4.4.4.10.1 Message RAM Configuration
            2. 12.4.4.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.4.4.10.3 Tx Buffer Element
            4. 12.4.4.4.10.4 Tx Event FIFO Element
            5. 12.4.4.4.10.5 Standard Message ID Filter Element
            6. 12.4.4.4.10.6 Extended Message ID Filter Element
        5. 12.4.4.5 MCAN Registers
          1. 12.4.4.5.1 MCAN Subsystem Registers
          2. 12.4.4.5.2 MCAN Core Registers
          3. 12.4.4.5.3 MCAN ECC Aggregator Registers
    5. 12.5 Audio Interfaces
      1. 12.5.1 Audio Tracking Logic (ATL)
        1. 12.5.1.1 ATL Overview
          1. 12.5.1.1.1 ATL Features Overview
          2. 12.5.1.1.2 ATL Not Supported Features
    6. 12.6 Timer Modules
      1. 12.6.1 Global Timebase Counter (GTC)
        1. 12.6.1.1 GTC Overview
          1. 12.6.1.1.1 GTC Features
          2. 12.6.1.1.2 GTC Not Supported Features
        2. 12.6.1.2 GTC Integration
        3. 12.6.1.3 GTC Functional Description
          1. 12.6.1.3.1 GTC Block Diagram
          2. 12.6.1.3.2 GTC Counter
          3. 12.6.1.3.3 GTC Gray Encoder
          4. 12.6.1.3.4 GTC Push Event Generation
          5. 12.6.1.3.5 GTC Register Partitioning
        4. 12.6.1.4 GTC Registers
          1. 12.6.1.4.1 GTC0_GTC_CFG0 Registers
          2. 12.6.1.4.2 GTC0_GTC_CFG1 Registers
          3. 12.6.1.4.3 GTC0_GTC_CFG2 Registers
          4. 12.6.1.4.4 GTC0_GTC_CFG3 Registers
      2. 12.6.2 Windowed Watchdog Timer (WWDT)
        1. 12.6.2.1 RTI Overview
          1. 12.6.2.1.1 RTI Features
          2. 12.6.2.1.2 RTI Not Supported Features
        2. 12.6.2.2 RTI Integration
          1. 12.6.2.2.1 RTI Integration in MCU Domain
          2. 12.6.2.2.2 RTI Integration in MAIN Domain
        3. 12.6.2.3 RTI Functional Description
          1. 12.6.2.3.1 RTI Counter Operation
          2. 12.6.2.3.2 RTI Digital Watchdog
          3. 12.6.2.3.3 RTI Digital Windowed Watchdog
          4. 12.6.2.3.4 RTI Low Power Mode Operation
          5. 12.6.2.3.5 RTI Debug Mode Behavior
        4. 12.6.2.4 RTI Registers
      3. 12.6.3 Timers
        1. 12.6.3.1 Timers Overview
          1. 12.6.3.1.1 Timers Features
          2. 12.6.3.1.2 Timers Not Supported Features
        2. 12.6.3.2 Timers Environment
          1. 12.6.3.2.1 Timer External System Interface
        3. 12.6.3.3 Timers Integration
          1. 12.6.3.3.1 Timers Integration in MCU Domain
          2. 12.6.3.3.2 Timers Integration in MAIN Domain
        4. 12.6.3.4 Timers Functional Description
          1. 12.6.3.4.1  Timer Block Diagram
          2. 12.6.3.4.2  Timer Power Management
            1. 12.6.3.4.2.1 Wake-Up Capability
          3. 12.6.3.4.3  Timer Software Reset
          4. 12.6.3.4.4  Timer Interrupts
          5. 12.6.3.4.5  Timer Mode Functionality
            1. 12.6.3.4.5.1 1-ms Tick Generation
          6. 12.6.3.4.6  Timer Capture Mode Functionality
          7. 12.6.3.4.7  Timer Compare Mode Functionality
          8. 12.6.3.4.8  Timer Prescaler Functionality
          9. 12.6.3.4.9  Timer Pulse-Width Modulation
          10. 12.6.3.4.10 Timer Counting Rate
          11. 12.6.3.4.11 Timer Under Emulation
          12. 12.6.3.4.12 Accessing Timer Registers
            1. 12.6.3.4.12.1 Writing to Timer Registers
              1. 12.6.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.6.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.6.3.4.12.2 Reading From Timer Counter Registers
              1. 12.6.3.4.12.2.1 Read Posted
              2. 12.6.3.4.12.2.2 Read Non-Posted
          13. 12.6.3.4.13 Timer Posted Mode Selection
        5. 12.6.3.5 Timers Low-Level Programming Models
          1. 12.6.3.5.1 Timer Global Initialization
            1. 12.6.3.5.1.1 Global Initialization of Surrounding Modules
            2. 12.6.3.5.1.2 Timer Module Global Initialization
              1. 12.6.3.5.1.2.1 Main Sequence – Timer Module Global Initialization
          2. 12.6.3.5.2 Timer Operational Mode Configuration
            1. 12.6.3.5.2.1 Timer Mode
              1. 12.6.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.6.3.5.2.2 Timer Compare Mode
              1. 12.6.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.6.3.5.2.3 Timer Capture Mode
              1. 12.6.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.6.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.6.3.5.2.3.3 Subsequence – Detect Event
            4. 12.6.3.5.2.4 Timer PWM Mode
              1. 12.6.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
        6. 12.6.3.6 Timers Registers
    7. 12.7 Internal Diagnostics Modules
      1. 12.7.1 Dual Clock Comparator (DCC)
        1. 12.7.1.1 DCC Overview
          1. 12.7.1.1.1 DCC Features
          2. 12.7.1.1.2 DCC Not Supported Features
        2. 12.7.1.2 DCC Integration
          1. 12.7.1.2.1 DCC Integration in MCU Domain
          2. 12.7.1.2.2 DCC Integration in MAIN Domain
        3. 12.7.1.3 DCC Functional Description
          1. 12.7.1.3.1 DCC Counter Operation
          2. 12.7.1.3.2 DCC Low Power Mode Operation
          3. 12.7.1.3.3 DCC Suspend Mode Behavior
          4. 12.7.1.3.4 DCC Single-Shot Mode
          5. 12.7.1.3.5 DCC Continuous mode
            1. 12.7.1.3.5.1 DCC Continue on Error
            2. 12.7.1.3.5.2 DCC Error Count
          6. 12.7.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.7.1.3.7 DCC Error Trajectory record
            1. 12.7.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.7.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.7.1.3.7.3 DCC FIFO Details
            4. 12.7.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.7.1.3.8 DCC Count read registers
        4. 12.7.1.4 DCC Registers
      2. 12.7.2 Error Signaling Module (ESM)
        1. 12.7.2.1 ESM Overview
          1. 12.7.2.1.1 ESM Features
        2. 12.7.2.2 ESM Environment
        3. 12.7.2.3 ESM Integration
          1. 12.7.2.3.1 ESM Integration in WKUP Domain
          2. 12.7.2.3.2 ESM Integration in MCU Domain
          3. 12.7.2.3.3 ESM Integration in MAIN Domain
        4. 12.7.2.4 ESM Functional Description
          1. 12.7.2.4.1 ESM Interrupt Requests
            1. 12.7.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.7.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.7.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.7.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.7.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.7.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.7.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.7.2.4.2 ESM Error Event Inputs
          3. 12.7.2.4.3 ESM Error Pin Output
          4. 12.7.2.4.4 ESM Minimum Time Interval
          5. 12.7.2.4.5 ESM Protection for Registers
          6. 12.7.2.4.6 ESM Clock Stop
        5. 12.7.2.5 ESM Registers
      3. 12.7.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.7.3.1 MCRC Overview
          1. 12.7.3.1.1 MCRC Features
          2. 12.7.3.1.2 MCRC Not Supported Features
        2. 12.7.3.2 MCRC Integration
        3. 12.7.3.3 MCRC Functional Description
          1. 12.7.3.3.1  MCRC Block Diagram
          2. 12.7.3.3.2  MCRC General Operation
          3. 12.7.3.3.3  MCRC Modes of Operation
            1. 12.7.3.3.3.1 AUTO Mode
            2. 12.7.3.3.3.2 Semi-CPU Mode
            3. 12.7.3.3.3.3 Full-CPU Mode
          4. 12.7.3.3.4  PSA Signature Register
          5. 12.7.3.3.5  PSA Sector Signature Register
          6. 12.7.3.3.6  CRC Value Register
          7. 12.7.3.3.7  Raw Data Register
          8. 12.7.3.3.8  Example DMA Controller Setup
            1. 12.7.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.7.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.7.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.7.3.3.9  Pattern Count Register
          10. 12.7.3.3.10 Sector Count Register/Current Sector Register
          11. 12.7.3.3.11 Interrupts
            1. 12.7.3.3.11.1 Compression Complete Interrupt
            2. 12.7.3.3.11.2 CRC Fail Interrupt
            3. 12.7.3.3.11.3 Overrun Interrupt
            4. 12.7.3.3.11.4 Underrun Interrupt
            5. 12.7.3.3.11.5 Timeout Interrupt
            6. 12.7.3.3.11.6 Interrupt Offset Register
            7. 12.7.3.3.11.7 Error Handling
          12. 12.7.3.3.12 Power Down Mode
          13. 12.7.3.3.13 Emulation
        4. 12.7.3.4 MCRC Programming Examples
          1. 12.7.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.7.3.4.1.1 DMA Setup
            2. 12.7.3.4.1.2 Timer Setup
            3. 12.7.3.4.1.3 CRC Setup
          2. 12.7.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.7.3.4.2.1 DMA Setup
            2. 12.7.3.4.2.2 CRC Setup
          3. 12.7.3.4.3 Example: Semi-CPU Mode
            1. 12.7.3.4.3.1 DMA Setup
            2. 12.7.3.4.3.2 Timer Setup
            3. 12.7.3.4.3.3 CRC Setup
          4. 12.7.3.4.4 Example: Full-CPU Mode
            1. 12.7.3.4.4.1 CRC Setup
        5. 12.7.3.5 MCRC Registers
      4. 12.7.4 ECC Aggregator
        1. 12.7.4.1 ECC Aggregator Overview
          1. 12.7.4.1.1 ECC Aggregator Features
        2. 12.7.4.2 ECC Aggregator Integration
        3. 12.7.4.3 ECC Aggregator Functional Description
          1. 12.7.4.3.1 ECC Aggregator Block Diagram
          2. 12.7.4.3.2 ECC Aggregator Register Groups
          3. 12.7.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.7.4.3.4 Serial Write Operation
          5. 12.7.4.3.5 Interrupts
          6. 12.7.4.3.6 Inject Only Mode
        4. 12.7.4.4 ECC Aggregator Registers
  15. 13On-Chip Debug
  16. 14Revision History

5.1.3.4 CTRL_MMR0 Registers

Table 5-695 lists the memory-mapped registers for the CTRL_MMR0. All register offset addresses not listed in Table 5-695 should be considered as reserved locations and the register contents should not be modified.

Table 5-694 CTRL_MMR0 Instances
InstanceBase Address
CTRL_MMR0_CFG00010 0000h
Table 5-695 CTRL_MMR0 Registers
Proxy0 Offset Proxy1 Offset Acronym Register Name CTRL_MMR0_CFG0 Proxy0 Physical Address CTRL_MMR0_CFG0 Proxy1 Physical Address
0h 2000h CTRLMMR_PID Peripheral Identification Register 0010 0000h 0010 2000h
8h 2008h CTRLMMR_MMR_CFG1 Configuration register 1 0010 0008h 0010 2008h
30h 2030h CTRLMMR_MAIN_DEVSTAT MAIN Domain Device Status Register 0010 0030h 0010 2030h
34h 2034h CTRLMMR_MAIN_BOOTCFG MAIN Domain Boot Configuration Register 0010 0034h 0010 2034h
44h 2044h CTRLMMR_MAIN_FEATURE_STAT1 MAIN Domain Feature Status Register 1 0010 0044h 0010 2044h
120h 2120h CTRLMMR_IPC_SET8 IPC Generation Register 8 0010 0120h 0010 2120h
124h 2124h CTRLMMR_IPC_SET9 IPC Generation Register 9 0010 0124h 0010 2124h
140h 2140h CTRLMMR_IPC_SET16 IPC Generation Register 16 0010 0140h 0010 2140h
144h 2144h CTRLMMR_IPC_SET17 IPC Generation Register 17 0010 0144h 0010 2144h
1A0h 21A0h CTRLMMR_IPC_CLR8 IPC Acknowledge Register8 0010 01A0h 0010 21A0h
1A4h 21A4h CTRLMMR_IPC_CLR9 IPC Acknowledge Register9 0010 01A4h 0010 21A4h
1C0h 21C0h CTRLMMR_IPC_CLR16 IPC Acknowledge Register 16 0010 01C0h 0010 21C0h
1C4h 21C4h CTRLMMR_IPC_CLR17 IPC Acknowledge Register 17 0010 01C4h 0010 21C4h
210h 2210h CTRLMMR_PCI_DEVICE_ID PCI Device ID Register 0010 0210h 0010 2210h
220h 2220h CTRLMMR_USB_DEVICE_ID USB Device ID Register 0010 0220h 0010 2220h
1008h 3008h CTRLMMR_LOCK0_KICK0 Partition 0 Lock Key 0 Register 0010 1008h 0010 3008h
100Ch 300Ch CTRLMMR_LOCK0_KICK1 Partition 0 Lock Key 1 Register 0010 100Ch 0010 300Ch
1010h 3010h CTRLMMR_INTR_RAW_STAT Interrupt Raw Status Register 0010 1010h 0010 3010h
1014h 3014h CTRLMMR_INTR_STAT_CLR Interrupt Status and Clear Register 0010 1014h 0010 3014h
1018h 3018h CTRLMMR_INTR_EN_SET Interrupt Enable Set Register 0010 1018h 0010 3018h
101Ch 301Ch CTRLMMR_INTR_EN_CLR Interrupt Enable Clear Register 0010 101Ch 0010 301Ch
1020h 3020h CTRLMMR_EOI End of Interrupt Register 0010 1020h 0010 3020h
1024h 3024h CTRLMMR_FAULT_ADDR Fault Address Register 0010 1024h 0010 3024h
1028h 3028h CTRLMMR_FAULT_TYPE Fault Type Register 0010 1028h 0010 3028h
102Ch 302Ch CTRLMMR_FAULT_ATTR Fault Attribute Register 0010 102Ch 0010 302Ch
1030h 3030h CTRLMMR_FAULT_CLR Fault Clear Register 0010 1030h 0010 3030h
4000h 6000h CTRLMMR_USB0_CTRL USB0 Control Register 0010 4000h 0010 6000h
4008h 6008h CTRLMMR_USB0_PHY_CTRL USB0 Phy Control Register 0010 4008h 0010 6008h
4044h 6044h CTRLMMR_ENET1_CTRL Ethernet1 Control Register 0010 4044h 0010 6044h
4048h 6048h CTRLMMR_ENET2_CTRL Ethernet2 Control Register 0010 4048h 0010 6048h
404Ch 604Ch CTRLMMR_ENET3_CTRL Ethernet3 Control Register 0010 404Ch 0010 604Ch
4050h 6050h CTRLMMR_ENET4_CTRL Ethernet4 Control Register 0010 4050h 0010 6050h
4074h 6074h CTRLMMR_PCIE1_CTRL PCEI1 Control Register 0010 4074h 0010 6074h
4080h 6080h CTRLMMR_SERDES0_LN0_CTRL SERDES0 Lane0 Control Register 0010 4080h 0010 6080h
4084h 6084h CTRLMMR_SERDES0_LN1_CTRL SERDES0 Lane1 Control Register 0010 4084h 0010 6084h
4088h 6088h CTRLMMR_SERDES0_LN2_CTRL SERDES0 Lane2 Control Register 0010 4088h 0010 6088h
408Ch 608Ch CTRLMMR_SERDES0_LN3_CTRL SERDES0 Lane3 Control Register 0010 408Ch 0010 608Ch
40E0h 60E0h CTRLMMR_SERDES0_CTRL SERDES0 Control Register 0010 40E0h 0010 60E0h
4140h 6140h CTRLMMR_EPWM0_CTRL PWM0 Control Register 0010 4140h 0010 6140h
4144h 6144h CTRLMMR_EPWM1_CTRL PWM1 Control Register 0010 4144h 0010 6144h
4148h 6148h CTRLMMR_EPWM2_CTRL PWM2 Control Register 0010 4148h 0010 6148h
414Ch 614Ch CTRLMMR_EPWM3_CTRL PWM3 Control Register 0010 414Ch 0010 614Ch
4150h 6150h CTRLMMR_EPWM4_CTRL PWM4 Control Register 0010 4150h 0010 6150h
4154h 6154h CTRLMMR_EPWM5_CTRL PWM5 Control Register 0010 4154h 0010 6154h
4160h 6160h CTRLMMR_SOCA_SEL PWM SOCA Select Register 0010 4160h 0010 6160h
4164h 6164h CTRLMMR_SOCB_SEL PWM SOCB Select Register 0010 4164h 0010 6164h
41A0h 61A0h CTRLMMR_EQEP_STAT EQEP Status Register 0010 41A0h 0010 61A0h
41B4h 61B4h CTRLMMR_SDIO1_CTRL SDIO1 Control Register 0010 41B4h 0010 61B4h
4200h 6200h CTRLMMR_TIMER0_CTRL TIMER0 Control Register 0010 4200h 0010 6200h
4204h 6204h CTRLMMR_TIMER1_CTRL TIMER1 Control Register 0010 4204h 0010 6204h
4208h 6208h CTRLMMR_TIMER2_CTRL TIMER2 Control Register 0010 4208h 0010 6208h
420Ch 620Ch CTRLMMR_TIMER3_CTRL TIMER3 Control Register 0010 420Ch 0010 620Ch
4210h 6210h CTRLMMR_TIMER4_CTRL TIMER4 Control Register 0010 4210h 0010 6210h
4214h 6214h CTRLMMR_TIMER5_CTRL TIMER5 Control Register 0010 4214h 0010 6214h
4218h 6218h CTRLMMR_TIMER6_CTRL TIMER6 Control Register 0010 4218h 0010 6218h
421Ch 621Ch CTRLMMR_TIMER7_CTRL TIMER7 Control Register 0010 421Ch 0010 621Ch
4220h 6220h CTRLMMR_TIMER8_CTRL TIMER8 Control Register 0010 4220h 0010 6220h
4224h 6224h CTRLMMR_TIMER9_CTRL TIMER9 Control Register 0010 4224h 0010 6224h
4228h 6228h CTRLMMR_TIMER10_CTRL TIMER10 Control Register 0010 4228h 0010 6228h
422Ch 622Ch CTRLMMR_TIMER11_CTRL TIMER11 Control Register 0010 422Ch 0010 622Ch
4230h 6230h CTRLMMR_TIMER12_CTRL TIMER12 Control Register 0010 4230h 0010 6230h
4234h 6234h CTRLMMR_TIMER13_CTRL TIMER13 Control Register 0010 4234h 0010 6234h
4238h 6238h CTRLMMR_TIMER14_CTRL TIMER14 Control Register 0010 4238h 0010 6238h
423Ch 623Ch CTRLMMR_TIMER15_CTRL TIMER15 Control Register 0010 423Ch 0010 623Ch
4240h 6240h CTRLMMR_TIMER16_CTRL TIMER16 Control Register 0010 4240h 0010 6240h
4244h 6244h CTRLMMR_TIMER17_CTRL TIMER17 Control Register 0010 4244h 0010 6244h
4248h 6248h CTRLMMR_TIMER18_CTRL TIMER18 Control Register 0010 4248h 0010 6248h
424Ch 624Ch CTRLMMR_TIMER19_CTRL TIMER19 Control Register 0010 424Ch 0010 624Ch
4280h 6280h CTRLMMR_TIMERIO0_CTRL TIMERIO0 Control Register 0010 4280h 0010 6280h
4284h 6284h CTRLMMR_TIMERIO1_CTRL TIMERIO1 Control Register 0010 4284h 0010 6284h
4288h 6288h CTRLMMR_TIMERIO2_CTRL TIMERIO2 Control Register 0010 4288h 0010 6288h
428Ch 628Ch CTRLMMR_TIMERIO3_CTRL TIMERIO3 Control Register 0010 428Ch 0010 628Ch
4290h 6290h CTRLMMR_TIMERIO4_CTRL TIMERIO4 Control Register 0010 4290h 0010 6290h
4294h 6294h CTRLMMR_TIMERIO5_CTRL TIMERIO5 Control Register 0010 4294h 0010 6294h
4298h 6298h CTRLMMR_TIMERIO6_CTRL TIMERIO6 Control Register 0010 4298h 0010 6298h
429Ch 629Ch CTRLMMR_TIMERIO7_CTRL TIMERIO7 Control Register 0010 429Ch 0010 629Ch
42C0h 62C0h CTRLMMR_I3C0_CTRL0 I3C0 Control Register 0 0010 42C0h 0010 62C0h
42C4h 62C4h CTRLMMR_I3C0_CTRL1 I3C0 Control Register 1 0010 42C4h 0010 62C4h
42E0h 62E0h CTRLMMR_I2C0_CTRL I2C0 Control Register 0010 42E0h 0010 62E0h
4584h 6584h CTRLMMR_MCASP1_CTRL McASP1 Control Register 0010 4584h 0010 6584h
4588h 6588h CTRLMMR_MCASP2_CTRL McASP2 Control Register 0010 4588h 0010 6588h
4600h 6600h CTRLMMR_MAIN_MTOG0_CTRL GIC Master Read Timeout Gasket Control Register 0010 4600h 0010 6600h
4604h 6604h CTRLMMR_MAIN_MTOG1_CTRL GIC Master Write Timeout Gasket Control Register 0010 4604h 0010 6604h
4608h 6608h CTRLMMR_MAIN_MTOG2_CTRL eMMC0 Master Read Timeout Gasket Control Register 0010 4608h 0010 6608h
460Ch 660Ch CTRLMMR_MAIN_MTOG3_CTRL eMMC0 Master Write Timeout Gasket Control Register 0010 460Ch 0010 660Ch
4610h 6610h CTRLMMR_MAIN_MTOG4_CTRL eMMC1 Master Read Timeout Gasket Control Register 0010 4610h 0010 6610h
4614h 6614h CTRLMMR_MAIN_MTOG5_CTRL eMMC1 Master Write Timeout Gasket Control Register 0010 4614h 0010 6614h
4628h 6628h CTRLMMR_MAIN_MTOG10_CTRL PCIe1 Master Read Timeout Gasket Control Register 0010 4628h 0010 6628h
462Ch 662Ch CTRLMMR_MAIN_MTOG11_CTRL PCIe1 Master Write Timeout Gasket Control Register 0010 462Ch 0010 662Ch
4630h 6630h CTRLMMR_MAIN_MTOG12_CTRL USB0 Master Read Timeout Gasket Control Register 0010 4630h 0010 6630h
4634h 6634h CTRLMMR_MAIN_MTOG13_CTRL USB0 Master Write Timeout Gasket Control Register 0010 4634h 0010 6634h
4638h 6638h CTRLMMR_MAIN_MTOG14_CTRL Navigator Subsystem Master Timeout Gasket Control Register 0010 4638h 0010 6638h
4640h 6640h CTRLMMR_MAIN_MTOG16_CTRL R5_0 Memory Mstr Rd Timeout Gasket Control Register 0010 4640h 0010 6640h
4644h 6644h CTRLMMR_MAIN_MTOG17_CTRL R5_0 Memory Mstr Wr Timeout Gasket Control Register 0010 4644h 0010 6644h
4648h 6648h CTRLMMR_MAIN_MTOG18_CTRL R5_1 Memory Mstr Rd Timeout Gasket Control Register 0010 4648h 0010 6648h
464Ch 664Ch CTRLMMR_MAIN_MTOG19_CTRL R5_1 Memory Mstr Wr Timeout Gasket Control Register 0010 464Ch 0010 664Ch
46C0h 66C0h CTRLMMR_CC_EN_FLUSH_CTRL Compute Cluster Eagles Nest Flush Control Register 0010 46C0h 0010 66C0h
5008h 7008h CTRLMMR_LOCK1_KICK0 Partition 1 Lock Key 0 Register 0010 5008h 0010 7008h
500Ch 700Ch CTRLMMR_LOCK1_KICK1 Partition 1 Lock Key 1 Register 0010 500Ch 0010 700Ch
8000h A000h CTRLMMR_OBSCLK0_CTRL Observe Clock 0 Output Control Register 0010 8000h 0010 A000h
8004h A004h CTRLMMR_OBSCLK1_CTRL Observe Clock 1 Select Register 0010 8004h 0010 A004h
8010h A010h CTRLMMR_CLKOUT_CTRL CLKOUT Control Register 0010 8010h 0010 A010h
8030h A030h CTRLMMR_GTC_CLKSEL GTC Clock Select Register 0010 8030h 0010 A030h
803Ch A03Ch CTRLMMR_EFUSE_CLKSEL Main eFuse Controller Clock Select Register 0010 803Ch 0010 A03Ch
8084h A084h CTRLMMR_PCIE1_CLKSEL PCIE1 Clock Select Register 0010 8084h 0010 A084h
8090h A090h CTRLMMR_CPSW_CLKSEL CPSW Clock Select Register 0010 8090h 0010 A090h
8098h A098h CTRLMMR_NAVSS_CLKSEL Navigator Subsystem Clock Select Register 0010 8098h 0010 A098h
80B0h A0B0h CTRLMMR_EMMC0_CLKSEL eMMC0 Clock Select Register 0010 80B0h 0010 A0B0h
80B4h A0B4h CTRLMMR_EMMC1_CLKSEL eMMC1 Clock Select Register 0010 80B4h 0010 A0B4h
80D0h A0D0h CTRLMMR_GPMC_CLKSEL GPMC Clock Select Register 0010 80D0h 0010 A0D0h
80E0h A0E0h CTRLMMR_USB0_CLKSEL USB0 Clock Select Register 0010 80E0h 0010 A0E0h
8100h A100h CTRLMMR_TIMER0_CLKSEL Timer0 Clock Select Register 0010 8100h 0010 A100h
8104h A104h CTRLMMR_TIMER1_CLKSEL Timer1 Clock Select Register 0010 8104h 0010 A104h
8108h A108h CTRLMMR_TIMER2_CLKSEL Timer2 Clock Select Register 0010 8108h 0010 A108h
810Ch A10Ch CTRLMMR_TIMER3_CLKSEL Timer3 Clock Select Register 0010 810Ch 0010 A10Ch
8110h A110h CTRLMMR_TIMER4_CLKSEL Timer4 Clock Select Register 0010 8110h 0010 A110h
8114h A114h CTRLMMR_TIMER5_CLKSEL Timer5 Clock Select Register 0010 8114h 0010 A114h
8118h A118h CTRLMMR_TIMER6_CLKSEL Timer6 Clock Select Register 0010 8118h 0010 A118h
811Ch A11Ch CTRLMMR_TIMER7_CLKSEL Timer7 Clock Select Register 0010 811Ch 0010 A11Ch
8120h A120h CTRLMMR_TIMER8_CLKSEL Timer8 Clock Select Register 0010 8120h 0010 A120h
8124h A124h CTRLMMR_TIMER9_CLKSEL Timer9 Clock Select Register 0010 8124h 0010 A124h
8128h A128h CTRLMMR_TIMER10_CLKSEL Timer10 Clock Select Register 0010 8128h 0010 A128h
812Ch A12Ch CTRLMMR_TIMER11_CLKSEL Timer11 Clock Select Register 0010 812Ch 0010 A12Ch
8130h A130h CTRLMMR_TIMER12_CLKSEL Timer12 Clock Select Register 0010 8130h 0010 A130h
8134h A134h CTRLMMR_TIMER13_CLKSEL Timer13 Clock Select Register 0010 8134h 0010 A134h
8138h A138h CTRLMMR_TIMER14_CLKSEL Timer14 Clock Select Register 0010 8138h 0010 A138h
813Ch A13Ch CTRLMMR_TIMER15_CLKSEL Timer15 Clock Select Register 0010 813Ch 0010 A13Ch
8140h A140h CTRLMMR_TIMER16_CLKSEL Timer16 Clock Select Register 0010 8140h 0010 A140h
8144h A144h CTRLMMR_TIMER17_CLKSEL Timer17 Clock Select Register 0010 8144h 0010 A144h
8148h A148h CTRLMMR_TIMER18_CLKSEL Timer18 Clock Select Register 0010 8148h 0010 A148h
814Ch A14Ch CTRLMMR_TIMER19_CLKSEL Timer19 Clock Select Register 0010 814Ch 0010 A14Ch
8190h A190h CTRLMMR_SPI0_CLKSEL SPI0 Clock Select Register 0010 8190h 0010 A190h
8194h A194h CTRLMMR_SPI1_CLKSEL SPI1 Clock Select Register 0010 8194h 0010 A194h
8198h A198h CTRLMMR_SPI2_CLKSEL SPI2 Clock Select Register 0010 8198h 0010 A198h
819Ch A19Ch CTRLMMR_SPI3_CLKSEL SPI3 Clock Select Register 0010 819Ch 0010 A19Ch
81A4h A1A4h CTRLMMR_SPI5_CLKSEL SPI5 Clock Select Register 0010 81A4h 0010 A1A4h
81A8h A1A8h CTRLMMR_SPI6_CLKSEL SPI6 Clock Select Register 0010 81A8h 0010 A1A8h
81ACh A1ACh CTRLMMR_SPI7_CLKSEL SPI7 Clock Select Register 0010 81ACh 0010 A1ACh
81C0h A1C0h CTRLMMR_USART0_CLK_CTRL USART0 Functional Clock Control 0010 81C0h 0010 A1C0h
81C4h A1C4h CTRLMMR_USART1_CLK_CTRL USART1 Functional Clock Control 0010 81C4h 0010 A1C4h
81C8h A1C8h CTRLMMR_USART2_CLK_CTRL USART2 Functional Clock Control 0010 81C8h 0010 A1C8h
81CCh A1CCh CTRLMMR_USART3_CLK_CTRL USART3 Functional Clock Control 0010 81CCh 0010 A1CCh
81D0h A1D0h CTRLMMR_USART4_CLK_CTRL USART4 Functional Clock Control 0010 81D0h 0010 A1D0h
81D4h A1D4h CTRLMMR_USART5_CLK_CTRL USART5 Functional Clock Control 0010 81D4h 0010 A1D4h
81D8h A1D8h CTRLMMR_USART6_CLK_CTRL USART6 Functional Clock Control 0010 81D8h 0010 A1D8h
81DCh A1DCh CTRLMMR_USART7_CLK_CTRL USART7 Functional Clock Control 0010 81DCh 0010 A1DCh
81E0h A1E0h CTRLMMR_USART8_CLK_CTRL USART8 Functional Clock Control 0010 81E0h 0010 A1E0h
81E4h A1E4h CTRLMMR_USART9_CLK_CTRL USART9 Functional Clock Control 0010 81E4h 0010 A1E4h
8200h A200h CTRLMMR_MCASP0_CLKSEL McASP0 Clock Select Register 0010 8200h 0010 A200h
8204h A204h CTRLMMR_MCASP1_CLKSEL McASP1 Clock Select Register 0010 8204h 0010 A204h
8208h A208h CTRLMMR_MCASP2_CLKSEL McASP2 Clock Select Register 0010 8208h 0010 A208h
8240h A240h CTRLMMR_MCASP0_AHCLKSEL McASP0 AHClock Select Register 0010 8240h 0010 A240h
8244h A244h CTRLMMR_MCASP1_AHCLKSEL McASP1 AHClock Select Register 0010 8244h 0010 A244h
8248h A248h CTRLMMR_MCASP2_AHCLKSEL McASP2 AHClock Select Register 0010 8248h 0010 A248h
82A0h A2A0h CTRLMMR_ATL_BWS0_SEL ATL BWS0 Select Register 0010 82A0h 0010 A2A0h
82A4h A2A4h CTRLMMR_ATL_BWS1_SEL ATL BWS1 Select Register 0010 82A4h 0010 A2A4h
82A8h A2A8h CTRLMMR_ATL_BWS2_SEL ATL BWS2 Select Register 0010 82A8h 0010 A2A8h
82ACh A2ACh CTRLMMR_ATL_BWS3_SEL ATL BWS3 Select Register 0010 82ACh 0010 A2ACh
82B0h A2B0h CTRLMMR_ATL_AWS0_SEL ATL AWS Select Register 0010 82B0h 0010 A2B0h
82B4h A2B4h CTRLMMR_ATL_AWS1_SEL ATL AWS Select Register 0010 82B4h 0010 A2B4h
82B8h A2B8h CTRLMMR_ATL_AWS2_SEL ATL AWS Select Register 0010 82B8h 0010 A2B8h
82BCh A2BCh CTRLMMR_ATL_AWS3_SEL ATL AWS Select Register 0010 82BCh 0010 A2BCh
82C0h A2C0h CTRLMMR_ATL_CLKSEL ATL Clock Select Register 0010 82C0h 0010 A2C0h
82E0h A2E0h CTRLMMR_AUDIO_REFCLK0_CTRL Audio External Reference Clock Control Register 0010 82E0h 0010 A2E0h
82E4h A2E4h CTRLMMR_AUDIO_REFCLK1_CTRL Audio External Reference Clock Control Register 0010 82E4h 0010 A2E4h
8380h A380h CTRLMMR_WWD0_CLKSEL WWD0 Clock Select Register 0010 8380h 0010 A380h
8384h A384h CTRLMMR_WWD1_CLKSEL WWD1 Clock Select Register 0010 8384h 0010 A384h
83F0h A3F0h CTRLMMR_WWD28_CLKSEL WWD28 Clock Select Register 0010 83F0h 0010 A3F0h
83F4h A3F4h CTRLMMR_WWD29_CLKSEL WWD29 Clock Select Register 0010 83F4h 0010 A3F4h
8400h A400h CTRLMMR_SERDES0_CLKSEL SERDES 0 Clock Select Register 0010 8400h 0010 A400h
8480h A480h CTRLMMR_MCAN0_CLKSEL MCAN0 Clock Select Register 0010 8480h 0010 A480h
8484h A484h CTRLMMR_MCAN1_CLKSEL MCAN1 Clock Select Register 0010 8484h 0010 A484h
8488h A488h CTRLMMR_MCAN2_CLKSEL MCAN2 Clock Select Register 0010 8488h 0010 A488h
848Ch A48Ch CTRLMMR_MCAN3_CLKSEL MCAN3 Clock Select Register 0010 848Ch 0010 A48Ch
8490h A490h CTRLMMR_MCAN4_CLKSEL MCAN4 Clock Select Register 0010 8490h 0010 A490h
8494h A494h CTRLMMR_MCAN5_CLKSEL MCAN5 Clock Select Register 0010 8494h 0010 A494h
8498h A498h CTRLMMR_MCAN6_CLKSEL MCAN6 Clock Select Register 0010 8498h 0010 A498h
849Ch A49Ch CTRLMMR_MCAN7_CLKSEL MCAN7 Clock Select Register 0010 849Ch 0010 A49Ch
84A0h A4A0h CTRLMMR_MCAN8_CLKSEL MCAN8 Clock Select Register 0010 84A0h 0010 A4A0h
84A4h A4A4h CTRLMMR_MCAN9_CLKSEL MCAN9 Clock Select Register 0010 84A4h 0010 A4A4h
84A8h A4A8h CTRLMMR_MCAN10_CLKSEL MCAN10 Clock Select Register 0010 84A8h 0010 A4A8h
84ACh A4ACh CTRLMMR_MCAN11_CLKSEL MCAN11 Clock Select Register 0010 84ACh 0010 A4ACh
84B0h A4B0h CTRLMMR_MCAN12_CLKSEL MCAN12 Clock Select Register 0010 84B0h 0010 A4B0h
84B4h A4B4h CTRLMMR_MCAN13_CLKSEL MCAN13 Clock Select Register 0010 84B4h 0010 A4B4h
84B8h A4B8h CTRLMMR_MCAN14_CLKSEL MCAN14 Clock Select Register 0010 84B8h 0010 A4B8h
84BCh A4BCh CTRLMMR_MCAN15_CLKSEL MCAN15 Clock Select Register 0010 84BCh 0010 A4BCh
84C0h A4C0h CTRLMMR_MCAN16_CLKSEL MCAN16 Clock Select Register 0010 84C0h 0010 A4C0h
84C4h A4C4h CTRLMMR_MCAN17_CLKSEL MCAN17 Clock Select Register 0010 84C4h 0010 A4C4h
9008h B008h CTRLMMR_LOCK2_KICK0 Partition 2 Lock Key 0 Register 0010 9008h 0010 B008h
900Ch B00Ch CTRLMMR_LOCK2_KICK1 Partition 2 Lock Key 1 Register 0010 900Ch 0010 B00Ch
C000h E000h CTRLMMR_MCU0_LBIST_CTRL SoC_Pulsar Logic BIST Control Register 0010 C000h 0010 E000h
C004h E004h CTRLMMR_MCU0_LBIST_PATCOUNT SoC_Pulsar Logic BIST Pattern Count Register 0010 C004h 0010 E004h
C008h E008h CTRLMMR_MCU0_LBIST_SEED0 SoC_Pulsar Logic BIST Seed0 Register 0010 C008h 0010 E008h
C00Ch E00Ch CTRLMMR_MCU0_LBIST_SEED1 SoC_Pulsar Logic BIST Seed1 Register 0010 C00Ch 0010 E00Ch
C010h E010h CTRLMMR_MCU0_LBIST_SPARE0 SoC_Pulsar Logic BIST Spare0 Register 0010 C010h 0010 E010h
C014h E014h CTRLMMR_MCU0_LBIST_SPARE1 SoC_Pulsar Logic BIST Spare1 Register 0010 C014h 0010 E014h
C018h E018h CTRLMMR_MCU0_LBIST_STAT SoC_Pulsar Logic BIST Status Register 0010 C018h 0010 E018h
C01Ch E01Ch CTRLMMR_MCU0_LBIST_MISR SoC_Pulsar Logic BIST MISR Register 0010 C01Ch 0010 E01Ch
C100h E100h CTRLMMR_MPU0_LBIST_CTRL ARM Cluster0 Logic BIST Control Register 0010 C100h 0010 E100h
C104h E104h CTRLMMR_MPU0_LBIST_PATCOUNT ARM Cluster0 Logic BIST Pattern Count Register 0010 C104h 0010 E104h
C108h E108h CTRLMMR_MPU0_LBIST_SEED0 ARM Cluster0 Logic BIST Seed0 Register 0010 C108h 0010 E108h
C10Ch E10Ch CTRLMMR_MPU0_LBIST_SEED1 ARM Cluster0 Logic BIST Seed1 Register 0010 C10Ch 0010 E10Ch
C110h E110h CTRLMMR_MPU0_LBIST_SPARE0 ARM Cluster0 Logic BIST Spare0 Register 0010 C110h 0010 E110h
C114h E114h CTRLMMR_MPU0_LBIST_SPARE1 ARM Cluster0 Logic BIST Spare1 Register 0010 C114h 0010 E114h
C118h E118h CTRLMMR_MPU0_LBIST_STAT ARM Cluster0 Logic BIST Status Register 0010 C118h 0010 E118h
C11Ch E11Ch CTRLMMR_MPU0_LBIST_MISR ARM Cluster0 Logic BIST MISR Register 0010 C11Ch 0010 E11Ch
C280h E280h CTRLMMR_MCU0_LBIST_SIG MCU Cluster0 Logic BIST MISR Signature Register 0010 C280h 0010 E280h
C2A0h E2A0h CTRLMMR_MPU0_LBIST_SIG ARM Cluster0 Logic BIST MISR Signature Register 0010 C2A0h 0010 E2A0h
C320h E320h CTRLMMR_FUSE_CRC_STAT MAIN eFUse CRC Status Register 0010 C320h 0010 E320h
D008h F008h CTRLMMR_LOCK3_KICK0 Partition 3 Lock Key 0 Register 0010 D008h 0010 F008h
D00Ch F00Ch CTRLMMR_LOCK3_KICK1 Partition 3 Lock Key 1 Register 0010 D00Ch 0010 F00Ch
14000h 16000h CTRLMMR_CHNG_DDR4_FSP_REQ Change LPDDR4 FSP Request Register 0011 4000h 0011 6000h
14004h 16004h CTRLMMR_CHNG_DDR4_FSP_ACK Change LPDDR4 FSP Acknowledge Register 0011 4004h 0011 6004h
14080h 16080h CTRLMMR_DDR4_FSP_CLKCHNG_REQ LPDDR4 FSP Clock Change Request Register 0011 4080h 0011 6080h
140C0h 160C0h CTRLMMR_DDR4_FSP_CLKCHNG_ACK LPDDR4 FSP Clock Change Acknowledge Register 0011 40C0h 0011 60C0h
15008h 17008h CTRLMMR_LOCK5_KICK0 Partition 5 Lock Key 0 Register 0011 5008h 0011 7008h
1500Ch 1700Ch CTRLMMR_LOCK5_KICK1 Partition 5 Lock Key 1 Register 0011 500Ch 0011 700Ch
1C000h 1E000h CTRLMMR_PADCONFIG0 PAD Configuration Register 0 0011 C000h 0011 E000h
1C004h 1E004h CTRLMMR_PADCONFIG1 PAD Configuration Register 1 0011 C004h 0011 E004h
1C008h 1E008h CTRLMMR_PADCONFIG2 PAD Configuration Register 2 0011 C008h 0011 E008h
1C00Ch 1E00Ch CTRLMMR_PADCONFIG3 PAD Configuration Register 3 0011 C00Ch 0011 E00Ch
1C010h 1E010h CTRLMMR_PADCONFIG4 PAD Configuration Register 4 0011 C010h 0011 E010h
1C014h 1E014h CTRLMMR_PADCONFIG5 PAD Configuration Register 5 0011 C014h 0011 E014h
1C018h 1E018h CTRLMMR_PADCONFIG6 PAD Configuration Register 6 0011 C018h 0011 E018h
1C01Ch 1E01Ch CTRLMMR_PADCONFIG7 PAD Configuration Register 7 0011 C01Ch 0011 E01Ch
1C020h 1E020h CTRLMMR_PADCONFIG8 PAD Configuration Register 8 0011 C020h 0011 E020h
1C024h 1E024h CTRLMMR_PADCONFIG9 PAD Configuration Register 9 0011 C024h 0011 E024h
1C028h 1E028h CTRLMMR_PADCONFIG10 PAD Configuration Register 10 0011 C028h 0011 E028h
1C02Ch 1E02Ch CTRLMMR_PADCONFIG11 PAD Configuration Register 11 0011 C02Ch 0011 E02Ch
1C030h 1E030h CTRLMMR_PADCONFIG12 PAD Configuration Register 12 0011 C030h 0011 E030h
1C034h 1E034h CTRLMMR_PADCONFIG13 PAD Configuration Register 13 0011 C034h 0011 E034h
1C038h 1E038h CTRLMMR_PADCONFIG14 PAD Configuration Register 14 0011 C038h 0011 E038h
1C03Ch 1E03Ch CTRLMMR_PADCONFIG15 PAD Configuration Register 15 0011 C03Ch 0011 E03Ch
1C040h 1E040h CTRLMMR_PADCONFIG16 PAD Configuration Register 16 0011 C040h 0011 E040h
1C044h 1E044h CTRLMMR_PADCONFIG17 PAD Configuration Register 17 0011 C044h 0011 E044h
1C048h 1E048h CTRLMMR_PADCONFIG18 PAD Configuration Register 18 0011 C048h 0011 E048h
1C04Ch 1E04Ch CTRLMMR_PADCONFIG19 PAD Configuration Register 19 0011 C04Ch 0011 E04Ch
1C050h 1E050h CTRLMMR_PADCONFIG20 PAD Configuration Register 20 0011 C050h 0011 E050h
1C054h 1E054h CTRLMMR_PADCONFIG21 PAD Configuration Register 21 0011 C054h 0011 E054h
1C058h 1E058h CTRLMMR_PADCONFIG22 PAD Configuration Register 22 0011 C058h 0011 E058h
1C05Ch 1E05Ch CTRLMMR_PADCONFIG23 PAD Configuration Register 23 0011 C05Ch 0011 E05Ch
1C060h 1E060h CTRLMMR_PADCONFIG24 PAD Configuration Register 24 0011 C060h 0011 E060h
1C064h 1E064h CTRLMMR_PADCONFIG25 PAD Configuration Register 25 0011 C064h 0011 E064h
1C068h 1E068h CTRLMMR_PADCONFIG26 PAD Configuration Register 26 0011 C068h 0011 E068h
1C06Ch 1E06Ch CTRLMMR_PADCONFIG27 PAD Configuration Register 27 0011 C06Ch 0011 E06Ch
1C070h 1E070h CTRLMMR_PADCONFIG28 PAD Configuration Register 28 0011 C070h 0011 E070h
1C074h 1E074h CTRLMMR_PADCONFIG29 PAD Configuration Register 29 0011 C074h 0011 E074h
1C078h 1E078h CTRLMMR_PADCONFIG30 PAD Configuration Register 30 0011 C078h 0011 E078h
1C07Ch 1E07Ch CTRLMMR_PADCONFIG31 PAD Configuration Register 31 0011 C07Ch 0011 E07Ch
1C080h 1E080h CTRLMMR_PADCONFIG32 PAD Configuration Register 32 0011 C080h 0011 E080h
1C084h 1E084h CTRLMMR_PADCONFIG33 PAD Configuration Register 33 0011 C084h 0011 E084h
1C088h 1E088h CTRLMMR_PADCONFIG34 PAD Configuration Register 34 0011 C088h 0011 E088h
1C08Ch 1E08Ch CTRLMMR_PADCONFIG35 PAD Configuration Register 35 0011 C08Ch 0011 E08Ch
1C090h 1E090h CTRLMMR_PADCONFIG36 PAD Configuration Register 36 0011 C090h 0011 E090h
1C094h 1E094h CTRLMMR_PADCONFIG37 PAD Configuration Register 37 0011 C094h 0011 E094h
1C098h 1E098h CTRLMMR_PADCONFIG38 PAD Configuration Register 38 0011 C098h 0011 E098h
1C09Ch 1E09Ch CTRLMMR_PADCONFIG39 PAD Configuration Register 39 0011 C09Ch 0011 E09Ch
1C0A0h 1E0A0h CTRLMMR_PADCONFIG40 PAD Configuration Register 40 0011 C0A0h 0011 E0A0h
1C0A4h 1E0A4h CTRLMMR_PADCONFIG41 PAD Configuration Register 41 0011 C0A4h 0011 E0A4h
1C0A8h 1E0A8h CTRLMMR_PADCONFIG42 PAD Configuration Register 42 0011 C0A8h 0011 E0A8h
1C0ACh 1E0ACh CTRLMMR_PADCONFIG43 PAD Configuration Register 43 0011 C0ACh 0011 E0ACh
1C0B0h 1E0B0h CTRLMMR_PADCONFIG44 PAD Configuration Register 44 0011 C0B0h 0011 E0B0h
1C0B4h 1E0B4h CTRLMMR_PADCONFIG45 PAD Configuration Register 45 0011 C0B4h 0011 E0B4h
1C0B8h 1E0B8h CTRLMMR_PADCONFIG46 PAD Configuration Register 46 0011 C0B8h 0011 E0B8h
1C0BCh 1E0BCh CTRLMMR_PADCONFIG47 PAD Configuration Register 47 0011 C0BCh 0011 E0BCh
1C0C0h 1E0C0h CTRLMMR_PADCONFIG48 PAD Configuration Register 48 0011 C0C0h 0011 E0C0h
1C0C4h 1E0C4h CTRLMMR_PADCONFIG49 PAD Configuration Register 49 0011 C0C4h 0011 E0C4h
1C0C8h 1E0C8h CTRLMMR_PADCONFIG50 PAD Configuration Register 50 0011 C0C8h 0011 E0C8h
1C0CCh 1E0CCh CTRLMMR_PADCONFIG51 PAD Configuration Register 51 0011 C0CCh 0011 E0CCh
1C0D0h 1E0D0h CTRLMMR_PADCONFIG52 PAD Configuration Register 52 0011 C0D0h 0011 E0D0h
1C0D4h 1E0D4h CTRLMMR_PADCONFIG53 PAD Configuration Register 53 0011 C0D4h 0011 E0D4h
1C0D8h 1E0D8h CTRLMMR_PADCONFIG54 PAD Configuration Register 54 0011 C0D8h 0011 E0D8h
1C0DCh 1E0DCh CTRLMMR_PADCONFIG55 PAD Configuration Register 55 0011 C0DCh 0011 E0DCh
1C0E0h 1E0E0h CTRLMMR_PADCONFIG56 PAD Configuration Register 56 0011 C0E0h 0011 E0E0h
1C0E4h 1E0E4h CTRLMMR_PADCONFIG57 PAD Configuration Register 57 0011 C0E4h 0011 E0E4h
1C0E8h 1E0E8h CTRLMMR_PADCONFIG58 PAD Configuration Register 58 0011 C0E8h 0011 E0E8h
1C0ECh 1E0ECh CTRLMMR_PADCONFIG59 PAD Configuration Register 59 0011 C0ECh 0011 E0ECh
1C0F0h 1E0F0h CTRLMMR_PADCONFIG60 PAD Configuration Register 60 0011 C0F0h 0011 E0F0h
1C0F4h 1E0F4h CTRLMMR_PADCONFIG61 PAD Configuration Register 61 0011 C0F4h 0011 E0F4h
1C0F8h 1E0F8h CTRLMMR_PADCONFIG62 PAD Configuration Register 62 0011 C0F8h 0011 E0F8h
1C0FCh 1E0FCh CTRLMMR_PADCONFIG63 PAD Configuration Register 63 0011 C0FCh 0011 E0FCh
1C100h 1E100h CTRLMMR_PADCONFIG64 PAD Configuration Register 64 0011 C100h 0011 E100h
1C104h 1E104h CTRLMMR_PADCONFIG65 PAD Configuration Register 65 0011 C104h 0011 E104h
1C108h 1E108h CTRLMMR_PADCONFIG66 PAD Configuration Register 66 0011 C108h 0011 E108h
1C110h 1E110h CTRLMMR_PADCONFIG68 PAD Configuration Register 68 0011 C110h 0011 E110h
1C11Ch 1E11Ch CTRLMMR_PADCONFIG71 PAD Configuration Register 71 0011 C11Ch 0011 E11Ch
1C120h 1E120h CTRLMMR_PADCONFIG72 PAD Configuration Register 72 0011 C120h 0011 E120h
1C124h 1E124h CTRLMMR_PADCONFIG73 PAD Configuration Register 73 0011 C124h 0011 E124h
1C164h 1E164h CTRLMMR_PADCONFIG89 PAD Configuration Register 89 0011 C164h 0011 E164h
1C168h 1E168h CTRLMMR_PADCONFIG90 PAD Configuration Register 90 0011 C168h 0011 E168h
1D008h 1F008h CTRLMMR_LOCK7_KICK0 Partition 7 Lock Key 0 Register 0011 D008h 0011 F008h
1D00Ch 1F00Ch CTRLMMR_LOCK7_KICK1 Partition 7 Lock Key 1 Register 0011 D00Ch 0011 F00Ch

1.3.4.1 CTRLMMR_PID Register ( Offset = 0h) [reset = 61800000h]

CTRLMMR_PID is shown in Figure 5-335 and described in Table 5-697.

Return to Summary Table.

Peripheral release details.

Table 5-696 CTRLMMR_PID Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0000h
Figure 5-335 CTRLMMR_PID Register
3130292827262524
SCHEMEBUFUNC
R-1hR-2hR-180h
2322212019181716
FUNC
R-180h
15141312111098
R_RTLX_MAJOR
R-0hR-0h
76543210
CUSTOMY_MINOR
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-697 CTRLMMR_PID Register Field Descriptions
BitFieldTypeResetDescription
31-30SCHEMER1h

CTRLMMR_PID follows new scheme

29-28BUR2h

Business unit - Processors

27-16FUNCR180h

Module functional identifier - CTRL MMR

15-11R_RTLR0h

RTL revision number

10-8X_MAJORR0h

Major revision number

7-6CUSTOMR0h

Custom revision number

5-0Y_MINORR0h

Minor revision number

1.3.4.2 CTRLMMR_MMR_CFG1 Register ( Offset = 8h) [reset = 800000BFh]

CTRLMMR_MMR_CFG1 is shown in Figure 5-336 and described in Table 5-699.

Return to Summary Table.

Indicates the MMR configuration.

Table 5-698 CTRLMMR_MMR_CFG1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0008h
Figure 5-336 CTRLMMR_MMR_CFG1 Register
3130292827262524
RESERVEDRESERVED
R-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
PARTITIONS
R-BFh
LEGEND: R = Read Only; -n = value after reset
Table 5-699 CTRLMMR_MMR_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR1h

Reserved

30-8RESERVEDR0h

Reserved

7-0PARTITIONSRBFh

Indicates present partitions

1.3.4.3 CTRLMMR_MAIN_DEVSTAT Register ( Offset = 30h) [reset = X]

CTRLMMR_MAIN_DEVSTAT is shown in Figure 5-337 and described in Table 5-701.

Return to Summary Table.

Indicates SoC bootstrap selection. The default value of this register is determined by the SoC bootstrap pins.

Table 5-700 CTRLMMR_MAIN_DEVSTAT Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0030h
Figure 5-337 CTRLMMR_MAIN_DEVSTAT Register
313029282726252423222120191817161514131211109876543210
RESERVEDBOOTMODE
R-0hR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-701 CTRLMMR_MAIN_DEVSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved

7-0BOOTMODER/WX

Specifies the device Primary and Backup boot media.

1.3.4.4 CTRLMMR_MAIN_BOOTCFG Register ( Offset = 34h) [reset = X]

CTRLMMR_MAIN_BOOTCFG is shown in Figure 5-338 and described in Table 5-703.

Return to Summary Table.

Indicates SoC bootstrap selection latched at power-on reset. The default value of this register is determined by the SoC bootstrap pins.

Table 5-702 CTRLMMR_MAIN_BOOTCFG Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0034h
Figure 5-338 CTRLMMR_MAIN_BOOTCFG Register
313029282726252423222120191817161514131211109876543210
RESERVEDBOOTMODE
R-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-703 CTRLMMR_MAIN_BOOTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved

7-0BOOTMODERX

Specifies the device Primary and Backup boot media as latched at PORz

1.3.4.5 CTRLMMR_MAIN_FEATURE_STAT1 Register ( Offset = 44h) [reset = X]

CTRLMMR_MAIN_FEATURE_STAT1 is shown in Figure 5-339 and described in Table 5-705.

Return to Summary Table.

Indicates enable status of MAIN domain IP features.

Table 5-704 CTRLMMR_MAIN_FEATURE_STAT1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0044h
Figure 5-339 CTRLMMR_MAIN_FEATURE_STAT1 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMCAN_FD_EN
R-0hR-X
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-705 CTRLMMR_MAIN_FEATURE_STAT1 Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MCAN_FD_ENRX

FD mode is supported on MAIN MCAN interfaces when set

15-0RESERVEDR0h

Reserved

1.3.4.6 CTRLMMR_IPC_SET8 Register ( Offset = 120h) [reset = 0h]

CTRLMMR_IPC_SET8 is shown in Figure 5-340 and described in Table 5-707.

Return to Summary Table.

Generate interprocessor communication interrupt to ARM MPU core0.

Table 5-706 CTRLMMR_IPC_SET8 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0120h
Figure 5-340 CTRLMMR_IPC_SET8 Register
3130292827262524
IPC_SRC_SET
W1TS-0h
2322212019181716
IPC_SRC_SET
W1TS-0h
15141312111098
IPC_SRC_SET
W1TS-0h
76543210
IPC_SRC_SETRESERVEDIPC_SET
W1TS-0hR-0hW1TS-0h
LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset
Table 5-707 CTRLMMR_IPC_SET8 Register Field Descriptions
BitFieldTypeResetDescription
31-4IPC_SRC_SETW1TS0h

Read returns current value
Write:
0h - No effect
1h - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR
register

3-1RESERVEDR0h

Reserved

0IPC_SETW1TS0h

Read returns 0
Write:
0h - No effect
1h - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register

1.3.4.7 CTRLMMR_IPC_SET9 Register ( Offset = 124h) [reset = 0h]

CTRLMMR_IPC_SET9 is shown in Figure 5-341 and described in Table 5-709.

Return to Summary Table.

Generate interprocessor communication interrupt to ARM MPU core1.

Table 5-708 CTRLMMR_IPC_SET9 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0124h
Figure 5-341 CTRLMMR_IPC_SET9 Register
3130292827262524
IPC_SRC_SET
W1TS-0h
2322212019181716
IPC_SRC_SET
W1TS-0h
15141312111098
IPC_SRC_SET
W1TS-0h
76543210
IPC_SRC_SETRESERVEDIPC_SET
W1TS-0hR-0hW1TS-0h
LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset
Table 5-709 CTRLMMR_IPC_SET9 Register Field Descriptions
BitFieldTypeResetDescription
31-4IPC_SRC_SETW1TS0h

Read returns current value
Write:
0h - No effect
1h - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR
register

3-1RESERVEDR0h

Reserved

0IPC_SETW1TS0h

Read returns 0
Write:
0h - No effect
1h - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register

1.3.4.8 CTRLMMR_IPC_SET16 Register ( Offset = 140h) [reset = 0h]

CTRLMMR_IPC_SET16 is shown in Figure 5-342 and described in Table 5-711.

Return to Summary Table.

Generate interprocessor communication interrupt to MAIN R5 core0.

Table 5-710 CTRLMMR_IPC_SET16 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0140h
Figure 5-342 CTRLMMR_IPC_SET16 Register
3130292827262524
IPC_SRC_SET
W1TS-0h
2322212019181716
IPC_SRC_SET
W1TS-0h
15141312111098
IPC_SRC_SET
W1TS-0h
76543210
IPC_SRC_SETRESERVEDIPC_SET
W1TS-0hR-0hW1TS-0h
LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset
Table 5-711 CTRLMMR_IPC_SET16 Register Field Descriptions
BitFieldTypeResetDescription
31-4IPC_SRC_SETW1TS0h

Read returns current value
Write:
0h - No effect
1h - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR
register

3-1RESERVEDR0h

Reserved

0IPC_SETW1TS0h

Read returns 0
Write:
0h - No effect
1h - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register

1.3.4.9 CTRLMMR_IPC_SET17 Register ( Offset = 144h) [reset = 0h]

CTRLMMR_IPC_SET17 is shown in Figure 5-343 and described in Table 5-713.

Return to Summary Table.

Generate interprocessor communication interrupt to MAIN R5 core1.

Table 5-712 CTRLMMR_IPC_SET17 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0144h
Figure 5-343 CTRLMMR_IPC_SET17 Register
3130292827262524
IPC_SRC_SET
W1TS-0h
2322212019181716
IPC_SRC_SET
W1TS-0h
15141312111098
IPC_SRC_SET
W1TS-0h
76543210
IPC_SRC_SETRESERVEDIPC_SET
W1TS-0hR-0hW1TS-0h
LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset
Table 5-713 CTRLMMR_IPC_SET17 Register Field Descriptions
BitFieldTypeResetDescription
31-4IPC_SRC_SETW1TS0h

Read returns current value
Write:
0h - No effect
1h - Sets both SRC_SETx and the SRC_CLRx bit in the corresponding IPC_CLR
register

3-1RESERVEDR0h

Reserved

0IPC_SETW1TS0h

Read returns 0
Write:
0h - No effect
1h - Sets both the IPC_SET and the IPC_CLR bit in the corresponding IPC_CLR register

1.3.4.10 CTRLMMR_IPC_CLR8 Register ( Offset = 1A0h) [reset = 0h]

CTRLMMR_IPC_CLR8 is shown in Figure 5-344 and described in Table 5-715.

Return to Summary Table.

Acknowledge interprocessor communication interrupt to ARM MPU core0.

Table 5-714 CTRLMMR_IPC_CLR8 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 01A0h
Figure 5-344 CTRLMMR_IPC_CLR8 Register
3130292827262524
IPC_SRC_CLR
W1TC-0h
2322212019181716
IPC_SRC_CLR
W1TC-0h
15141312111098
IPC_SRC_CLR
W1TC-0h
76543210
IPC_SRC_CLRRESERVEDIPC_CLR
W1TC-0hR-0hW1TC-0h
LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset
Table 5-715 CTRLMMR_IPC_CLR8 Register Field Descriptions
BitFieldTypeResetDescription
31-4IPC_SRC_CLRW1TC0h

Read returns current value
Write:
0h - No effect
1h - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register

3-1RESERVEDR0h

Reserved

0IPC_CLRW1TC0h

Read returns current value
Write:
0h - No effect
1h - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register

1.3.4.11 CTRLMMR_IPC_CLR9 Register ( Offset = 1A4h) [reset = 0h]

CTRLMMR_IPC_CLR9 is shown in Figure 5-345 and described in Table 5-717.

Return to Summary Table.

Acknowledge interprocessor communication interrupt to ARM MPU core1.

Table 5-716 CTRLMMR_IPC_CLR9 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 01A4h
Figure 5-345 CTRLMMR_IPC_CLR9 Register
3130292827262524
IPC_SRC_CLR
W1TC-0h
2322212019181716
IPC_SRC_CLR
W1TC-0h
15141312111098
IPC_SRC_CLR
W1TC-0h
76543210
IPC_SRC_CLRRESERVEDIPC_CLR
W1TC-0hR-0hW1TC-0h
LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset
Table 5-717 CTRLMMR_IPC_CLR9 Register Field Descriptions
BitFieldTypeResetDescription
31-4IPC_SRC_CLRW1TC0h

Read returns current value
Write:
0h - No effect
1h - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register

3-1RESERVEDR0h

Reserved

0IPC_CLRW1TC0h

Read returns current value
Write:
0h - No effect
1h - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register

1.3.4.12 CTRLMMR_IPC_CLR16 Register ( Offset = 1C0h) [reset = 0h]

CTRLMMR_IPC_CLR16 is shown in Figure 5-346 and described in Table 5-719.

Return to Summary Table.

Acknowledge interprocessor communication interrupt to MAIN R5 core0.

Table 5-718 CTRLMMR_IPC_CLR16 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 01C0h
Figure 5-346 CTRLMMR_IPC_CLR16 Register
3130292827262524
IPC_SRC_CLR
W1TC-0h
2322212019181716
IPC_SRC_CLR
W1TC-0h
15141312111098
IPC_SRC_CLR
W1TC-0h
76543210
IPC_SRC_CLRRESERVEDIPC_CLR
W1TC-0hR-0hW1TC-0h
LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset
Table 5-719 CTRLMMR_IPC_CLR16 Register Field Descriptions
BitFieldTypeResetDescription
31-4IPC_SRC_CLRW1TC0h

Read returns current value
Write:
0h - No effect
1h - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register

3-1RESERVEDR0h

Reserved

0IPC_CLRW1TC0h

Read returns current value
Write:
0h - No effect
1h - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register

1.3.4.13 CTRLMMR_IPC_CLR17 Register ( Offset = 1C4h) [reset = 0h]

CTRLMMR_IPC_CLR17 is shown in Figure 5-347 and described in Table 5-721.

Return to Summary Table.

Acknowledge interprocessor communication interrupt to MAIN R5 core1.

Table 5-720 CTRLMMR_IPC_CLR17 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 01C4h
Figure 5-347 CTRLMMR_IPC_CLR17 Register
3130292827262524
IPC_SRC_CLR
W1TC-0h
2322212019181716
IPC_SRC_CLR
W1TC-0h
15141312111098
IPC_SRC_CLR
W1TC-0h
76543210
IPC_SRC_CLRRESERVEDIPC_CLR
W1TC-0hR-0hW1TC-0h
LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset
Table 5-721 CTRLMMR_IPC_CLR17 Register Field Descriptions
BitFieldTypeResetDescription
31-4IPC_SRC_CLRW1TC0h

Read returns current value
Write:
0h - No effect
1h - Clears both SRC_CLRx and the SRC_SETx bit in the corresponding IPC_GEN register

3-1RESERVEDR0h

Reserved

0IPC_CLRW1TC0h

Read returns current value
Write:
0h - No effect
1h - Clears both IPC_CLR and the IPC_SET bit in the corresponding IPC_SET register

1.3.4.14 CTRLMMR_PCI_DEVICE_ID Register ( Offset = 210h) [reset = B00F104Ch]

CTRLMMR_PCI_DEVICE_ID is shown in Figure 5-348 and described in Table 5-723.

Return to Summary Table.

PCIe device ID and vendor ID register.

Table 5-722 CTRLMMR_PCI_DEVICE_ID Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0210h
Figure 5-348 CTRLMMR_PCI_DEVICE_ID Register
313029282726252423222120191817161514131211109876543210
DEVICE_IDVENDOR_ID
WOT-B00FhWOT-104Ch
LEGEND: WOT = Write one time only (subsequent writes are ignored)-n = value after reset
Table 5-723 CTRLMMR_PCI_DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
31-16DEVICE_IDWOTB00Fh

Product ID

15-0VENDOR_IDWOT104Ch

TI Vendor ID

1.3.4.15 CTRLMMR_USB_DEVICE_ID Register ( Offset = 220h) [reset = 61640451h]

CTRLMMR_USB_DEVICE_ID is shown in Figure 5-349 and described in Table 5-725.

Return to Summary Table.

USB device and vendor ID register.

Table 5-724 CTRLMMR_USB_DEVICE_ID Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 0220h
Figure 5-349 CTRLMMR_USB_DEVICE_ID Register
313029282726252423222120191817161514131211109876543210
DEVICE_IDVENDOR_ID
WOT-6164hWOT-451h
LEGEND: WOT = Write one time only (subsequent writes are ignored)-n = value after reset
Table 5-725 CTRLMMR_USB_DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
31-16DEVICE_IDWOT6164h

Product ID

15-0VENDOR_IDWOT451h

TI Vendor ID

1.3.4.16 CTRLMMR_LOCK0_KICK0 Register ( Offset = 1008h) [reset = 0h]

CTRLMMR_LOCK0_KICK0 is shown in Figure 5-350 and described in Table 5-727.

Return to Summary Table.

Lower 32-bits of Partition0 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK0_KICK1 with its key value before write-protected Partition 0 registers can be written.

Table 5-726 CTRLMMR_LOCK0_KICK0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 1008h
Figure 5-350 CTRLMMR_LOCK0_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-727 CTRLMMR_LOCK0_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition0 registers

0UNLOCKEDR0h

Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.3.4.17 CTRLMMR_LOCK0_KICK1 Register ( Offset = 100Ch) [reset = 0h]

CTRLMMR_LOCK0_KICK1 is shown in Figure 5-351 and described in Table 5-729.

Return to Summary Table.

Upper 32-bits of Partition 0 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK0_KICK0 with its key value before write-protected Partition 0 registers can be written.

Table 5-728 CTRLMMR_LOCK0_KICK1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 100Ch
Figure 5-351 CTRLMMR_LOCK0_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-729 CTRLMMR_LOCK0_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition0 registers

1.3.4.18 CTRLMMR_INTR_RAW_STAT Register ( Offset = 1010h) [reset = 0h]

CTRLMMR_INTR_RAW_STAT is shown in Figure 5-352 and described in Table 5-731.

Return to Summary Table.

Shows the interrupt status (before enabling) and allows setting of the interrupt status (for test).

Table 5-730 CTRLMMR_INTR_RAW_STAT Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 1010h
Figure 5-352 CTRLMMR_INTR_RAW_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDLOCK_ERRADDR_ERRPROT_ERR
R-0hW1TS-0hW1TS-0hW1TS-0hW1TS-0h
LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset
Table 5-731 CTRLMMR_INTR_RAW_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3RESERVEDW1TS0h

Reserved

2LOCK_ERRW1TS0h

Lock violation occurred (attempt to write a write-locked register with partition locked)
Write 1 to set the status bit (for test)
Writing 0 has no effect.

1ADDR_ERRW1TS0h

Address violation occurred (attempt to read or write an invalid register address)
Write 1 to set the status bit (for test)
Writing 0 has no effect.

0PROT_ERRW1TS0h

Protection violation occurred (attempt to read or write a register with insufficient security or privilege access rights)
Write 1 to set the status bit (for test)
Writing 0 has no effect.

1.3.4.19 CTRLMMR_INTR_STAT_CLR Register ( Offset = 1014h) [reset = 0h]

CTRLMMR_INTR_STAT_CLR is shown in Figure 5-353 and described in Table 5-733.

Return to Summary Table.

Shows the enabled interrupt status and allows the interrupt to be cleared.

Table 5-732 CTRLMMR_INTR_STAT_CLR Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 1014h
Figure 5-353 CTRLMMR_INTR_STAT_CLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDEN_LOCK_ERREN_ADDR_ERREN_PROT_ERR
R-0hW1TC-0hW1TC-0hW1TC-0hW1TC-0h
LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset
Table 5-733 CTRLMMR_INTR_STAT_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3RESERVEDW1TC0h

Reserved

2EN_LOCK_ERRW1TC0h

Enabled lock interrupt event status
Write 1 to clear the interrupt event
Writing 0 has no effect.

1EN_ADDR_ERRW1TC0h

Enabled address interrupt event status
Write 1 to clear the interrupt event
Writing 0 has no effect.

0EN_PROT_ERRW1TC0h

Enabled protection interrupt event status
Write 1 to clear the interrupt event
Writing 0 has no effect.

1.3.4.20 CTRLMMR_INTR_EN_SET Register ( Offset = 1018h) [reset = 0h]

CTRLMMR_INTR_EN_SET is shown in Figure 5-354 and described in Table 5-735.

Return to Summary Table.

Allows interrupt enables to be set.

Table 5-734 CTRLMMR_INTR_EN_SET Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 1018h
Figure 5-354 CTRLMMR_INTR_EN_SET Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDLOCK_ERR_EN_SETADDR_ERR_EN_SETPROT_ERR_EN_SET
R-0hW1TS-0hW1TS-0hW1TS-0hW1TS-0h
LEGEND: R = Read Only; W1TS = Write 1 to Set Bit; -n = value after reset
Table 5-735 CTRLMMR_INTR_EN_SET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3RESERVEDW1TS0h

Reserved

2LOCK_ERR_EN_SETW1TS0h

Lock interrupt enable
Write 1 to enable lock interrupt events
Writing 0 has no effect.

1ADDR_ERR_EN_SETW1TS0h

Address interrupt enable
Write 1 to enable address interrupt events
Writing 0 has no effect.

0PROT_ERR_EN_SETW1TS0h

Protection interrupt enable
Write 1 to enable protection interrupt events
Writing 0 has no effect.

1.3.4.21 CTRLMMR_INTR_EN_CLR Register ( Offset = 101Ch) [reset = 0h]

CTRLMMR_INTR_EN_CLR is shown in Figure 5-355 and described in Table 5-737.

Return to Summary Table.

Allows interrupt enables to be cleared.

Table 5-736 CTRLMMR_INTR_EN_CLR Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 101Ch
Figure 5-355 CTRLMMR_INTR_EN_CLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDLOCK_ERR_EN_CLRADDR_ERR_EN_CLRPROT_ERR_EN_CLR
R-0hW1TC-0hW1TC-0hW1TC-0hW1TC-0h
LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset
Table 5-737 CTRLMMR_INTR_EN_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3RESERVEDW1TC0h

Reserved

2LOCK_ERR_EN_CLRW1TC0h

Lock interrupt disable
Write 1 to disable lock interrupt events
Writing 0 has no effect.

1ADDR_ERR_EN_CLRW1TC0h

Address interrupt disable
Write 1 to disable address interrupt events
Writing 0 has no effect.

0PROT_ERR_EN_CLRW1TC0h

Protection interrupt disable
Write 1 to disable protection interrupt events
Writing 0 has no effect.

1.3.4.22 CTRLMMR_EOI Register ( Offset = 1020h) [reset = 0h]

CTRLMMR_EOI is shown in Figure 5-356 and described in Table 5-739.

Return to Summary Table.

CTRLMMR_EOI Vector value This register should be written with interrupt distribution value required by the device architecture to indicate service completion of the MMR interrupt.

Table 5-738 CTRLMMR_EOI Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 1020h
Figure 5-356 CTRLMMR_EOI Register
313029282726252423222120191817161514131211109876543210
RESERVEDVECTOR
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-739 CTRLMMR_EOI Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved

7-0VECTORR/W0h

CTRLMMR_EOI vector value

1.3.4.23 CTRLMMR_FAULT_ADDR Register ( Offset = 1024h) [reset = 0h]

CTRLMMR_FAULT_ADDR is shown in Figure 5-357 and described in Table 5-741.

Return to Summary Table.

Indicates the address of the first transfer that caused a fault to occur.

Table 5-740 CTRLMMR_FAULT_ADDR Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 1024h
Figure 5-357 CTRLMMR_FAULT_ADDR Register
313029282726252423222120191817161514131211109876543210
ADDRESS
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-741 CTRLMMR_FAULT_ADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR0h

Address of the faulted access

1.3.4.24 CTRLMMR_FAULT_TYPE Register ( Offset = 1028h) [reset = 0h]

CTRLMMR_FAULT_TYPE is shown in Figure 5-358 and described in Table 5-743.

Return to Summary Table.

Indicates the access type of the first transfer that caused a fault to occur.

Table 5-742 CTRLMMR_FAULT_TYPE Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 1028h
Figure 5-358 CTRLMMR_FAULT_TYPE Register
313029282726252423222120191817161514131211109876543210
RESERVEDTYPE
R-0hR-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-743 CTRLMMR_FAULT_TYPE Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h

Reserved

5-0TYPER0h

Type of access which faulted

0h - No fault

1h - User execute access

2h - User write access

4h - User read access

8h - Supervisor execute access

10h - Supervisor write access

20h - Supervisor read access

1.3.4.25 CTRLMMR_FAULT_ATTR Register ( Offset = 102Ch) [reset = 0h]

CTRLMMR_FAULT_ATTR is shown in Figure 5-359 and described in Table 5-745.

Return to Summary Table.

Indicates the attributes of the first transfer that caused a fault to occur.

Table 5-744 CTRLMMR_FAULT_ATTR Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 102Ch
Figure 5-359 CTRLMMR_FAULT_ATTR Register
3130292827262524
XID
R-0h
2322212019181716
XIDROUTEID
R-0hR-0h
15141312111098
ROUTEID
R-0h
76543210
PRIVID
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-745 CTRLMMR_FAULT_ATTR Register Field Descriptions
BitFieldTypeResetDescription
31-20XIDR0h

Transaction ID

19-8ROUTEIDR0h

Route ID

7-0PRIVIDR0h

Privilege ID

1.3.4.26 CTRLMMR_FAULT_CLR Register ( Offset = 1030h) [reset = 0h]

CTRLMMR_FAULT_CLR is shown in Figure 5-360 and described in Table 5-747.

Return to Summary Table.

Allows software to clear the current fault Clearing the current fault allows the CTRLMMR_FAULT_ADDR, CTRLMMR_FAULT_TYPE, and CTRLMMR_FAULT_ATTR registers to latch the attributes of the next fault that occurs. This does not affect the fault interrupt event itself. The interrupt must be cleared using the appropriate INTR_STATUS_CLR register bits.

Table 5-746 CTRLMMR_FAULT_CLR Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 1030h
Figure 5-360 CTRLMMR_FAULT_CLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLEAR
R-0hW1TC-0h
LEGEND: R = Read Only; W1TC = Write 1 to Clear Bit; -n = value after reset
Table 5-747 CTRLMMR_FAULT_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0CLEARW1TC0h

Fault clear
Write 1 to clear the current fault
Writing 0 has no effect

1.3.4.27 CTRLMMR_USB0_CTRL Register ( Offset = 4000h) [reset = 0h]

CTRLMMR_USB0_CTRL is shown in Figure 5-361 and described in Table 5-749.

Return to Summary Table.

Controls USB0 operation.

Table 5-748 CTRLMMR_USB0_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4000h
Figure 5-361 CTRLMMR_USB0_CTRL Register
3130292827262524
RESERVEDSERDES_SELRESERVED
R-0hR/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-749 CTRLMMR_USB0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0h

Reserved

27SERDES_SELR/W0h

Serdes Selection.
The USB3 0 interface can be mapped to 2 different SERDES0 lanes. This bit selects which SERDES lane drives the USB3 PIPE interface input clock, data and control signals. Programming should align with the CTRLMMR_SERDES0_LN1_CTRL and SERDES3_LN0_CTRL lane_func_sel programming.
0h - SERDES0 Ln1 drives USB3.1 inputs
1h - SERDES0 Ln3 drives USB3.1 inputs

26-0RESERVEDR0h

Reserved

1.3.4.28 CTRLMMR_USB0_PHY_CTRL Register ( Offset = 4008h) [reset = 80000000h]

CTRLMMR_USB0_PHY_CTRL is shown in Figure 5-362 and described in Table 5-751.

Return to Summary Table.

Configures the USB0 Phy operation.

Table 5-750 CTRLMMR_USB0_PHY_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4008h
Figure 5-362 CTRLMMR_USB0_PHY_CTRL Register
3130292827262524
CORE_VOLTAGERESERVED
R/W-1hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-751 CTRLMMR_USB0_PHY_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31CORE_VOLTAGER/W1h

Selects the USB PHY core voltage
0h - Core voltage is 0.85 V
1h - Core voltage is 0.80 V

30-0RESERVEDR0h

Reserved

1.3.4.29 CTRLMMR_ENET1_CTRL Register ( Offset = 4044h) [reset = 2h]

CTRLMMR_ENET1_CTRL is shown in Figure 5-363 and described in Table 5-753.

Return to Summary Table.

Controls Ethernet Port1 operation.

Table 5-752 CTRLMMR_ENET1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4044h
Figure 5-363 CTRLMMR_ENET1_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRGMII_ID_MODERESERVEDPORT_MODE_SEL
R-0hR/W-0hR-0hR/W-2h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-753 CTRLMMR_ENET1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4RGMII_ID_MODER/W0h

Port1 RGMII internal transmit delay selection
0h - Internal transmit delay
1h - Reserved

3RESERVEDR0h

Reserved

2-0PORT_MODE_SELR/W2h

Selects Ethernet switch Port1 interface

0h - GMII/MII (not supported)

1h - RMII

2h - RGMII

3h - SGMII

4h - QSGMII

5h - XFI (not supported)

6h - QSGMII_SUB

7h - Reserved

1.3.4.30 CTRLMMR_ENET2_CTRL Register ( Offset = 4048h) [reset = 2h]

CTRLMMR_ENET2_CTRL is shown in Figure 5-364 and described in Table 5-755.

Return to Summary Table.

Controls Ethernet Port2 operation.

Table 5-754 CTRLMMR_ENET2_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4048h
Figure 5-364 CTRLMMR_ENET2_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRGMII_ID_MODERESERVEDPORT_MODE_SEL
R-0hR/W-0hR-0hR/W-2h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-755 CTRLMMR_ENET2_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4RGMII_ID_MODER/W0h

Port2 RGMII internal transmit delay selection
0h - Internal transmit delay
1h - Reserved

3RESERVEDR0h

Reserved

2-0PORT_MODE_SELR/W2h

Selects Ethernet switch Port2 interface

0h - GMII/MII (not supported)

1h - RMII

2h - RGMII

3h - SGMII

4h - QSGMII

5h - XFI (not supported)

6h - QSGMII_SUB

7h - Reserved

1.3.4.31 CTRLMMR_ENET3_CTRL Register ( Offset = 404Ch) [reset = 2h]

CTRLMMR_ENET3_CTRL is shown in Figure 5-365 and described in Table 5-757.

Return to Summary Table.

Controls Ethernet Port3 operation.

Table 5-756 CTRLMMR_ENET3_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 404Ch
Figure 5-365 CTRLMMR_ENET3_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRGMII_ID_MODERESERVEDPORT_MODE_SEL
R-0hR/W-0hR-0hR/W-2h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-757 CTRLMMR_ENET3_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4RGMII_ID_MODER/W0h

Port3 RGMII internal transmit delay selection
0h - Internal transmit delay
1h - Reserved

3RESERVEDR0h

Reserved

2-0PORT_MODE_SELR/W2h

Selects Ethernet switch Port3 interface

0h - GMII/MII (not supported)

1h - RMII

2h - RGMII

3h - SGMII

4h - QSGMII

5h - XFI (not supported)

6h - QSGMII_SUB

7h - Reserved

1.3.4.32 CTRLMMR_ENET4_CTRL Register ( Offset = 4050h) [reset = 2h]

CTRLMMR_ENET4_CTRL is shown in Figure 5-366 and described in Table 5-759.

Return to Summary Table.

Controls Ethernet Port4 operation.

Table 5-758 CTRLMMR_ENET4_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4050h
Figure 5-366 CTRLMMR_ENET4_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRGMII_ID_MODERESERVEDPORT_MODE_SEL
R-0hR/W-0hR-0hR/W-2h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-759 CTRLMMR_ENET4_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4RGMII_ID_MODER/W0h

Port4 RGMII internal transmit delay selection
0h - Internal transmit delay
1h - Reserved

3RESERVEDR0h

Reserved

2-0PORT_MODE_SELR/W2h

Selects Ethernet switch Port4 interface

0h - GMII/MII (not supported)

1h - RMII

2h - RGMII

3h - SGMII

4h - QSGMII

5h - XFI (not supported)

6h - QSGMII_SUB

7h - Reserved

1.3.4.33 CTRLMMR_PCIE1_CTRL Register ( Offset = 4074h) [reset = 2h]

CTRLMMR_PCIE1_CTRL is shown in Figure 5-367 and described in Table 5-761.

Return to Summary Table.

Controls PCIe1 operation.

Table 5-760 CTRLMMR_PCIE1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4074h
Figure 5-367 CTRLMMR_PCIE1_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDLANE_COUNT
R-0hR/W-0h
76543210
MODE_SELRESERVEDGENERATION_SEL
R/W-0hR-0hR/W-2h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-761 CTRLMMR_PCIE1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h

Reserved

9-8LANE_COUNTR/W0h

Configures the PCIe lane count
0h - Select 1-lane operation
1h - Select 2-lane operation
1x - Select 4-lane operation

7MODE_SELR/W0h

Selects the operating mode
0h - Endpoint
1h - Root Complex

6-2RESERVEDR0h

Reserved

1-0GENERATION_SELR/W2h

Configures the PCIe generation support in the PCIe capabilities linked-list

1h - Gen2 - Controller advertises Gen1 & Gen2 capability and link operates at either speed

2h - Gen3 - Controller advertises Gen1, Gen2, & Gen3 capability and link operates at any of the three speeds

3h - Reserved

1.3.4.34 CTRLMMR_SERDES0_LN0_CTRL Register ( Offset = 4080h) [reset = 0h]

CTRLMMR_SERDES0_LN0_CTRL is shown in Figure 5-368 and described in Table 5-763.

Return to Summary Table.

Controls 10G SERDES0 lane0 selection.

Table 5-762 CTRLMMR_SERDES0_LN0_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4080h
Figure 5-368 CTRLMMR_SERDES0_LN0_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLANE_FUNC_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-763 CTRLMMR_SERDES0_LN0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0LANE_FUNC_SELR/W0h

Selects the SERDES0 lane0 function

0h - IP1 - Enet Switch Q/SGMII Lane 3

1h - IP2 - PCIe1 Lane0

2h - IP3 - Not used

3h - IP4 - Not used

1.3.4.35 CTRLMMR_SERDES0_LN1_CTRL Register ( Offset = 4084h) [reset = 0h]

CTRLMMR_SERDES0_LN1_CTRL is shown in Figure 5-369 and described in Table 5-765.

Return to Summary Table.

Controls 10G SERDES0 lane1 selection.

Table 5-764 CTRLMMR_SERDES0_LN1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4084h
Figure 5-369 CTRLMMR_SERDES0_LN1_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLANE_FUNC_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-765 CTRLMMR_SERDES0_LN1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0LANE_FUNC_SELR/W0h

Selects the SERDES0 lane1 function

0h - IP1 - Enet Switch Q/SGMII Lane 4

1h - IP2 - PCIe1 Lane1

2h - IP3 - USB3

3h - IP4 - Not Used

1.3.4.36 CTRLMMR_SERDES0_LN2_CTRL Register ( Offset = 4088h) [reset = 0h]

CTRLMMR_SERDES0_LN2_CTRL is shown in Figure 5-370 and described in Table 5-767.

Return to Summary Table.

Controls 10G SERDES0 lane2 selection.

Table 5-766 CTRLMMR_SERDES0_LN2_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4088h
Figure 5-370 CTRLMMR_SERDES0_LN2_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLANE_FUNC_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-767 CTRLMMR_SERDES0_LN2_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0LANE_FUNC_SELR/W0h

Selects the SERDES0 lane2 function

0h - IP1 - Enet Switch Q/SGMII Lane 1

1h - IP2 - PCIe1 Lane2

2h - IP3 - Not Used

3h - IP4 - Not Used

1.3.4.37 CTRLMMR_SERDES0_LN3_CTRL Register ( Offset = 408Ch) [reset = 0h]

CTRLMMR_SERDES0_LN3_CTRL is shown in Figure 5-371 and described in Table 5-769.

Return to Summary Table.

Controls 10G SERDES0 lane3 selection.

Table 5-768 CTRLMMR_SERDES0_LN3_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 408Ch
Figure 5-371 CTRLMMR_SERDES0_LN3_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLANE_FUNC_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-769 CTRLMMR_SERDES0_LN3_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0LANE_FUNC_SELR/W0h

Selects the SERDES0 lane3 function

0h - IP1 - Enet Switch Q/SGMII Lane 2

1h - IP2 - PCIe1 Lane3

2h - IP3 - USB3

3h - IP4 - Not Used

1.3.4.38 CTRLMMR_SERDES0_CTRL Register ( Offset = 40E0h) [reset = 0h]

CTRLMMR_SERDES0_CTRL is shown in Figure 5-372 and described in Table 5-771.

Return to Summary Table.

Controls SERDES0 operation.

Table 5-770 CTRLMMR_SERDES0_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 40E0h
Figure 5-372 CTRLMMR_SERDES0_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRET_EN
R-0hR/W-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-771 CTRLMMR_SERDES0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8RET_ENR/W0h

Retention enable

7-0RESERVEDR0h

Reserved

1.3.4.39 CTRLMMR_EPWM0_CTRL Register ( Offset = 4140h) [reset = 0h]

CTRLMMR_EPWM0_CTRL is shown in Figure 5-373 and described in Table 5-773.

Return to Summary Table.

Controls eHRPWM0 Operation.

Table 5-772 CTRLMMR_EPWM0_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4140h
Figure 5-373 CTRLMMR_EPWM0_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEALLOWRESERVEDTB_CLKEN
R-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-773 CTRLMMR_EPWM0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4EALLOWR/W0h

Enable write access to ePWM tripzone and HRPWM config registers
0h - Disabled
1h - Enabled

3-1RESERVEDR0h

Reserved

0TB_CLKENR/W0h

Enable eHRPWM timebase clock
0h - Disabled
1h - Enabled

1.3.4.40 CTRLMMR_EPWM1_CTRL Register ( Offset = 4144h) [reset = 0h]

CTRLMMR_EPWM1_CTRL is shown in Figure 5-374 and described in Table 5-775.

Return to Summary Table.

Controls eHRPWM1 Operation.

Table 5-774 CTRLMMR_EPWM1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4144h
Figure 5-374 CTRLMMR_EPWM1_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEALLOWRESERVEDTB_CLKEN
R-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-775 CTRLMMR_EPWM1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4EALLOWR/W0h

Enable write access to ePWM tripzone and HRPWM config registers
0h - Disabled
1h - Enabled

3-1RESERVEDR0h

Reserved

0TB_CLKENR/W0h

Enable eHRPWM timebase clock
0h - Disabled
1h - Enabled

1.3.4.41 CTRLMMR_EPWM2_CTRL Register ( Offset = 4148h) [reset = 0h]

CTRLMMR_EPWM2_CTRL is shown in Figure 5-375 and described in Table 5-777.

Return to Summary Table.

Controls eHRPWM2 Operation.

Table 5-776 CTRLMMR_EPWM2_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4148h
Figure 5-375 CTRLMMR_EPWM2_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEALLOWRESERVEDTB_CLKEN
R-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-777 CTRLMMR_EPWM2_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4EALLOWR/W0h

Enable write access to ePWM tripzone and HRPWM config registers
0h - Disabled
1h - Enabled

3-1RESERVEDR0h

Reserved

0TB_CLKENR/W0h

Enable eHRPWM timebase clock
0h - Disabled
1h - Enabled

1.3.4.42 CTRLMMR_EPWM3_CTRL Register ( Offset = 414Ch) [reset = 0h]

CTRLMMR_EPWM3_CTRL is shown in Figure 5-376 and described in Table 5-779.

Return to Summary Table.

Controls eHRPWM3 Operation.

Table 5-778 CTRLMMR_EPWM3_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 414Ch
Figure 5-376 CTRLMMR_EPWM3_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDSYNCIN_SEL
R-0hR/W-0h
76543210
RESERVEDEALLOWRESERVEDTB_CLKEN
R-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-779 CTRLMMR_EPWM3_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR0h

Reserved

10-8SYNCIN_SELR/W0h

Selects the source of the PWM3 synchronization input

0h - PWM3_SYNCIN Pin

1h - PWM2 syncout signal, daisy chained

2h - None

3h - None

4h - None

5h - None

6h - None

7h - None

7-5RESERVEDR0h

Reserved

4EALLOWR/W0h

Enable write access to ePWM tripzone and HRPWM config registers
0h - Disabled
1h - Enabled

3-1RESERVEDR0h

Reserved

0TB_CLKENR/W0h

Enable eHRPWM timebase clock
0h - Disabled
1h - Enabled

1.3.4.43 CTRLMMR_EPWM4_CTRL Register ( Offset = 4150h) [reset = 0h]

CTRLMMR_EPWM4_CTRL is shown in Figure 5-377 and described in Table 5-781.

Return to Summary Table.

Controls eHRPWM4 Operation.

Table 5-780 CTRLMMR_EPWM4_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4150h
Figure 5-377 CTRLMMR_EPWM4_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEALLOWRESERVEDTB_CLKEN
R-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-781 CTRLMMR_EPWM4_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4EALLOWR/W0h

Enable write access to ePWM tripzone and HRPWM config registers
0h - Disabled
1h - Enabled

3-1RESERVEDR0h

Reserved

0TB_CLKENR/W0h

Enable eHRPWM timebase clock
0h - Disabled
1h - Enabled

1.3.4.44 CTRLMMR_EPWM5_CTRL Register ( Offset = 4154h) [reset = 0h]

CTRLMMR_EPWM5_CTRL is shown in Figure 5-378 and described in Table 5-783.

Return to Summary Table.

Controls eHRPWM5 Operation.

Table 5-782 CTRLMMR_EPWM5_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4154h
Figure 5-378 CTRLMMR_EPWM5_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEALLOWRESERVEDTB_CLKEN
R-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-783 CTRLMMR_EPWM5_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4EALLOWR/W0h

Enable write access to ePWM tripzone and HRPWM config registers
0h - Disabled
1h - Enabled

3-1RESERVEDR0h

Reserved

0TB_CLKENR/W0h

Enable eHRPWM timebase clock
0h - Disabled
1h - Enabled

1.3.4.45 CTRLMMR_SOCA_SEL Register ( Offset = 4160h) [reset = 0h]

CTRLMMR_SOCA_SEL is shown in Figure 5-379 and described in Table 5-785.

Return to Summary Table.

Selects Start of Conversion A output signal source. Each eHRPWM provides a SOCA event that can be used to trigger external ADCs. All eHRPWM SOCA events are ORed together allowing any of the 6 eHRPWMs to generate the event (if enabled within the eHRPWM). This event is then muxed with an ICSSx host interrupt allowing either an ICSSx or eHRPWMs to source the SOCA event pin.

Table 5-784 CTRLMMR_SOCA_SEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4160h
Figure 5-379 CTRLMMR_SOCA_SEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSOCA_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-785 CTRLMMR_SOCA_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0SOCA_SELR/W0h

Selects the SOC A output source

0h - OR of all eHRPWM SOCA outputs

1h - None

2h - None

3h - None

1.3.4.46 CTRLMMR_SOCB_SEL Register ( Offset = 4164h) [reset = 0h]

CTRLMMR_SOCB_SEL is shown in Figure 5-380 and described in Table 5-787.

Return to Summary Table.

Selects Start of Conversion B output signal source.. Each eHRPWM provides a SOCB event that can be used to trigger external ADCs. All eHRPWM SOCB events are ORed together allowing any of the 6 eHRPWMs to generate the event (if enabled within the eHRPWM).

Table 5-786 CTRLMMR_SOCB_SEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4164h
Figure 5-380 CTRLMMR_SOCB_SEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSOCB_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-787 CTRLMMR_SOCB_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0SOCB_SELR/W0h

Selects the SOC B output source

0h - OR of all eHRPWM SOCB ouputs

1h - None

2h - None

3h - None

1.3.4.47 CTRLMMR_EQEP_STAT Register ( Offset = 41A0h) [reset = X]

CTRLMMR_EQEP_STAT is shown in Figure 5-381 and described in Table 5-789.

Return to Summary Table.

Displays status of EQEP modules.

Table 5-788 CTRLMMR_EQEP_STAT Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 41A0h
Figure 5-381 CTRLMMR_EQEP_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPHASE_ERR2PHASE_ERR1PHASE_ERR0
R-0hR-XR-XR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-789 CTRLMMR_EQEP_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2PHASE_ERR2RX

eQEP2 Phase error status
0h - No error
1h - Phase error occurred

1PHASE_ERR1RX

eQEP1 Phase error status
0h - No error
1h - Phase error occurred

0PHASE_ERR0RX

eQEP0 Phase error status
0h - No error
1h - Phase error occurred

1.3.4.48 CTRLMMR_SDIO1_CTRL Register ( Offset = 41B4h) [reset = X]

CTRLMMR_SDIO1_CTRL is shown in Figure 5-382 and described in Table 5-791.

Return to Summary Table.

Controls drive strength of MMC1 SDIO mode pins.

Table 5-790 CTRLMMR_SDIO1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 41B4h
Figure 5-382 CTRLMMR_SDIO1_CTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDDRV_STR
R-0hR/W-X
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-791 CTRLMMR_SDIO1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0DRV_STRR/WX

Selects the SDIO drive strength

1.3.4.49 CTRLMMR_TIMER0_CTRL Register ( Offset = 4200h) [reset = 0h]

CTRLMMR_TIMER0_CTRL is shown in Figure 5-383 and described in Table 5-793.

Return to Summary Table.

Controls TIMER0 operation.

Table 5-792 CTRLMMR_TIMER0_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4200h
Figure 5-383 CTRLMMR_TIMER0_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-793 CTRLMMR_TIMER0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER0 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.50 CTRLMMR_TIMER1_CTRL Register ( Offset = 4204h) [reset = 0h]

CTRLMMR_TIMER1_CTRL is shown in Figure 5-384 and described in Table 5-795.

Return to Summary Table.

Controls TIMER1 operation.

Table 5-794 CTRLMMR_TIMER1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4204h
Figure 5-384 CTRLMMR_TIMER1_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCASCADE_EN
R-0hR/W-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-795 CTRLMMR_TIMER1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8CASCADE_ENR/W0h

Enables cascading of TIMER1 to TIMER0

7-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER1 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.51 CTRLMMR_TIMER2_CTRL Register ( Offset = 4208h) [reset = 0h]

CTRLMMR_TIMER2_CTRL is shown in Figure 5-385 and described in Table 5-797.

Return to Summary Table.

Controls TIMER2 operation.

Table 5-796 CTRLMMR_TIMER2_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4208h
Figure 5-385 CTRLMMR_TIMER2_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-797 CTRLMMR_TIMER2_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER2 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.52 CTRLMMR_TIMER3_CTRL Register ( Offset = 420Ch) [reset = 0h]

CTRLMMR_TIMER3_CTRL is shown in Figure 5-386 and described in Table 5-799.

Return to Summary Table.

Controls TIMER3 operation.

Table 5-798 CTRLMMR_TIMER3_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 420Ch
Figure 5-386 CTRLMMR_TIMER3_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCASCADE_EN
R-0hR/W-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-799 CTRLMMR_TIMER3_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8CASCADE_ENR/W0h

Enables cascading of TIMER3 to TIMER2

7-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER3 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.53 CTRLMMR_TIMER4_CTRL Register ( Offset = 4210h) [reset = 0h]

CTRLMMR_TIMER4_CTRL is shown in Figure 5-387 and described in Table 5-801.

Return to Summary Table.

Controls TIMER4 operation.

Table 5-800 CTRLMMR_TIMER4_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4210h
Figure 5-387 CTRLMMR_TIMER4_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-801 CTRLMMR_TIMER4_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER4 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.54 CTRLMMR_TIMER5_CTRL Register ( Offset = 4214h) [reset = 0h]

CTRLMMR_TIMER5_CTRL is shown in Figure 5-388 and described in Table 5-803.

Return to Summary Table.

Controls TIMER5 operation.

Table 5-802 CTRLMMR_TIMER5_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4214h
Figure 5-388 CTRLMMR_TIMER5_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCASCADE_EN
R-0hR/W-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-803 CTRLMMR_TIMER5_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8CASCADE_ENR/W0h

Enables cascading of TIMER5 to TIMER4

7-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER5 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.55 CTRLMMR_TIMER6_CTRL Register ( Offset = 4218h) [reset = 0h]

CTRLMMR_TIMER6_CTRL is shown in Figure 5-389 and described in Table 5-805.

Return to Summary Table.

Controls TIMER6 operation.

Table 5-804 CTRLMMR_TIMER6_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4218h
Figure 5-389 CTRLMMR_TIMER6_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-805 CTRLMMR_TIMER6_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER6 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.56 CTRLMMR_TIMER7_CTRL Register ( Offset = 421Ch) [reset = 0h]

CTRLMMR_TIMER7_CTRL is shown in Figure 5-390 and described in Table 5-807.

Return to Summary Table.

Controls TIMER7 operation.

Table 5-806 CTRLMMR_TIMER7_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 421Ch
Figure 5-390 CTRLMMR_TIMER7_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCASCADE_EN
R-0hR/W-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-807 CTRLMMR_TIMER7_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8CASCADE_ENR/W0h

Enables cascading of TIMER7 to TIMER6

7-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER7 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.57 CTRLMMR_TIMER8_CTRL Register ( Offset = 4220h) [reset = 0h]

CTRLMMR_TIMER8_CTRL is shown in Figure 5-391 and described in Table 5-809.

Return to Summary Table.

Controls TIMER8 operation.

Table 5-808 CTRLMMR_TIMER8_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4220h
Figure 5-391 CTRLMMR_TIMER8_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-809 CTRLMMR_TIMER8_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER8 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.58 CTRLMMR_TIMER9_CTRL Register ( Offset = 4224h) [reset = 0h]

CTRLMMR_TIMER9_CTRL is shown in Figure 5-392 and described in Table 5-811.

Return to Summary Table.

Controls TIMER9 operation.

Table 5-810 CTRLMMR_TIMER9_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4224h
Figure 5-392 CTRLMMR_TIMER9_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCASCADE_EN
R-0hR/W-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-811 CTRLMMR_TIMER9_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8CASCADE_ENR/W0h

Enables cascading of TIMER9 to TIMER8

7-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER9 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.59 CTRLMMR_TIMER10_CTRL Register ( Offset = 4228h) [reset = 0h]

CTRLMMR_TIMER10_CTRL is shown in Figure 5-393 and described in Table 5-813.

Return to Summary Table.

Controls TIMER10 operation.

Table 5-812 CTRLMMR_TIMER10_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4228h
Figure 5-393 CTRLMMR_TIMER10_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-813 CTRLMMR_TIMER10_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER10 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.60 CTRLMMR_TIMER11_CTRL Register ( Offset = 422Ch) [reset = 0h]

CTRLMMR_TIMER11_CTRL is shown in Figure 5-394 and described in Table 5-815.

Return to Summary Table.

Controls TIMER11 operation.

Table 5-814 CTRLMMR_TIMER11_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 422Ch
Figure 5-394 CTRLMMR_TIMER11_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCASCADE_EN
R-0hR/W-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-815 CTRLMMR_TIMER11_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8CASCADE_ENR/W0h

Enables cascading of TIMER11 to TIMER10

7-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER11 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.61 CTRLMMR_TIMER12_CTRL Register ( Offset = 4230h) [reset = 0h]

CTRLMMR_TIMER12_CTRL is shown in Figure 5-395 and described in Table 5-817.

Return to Summary Table.

Controls TIMER12 operation.

Table 5-816 CTRLMMR_TIMER12_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4230h
Figure 5-395 CTRLMMR_TIMER12_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-817 CTRLMMR_TIMER12_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER12 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.62 CTRLMMR_TIMER13_CTRL Register ( Offset = 4234h) [reset = 0h]

CTRLMMR_TIMER13_CTRL is shown in Figure 5-396 and described in Table 5-819.

Return to Summary Table.

Controls TIMER13 operation.

Table 5-818 CTRLMMR_TIMER13_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4234h
Figure 5-396 CTRLMMR_TIMER13_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCASCADE_EN
R-0hR/W-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-819 CTRLMMR_TIMER13_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8CASCADE_ENR/W0h

Enables cascading of TIMER13 to TIMER12

7-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER13 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.63 CTRLMMR_TIMER14_CTRL Register ( Offset = 4238h) [reset = 0h]

CTRLMMR_TIMER14_CTRL is shown in Figure 5-397 and described in Table 5-821.

Return to Summary Table.

Controls TIMER14 operation.

Table 5-820 CTRLMMR_TIMER14_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4238h
Figure 5-397 CTRLMMR_TIMER14_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-821 CTRLMMR_TIMER14_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER14 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.64 CTRLMMR_TIMER15_CTRL Register ( Offset = 423Ch) [reset = 0h]

CTRLMMR_TIMER15_CTRL is shown in Figure 5-398 and described in Table 5-823.

Return to Summary Table.

Controls TIMER15 operation.

Table 5-822 CTRLMMR_TIMER15_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 423Ch
Figure 5-398 CTRLMMR_TIMER15_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCASCADE_EN
R-0hR/W-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-823 CTRLMMR_TIMER15_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8CASCADE_ENR/W0h

Enables cascading of TIMER15 to TIMER14

7-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER15 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.65 CTRLMMR_TIMER16_CTRL Register ( Offset = 4240h) [reset = 0h]

CTRLMMR_TIMER16_CTRL is shown in Figure 5-399 and described in Table 5-825.

Return to Summary Table.

Controls TIMER16 operation.

Table 5-824 CTRLMMR_TIMER16_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4240h
Figure 5-399 CTRLMMR_TIMER16_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-825 CTRLMMR_TIMER16_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER16 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.66 CTRLMMR_TIMER17_CTRL Register ( Offset = 4244h) [reset = 0h]

CTRLMMR_TIMER17_CTRL is shown in Figure 5-400 and described in Table 5-827.

Return to Summary Table.

Controls TIMER17 operation.

Table 5-826 CTRLMMR_TIMER17_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4244h
Figure 5-400 CTRLMMR_TIMER17_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCASCADE_EN
R-0hR/W-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-827 CTRLMMR_TIMER17_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8CASCADE_ENR/W0h

Enables cascading of TIMER17 to TIMER16

7-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER17 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.67 CTRLMMR_TIMER18_CTRL Register ( Offset = 4248h) [reset = 0h]

CTRLMMR_TIMER18_CTRL is shown in Figure 5-401 and described in Table 5-829.

Return to Summary Table.

Controls TIMER18 operation.

Table 5-828 CTRLMMR_TIMER18_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4248h
Figure 5-401 CTRLMMR_TIMER18_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-829 CTRLMMR_TIMER18_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER18 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.68 CTRLMMR_TIMER19_CTRL Register ( Offset = 424Ch) [reset = 0h]

CTRLMMR_TIMER19_CTRL is shown in Figure 5-402 and described in Table 5-831.

Return to Summary Table.

Controls TIMER19 operation.

Table 5-830 CTRLMMR_TIMER19_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 424Ch
Figure 5-402 CTRLMMR_TIMER19_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCASCADE_EN
R-0hR/W-0h
76543210
RESERVEDCAP_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-831 CTRLMMR_TIMER19_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8CASCADE_ENR/W0h

Enables cascading of TIMER19 to TIMER18

7-3RESERVEDR0h

Reserved

2-0CAP_SELR/W0h

Selects the TIMERIO input pin for capture input signal. This control is only used when TIMER19 is configured for capture operation.

0h - Use TIMERIO0 pin

1h - Use TIMERIO1 pin

2h - Use TIMERIO2 pin

3h - Use TIMERIO3 pin

4h - Use TIMERIO4 pin

5h - Use TIMERIO5 pin

6h - Use TIMERIO6 pin

7h - Use TIMERIO7 pin

1.3.4.69 CTRLMMR_TIMERIO0_CTRL Register ( Offset = 4280h) [reset = 0h]

CTRLMMR_TIMERIO0_CTRL is shown in Figure 5-403 and described in Table 5-833.

Return to Summary Table.

Controls Timer IO muxing.

Table 5-832 CTRLMMR_TIMERIO0_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4280h
Figure 5-403 CTRLMMR_TIMERIO0_CTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOUT_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-833 CTRLMMR_TIMERIO0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0OUT_SELR/W0h

Selects the source of the TIMERIO0 output

0h - TIMERIO0 is driven by TIMER0 output

1h - TIMERIO0 is driven by TIMER1 output

2h - TIMERIO0 is driven by TIMER2 output

3h - TIMERIO0 is driven by TIMER3 output

4h - TIMERIO0 is driven by TIMER4 output

5h - TIMERIO0 is driven by TIMER5 output

6h - TIMERIO0 is driven by TIMER6 output

7h - TIMERIO0 is driven by TIMER7 output

8h - TIMERIO0 is driven by TIMER8 output

9h - TIMERIO0 is driven by TIMER9 output

Ah - TIMERIO0 is driven by TIMER10 output

Bh - TIMERIO0 is driven by TIMER11 output

Ch - TIMERIO0 is driven by TIMER12 output

Dh - TIMERIO0 is driven by TIMER13 output

Eh - TIMERIO0 is driven by TIMER14 output

Fh - TIMERIO0 is driven by TIMER15 output

10h - TIMERIO0 is driven by TIMER16 output

11h - TIMERIO0 is driven by TIMER17 output

12h - TIMERIO0 is driven by TIMER18 output

13h - TIMERIO0 is driven by TIMER19 output

1.3.4.70 CTRLMMR_TIMERIO1_CTRL Register ( Offset = 4284h) [reset = 0h]

CTRLMMR_TIMERIO1_CTRL is shown in Figure 5-404 and described in Table 5-835.

Return to Summary Table.

Controls Timer IO muxing.

Table 5-834 CTRLMMR_TIMERIO1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4284h
Figure 5-404 CTRLMMR_TIMERIO1_CTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOUT_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-835 CTRLMMR_TIMERIO1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0OUT_SELR/W0h

Selects the source of the TIMERIO1 output

0h - TIMERIO1 is driven by TIMER0 output

1h - TIMERIO1 is driven by TIMER1 output

2h - TIMERIO1 is driven by TIMER2 output

3h - TIMERIO1 is driven by TIMER3 output

4h - TIMERIO1 is driven by TIMER4 output

5h - TIMERIO1 is driven by TIMER5 output

6h - TIMERIO1 is driven by TIMER6 output

7h - TIMERIO1 is driven by TIMER7 output

8h - TIMERIO1 is driven by TIMER8 output

9h - TIMERIO1 is driven by TIMER9 output

Ah - TIMERIO1 is driven by TIMER10 output

Bh - TIMERIO1 is driven by TIMER11 output

Ch - TIMERIO1 is driven by TIMER12 output

Dh - TIMERIO1 is driven by TIMER13 output

Eh - TIMERIO1 is driven by TIMER14 output

Fh - TIMERIO1 is driven by TIMER15 output

10h - TIMERIO1 is driven by TIMER16 output

11h - TIMERIO1 is driven by TIMER17 output

12h - TIMERIO1 is driven by TIMER18 output

13h - TIMERIO1 is driven by TIMER19 output

1.3.4.71 CTRLMMR_TIMERIO2_CTRL Register ( Offset = 4288h) [reset = 0h]

CTRLMMR_TIMERIO2_CTRL is shown in Figure 5-405 and described in Table 5-837.

Return to Summary Table.

Controls Timer IO muxing.

Table 5-836 CTRLMMR_TIMERIO2_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4288h
Figure 5-405 CTRLMMR_TIMERIO2_CTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOUT_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-837 CTRLMMR_TIMERIO2_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0OUT_SELR/W0h

Selects the source of the TIMERIO2 output

0h - TIMERIO2 is driven by TIMER0 output

1h - TIMERIO2 is driven by TIMER1 output

2h - TIMERIO2 is driven by TIMER2 output

3h - TIMERIO2 is driven by TIMER3 output

4h - TIMERIO2 is driven by TIMER4 output

5h - TIMERIO2 is driven by TIMER5 output

6h - TIMERIO2 is driven by TIMER6 output

7h - TIMERIO2 is driven by TIMER7 output

8h - TIMERIO2 is driven by TIMER8 output

9h - TIMERIO2 is driven by TIMER9 output

Ah - TIMERIO2 is driven by TIMER10 output

Bh - TIMERIO2 is driven by TIMER11 output

Ch - TIMERIO2 is driven by TIMER12 output

Dh - TIMERIO2 is driven by TIMER13 output

Eh - TIMERIO2 is driven by TIMER14 output

Fh - TIMERIO2 is driven by TIMER15 output

10h - TIMERIO2 is driven by TIMER16 output

11h - TIMERIO2 is driven by TIMER17 output

12h - TIMERIO2 is driven by TIMER18 output

13h - TIMERIO2 is driven by TIMER19 output

1.3.4.72 CTRLMMR_TIMERIO3_CTRL Register ( Offset = 428Ch) [reset = 0h]

CTRLMMR_TIMERIO3_CTRL is shown in Figure 5-406 and described in Table 5-839.

Return to Summary Table.

Controls Timer IO muxing.

Table 5-838 CTRLMMR_TIMERIO3_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 428Ch
Figure 5-406 CTRLMMR_TIMERIO3_CTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOUT_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-839 CTRLMMR_TIMERIO3_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0OUT_SELR/W0h

Selects the source of the TIMERIO3 output

0h - TIMERIO3 is driven by TIMER0 output

1h - TIMERIO3 is driven by TIMER1 output

2h - TIMERIO3 is driven by TIMER2 output

3h - TIMERIO3 is driven by TIMER3 output

4h - TIMERIO3 is driven by TIMER4 output

5h - TIMERIO3 is driven by TIMER5 output

6h - TIMERIO3 is driven by TIMER6 output

7h - TIMERIO3 is driven by TIMER7 output

8h - TIMERIO3 is driven by TIMER8 output

9h - TIMERIO3 is driven by TIMER9 output

Ah - TIMERIO3 is driven by TIMER10 output

Bh - TIMERIO3 is driven by TIMER11 output

Ch - TIMERIO3 is driven by TIMER12 output

Dh - TIMERIO3 is driven by TIMER13 output

Eh - TIMERIO3 is driven by TIMER14 output

Fh - TIMERIO3 is driven by TIMER15 output

10h - TIMERIO3 is driven by TIMER16 output

11h - TIMERIO3 is driven by TIMER17 output

12h - TIMERIO3 is driven by TIMER18 output

13h - TIMERIO3 is driven by TIMER19 output

1.3.4.73 CTRLMMR_TIMERIO4_CTRL Register ( Offset = 4290h) [reset = 0h]

CTRLMMR_TIMERIO4_CTRL is shown in Figure 5-407 and described in Table 5-841.

Return to Summary Table.

Controls Timer IO muxing.

Table 5-840 CTRLMMR_TIMERIO4_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4290h
Figure 5-407 CTRLMMR_TIMERIO4_CTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOUT_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-841 CTRLMMR_TIMERIO4_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0OUT_SELR/W0h

Selects the source of the TIMERIO4 output

0h - TIMERIO4 is driven by TIMER0 output

1h - TIMERIO4 is driven by TIMER1 output

2h - TIMERIO4 is driven by TIMER2 output

3h - TIMERIO4 is driven by TIMER3 output

4h - TIMERIO4 is driven by TIMER4 output

5h - TIMERIO4 is driven by TIMER5 output

6h - TIMERIO4 is driven by TIMER6 output

7h - TIMERIO4 is driven by TIMER7 output

8h - TIMERIO4 is driven by TIMER8 output

9h - TIMERIO4 is driven by TIMER9 output

Ah - TIMERIO4 is driven by TIMER10 output

Bh - TIMERIO4 is driven by TIMER11 output

Ch - TIMERIO4 is driven by TIMER12 output

Dh - TIMERIO4 is driven by TIMER13 output

Eh - TIMERIO4 is driven by TIMER14 output

Fh - TIMERIO4 is driven by TIMER15 output

10h - TIMERIO4 is driven by TIMER16 output

11h - TIMERIO4 is driven by TIMER17 output

12h - TIMERIO4 is driven by TIMER18 output

13h - TIMERIO4 is driven by TIMER19 output

1.3.4.74 CTRLMMR_TIMERIO5_CTRL Register ( Offset = 4294h) [reset = 0h]

CTRLMMR_TIMERIO5_CTRL is shown in Figure 5-408 and described in Table 5-843.

Return to Summary Table.

Controls Timer IO muxing.

Table 5-842 CTRLMMR_TIMERIO5_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4294h
Figure 5-408 CTRLMMR_TIMERIO5_CTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOUT_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-843 CTRLMMR_TIMERIO5_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0OUT_SELR/W0h

Selects the source of the TIMERIO5 output

0h - TIMERIO5 is driven by TIMER0 output

1h - TIMERIO5 is driven by TIMER1 output

2h - TIMERIO5 is driven by TIMER2 output

3h - TIMERIO5 is driven by TIMER3 output

4h - TIMERIO5 is driven by TIMER4 output

5h - TIMERIO5 is driven by TIMER5 output

6h - TIMERIO5 is driven by TIMER6 output

7h - TIMERIO5 is driven by TIMER7 output

8h - TIMERIO5 is driven by TIMER8 output

9h - TIMERIO5 is driven by TIMER9 output

Ah - TIMERIO5 is driven by TIMER10 output

Bh - TIMERIO5 is driven by TIMER11 output

Ch - TIMERIO5 is driven by TIMER12 output

Dh - TIMERIO5 is driven by TIMER13 output

Eh - TIMERIO5 is driven by TIMER14 output

Fh - TIMERIO5 is driven by TIMER15 output

10h - TIMERIO5 is driven by TIMER16 output

11h - TIMERIO5 is driven by TIMER17 output

12h - TIMERIO5 is driven by TIMER18 output

13h - TIMERIO5 is driven by TIMER19 output

1.3.4.75 CTRLMMR_TIMERIO6_CTRL Register ( Offset = 4298h) [reset = 0h]

CTRLMMR_TIMERIO6_CTRL is shown in Figure 5-409 and described in Table 5-845.

Return to Summary Table.

Controls Timer IO muxing.

Table 5-844 CTRLMMR_TIMERIO6_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4298h
Figure 5-409 CTRLMMR_TIMERIO6_CTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOUT_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-845 CTRLMMR_TIMERIO6_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0OUT_SELR/W0h

Selects the source of the TIMERIO6 output

0h - TIMERIO6 is driven by TIMER0 output

1h - TIMERIO6 is driven by TIMER1 output

2h - TIMERIO6 is driven by TIMER2 output

3h - TIMERIO6 is driven by TIMER3 output

4h - TIMERIO6 is driven by TIMER4 output

5h - TIMERIO6 is driven by TIMER5 output

6h - TIMERIO6 is driven by TIMER6 output

7h - TIMERIO6 is driven by TIMER7 output

8h - TIMERIO6 is driven by TIMER8 output

9h - TIMERIO6 is driven by TIMER9 output

Ah - TIMERIO6 is driven by TIMER10 output

Bh - TIMERIO6 is driven by TIMER11 output

Ch - TIMERIO6 is driven by TIMER12 output

Dh - TIMERIO6 is driven by TIMER13 output

Eh - TIMERIO6 is driven by TIMER14 output

Fh - TIMERIO6 is driven by TIMER15 output

10h - TIMERIO6 is driven by TIMER16 output

11h - TIMERIO6 is driven by TIMER17 output

12h - TIMERIO6 is driven by TIMER18 output

13h - TIMERIO6 is driven by TIMER19 output

1.3.4.76 CTRLMMR_TIMERIO7_CTRL Register ( Offset = 429Ch) [reset = 0h]

CTRLMMR_TIMERIO7_CTRL is shown in Figure 5-410 and described in Table 5-847.

Return to Summary Table.

Controls Timer IO muxing.

Table 5-846 CTRLMMR_TIMERIO7_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 429Ch
Figure 5-410 CTRLMMR_TIMERIO7_CTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDOUT_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-847 CTRLMMR_TIMERIO7_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0OUT_SELR/W0h

Selects the source of the TIMERIO7 output

0h - TIMERIO7 is driven by TIMER0 output

1h - TIMERIO7 is driven by TIMER1 output

2h - TIMERIO7 is driven by TIMER2 output

3h - TIMERIO7 is driven by TIMER3 output

4h - TIMERIO7 is driven by TIMER4 output

5h - TIMERIO7 is driven by TIMER5 output

6h - TIMERIO7 is driven by TIMER6 output

7h - TIMERIO7 is driven by TIMER7 output

8h - TIMERIO7 is driven by TIMER8 output

9h - TIMERIO7 is driven by TIMER9 output

Ah - TIMERIO7 is driven by TIMER10 output

Bh - TIMERIO7 is driven by TIMER11 output

Ch - TIMERIO7 is driven by TIMER12 output

Dh - TIMERIO7 is driven by TIMER13 output

Eh - TIMERIO7 is driven by TIMER14 output

Fh - TIMERIO7 is driven by TIMER15 output

10h - TIMERIO7 is driven by TIMER16 output

11h - TIMERIO7 is driven by TIMER17 output

12h - TIMERIO7 is driven by TIMER18 output

13h - TIMERIO7 is driven by TIMER19 output

1.3.4.77 CTRLMMR_I3C0_CTRL0 Register ( Offset = 42C0h) [reset = 1020000h]

CTRLMMR_I3C0_CTRL0 is shown in Figure 5-411 and described in Table 5-849.

Return to Summary Table.

Controls I3C0 operation.

Table 5-848 CTRLMMR_I3C0_CTRL0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 42C0h
Figure 5-411 CTRLMMR_I3C0_CTRL0 Register
3130292827262524
RESERVEDPID_MFR_ID
R-0hR/W-102h
2322212019181716
PID_MFR_ID
R/W-102h
15141312111098
RESERVEDROLE
R-0hR/W-0h
76543210
RESERVEDPID_INSTANCE
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-849 CTRLMMR_I3C0_CTRL0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h

Reserved

30-16PID_MFR_IDR/W102h

Manufacturer ID
This input corresponds to bits[47:33] of the Provisional ID to identify the manufacturer.
Defaults to TI value.

15-9RESERVEDR0h

Reserved

8ROLER/W0h

Master Role
0h - Main master
1h - Secondary master

7-4RESERVEDR0h

Reserved

3-0PID_INSTANCER/W0h

Provisional ID Instance. This input corresponds to bits[15:12] of the Provisional ID. It is intended to provide a way of differentiating several I3C devices if there would be no other way to have each manufactured device have a unique Provisional ID

1.3.4.78 CTRLMMR_I3C0_CTRL1 Register ( Offset = 42C4h) [reset = 0h]

CTRLMMR_I3C0_CTRL1 is shown in Figure 5-412 and described in Table 5-851.

Return to Summary Table.

Controls I3C0 operation.

Table 5-850 CTRLMMR_I3C0_CTRL1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 42C4h
Figure 5-412 CTRLMMR_I3C0_CTRL1 Register
3130292827262524
BUS_AVAIL_TIME
R/W-0h
2322212019181716
RESERVEDBUS_IDLE_TIME
R-0hR/W-0h
15141312111098
BUS_IDLE_TIME
R/W-0h
76543210
BUS_IDLE_TIME
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-851 CTRLMMR_I3C0_CTRL1 Register Field Descriptions
BitFieldTypeResetDescription
31-24BUS_AVAIL_TIMER/W0h

Indicates the number of sclk cycles in the Bus Available condition

23-18RESERVEDR0h

Reserved

17-0BUS_IDLE_TIMER/W0h

Indicates the number of sclk cycles in the Bus Idle condition

1.3.4.79 CTRLMMR_I2C0_CTRL Register ( Offset = 42E0h) [reset = 0h]

CTRLMMR_I2C0_CTRL is shown in Figure 5-413 and described in Table 5-853.

Return to Summary Table.

Controls I2C0 operation for open drain I/Os.

Table 5-852 CTRLMMR_I2C0_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 42E0h
Figure 5-413 CTRLMMR_I2C0_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDHS_MCS_EN
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-853 CTRLMMR_I2C0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0HS_MCS_ENR/W0h

HS Mode master current source enable.
When set, enables the current-source pull-up on the SCL output. Only one master on the I2C bus should enable SCL current sourcing.

1.3.4.80 CTRLMMR_MCASP1_CTRL Register ( Offset = 4584h) [reset = 0h]

CTRLMMR_MCASP1_CTRL is shown in Figure 5-414 and described in Table 5-855.

Return to Summary Table.

Controls McASP1 operation.

Table 5-854 CTRLMMR_MCASP1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4584h
Figure 5-414 CTRLMMR_MCASP1_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
AXR15_ENRESERVEDAXR15_SRC
R/W-0hR-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
AXR14_ENRESERVEDAXR14_SRC
R/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-855 CTRLMMR_MCASP1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23AXR15_ENR/W0h

Enable AXR15 receive data.
0h - AXR15 input driven 0h
1h - AXR15 input driven by AFSR/X input selected by axr15_src value

22-19RESERVEDR0h

Reserved

18-16AXR15_SRCR/W0h

Selects one of the AFSX or AFSR inputs as the AXR15 data input

0h - McASP0_AFSR

1h - McASP0_AFSX

2h - McASP1_AFSR

3h - McASP1_AFSX

4h - McASP2_AFSR

5h - McASP2_AFSX

6h - "0"

7h - "0"

15-8RESERVEDR0h

Reserved

7AXR14_ENR/W0h

Enable AXR14 receive data.
0h - AXR14 input driven 0h
1h - AXR14 input driven by AFSR/X input selected by axr14_src value

6-3RESERVEDR0h

Reserved

2-0AXR14_SRCR/W0h

Selects one of the AFSX or AFSR inputs as the AXR14 data input

0h - McASP0_AFSR

1h - McASP0_AFSX

2h - McASP1_AFSR

3h - McASP1_AFSX

4h - McASP2_AFSR

5h - McASP2_AFSX

6h - "0"

7h - "0"

1.3.4.81 CTRLMMR_MCASP2_CTRL Register ( Offset = 4588h) [reset = 0h]

CTRLMMR_MCASP2_CTRL is shown in Figure 5-415 and described in Table 5-857.

Return to Summary Table.

Controls McASP2 operation.

Table 5-856 CTRLMMR_MCASP2_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4588h
Figure 5-415 CTRLMMR_MCASP2_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
AXR15_ENRESERVEDAXR15_SRC
R/W-0hR-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
AXR14_ENRESERVEDAXR14_SRC
R/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-857 CTRLMMR_MCASP2_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23AXR15_ENR/W0h

Enable AXR15 receive data.
0h - AXR15 input driven 0h
1h - AXR15 input driven by AFSR/X input selected by axr15_src value

22-19RESERVEDR0h

Reserved

18-16AXR15_SRCR/W0h

Selects one of the AFSX or AFSR inputs as the AXR15 data input

0h - McASP0_AFSR

1h - McASP0_AFSX

2h - McASP1_AFSR

3h - McASP1_AFSX

4h - McASP2_AFSR

5h - McASP2_AFSX

6h - "0"

7h - "0"

15-8RESERVEDR0h

Reserved

7AXR14_ENR/W0h

Enable AXR14 receive data.
0h - AXR14 input driven 0h
1h - AXR14 input driven by AFSR/X input selected by axr14_src value

6-3RESERVEDR0h

Reserved

2-0AXR14_SRCR/W0h

Selects one of the AFSX or AFSR inputs as the AXR14 data input

0h - McASP0_AFSR

1h - McASP0_AFSX

2h - McASP1_AFSR

3h - McASP1_AFSX

4h - McASP2_AFSR

5h - McASP2_AFSX

6h - "0"

7h - "0"

1.3.4.82 CTRLMMR_MAIN_MTOG0_CTRL Register ( Offset = 4600h) [reset = X]

CTRLMMR_MAIN_MTOG0_CTRL is shown in Figure 5-416 and described in Table 5-859.

Return to Summary Table.

Controls timeout operation of read transactions from the GIC master port.

Table 5-858 CTRLMMR_MAIN_MTOG0_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4600h
Figure 5-416 CTRLMMR_MAIN_MTOG0_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-859 CTRLMMR_MAIN_MTOG0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG0 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.83 CTRLMMR_MAIN_MTOG1_CTRL Register ( Offset = 4604h) [reset = X]

CTRLMMR_MAIN_MTOG1_CTRL is shown in Figure 5-417 and described in Table 5-861.

Return to Summary Table.

Controls timeout operation of write transactions from the GIC master port.

Table 5-860 CTRLMMR_MAIN_MTOG1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4604h
Figure 5-417 CTRLMMR_MAIN_MTOG1_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-861 CTRLMMR_MAIN_MTOG1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG1 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.84 CTRLMMR_MAIN_MTOG2_CTRL Register ( Offset = 4608h) [reset = X]

CTRLMMR_MAIN_MTOG2_CTRL is shown in Figure 5-418 and described in Table 5-863.

Return to Summary Table.

Controls timeout operation of read transactions from the 8-bit eMMC0 master port.

Table 5-862 CTRLMMR_MAIN_MTOG2_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4608h
Figure 5-418 CTRLMMR_MAIN_MTOG2_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-863 CTRLMMR_MAIN_MTOG2_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG2 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.85 CTRLMMR_MAIN_MTOG3_CTRL Register ( Offset = 460Ch) [reset = X]

CTRLMMR_MAIN_MTOG3_CTRL is shown in Figure 5-419 and described in Table 5-865.

Return to Summary Table.

Controls timeout operation of write transactions from the 8-bit eMMC0 master port.

Table 5-864 CTRLMMR_MAIN_MTOG3_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 460Ch
Figure 5-419 CTRLMMR_MAIN_MTOG3_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-865 CTRLMMR_MAIN_MTOG3_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG3 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.86 CTRLMMR_MAIN_MTOG4_CTRL Register ( Offset = 4610h) [reset = X]

CTRLMMR_MAIN_MTOG4_CTRL is shown in Figure 5-420 and described in Table 5-867.

Return to Summary Table.

Controls timeout operation of read transactions from the 4-bit eMMC1 master port.

Table 5-866 CTRLMMR_MAIN_MTOG4_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4610h
Figure 5-420 CTRLMMR_MAIN_MTOG4_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-867 CTRLMMR_MAIN_MTOG4_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG4 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.87 CTRLMMR_MAIN_MTOG5_CTRL Register ( Offset = 4614h) [reset = X]

CTRLMMR_MAIN_MTOG5_CTRL is shown in Figure 5-421 and described in Table 5-869.

Return to Summary Table.

Controls timeout operation of write transactions from the 4-bit eMMC1 master port.

Table 5-868 CTRLMMR_MAIN_MTOG5_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4614h
Figure 5-421 CTRLMMR_MAIN_MTOG5_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-869 CTRLMMR_MAIN_MTOG5_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG5 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.88 CTRLMMR_MAIN_MTOG10_CTRL Register ( Offset = 4628h) [reset = X]

CTRLMMR_MAIN_MTOG10_CTRL is shown in Figure 5-422 and described in Table 5-871.

Return to Summary Table.

Controls timeout operation of read transactions from the PCIe1 master port.

Table 5-870 CTRLMMR_MAIN_MTOG10_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4628h
Figure 5-422 CTRLMMR_MAIN_MTOG10_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-871 CTRLMMR_MAIN_MTOG10_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG10 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.89 CTRLMMR_MAIN_MTOG11_CTRL Register ( Offset = 462Ch) [reset = X]

CTRLMMR_MAIN_MTOG11_CTRL is shown in Figure 5-423 and described in Table 5-873.

Return to Summary Table.

Controls timeout operation of write transactions from the PCIe1 master port.

Table 5-872 CTRLMMR_MAIN_MTOG11_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 462Ch
Figure 5-423 CTRLMMR_MAIN_MTOG11_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-873 CTRLMMR_MAIN_MTOG11_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG11 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.90 CTRLMMR_MAIN_MTOG12_CTRL Register ( Offset = 4630h) [reset = X]

CTRLMMR_MAIN_MTOG12_CTRL is shown in Figure 5-424 and described in Table 5-875.

Return to Summary Table.

Controls timeout operation of read transactions from the USB0 master port.

Table 5-874 CTRLMMR_MAIN_MTOG12_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4630h
Figure 5-424 CTRLMMR_MAIN_MTOG12_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-875 CTRLMMR_MAIN_MTOG12_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG12 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.91 CTRLMMR_MAIN_MTOG13_CTRL Register ( Offset = 4634h) [reset = X]

CTRLMMR_MAIN_MTOG13_CTRL is shown in Figure 5-425 and described in Table 5-877.

Return to Summary Table.

Controls timeout operation of write transactions from the USB0 master port.

Table 5-876 CTRLMMR_MAIN_MTOG13_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4634h
Figure 5-425 CTRLMMR_MAIN_MTOG13_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-877 CTRLMMR_MAIN_MTOG13_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG13 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.92 CTRLMMR_MAIN_MTOG14_CTRL Register ( Offset = 4638h) [reset = X]

CTRLMMR_MAIN_MTOG14_CTRL is shown in Figure 5-426 and described in Table 5-879.

Return to Summary Table.

Controls timeout operation of transactions from the NavSS PVU to VIRTSS.

Table 5-878 CTRLMMR_MAIN_MTOG14_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4638h
Figure 5-426 CTRLMMR_MAIN_MTOG14_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-879 CTRLMMR_MAIN_MTOG14_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG14 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.93 CTRLMMR_MAIN_MTOG16_CTRL Register ( Offset = 4640h) [reset = X]

CTRLMMR_MAIN_MTOG16_CTRL is shown in Figure 5-427 and described in Table 5-881.

Return to Summary Table.

Controls timeout operation of read transactions from the MAIN R5 Core 0 VBUSM Memory master port.

Table 5-880 CTRLMMR_MAIN_MTOG16_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4640h
Figure 5-427 CTRLMMR_MAIN_MTOG16_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-881 CTRLMMR_MAIN_MTOG16_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG16 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.94 CTRLMMR_MAIN_MTOG17_CTRL Register ( Offset = 4644h) [reset = X]

CTRLMMR_MAIN_MTOG17_CTRL is shown in Figure 5-428 and described in Table 5-883.

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Controls timeout operation of write transactions from the MAIN R5 Core 0 VBUSM Memory master port.

Table 5-882 CTRLMMR_MAIN_MTOG17_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4644h
Figure 5-428 CTRLMMR_MAIN_MTOG17_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-883 CTRLMMR_MAIN_MTOG17_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG17 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.95 CTRLMMR_MAIN_MTOG18_CTRL Register ( Offset = 4648h) [reset = X]

CTRLMMR_MAIN_MTOG18_CTRL is shown in Figure 5-429 and described in Table 5-885.

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Controls timeout operation of read transactions from the MAIN R5 Core 1 VBUSM Memory master port.

Table 5-884 CTRLMMR_MAIN_MTOG18_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 4648h
Figure 5-429 CTRLMMR_MAIN_MTOG18_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-885 CTRLMMR_MAIN_MTOG18_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG18 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.96 CTRLMMR_MAIN_MTOG19_CTRL Register ( Offset = 464Ch) [reset = X]

CTRLMMR_MAIN_MTOG19_CTRL is shown in Figure 5-430 and described in Table 5-887.

Return to Summary Table.

Controls timeout operation of write transactions from the MAIN R5 Core 1 VBUSM Memory master port.

Table 5-886 CTRLMMR_MAIN_MTOG19_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 464Ch
Figure 5-430 CTRLMMR_MAIN_MTOG19_CTRL Register
3130292827262524
IDLE_STATRESERVED
R-XR-0h
2322212019181716
FORCE_TIMEOUT
R/W-0h
15141312111098
TIMEOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDTIMEOUT_VAL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-887 CTRLMMR_MAIN_MTOG19_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31IDLE_STATRX

Idle status
When high, indicates MTOG19 is idle.

30-24RESERVEDR0h

Reserved

23-16FORCE_TIMEOUTR/W0h

Force Timout
Forces a flush of the interface transactions. This bitfield is only relevant if timeout_en=1. After forcing a timeout by writing the encoded value, the force_timeout and timeout_en bitfields must be cleared to clear the timeout before re-enabling the gasket.

95h - Force a gasket timeout
All others - Normal operation

15TIMEOUT_ENR/W0h

Timeout Enable
0h - Disable the gasket. Clear the interrupt and reset the counter
1h - Enable the timeout gasket functions

14-3RESERVEDR0h

Reserved

2-0TIMEOUT_VALR/W0h

Gasket Timeout Value
Selects the number of clock cycles before the interface is considered to have timed out

0h - 1024 clock cycles

1h - 4096 clock cycles

2h - 16,384 clock cycles

3h - 65,536 clock cycles

4h - 262,144 clock cycles

5h - 1,048,576 clock cycles

6h - 2,097,152 clock cycles

7h - 4,194,303 clock cycles

1.3.4.97 CTRLMMR_CC_EN_FLUSH_CTRL Register ( Offset = 46C0h) [reset = 0h]

CTRLMMR_CC_EN_FLUSH_CTRL is shown in Figure 5-431 and described in Table 5-889.

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Enables flushing of the Eagles Nest ARM Corepac / MSMC interface. This register is used isolate the MSMC ARM Corepac interfaces from other MSMC transactions in case of an ARM Corepac access hang. This allows continuation of other MSMC traffic (e.g. R5 processors) without interferance. After asserting this flush, the ARM Corepac can be forced through a power cycle sequence to clear the hang condition.

Table 5-888 CTRLMMR_CC_EN_FLUSH_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 46C0h
Figure 5-431 CTRLMMR_CC_EN_FLUSH_CTRL Register
313029282726252423222120191817161514131211109876543210
RESERVEDFLUSH
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-889 CTRLMMR_CC_EN_FLUSH_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved

15-0FLUSHR/W0h

Flush ARM / MSMC Interface Transactions
Forces a flush of the A72 MSMC interface. This bit field can be used to force a flush of A72 transcastions to the MSMC and force an auto response of any MSMC snoop requests the the A72. This field only has effect if the dis_egln_external_flush_cntrl bit in the Compute Cluster CorepacPower Management FFI CFG Register is 0. An encoded bit value is used to prevent accidental activation of the flush signal.

95h - Force a flush (FFI Mode) condition (flush signal driven high)
All others - Normal operation (flush signal driven low)

1.3.4.98 CTRLMMR_LOCK1_KICK0 Register ( Offset = 5008h) [reset = 0h]

CTRLMMR_LOCK1_KICK0 is shown in Figure 5-432 and described in Table 5-891.

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Lower 32-bits of Partition1 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK1_KICK1 with its key value before write-protected Partition 1 registers can be written.

Table 5-890 CTRLMMR_LOCK1_KICK0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 5008h
Figure 5-432 CTRLMMR_LOCK1_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-891 CTRLMMR_LOCK1_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition1 registers

0UNLOCKEDR0h

Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.3.4.99 CTRLMMR_LOCK1_KICK1 Register ( Offset = 500Ch) [reset = 0h]

CTRLMMR_LOCK1_KICK1 is shown in Figure 5-433 and described in Table 5-893.

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Upper 32-bits of Partition 1 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK1_KICK0 with its key value before write-protected Partition 1 registers can be written.

Table 5-892 CTRLMMR_LOCK1_KICK1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 500Ch
Figure 5-433 CTRLMMR_LOCK1_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-893 CTRLMMR_LOCK1_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition1 registers

1.3.4.100 CTRLMMR_OBSCLK0_CTRL Register ( Offset = 8000h) [reset = 1Dh]

CTRLMMR_OBSCLK0_CTRL is shown in Figure 5-434 and described in Table 5-895.

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This register controls which internal clock is made observable on the OBSCLK[2:0] output pins.

Table 5-894 CTRLMMR_OBSCLK0_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8000h
Figure 5-434 CTRLMMR_OBSCLK0_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
CLK_DIV
R/W-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-1Dh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-895 CTRLMMR_OBSCLK0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the OBSCLK0 divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-8CLK_DIVR/W0h

OBSCLK0 output divider
Divides the selected clock by clkdiv+1 for output to the OBSCLK[2:0] pins. Supports divide by 1 to 256 (default to 1). To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

7-5RESERVEDR0h

Reserved

4-0CLK_SELR/W1Dh

OBSCLK0 clock source selection.
Selects the source of the clock to be divided by the OBSCLK0 divider and output on the OBSCLK[2:0] pins.

0h - MAIN_PLL0_HSDIV0_CLKOUT

1h - MAIN_PLL1_HSDIV0_CLKOUT

2h - MAIN_PLL2_HSDIV1_CLKOUT

3h - MAIN_PLL3_HSDIV0_CLKOUT

4h - MAIN_PLL4_HSDIV0_CLKOUT

5h - "0"

6h - "0"

7h - "0"

8h - "0"

9h - "0"

Ah - "0"

Bh - "0"

Ch - MAIN_PLL12_HSDIV0_CLKOUT

Dh - OBSCLK1 OUT

Eh - MAIN_PLL14_HSDIV0_CLKOUT

Fh - "0"

10h - "0"

11h - "0"

12h - "0"

13h - "0"

14h - "0"

15h - "0"

16h - "0"

17h - "0"

18h - "0"

19h - "0"

1Ah - CPTS_GENF3

1Bh - CLK_12M_RC

1Ch - LFXOSC_CLKOUT

1Dh - PLLCTRL_OBSCLK

1Eh - HFOSC1_CLKOUT

1Fh - HFOSC0_CLKOUT

1.3.4.101 CTRLMMR_OBSCLK1_CTRL Register ( Offset = 8004h) [reset = 0h]

CTRLMMR_OBSCLK1_CTRL is shown in Figure 5-435 and described in Table 5-897.

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This register controls which internal clock is made observable on the OBSCLK1_OUT internal clock signal.

Table 5-896 CTRLMMR_OBSCLK1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8004h
Figure 5-435 CTRLMMR_OBSCLK1_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-897 CTRLMMR_OBSCLK1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

OBSCLK1_OUT signal output clock source selection

0h - "0"

1h - MAIN_PLL8_HSDIV0_CLKOUT / DIV8

2h - "0"

3h - "0"

1.3.4.102 CTRLMMR_CLKOUT_CTRL Register ( Offset = 8010h) [reset = 0h]

CTRLMMR_CLKOUT_CTRL is shown in Figure 5-436 and described in Table 5-899.

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Enables and selects clock source of CPSW CLKOUT pin.

Table 5-898 CTRLMMR_CLKOUT_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8010h
Figure 5-436 CTRLMMR_CLKOUT_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_ENRESERVEDCLK_SEL
R-0hR/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-899 CTRLMMR_CLKOUT_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4CLK_ENR/W0h

When set, enables CLKOUT output

3-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects CLKOUT clock source
0h - RGMII_MHZ_50_CLK (50 MHz)
1h - RGMII_MHZ_50_CLK_DIV2 (25 MHz)

1.3.4.103 CTRLMMR_GTC_CLKSEL Register ( Offset = 8030h) [reset = 0h]

CTRLMMR_GTC_CLKSEL is shown in Figure 5-437 and described in Table 5-901.

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Selects the timebase clock source for the Global Timebase Counter.

Table 5-900 CTRLMMR_GTC_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8030h
Figure 5-437 CTRLMMR_GTC_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-901 CTRLMMR_GTC_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Selects the GTC timebase clock source

0h - MAIN_PLL3_HSDIV1_CLKOUT

1h - MAIN_PLL0_HSDIV6_CLKOUT

2h - MCU_CPTS_REF_CLK (pin)

3h - CPTS_RFT_CLK (pin)

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - SERDES0_IP2_LN0_TXMCLK

7h - SERDES0_IP2_LN1_TXMCLK

8h - SERDES0_IP2_LN2_TXMCLK

9h - SERDES0_IP2_LN3_TXMCLK

Ah - "0"

Bh - "0"

Ch - "0"

Dh - "0"

Eh - MCU_PLL2_HSDIV1_CLKOUT

Fh - MAIN_SYSCLK0

1.3.4.104 CTRLMMR_EFUSE_CLKSEL Register ( Offset = 803Ch) [reset = 0h]

CTRLMMR_EFUSE_CLKSEL is shown in Figure 5-438 and described in Table 5-903.

Return to Summary Table.

Selects the functional clock source for the MAIN domain eFuse Controller.

Table 5-902 CTRLMMR_EFUSE_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 803Ch
Figure 5-438 CTRLMMR_EFUSE_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-903 CTRLMMR_EFUSE_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0CLK_SELR/W0h

Selects the clock source

0h - HFOSC0_CLKOUT

1h - MAIN_SYSCLK0 / 4

1.3.4.105 CTRLMMR_PCIE1_CLKSEL Register ( Offset = 8084h) [reset = 0h]

CTRLMMR_PCIE1_CLKSEL is shown in Figure 5-439 and described in Table 5-905.

Return to Summary Table.

Selects PCIe1 functional clock sources.

Table 5-904 CTRLMMR_PCIE1_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8084h
Figure 5-439 CTRLMMR_PCIE1_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCPTS_CLKSEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-905 CTRLMMR_PCIE1_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CPTS_CLKSELR/W0h

Selects the clock source for the PCIE1 Common Platform Time Stamp module

0h - MAIN_PLL3_HSDIV1_CLKOUT

1h - MAIN_PLL0_HSDIV6_CLKOUT

2h - MCU_CPTS_REF_CLK (pin)

3h - CPTS_RFT_CLK (pin)

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - SERDES0_IP2_LN0_TXMCLK

7h - SERDES0_IP2_LN1_TXMCLK

8h - SERDES0_IP2_LN2_TXMCLK

9h - SERDES0_IP2_LN3_TXMCLK

Ah - "0"

Bh - "0"

Ch - "0"

Dh - "0"

Eh - MCU_PLL2_HSDIV1_CLKOUT

Fh - MAIN_SYSCLK0

1.3.4.106 CTRLMMR_CPSW_CLKSEL Register ( Offset = 8090h) [reset = 0h]

CTRLMMR_CPSW_CLKSEL is shown in Figure 5-440 and described in Table 5-907.

Return to Summary Table.

Selects the 9X CP Switch clock sources.

Table 5-906 CTRLMMR_CPSW_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8090h
Figure 5-440 CTRLMMR_CPSW_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCPTS_CLKSEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-907 CTRLMMR_CPSW_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CPTS_CLKSELR/W0h

Selects the clock source for the CPSW Ethernet switch Common Platform Time Stamp module

0h - MAIN_PLL3_HSDIV1_CLKOUT

1h - MAIN_PLL0_HSDIV6_CLKOUT

2h - MCU_CPTS_REF_CLK (pin)

3h - CPTS_RFT_CLK (pin)

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - SERDES0_IP2_LN0_TXMCLK

7h - SERDES0_IP2_LN1_TXMCLK

8h - SERDES0_IP2_LN2_TXMCLK

9h - SERDES0_IP2_LN3_TXMCLK

Ah - "0"

Bh - "0"

Ch - "0"

Dh - "0"

Eh - MCU_PLL2_HSDIV1_CLKOUT

Fh - MAIN_SYSCLK0

1.3.4.107 CTRLMMR_NAVSS_CLKSEL Register ( Offset = 8098h) [reset = 0h]

CTRLMMR_NAVSS_CLKSEL is shown in Figure 5-441 and described in Table 5-909.

Return to Summary Table.

Selects the clock source for the Nav Subsystem.

Table 5-908 CTRLMMR_NAVSS_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8098h
Figure 5-441 CTRLMMR_NAVSS_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCPTS_CLKSEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-909 CTRLMMR_NAVSS_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CPTS_CLKSELR/W0h

Selects the clock source for the SoC] Common Platform Time Stamp module located within the Nav Subsystem

0h - MAIN_PLL3_HSDIV1_CLKOUT

1h - MAIN_PLL0_HSDIV6_CLKOUT

2h - MCU_CPTS_REF_CLK (pin)

3h - CPTS_RFT_CLK (pin)

4h - MCU_EXT_REFCLK0 (pin)

5h - EXT_REFCLK1 (pin)

6h - SERDES0_IP2_LN0_TXMCLK

7h - SERDES0_IP2_LN1_TXMCLK

8h - SERDES0_IP2_LN2_TXMCLK

9h - SERDES0_IP2_LN3_TXMCLK

Ah - "0"

Bh - "0"

Ch - "0"

Dh - "0"

Eh - MCU_PLL2_HSDIV1_CLKOUT

Fh - MAIN_SYSCLK0

1.3.4.108 CTRLMMR_EMMC0_CLKSEL Register ( Offset = 80B0h) [reset = 0h]

CTRLMMR_EMMC0_CLKSEL is shown in Figure 5-442 and described in Table 5-911.

Return to Summary Table.

Selects the functional clock source for 8-bit eMMC0.

Table 5-910 CTRLMMR_EMMC0_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 80B0h
Figure 5-442 CTRLMMR_EMMC0_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-911 CTRLMMR_EMMC0_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

eMMC XIN_CLK selection
0h - MAIN_PLL0_HSDIV2_CLKOUT
1h - MAIN_PLL1_HSDIV2_CLKOUT
2h - MAIN_PLL2_HSDIV2_CLKOUT
3h - MAIN_PLL3_HSDIV2_CLKOUT

1.3.4.109 CTRLMMR_EMMC1_CLKSEL Register ( Offset = 80B4h) [reset = 1h]

CTRLMMR_EMMC1_CLKSEL is shown in Figure 5-443 and described in Table 5-913.

Return to Summary Table.

Selects the functional clock source for 4-bit eMMC1.

Table 5-912 CTRLMMR_EMMC1_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 80B4h
Figure 5-443 CTRLMMR_EMMC1_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDLB_CLKSEL
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-1h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-913 CTRLMMR_EMMC1_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16LB_CLKSELR/W0h

eMMC Loopback clock selection
0h - Loopback clock from MMC1_CLKLB pad
1h - Loopback clock from MMC1_CLK pin

15-2RESERVEDR0h

Reserved

1-0CLK_SELR/W1h

eMMC XIN_CLK selection
0h - MAIN_PLL0_HSDIV2_CLKOUT
1h - MAIN_PLL1_HSDIV2_CLKOUT
2h - MAIN_PLL2_HSDIV2_CLKOUT
3h - MAIN_PLL3_HSDIV2_CLKOUT

1.3.4.110 CTRLMMR_GPMC_CLKSEL Register ( Offset = 80D0h) [reset = 0h]

CTRLMMR_GPMC_CLKSEL is shown in Figure 5-444 and described in Table 5-915.

Return to Summary Table.

Selects the bus and functional clock source for the GPMC module. This allows the GPMC to run asynchronously to the bus fabric in order to optimize parallel port performance.

Table 5-914 CTRLMMR_GPMC_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 80D0h
Figure 5-444 CTRLMMR_GPMC_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-915 CTRLMMR_GPMC_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

Selects the GPMC clock source
0h - MAIN_PLL0_HSDIV3_CLKOUT
1h - MAIN_PLL2_HSDIV1_CLKOUT / 6
2h - MAIN_PLL2_HSDIV1_CLKOUT / 4
3h - MAIN_SYSCLK0 / 4

1.3.4.111 CTRLMMR_USB0_CLKSEL Register ( Offset = 80E0h) [reset = 0h]

CTRLMMR_USB0_CLKSEL is shown in Figure 5-445 and described in Table 5-917.

Return to Summary Table.

Selects the functional clock sources for USB0.

Table 5-916 CTRLMMR_USB0_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 80E0h
Figure 5-445 CTRLMMR_USB0_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDREFCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-917 CTRLMMR_USB0_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0REFCLK_SELR/W0h

Selects the clock source for the USB0 ref_clk.
0h - Use HFOSC0_CLKOUT
1h - Use HFOSC1_CLKOUT

1.3.4.112 CTRLMMR_TIMER0_CLKSEL Register ( Offset = 8100h) [reset = 0h]

CTRLMMR_TIMER0_CLKSEL is shown in Figure 5-446 and described in Table 5-919.

Return to Summary Table.

Timer0 functional clock selection control.

Table 5-918 CTRLMMR_TIMER0_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8100h
Figure 5-446 CTRLMMR_TIMER0_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-919 CTRLMMR_TIMER0_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.113 CTRLMMR_TIMER1_CLKSEL Register ( Offset = 8104h) [reset = 0h]

CTRLMMR_TIMER1_CLKSEL is shown in Figure 5-447 and described in Table 5-921.

Return to Summary Table.

Timer1 functional clock selection control.

Table 5-920 CTRLMMR_TIMER1_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8104h
Figure 5-447 CTRLMMR_TIMER1_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-921 CTRLMMR_TIMER1_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.114 CTRLMMR_TIMER2_CLKSEL Register ( Offset = 8108h) [reset = 0h]

CTRLMMR_TIMER2_CLKSEL is shown in Figure 5-448 and described in Table 5-923.

Return to Summary Table.

Timer2 functional clock selection control.

Table 5-922 CTRLMMR_TIMER2_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8108h
Figure 5-448 CTRLMMR_TIMER2_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-923 CTRLMMR_TIMER2_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.115 CTRLMMR_TIMER3_CLKSEL Register ( Offset = 810Ch) [reset = 0h]

CTRLMMR_TIMER3_CLKSEL is shown in Figure 5-449 and described in Table 5-925.

Return to Summary Table.

Timer3 functional clock selection control.

Table 5-924 CTRLMMR_TIMER3_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 810Ch
Figure 5-449 CTRLMMR_TIMER3_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-925 CTRLMMR_TIMER3_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.116 CTRLMMR_TIMER4_CLKSEL Register ( Offset = 8110h) [reset = 0h]

CTRLMMR_TIMER4_CLKSEL is shown in Figure 5-450 and described in Table 5-927.

Return to Summary Table.

Timer4 functional clock selection control.

Table 5-926 CTRLMMR_TIMER4_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8110h
Figure 5-450 CTRLMMR_TIMER4_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-927 CTRLMMR_TIMER4_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.117 CTRLMMR_TIMER5_CLKSEL Register ( Offset = 8114h) [reset = 0h]

CTRLMMR_TIMER5_CLKSEL is shown in Figure 5-451 and described in Table 5-929.

Return to Summary Table.

Timer5 functional clock selection control.

Table 5-928 CTRLMMR_TIMER5_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8114h
Figure 5-451 CTRLMMR_TIMER5_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-929 CTRLMMR_TIMER5_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.118 CTRLMMR_TIMER6_CLKSEL Register ( Offset = 8118h) [reset = 0h]

CTRLMMR_TIMER6_CLKSEL is shown in Figure 5-452 and described in Table 5-931.

Return to Summary Table.

Timer6 functional clock selection control.

Table 5-930 CTRLMMR_TIMER6_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8118h
Figure 5-452 CTRLMMR_TIMER6_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-931 CTRLMMR_TIMER6_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.119 CTRLMMR_TIMER7_CLKSEL Register ( Offset = 811Ch) [reset = 0h]

CTRLMMR_TIMER7_CLKSEL is shown in Figure 5-453 and described in Table 5-933.

Return to Summary Table.

Timer7 functional clock selection control.

Table 5-932 CTRLMMR_TIMER7_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 811Ch
Figure 5-453 CTRLMMR_TIMER7_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-933 CTRLMMR_TIMER7_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.120 CTRLMMR_TIMER8_CLKSEL Register ( Offset = 8120h) [reset = 0h]

CTRLMMR_TIMER8_CLKSEL is shown in Figure 5-454 and described in Table 5-935.

Return to Summary Table.

Timer8 functional clock selection control.

Table 5-934 CTRLMMR_TIMER8_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8120h
Figure 5-454 CTRLMMR_TIMER8_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-935 CTRLMMR_TIMER8_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.121 CTRLMMR_TIMER9_CLKSEL Register ( Offset = 8124h) [reset = 0h]

CTRLMMR_TIMER9_CLKSEL is shown in Figure 5-455 and described in Table 5-937.

Return to Summary Table.

Timer9 functional clock selection control.

Table 5-936 CTRLMMR_TIMER9_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8124h
Figure 5-455 CTRLMMR_TIMER9_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-937 CTRLMMR_TIMER9_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.122 CTRLMMR_TIMER10_CLKSEL Register ( Offset = 8128h) [reset = 0h]

CTRLMMR_TIMER10_CLKSEL is shown in Figure 5-456 and described in Table 5-939.

Return to Summary Table.

Timer10 functional clock selection control.

Table 5-938 CTRLMMR_TIMER10_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8128h
Figure 5-456 CTRLMMR_TIMER10_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-939 CTRLMMR_TIMER10_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.123 CTRLMMR_TIMER11_CLKSEL Register ( Offset = 812Ch) [reset = 0h]

CTRLMMR_TIMER11_CLKSEL is shown in Figure 5-457 and described in Table 5-941.

Return to Summary Table.

Timer11 functional clock selection control.

Table 5-940 CTRLMMR_TIMER11_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 812Ch
Figure 5-457 CTRLMMR_TIMER11_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-941 CTRLMMR_TIMER11_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.124 CTRLMMR_TIMER12_CLKSEL Register ( Offset = 8130h) [reset = 0h]

CTRLMMR_TIMER12_CLKSEL is shown in Figure 5-458 and described in Table 5-943.

Return to Summary Table.

Timer12 functional clock selection control.

Table 5-942 CTRLMMR_TIMER12_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8130h
Figure 5-458 CTRLMMR_TIMER12_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-943 CTRLMMR_TIMER12_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.125 CTRLMMR_TIMER13_CLKSEL Register ( Offset = 8134h) [reset = 0h]

CTRLMMR_TIMER13_CLKSEL is shown in Figure 5-459 and described in Table 5-945.

Return to Summary Table.

Timer13 functional clock selection control.

Table 5-944 CTRLMMR_TIMER13_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8134h
Figure 5-459 CTRLMMR_TIMER13_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-945 CTRLMMR_TIMER13_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.126 CTRLMMR_TIMER14_CLKSEL Register ( Offset = 8138h) [reset = 0h]

CTRLMMR_TIMER14_CLKSEL is shown in Figure 5-460 and described in Table 5-947.

Return to Summary Table.

Timer14 functional clock selection control.

Table 5-946 CTRLMMR_TIMER14_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8138h
Figure 5-460 CTRLMMR_TIMER14_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-947 CTRLMMR_TIMER14_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.127 CTRLMMR_TIMER15_CLKSEL Register ( Offset = 813Ch) [reset = 0h]

CTRLMMR_TIMER15_CLKSEL is shown in Figure 5-461 and described in Table 5-949.

Return to Summary Table.

Timer15 functional clock selection control.

Table 5-948 CTRLMMR_TIMER15_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 813Ch
Figure 5-461 CTRLMMR_TIMER15_CLKSEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-949 CTRLMMR_TIMER15_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.128 CTRLMMR_TIMER16_CLKSEL Register ( Offset = 8140h) [reset = 0h]

CTRLMMR_TIMER16_CLKSEL is shown in Figure 5-462 and described in Table 5-951.

Return to Summary Table.

Timer16 functional clock selection control.

Table 5-950 CTRLMMR_TIMER16_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8140h
Figure 5-462 CTRLMMR_TIMER16_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
AFS_SRC_ENRESERVEDAFS_SRC_SEL
R/W-0hR-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-951 CTRLMMR_TIMER16_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23AFS_SRC_ENR/W0h

Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set.
0h - Use functional clock selected by clk_sel value
1h - Use AFS input selected by afs_src_sel value

22-19RESERVEDR0h

Reserved

18-16AFS_SRC_SELR/W0h

Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set.

0h - McASP0_AFSR

1h - McASP0_AFSX

2h - McASP1_AFSR

3h - McASP1_AFSX

4h - McASP2_AFSR

5h - McASP2_AFSX

6h - "0"

7h - "0"

15-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.129 CTRLMMR_TIMER17_CLKSEL Register ( Offset = 8144h) [reset = 0h]

CTRLMMR_TIMER17_CLKSEL is shown in Figure 5-463 and described in Table 5-953.

Return to Summary Table.

Timer17 functional clock selection control.

Table 5-952 CTRLMMR_TIMER17_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8144h
Figure 5-463 CTRLMMR_TIMER17_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
AFS_SRC_ENRESERVEDAFS_SRC_SEL
R/W-0hR-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-953 CTRLMMR_TIMER17_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23AFS_SRC_ENR/W0h

Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set.
0h - Use functional clock selected by clk_sel value
1h - Use AFS input selected by afs_src_sel value

22-19RESERVEDR0h

Reserved

18-16AFS_SRC_SELR/W0h

Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set.

0h - McASP0_AFSR

1h - McASP0_AFSX

2h - McASP1_AFSR

3h - McASP1_AFSX

4h - McASP2_AFSR

5h - McASP2_AFSX

6h - "0"

7h - "0"

15-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.130 CTRLMMR_TIMER18_CLKSEL Register ( Offset = 8148h) [reset = 0h]

CTRLMMR_TIMER18_CLKSEL is shown in Figure 5-464 and described in Table 5-955.

Return to Summary Table.

Timer18 functional clock selection control.

Table 5-954 CTRLMMR_TIMER18_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8148h
Figure 5-464 CTRLMMR_TIMER18_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
AFS_SRC_ENRESERVEDAFS_SRC_SEL
R/W-0hR-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-955 CTRLMMR_TIMER18_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23AFS_SRC_ENR/W0h

Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set.
0h - Use functional clock selected by clk_sel value
1h - Use AFS input selected by afs_src_sel value

22-19RESERVEDR0h

Reserved

18-16AFS_SRC_SELR/W0h

Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set.

0h - McASP0_AFSR

1h - McASP0_AFSX

2h - McASP1_AFSR

3h - McASP1_AFSX

4h - McASP2_AFSR

5h - McASP2_AFSX

6h - "0"

7h - "0"

15-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.131 CTRLMMR_TIMER19_CLKSEL Register ( Offset = 814Ch) [reset = 0h]

CTRLMMR_TIMER19_CLKSEL is shown in Figure 5-465 and described in Table 5-957.

Return to Summary Table.

Timer19 functional clock selection control.

Table 5-956 CTRLMMR_TIMER19_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 814Ch
Figure 5-465 CTRLMMR_TIMER19_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
AFS_SRC_ENRESERVEDAFS_SRC_SEL
R/W-0hR-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-957 CTRLMMR_TIMER19_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h

Reserved

23AFS_SRC_ENR/W0h

Enable AFS source mux output as the Timer clock source. Note that for TIMER17 and TIMER19 this selection will be overridden if cascade_en in the associated TIMERn_CTRL register is set.
0h - Use functional clock selected by clk_sel value
1h - Use AFS input selected by afs_src_sel value

22-19RESERVEDR0h

Reserved

18-16AFS_SRC_SELR/W0h

Selects the ASFR/AFSX input to use as a timer clock when afs_src_en is set.

0h - McASP0_AFSR

1h - McASP0_AFSX

2h - McASP1_AFSR

3h - McASP1_AFSX

4h - McASP2_AFSR

5h - McASP2_AFSX

6h - "0"

7h - "0"

15-4RESERVEDR0h

Reserved

3-0CLK_SELR/W0h

Timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL0_HSDIV1_CLKOUT

3h - CLK_12M_RC

4h - MAIN_PLL3_HSDIV3_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - LFXOSC_CLKOUT

8h - CPTS_RFT_CLK (pin)

9h - MAIN_PLL1_HSDIV3_CLKOUT

Ah - MAIN_PLL2_HSDIV6_CLKOUT

Bh - MAIN_PLL4_HSDIV2_CLKOUT

Ch - CPTS_GENF2

Dh - CPTS_GENF3

Eh - CPSW5X_CPTS_GENF0

Fh - CPTS_GENF4

1.3.4.132 CTRLMMR_SPI0_CLKSEL Register ( Offset = 8190h) [reset = 0h]

CTRLMMR_SPI0_CLKSEL is shown in Figure 5-466 and described in Table 5-959.

Return to Summary Table.

SPI0 clock control.

Table 5-958 CTRLMMR_SPI0_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8190h
Figure 5-466 CTRLMMR_SPI0_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMSTR_LB_CLKSEL
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-959 CTRLMMR_SPI0_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MSTR_LB_CLKSELR/W0h

Master mode receive capture clock loopback selection
0h - Internal clock loopback
1h - Loopback from pad

15-0RESERVEDR0h

Reserved

1.3.4.133 CTRLMMR_SPI1_CLKSEL Register ( Offset = 8194h) [reset = 0h]

CTRLMMR_SPI1_CLKSEL is shown in Figure 5-467 and described in Table 5-961.

Return to Summary Table.

SPI1 clock control.

Table 5-960 CTRLMMR_SPI1_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8194h
Figure 5-467 CTRLMMR_SPI1_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMSTR_LB_CLKSEL
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-961 CTRLMMR_SPI1_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MSTR_LB_CLKSELR/W0h

Master mode receive capture clock loopback selection
0h - Internal clock loopback
1h - Loopback from pad

15-0RESERVEDR0h

Reserved

1.3.4.134 CTRLMMR_SPI2_CLKSEL Register ( Offset = 8198h) [reset = 0h]

CTRLMMR_SPI2_CLKSEL is shown in Figure 5-468 and described in Table 5-963.

Return to Summary Table.

SPI2 clock control.

Table 5-962 CTRLMMR_SPI2_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8198h
Figure 5-468 CTRLMMR_SPI2_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMSTR_LB_CLKSEL
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-963 CTRLMMR_SPI2_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MSTR_LB_CLKSELR/W0h

Master mode receive capture clock loopback selection
0h - Internal clock loopback
1h - Loopback from pad

15-0RESERVEDR0h

Reserved

1.3.4.135 CTRLMMR_SPI3_CLKSEL Register ( Offset = 819Ch) [reset = 0h]

CTRLMMR_SPI3_CLKSEL is shown in Figure 5-469 and described in Table 5-965.

Return to Summary Table.

SPI3 clock control.

Table 5-964 CTRLMMR_SPI3_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 819Ch
Figure 5-469 CTRLMMR_SPI3_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMSTR_LB_CLKSEL
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-965 CTRLMMR_SPI3_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MSTR_LB_CLKSELR/W0h

Master mode receive capture clock loopback selection
0h - Internal clock loopback
1h - Loopback from pad

15-0RESERVEDR0h

Reserved

1.3.4.136 CTRLMMR_SPI5_CLKSEL Register ( Offset = 81A4h) [reset = 0h]

CTRLMMR_SPI5_CLKSEL is shown in Figure 5-470 and described in Table 5-967.

Return to Summary Table.

SPI5 clock control.

Table 5-966 CTRLMMR_SPI5_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81A4h
Figure 5-470 CTRLMMR_SPI5_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMSTR_LB_CLKSEL
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-967 CTRLMMR_SPI5_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MSTR_LB_CLKSELR/W0h

Master mode receive capture clock loopback selection
0h - Internal clock loopback
1h - Loopback from pad

15-0RESERVEDR0h

Reserved

1.3.4.137 CTRLMMR_SPI6_CLKSEL Register ( Offset = 81A8h) [reset = 0h]

CTRLMMR_SPI6_CLKSEL is shown in Figure 5-471 and described in Table 5-969.

Return to Summary Table.

SPI6 clock control.

Table 5-968 CTRLMMR_SPI6_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81A8h
Figure 5-471 CTRLMMR_SPI6_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMSTR_LB_CLKSEL
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-969 CTRLMMR_SPI6_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MSTR_LB_CLKSELR/W0h

Master mode receive capture clock loopback selection
0h - Internal clock loopback
1h - Loopback from pad

15-0RESERVEDR0h

Reserved

1.3.4.138 CTRLMMR_SPI7_CLKSEL Register ( Offset = 81ACh) [reset = 0h]

CTRLMMR_SPI7_CLKSEL is shown in Figure 5-472 and described in Table 5-971.

Return to Summary Table.

SPI7 clock control.

Table 5-970 CTRLMMR_SPI7_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81ACh
Figure 5-472 CTRLMMR_SPI7_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDMSTR_LB_CLKSEL
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-971 CTRLMMR_SPI7_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16MSTR_LB_CLKSELR/W0h

Master mode receive capture clock loopback selection
0h - Internal clock loopback
1h - Loopback from pad

15-0RESERVEDR0h

Reserved

1.3.4.139 CTRLMMR_USART0_CLK_CTRL Register ( Offset = 81C0h) [reset = 3h]

CTRLMMR_USART0_CLK_CTRL is shown in Figure 5-473 and described in Table 5-973.

Return to Summary Table.

Selects the clock divider of the USART0 functional clock.

Table 5-972 CTRLMMR_USART0_CLK_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81C0h
Figure 5-473 CTRLMMR_USART0_CLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_DIV
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-973 CTRLMMR_USART0_CLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the USART0 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-2RESERVEDR0h

Reserved

1-0CLK_DIVR/W3h

Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

0h - Divide by 1

1h - Divide by 2

2h - Divide by 3

3h - Divide by 4

1.3.4.140 CTRLMMR_USART1_CLK_CTRL Register ( Offset = 81C4h) [reset = 3h]

CTRLMMR_USART1_CLK_CTRL is shown in Figure 5-474 and described in Table 5-975.

Return to Summary Table.

Selects the clock divider of the USART1 functional clock.

Table 5-974 CTRLMMR_USART1_CLK_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81C4h
Figure 5-474 CTRLMMR_USART1_CLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_DIV
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-975 CTRLMMR_USART1_CLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the USART1 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-2RESERVEDR0h

Reserved

1-0CLK_DIVR/W3h

Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

0h - Divide by 1

1h - Divide by 2

2h - Divide by 3

3h - Divide by 4

1.3.4.141 CTRLMMR_USART2_CLK_CTRL Register ( Offset = 81C8h) [reset = 3h]

CTRLMMR_USART2_CLK_CTRL is shown in Figure 5-475 and described in Table 5-977.

Return to Summary Table.

Selects the clock divider of the USART2 functional clock.

Table 5-976 CTRLMMR_USART2_CLK_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81C8h
Figure 5-475 CTRLMMR_USART2_CLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_DIV
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-977 CTRLMMR_USART2_CLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the USART2 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-2RESERVEDR0h

Reserved

1-0CLK_DIVR/W3h

Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

0h - Divide by 1

1h - Divide by 2

2h - Divide by 3

3h - Divide by 4

1.3.4.142 CTRLMMR_USART3_CLK_CTRL Register ( Offset = 81CCh) [reset = 3h]

CTRLMMR_USART3_CLK_CTRL is shown in Figure 5-476 and described in Table 5-979.

Return to Summary Table.

Selects the clock divider of the USART3 functional clock.

Table 5-978 CTRLMMR_USART3_CLK_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81CCh
Figure 5-476 CTRLMMR_USART3_CLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_DIV
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-979 CTRLMMR_USART3_CLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the USART3 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-2RESERVEDR0h

Reserved

1-0CLK_DIVR/W3h

Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

0h - Divide by 1

1h - Divide by 2

2h - Divide by 3

3h - Divide by 4

1.3.4.143 CTRLMMR_USART4_CLK_CTRL Register ( Offset = 81D0h) [reset = 3h]

CTRLMMR_USART4_CLK_CTRL is shown in Figure 5-477 and described in Table 5-981.

Return to Summary Table.

Selects the clock divider of the USART4 functional clock.

Table 5-980 CTRLMMR_USART4_CLK_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81D0h
Figure 5-477 CTRLMMR_USART4_CLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_DIV
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-981 CTRLMMR_USART4_CLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the USART4 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-2RESERVEDR0h

Reserved

1-0CLK_DIVR/W3h

Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

0h - Divide by 1

1h - Divide by 2

2h - Divide by 3

3h - Divide by 4

1.3.4.144 CTRLMMR_USART5_CLK_CTRL Register ( Offset = 81D4h) [reset = 3h]

CTRLMMR_USART5_CLK_CTRL is shown in Figure 5-478 and described in Table 5-983.

Return to Summary Table.

Selects the clock divider of the USART5 functional clock.

Table 5-982 CTRLMMR_USART5_CLK_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81D4h
Figure 5-478 CTRLMMR_USART5_CLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_DIV
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-983 CTRLMMR_USART5_CLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the USART5 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-2RESERVEDR0h

Reserved

1-0CLK_DIVR/W3h

Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

0h - Divide by 1

1h - Divide by 2

2h - Divide by 3

3h - Divide by 4

1.3.4.145 CTRLMMR_USART6_CLK_CTRL Register ( Offset = 81D8h) [reset = 3h]

CTRLMMR_USART6_CLK_CTRL is shown in Figure 5-479 and described in Table 5-985.

Return to Summary Table.

Selects the clock divider of the USART6 functional clock.

Table 5-984 CTRLMMR_USART6_CLK_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81D8h
Figure 5-479 CTRLMMR_USART6_CLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_DIV
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-985 CTRLMMR_USART6_CLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the USART6 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-2RESERVEDR0h

Reserved

1-0CLK_DIVR/W3h

Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

0h - Divide by 1

1h - Divide by 2

2h - Divide by 3

3h - Divide by 4

1.3.4.146 CTRLMMR_USART7_CLK_CTRL Register ( Offset = 81DCh) [reset = 3h]

CTRLMMR_USART7_CLK_CTRL is shown in Figure 5-480 and described in Table 5-987.

Return to Summary Table.

Selects the clock divider of the USART7 functional clock.

Table 5-986 CTRLMMR_USART7_CLK_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81DCh
Figure 5-480 CTRLMMR_USART7_CLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_DIV
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-987 CTRLMMR_USART7_CLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the USART7 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-2RESERVEDR0h

Reserved

1-0CLK_DIVR/W3h

Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

0h - Divide by 1

1h - Divide by 2

2h - Divide by 3

3h - Divide by 4

1.3.4.147 CTRLMMR_USART8_CLK_CTRL Register ( Offset = 81E0h) [reset = 3h]

CTRLMMR_USART8_CLK_CTRL is shown in Figure 5-481 and described in Table 5-989.

Return to Summary Table.

Selects the clock divider of the USART8 functional clock.

Table 5-988 CTRLMMR_USART8_CLK_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81E0h
Figure 5-481 CTRLMMR_USART8_CLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_DIV
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-989 CTRLMMR_USART8_CLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the USART8 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-2RESERVEDR0h

Reserved

1-0CLK_DIVR/W3h

Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

0h - Divide by 1

1h - Divide by 2

2h - Divide by 3

3h - Divide by 4

1.3.4.148 CTRLMMR_USART9_CLK_CTRL Register ( Offset = 81E4h) [reset = 3h]

CTRLMMR_USART9_CLK_CTRL is shown in Figure 5-482 and described in Table 5-991.

Return to Summary Table.

Selects the clock divider of the USART9 functional clock.

Table 5-990 CTRLMMR_USART9_CLK_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 81E4h
Figure 5-482 CTRLMMR_USART9_CLK_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDCLK_DIV_LD
R-0hR/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_DIV
R-0hR/W-3h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-991 CTRLMMR_USART9_CLK_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h

Reserved

16CLK_DIV_LDR/W0h

Load the output divider value
Writing 1 to this bit will generate a load pulse to load the USART9 clock programmable divider value. This bit can be cleared but must not be set in the same write cycle in which the clk_div value is changed.

15-2RESERVEDR0h

Reserved

1-0CLK_DIVR/W3h

Selects the clock divider value. Supports divide values of 1 to 4 Default is /4. To load the new divider value the clk_div_ld bit must be cleared and then set to 1.

0h - Divide by 1

1h - Divide by 2

2h - Divide by 3

3h - Divide by 4

1.3.4.149 CTRLMMR_MCASP0_CLKSEL Register ( Offset = 8200h) [reset = 0h]

CTRLMMR_MCASP0_CLKSEL is shown in Figure 5-483 and described in Table 5-993.

Return to Summary Table.

Selects the functional clock source for McASP0.

Table 5-992 CTRLMMR_MCASP0_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8200h
Figure 5-483 CTRLMMR_MCASP0_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDAUXCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-993 CTRLMMR_MCASP0_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0AUXCLK_SELR/W0h

Selects the McASP0 auxclk clock source

0h - MAIN_PLL4_HSDIV0_CLKOUT

1h - MAIN_PLL2_HSDIV2_CLKOUT

2h - "0"

3h - "0"

4h - ATCLK0

5h - ATCLK1

6h - ATCLK2

7h - ATCLK3

1.3.4.150 CTRLMMR_MCASP1_CLKSEL Register ( Offset = 8204h) [reset = 0h]

CTRLMMR_MCASP1_CLKSEL is shown in Figure 5-484 and described in Table 5-995.

Return to Summary Table.

Selects the functional clock source for McASP1.

Table 5-994 CTRLMMR_MCASP1_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8204h
Figure 5-484 CTRLMMR_MCASP1_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDAUXCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-995 CTRLMMR_MCASP1_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0AUXCLK_SELR/W0h

Selects the McASP1 auxclk clock source

0h - MAIN_PLL4_HSDIV0_CLKOUT

1h - MAIN_PLL2_HSDIV2_CLKOUT

2h - "0"

3h - "0"

4h - ATCLK0

5h - ATCLK1

6h - ATCLK2

7h - ATCLK3

1.3.4.151 CTRLMMR_MCASP2_CLKSEL Register ( Offset = 8208h) [reset = 0h]

CTRLMMR_MCASP2_CLKSEL is shown in Figure 5-485 and described in Table 5-997.

Return to Summary Table.

Selects the functional clock source for McASP2.

Table 5-996 CTRLMMR_MCASP2_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8208h
Figure 5-485 CTRLMMR_MCASP2_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDAUXCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-997 CTRLMMR_MCASP2_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h

Reserved

2-0AUXCLK_SELR/W0h

Selects the McASP2 auxclk clock source

0h - MAIN_PLL4_HSDIV0_CLKOUT

1h - MAIN_PLL2_HSDIV2_CLKOUT

2h - "0"

3h - "0"

4h - ATCLK0

5h - ATCLK1

6h - ATCLK2

7h - ATCLK3

1.3.4.152 CTRLMMR_MCASP0_AHCLKSEL Register ( Offset = 8240h) [reset = 0h]

CTRLMMR_MCASP0_AHCLKSEL is shown in Figure 5-486 and described in Table 5-999.

Return to Summary Table.

Selects the AHCLKX and AHCLKR clock source for McASP0.

Table 5-998 CTRLMMR_MCASP0_AHCLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8240h
Figure 5-486 CTRLMMR_MCASP0_AHCLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAHCLKX_SEL
R-0hR/W-0h
76543210
RESERVEDAHCLKR_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-999 CTRLMMR_MCASP0_AHCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h

Reserved

11-8AHCLKX_SELR/W0h

Selects the AHCLKX input source for McASP0

0h - HFOSC1_CLKOUT

1h - HFOSC0_CLKOUT

2h - AUDIO_EXT_REFCLK0_IN

3h - AUDIO_EXT_REFCLK1_IN

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - ATCLK0

9h - ATCLK1

Ah - ATCLK2

Bh - ATCLK3

7-4RESERVEDR0h

Reserved

3-0AHCLKR_SELR/W0h

Selects the AHCLKR input source for McASP0

0h - HFOSC1_CLKOUT

1h - HFOSC0_CLKOUT

2h - AUDIO_EXT_REFCLK0_IN

3h - AUDIO_EXT_REFCLK1_IN

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - ATCLK0

9h - ATCLK1

Ah - ATCLK2

Bh - ATCLK3

Ch - "0"

Dh - "0"

Eh - "0"

Fh - "0"

1.3.4.153 CTRLMMR_MCASP1_AHCLKSEL Register ( Offset = 8244h) [reset = 0h]

CTRLMMR_MCASP1_AHCLKSEL is shown in Figure 5-487 and described in Table 5-1001.

Return to Summary Table.

Selects the AHCLKX and AHCLKR clock source for McASP1.

Table 5-1000 CTRLMMR_MCASP1_AHCLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8244h
Figure 5-487 CTRLMMR_MCASP1_AHCLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAHCLKX_SEL
R-0hR/W-0h
76543210
RESERVEDAHCLKR_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1001 CTRLMMR_MCASP1_AHCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h

Reserved

11-8AHCLKX_SELR/W0h

Selects the AHCLKX input source for McASP1

0h - HFOSC1_CLKOUT

1h - HFOSC0_CLKOUT

2h - AUDIO_EXT_REFCLK0_IN

3h - AUDIO_EXT_REFCLK1_IN

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - ATCLK0

9h - ATCLK1

Ah - ATCLK2

Bh - ATCLK3

7-4RESERVEDR0h

Reserved

3-0AHCLKR_SELR/W0h

Selects the AHCLKR input source for McASP1

0h - HFOSC1_CLKOUT

1h - HFOSC0_CLKOUT

2h - AUDIO_EXT_REFCLK0_IN

3h - AUDIO_EXT_REFCLK1_IN

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - ATCLK0

9h - ATCLK1

Ah - ATCLK2

Bh - ATCLK3

Ch - "0"

Dh - "0"

Eh - "0"

Fh - "0"

1.3.4.154 CTRLMMR_MCASP2_AHCLKSEL Register ( Offset = 8248h) [reset = 0h]

CTRLMMR_MCASP2_AHCLKSEL is shown in Figure 5-488 and described in Table 5-1003.

Return to Summary Table.

Selects the AHCLKX and AHCLKR clock source for McASP2.

Table 5-1002 CTRLMMR_MCASP2_AHCLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8248h
Figure 5-488 CTRLMMR_MCASP2_AHCLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDAHCLKX_SEL
R-0hR/W-0h
76543210
RESERVEDAHCLKR_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1003 CTRLMMR_MCASP2_AHCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h

Reserved

11-8AHCLKX_SELR/W0h

Selects the AHCLKX input source for McASP2

0h - HFOSC1_CLKOUT

1h - HFOSC0_CLKOUT

2h - AUDIO_EXT_REFCLK0_IN

3h - AUDIO_EXT_REFCLK1_IN

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - ATCLK0

9h - ATCLK1

Ah - ATCLK2

Bh - ATCLK3

7-4RESERVEDR0h

Reserved

3-0AHCLKR_SELR/W0h

Selects the AHCLKR input source for McASP2

0h - HFOSC1_CLKOUT

1h - HFOSC0_CLKOUT

2h - AUDIO_EXT_REFCLK0_IN

3h - AUDIO_EXT_REFCLK1_IN

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - ATCLK0

9h - ATCLK1

Ah - ATCLK2

Bh - ATCLK3

Ch - "0"

Dh - "0"

Eh - "0"

Fh - "0"

1.3.4.155 CTRLMMR_ATL_BWS0_SEL Register ( Offset = 82A0h) [reset = 0h]

CTRLMMR_ATL_BWS0_SEL is shown in Figure 5-489 and described in Table 5-1005.

Return to Summary Table.

Selects the source of ATL Baseband Word Select 0.

Table 5-1004 CTRLMMR_ATL_BWS0_SEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82A0h
Figure 5-489 CTRLMMR_ATL_BWS0_SEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDWD_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1005 CTRLMMR_ATL_BWS0_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0WD_SELR/W0h

BWS source signal

0h - McASP0 AFSR Pin Input

1h - McASP1 AFSR Pin Input

2h - McASP2 AFSR Pin Input

3h - "0"

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - "0"

9h - "0"

Ah - "0"

Bh - "0"

Ch - McASP0 AFSX Pin Input

Dh - McASP1 AFSX Pin Input

Eh - McASP2 AFSX Pin Input

Fh - "0"

10h - "0"

11h - "0"

12h - "0"

13h - "0"

14h - "0"

15h - "0"

16h - "0"

17h - "0"

18h - AUDIO_EXT_REFCLK0 Pin input

19h - AUDIO_EXT_REFCLK1 Pin input

1Ah - "0"

1Bh - "0"

1.3.4.156 CTRLMMR_ATL_BWS1_SEL Register ( Offset = 82A4h) [reset = 0h]

CTRLMMR_ATL_BWS1_SEL is shown in Figure 5-490 and described in Table 5-1007.

Return to Summary Table.

Selects the source of ATL Baseband Word Select 1.

Table 5-1006 CTRLMMR_ATL_BWS1_SEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82A4h
Figure 5-490 CTRLMMR_ATL_BWS1_SEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDWD_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1007 CTRLMMR_ATL_BWS1_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0WD_SELR/W0h

BWS source signal

0h - McASP0 AFSR Pin Input

1h - McASP1 AFSR Pin Input

2h - McASP2 AFSR Pin Input

3h - "0"

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - "0"

9h - "0"

Ah - "0"

Bh - "0"

Ch - McASP0 AFSX Pin Input

Dh - McASP1 AFSX Pin Input

Eh - McASP2 AFSX Pin Input

Fh - "0"

10h - "0"

11h - "0"

12h - "0"

13h - "0"

14h - "0"

15h - "0"

16h - "0"

17h - "0"

18h - AUDIO_EXT_REFCLK0 Pin input

19h - AUDIO_EXT_REFCLK1 Pin input

1Ah - "0"

1Bh - "0"

1.3.4.157 CTRLMMR_ATL_BWS2_SEL Register ( Offset = 82A8h) [reset = 0h]

CTRLMMR_ATL_BWS2_SEL is shown in Figure 5-491 and described in Table 5-1009.

Return to Summary Table.

Selects the source of ATL Baseband Word Select 2.

Table 5-1008 CTRLMMR_ATL_BWS2_SEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82A8h
Figure 5-491 CTRLMMR_ATL_BWS2_SEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDWD_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1009 CTRLMMR_ATL_BWS2_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0WD_SELR/W0h

BWS source signal

0h - McASP0 AFSR Pin Input

1h - McASP1 AFSR Pin Input

2h - McASP2 AFSR Pin Input

3h - "0"

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - "0"

9h - "0"

Ah - "0"

Bh - "0"

Ch - McASP0 AFSX Pin Input

Dh - McASP1 AFSX Pin Input

Eh - McASP2 AFSX Pin Input

Fh - "0"

10h - "0"

11h - "0"

12h - "0"

13h - "0"

14h - "0"

15h - "0"

16h - "0"

17h - "0"

18h - AUDIO_EXT_REFCLK0 Pin input

19h - AUDIO_EXT_REFCLK1 Pin input

1Ah - "0"

1Bh - "0"

1.3.4.158 CTRLMMR_ATL_BWS3_SEL Register ( Offset = 82ACh) [reset = 0h]

CTRLMMR_ATL_BWS3_SEL is shown in Figure 5-492 and described in Table 5-1011.

Return to Summary Table.

Selects the source of ATL Baseband Word Select 3.

Table 5-1010 CTRLMMR_ATL_BWS3_SEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82ACh
Figure 5-492 CTRLMMR_ATL_BWS3_SEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDWD_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1011 CTRLMMR_ATL_BWS3_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0WD_SELR/W0h

BWS source signal

0h - McASP0 AFSR Pin Input

1h - McASP1 AFSR Pin Input

2h - McASP2 AFSR Pin Input

3h - "0"

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - "0"

9h - "0"

Ah - "0"

Bh - "0"

Ch - McASP0 AFSX Pin Input

Dh - McASP1 AFSX Pin Input

Eh - McASP2 AFSX Pin Input

Fh - "0"

10h - "0"

11h - "0"

12h - "0"

13h - "0"

14h - "0"

15h - "0"

16h - "0"

17h - "0"

18h - AUDIO_EXT_REFCLK0 Pin input

19h - AUDIO_EXT_REFCLK1 Pin input

1Ah - "0"

1Bh - "0"

1.3.4.159 CTRLMMR_ATL_AWS0_SEL Register ( Offset = 82B0h) [reset = 0h]

CTRLMMR_ATL_AWS0_SEL is shown in Figure 5-493 and described in Table 5-1013.

Return to Summary Table.

Selects the source of ATL Audio Word Select 0.

Table 5-1012 CTRLMMR_ATL_AWS0_SEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82B0h
Figure 5-493 CTRLMMR_ATL_AWS0_SEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDWD_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1013 CTRLMMR_ATL_AWS0_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0WD_SELR/W0h

AWS source signal

0h - McASP0 AFSX Pin Input

1h - McASP1 AFSX Pin Input

2h - McASP2 AFSX Pin Input

3h - "0"

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - "0"

9h - "0"

Ah - "0"

Bh - "0"

Ch - McASP0 AFSX Pin Input

Dh - McASP1 AFSX Pin Input

Eh - McASP2 AFSX Pin Input

Fh - "0"

10h - "0"

11h - "0"

12h - "0"

13h - "0"

14h - "0"

15h - "0"

16h - "0"

17h - "0"

18h - AUDIO_EXT_REFCLK0 Pin input

19h - AUDIO_EXT_REFCLK1 Pin input

1Ah - "0"

1Bh - "0"

1Ch - "0"

1Dh - "0"

1.3.4.160 CTRLMMR_ATL_AWS1_SEL Register ( Offset = 82B4h) [reset = 0h]

CTRLMMR_ATL_AWS1_SEL is shown in Figure 5-494 and described in Table 5-1015.

Return to Summary Table.

Selects the source of ATL Audio Word Select 1.

Table 5-1014 CTRLMMR_ATL_AWS1_SEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82B4h
Figure 5-494 CTRLMMR_ATL_AWS1_SEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDWD_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1015 CTRLMMR_ATL_AWS1_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0WD_SELR/W0h

AWS source signal

0h - McASP0 AFSX Pin Input

1h - McASP1 AFSX Pin Input

2h - McASP2 AFSX Pin Input

3h - "0"

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - "0"

9h - "0"

Ah - "0"

Bh - "0"

Ch - McASP0 AFSX Pin Input

Dh - McASP1 AFSX Pin Input

Eh - McASP2 AFSX Pin Input

Fh - "0"

10h - "0"

11h - "0"

12h - "0"

13h - "0"

14h - "0"

15h - "0"

16h - "0"

17h - "0"

18h - AUDIO_EXT_REFCLK0 Pin input

19h - AUDIO_EXT_REFCLK1 Pin input

1Ah - "0"

1Bh - "0"

1Ch - "0"

1Dh - "0"

1.3.4.161 CTRLMMR_ATL_AWS2_SEL Register ( Offset = 82B8h) [reset = 0h]

CTRLMMR_ATL_AWS2_SEL is shown in Figure 5-495 and described in Table 5-1017.

Return to Summary Table.

Selects the source of ATL Audio Word Select 2.

Table 5-1016 CTRLMMR_ATL_AWS2_SEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82B8h
Figure 5-495 CTRLMMR_ATL_AWS2_SEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDWD_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1017 CTRLMMR_ATL_AWS2_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0WD_SELR/W0h

AWS source signal

0h - McASP0 AFSX Pin Input

1h - McASP1 AFSX Pin Input

2h - McASP2 AFSX Pin Input

3h - "0"

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - "0"

9h - "0"

Ah - "0"

Bh - "0"

Ch - McASP0 AFSX Pin Input

Dh - McASP1 AFSX Pin Input

Eh - McASP2 AFSX Pin Input

Fh - "0"

10h - "0"

11h - "0"

12h - "0"

13h - "0"

14h - "0"

15h - "0"

16h - "0"

17h - "0"

18h - AUDIO_EXT_REFCLK0 Pin input

19h - AUDIO_EXT_REFCLK1 Pin input

1Ah - "0"

1Bh - "0"

1Ch - "0"

1Dh - "0"

1.3.4.162 CTRLMMR_ATL_AWS3_SEL Register ( Offset = 82BCh) [reset = 0h]

CTRLMMR_ATL_AWS3_SEL is shown in Figure 5-496 and described in Table 5-1019.

Return to Summary Table.

Selects the source of ATL Audio Word Select 3.

Table 5-1018 CTRLMMR_ATL_AWS3_SEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82BCh
Figure 5-496 CTRLMMR_ATL_AWS3_SEL Register
313029282726252423222120191817161514131211109876543210
RESERVEDWD_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1019 CTRLMMR_ATL_AWS3_SEL Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h

Reserved

4-0WD_SELR/W0h

AWS source signal

0h - McASP0 AFSX Pin Input

1h - McASP1 AFSX Pin Input

2h - McASP2 AFSX Pin Input

3h - "0"

4h - "0"

5h - "0"

6h - "0"

7h - "0"

8h - "0"

9h - "0"

Ah - "0"

Bh - "0"

Ch - McASP0 AFSX Pin Input

Dh - McASP1 AFSX Pin Input

Eh - McASP2 AFSX Pin Input

Fh - "0"

10h - "0"

11h - "0"

12h - "0"

13h - "0"

14h - "0"

15h - "0"

16h - "0"

17h - "0"

18h - AUDIO_EXT_REFCLK0 Pin input

19h - AUDIO_EXT_REFCLK1 Pin input

1Ah - "0"

1Bh - "0"

1Ch - "0"

1Dh - "0"

1.3.4.163 CTRLMMR_ATL_CLKSEL Register ( Offset = 82C0h) [reset = 0h]

CTRLMMR_ATL_CLKSEL is shown in Figure 5-497 and described in Table 5-1021.

Return to Summary Table.

Selects the source of the ATL PCLK.

Table 5-1020 CTRLMMR_ATL_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82C0h
Figure 5-497 CTRLMMR_ATL_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1021 CTRLMMR_ATL_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h

Reserved

3-0PCLK_SELR/W0h

Selects the PCLK clock source

0h - MAIN_PLL4_HSDIV1_CLKOUT

1h - MAIN_PLL2_HSDIV2_CLKOUT

2h - "0"

3h - "0"

4h - MAIN_PLL0_HSDIV7_CLKOUT

5h - MCU_EXT_REFCLK0 (pin)

6h - EXT_REFCLK1 (pin)

7h - "0"

1.3.4.164 CTRLMMR_AUDIO_REFCLK0_CTRL Register ( Offset = 82E0h) [reset = 1Fh]

CTRLMMR_AUDIO_REFCLK0_CTRL is shown in Figure 5-498 and described in Table 5-1023.

Return to Summary Table.

Selects the clock source for the AUDIO_EXT_REFCLK0 output.

Table 5-1022 CTRLMMR_AUDIO_REFCLK0_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82E0h
Figure 5-498 CTRLMMR_AUDIO_REFCLK0_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
CLKOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-1Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1023 CTRLMMR_AUDIO_REFCLK0_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved

15CLKOUT_ENR/W0h

AUDIO_REFCLK 0 output enable
This bit is inverted to drive the active low output buffer enable
0h - AUDIO_EXT_REFCLK0 pin is configured as an input
1h - AUDIO_EXT_REFCLK0 pin is configured as an output

14-5RESERVEDR0h

Reserved

4-0CLK_SELR/W1Fh

Clock source

0h - MCASP0 AHCLKR Output

1h - MCASP1 AHCLKR Output

2h - MCASP2 AHCLKR Output

3h - Reserved

4h - Reserved

5h - Reserved

6h - Reserved

7h - Reserved

8h - Reserved

9h - Reserved

Ah - Reserved

Bh - Reserved

Ch - MCASP0 AHCLKX Output

Dh - MCASP1 AHCLKX Output

Eh - MCASP2 AHCLKX Output

Fh - Reserved

10h - Reserved

11h - Reserved

12h - Reserved

13h - Reserved

14h - Reserved

15h - Reserved

16h - Reserved

17h - Reserved

18h - ATCLK0

19h - ATCLK1

1Ah - ATCLK2

1Bh - ATCLK3

1Ch - MAIN_PLL4_HSDIV2_CLKOUT

1Dh - "0"

1Eh - "0"

1Fh - "0"

1.3.4.165 CTRLMMR_AUDIO_REFCLK1_CTRL Register ( Offset = 82E4h) [reset = 1Fh]

CTRLMMR_AUDIO_REFCLK1_CTRL is shown in Figure 5-499 and described in Table 5-1025.

Return to Summary Table.

Selects the clock source for the AUDIO_EXT_REFCLK1 output.

Table 5-1024 CTRLMMR_AUDIO_REFCLK1_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 82E4h
Figure 5-499 CTRLMMR_AUDIO_REFCLK1_CTRL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
CLKOUT_ENRESERVED
R/W-0hR-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-1Fh
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1025 CTRLMMR_AUDIO_REFCLK1_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h

Reserved

15CLKOUT_ENR/W0h

AUDIO_REFCLK 1 output enable
This bit is inverted to drive the active low output buffer enable
0h - AUDIO_EXT_REFCLK1 pin is configured as an input
1h - AUDIO_EXT_REFCLK1 pin is configured as an output

14-5RESERVEDR0h

Reserved

4-0CLK_SELR/W1Fh

Clock source

0h - MCASP0 AHCLKR Output

1h - MCASP1 AHCLKR Output

2h - MCASP2 AHCLKR Output

3h - Reserved

4h - Reserved

5h - Reserved

6h - Reserved

7h - Reserved

8h - Reserved

9h - Reserved

Ah - Reserved

Bh - Reserved

Ch - MCASP0 AHCLKX Output

Dh - MCASP1 AHCLKX Output

Eh - MCASP2 AHCLKX Output

Fh - Reserved

10h - Reserved

11h - Reserved

12h - Reserved

13h - Reserved

14h - Reserved

15h - Reserved

16h - Reserved

17h - Reserved

18h - ATCLK0

19h - ATCLK1

1Ah - ATCLK2

1Bh - ATCLK3

1Ch - MAIN_PLL4_HSDIV2_CLKOUT

1Dh - "0"

1Eh - "0"

1Fh - "0"

1.3.4.166 CTRLMMR_WWD0_CLKSEL Register ( Offset = 8380h) [reset = 0h]

CTRLMMR_WWD0_CLKSEL is shown in Figure 5-500 and described in Table 5-1027.

Return to Summary Table.

ARM MPU Core 0 Windowed watchdog timer functional clock selection control.

Table 5-1026 CTRLMMR_WWD0_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8380h
Figure 5-500 CTRLMMR_WWD0_CLKSEL Register
3130292827262524
WRTLOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1027 CTRLMMR_WWD0_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31WRTLOCKR/W0h

When set, locks CTRLMMR_WWD0_CLKSEL from further writes until the next module reset.

30-3RESERVEDR0h

Reserved

2-0CLK_SELR/W0h

Windowed watchdog timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - LFXOSC_CLKOUT

2h - CLK_12M_RC

3h - CLK_32K

4h - HFOSC1_CLKOUT

5h - reserved (HFOSC1_CLKOUT)

6h - reserved (HFOSC1_CLKOUT)

7h - reserved (HFOSC1_CLKOUT)

1.3.4.167 CTRLMMR_WWD1_CLKSEL Register ( Offset = 8384h) [reset = 0h]

CTRLMMR_WWD1_CLKSEL is shown in Figure 5-501 and described in Table 5-1029.

Return to Summary Table.

ARM MPU Core 1 Windowed watchdog timer functional clock selection control.

Table 5-1028 CTRLMMR_WWD1_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8384h
Figure 5-501 CTRLMMR_WWD1_CLKSEL Register
3130292827262524
WRTLOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1029 CTRLMMR_WWD1_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31WRTLOCKR/W0h

When set, locks CTRLMMR_WWD1_CLKSEL from further writes until the next module reset.

30-3RESERVEDR0h

Reserved

2-0CLK_SELR/W0h

Windowed watchdog timer functional clock input select mux control

0h - HFOSC0_CLKOUT

1h - LFXOSC_CLKOUT

2h - CLK_12M_RC

3h - CLK_32K

4h - HFOSC1_CLKOUT

5h - reserved (HFOSC1_CLKOUT)

6h - reserved (HFOSC1_CLKOUT)

7h - reserved (HFOSC1_CLKOUT)

1.3.4.168 CTRLMMR_WWD28_CLKSEL Register ( Offset = 83F0h) [reset = 0h]

CTRLMMR_WWD28_CLKSEL is shown in Figure 5-502 and described in Table 5-1031.

Return to Summary Table.

Main R5 Core 0 Windowed watchdog timer functional clock selection control.

Table 5-1030 CTRLMMR_WWD28_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 83F0h
Figure 5-502 CTRLMMR_WWD28_CLKSEL Register
3130292827262524
WRTLOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1031 CTRLMMR_WWD28_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31WRTLOCKR/W0h

When set, locks CTRLMMR_WWD28_CLKSEL from further writes until the next module reset.

30-3RESERVEDR0h

Reserved

2-0CLK_SELR/W0h

Windowed watchdog timer functional clock input select mux control
These bits are warm reset isolated to preserve R5 RTI clock selection.

0h - HFOSC0_CLKOUT

1h - LFXOSC_CLKOUT

2h - CLK_12M_RC

3h - CLK_32K

4h - HFOSC1_CLKOUT

5h - reserved (HFOSC1_CLKOUT)

6h - reserved (HFOSC1_CLKOUT)

7h - reserved (HFOSC1_CLKOUT)

1.3.4.169 CTRLMMR_WWD29_CLKSEL Register ( Offset = 83F4h) [reset = 0h]

CTRLMMR_WWD29_CLKSEL is shown in Figure 5-503 and described in Table 5-1033.

Return to Summary Table.

Main R5 Core 1 Windowed watchdog timer functional clock selection control.

Table 5-1032 CTRLMMR_WWD29_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 83F4h
Figure 5-503 CTRLMMR_WWD29_CLKSEL Register
3130292827262524
WRTLOCKRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1033 CTRLMMR_WWD29_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31WRTLOCKR/W0h

When set, locks CTRLMMR_WWD29_CLKSEL from further writes until the next module reset.

30-3RESERVEDR0h

Reserved

2-0CLK_SELR/W0h

Windowed watchdog timer functional clock input select mux control
These bits are warm reset isolated to preserve R5 RTI clock selection.

0h - HFOSC0_CLKOUT

1h - LFXOSC_CLKOUT

2h - CLK_12M_RC

3h - CLK_32K

4h - HFOSC1_CLKOUT

5h - reserved (HFOSC1_CLKOUT)

6h - reserved (HFOSC1_CLKOUT)

7h - reserved (HFOSC1_CLKOUT)

1.3.4.170 CTRLMMR_SERDES0_CLKSEL Register ( Offset = 8400h) [reset = 0h]

CTRLMMR_SERDES0_CLKSEL is shown in Figure 5-504 and described in Table 5-1035.

Return to Summary Table.

Selects the clock source for Serdes0.

Table 5-1034 CTRLMMR_SERDES0_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8400h
Figure 5-504 CTRLMMR_SERDES0_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCORE_REFCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1035 CTRLMMR_SERDES0_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CORE_REFCLK_SELR/W0h

Selects the source for the core_refclk input

0h - HFOSC0_CLKOUT

1h - HFOSC1_CLKOUT

2h - MAIN_PLL3_HSDIV4_CLKOUT

3h - MAIN_PLL2_HSDIV4_CLKOUT

1.3.4.171 CTRLMMR_MCAN0_CLKSEL Register ( Offset = 8480h) [reset = 0h]

CTRLMMR_MCAN0_CLKSEL is shown in Figure 5-505 and described in Table 5-1037.

Return to Summary Table.

Controls the functional clock source MCAN0.

Table 5-1036 CTRLMMR_MCAN0_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8480h
Figure 5-505 CTRLMMR_MCAN0_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1037 CTRLMMR_MCAN0_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.172 CTRLMMR_MCAN1_CLKSEL Register ( Offset = 8484h) [reset = 0h]

CTRLMMR_MCAN1_CLKSEL is shown in Figure 5-506 and described in Table 5-1039.

Return to Summary Table.

Controls the functional clock source MCAN1.

Table 5-1038 CTRLMMR_MCAN1_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8484h
Figure 5-506 CTRLMMR_MCAN1_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1039 CTRLMMR_MCAN1_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.173 CTRLMMR_MCAN2_CLKSEL Register ( Offset = 8488h) [reset = 0h]

CTRLMMR_MCAN2_CLKSEL is shown in Figure 5-507 and described in Table 5-1041.

Return to Summary Table.

Controls the functional clock source MCAN2.

Table 5-1040 CTRLMMR_MCAN2_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8488h
Figure 5-507 CTRLMMR_MCAN2_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1041 CTRLMMR_MCAN2_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.174 CTRLMMR_MCAN3_CLKSEL Register ( Offset = 848Ch) [reset = 0h]

CTRLMMR_MCAN3_CLKSEL is shown in Figure 5-508 and described in Table 5-1043.

Return to Summary Table.

Controls the functional clock source MCAN3.

Table 5-1042 CTRLMMR_MCAN3_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 848Ch
Figure 5-508 CTRLMMR_MCAN3_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1043 CTRLMMR_MCAN3_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.175 CTRLMMR_MCAN4_CLKSEL Register ( Offset = 8490h) [reset = 0h]

CTRLMMR_MCAN4_CLKSEL is shown in Figure 5-509 and described in Table 5-1045.

Return to Summary Table.

Controls the functional clock source MCAN4.

Table 5-1044 CTRLMMR_MCAN4_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8490h
Figure 5-509 CTRLMMR_MCAN4_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1045 CTRLMMR_MCAN4_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.176 CTRLMMR_MCAN5_CLKSEL Register ( Offset = 8494h) [reset = 0h]

CTRLMMR_MCAN5_CLKSEL is shown in Figure 5-510 and described in Table 5-1047.

Return to Summary Table.

Controls the functional clock source MCAN5.

Table 5-1046 CTRLMMR_MCAN5_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8494h
Figure 5-510 CTRLMMR_MCAN5_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1047 CTRLMMR_MCAN5_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.177 CTRLMMR_MCAN6_CLKSEL Register ( Offset = 8498h) [reset = 0h]

CTRLMMR_MCAN6_CLKSEL is shown in Figure 5-511 and described in Table 5-1049.

Return to Summary Table.

Controls the functional clock source MCAN6.

Table 5-1048 CTRLMMR_MCAN6_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 8498h
Figure 5-511 CTRLMMR_MCAN6_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1049 CTRLMMR_MCAN6_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.178 CTRLMMR_MCAN7_CLKSEL Register ( Offset = 849Ch) [reset = 0h]

CTRLMMR_MCAN7_CLKSEL is shown in Figure 5-512 and described in Table 5-1051.

Return to Summary Table.

Controls the functional clock source MCAN7.

Table 5-1050 CTRLMMR_MCAN7_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 849Ch
Figure 5-512 CTRLMMR_MCAN7_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1051 CTRLMMR_MCAN7_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.179 CTRLMMR_MCAN8_CLKSEL Register ( Offset = 84A0h) [reset = 0h]

CTRLMMR_MCAN8_CLKSEL is shown in Figure 5-513 and described in Table 5-1053.

Return to Summary Table.

Controls the functional clock source MCAN8.

Table 5-1052 CTRLMMR_MCAN8_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 84A0h
Figure 5-513 CTRLMMR_MCAN8_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1053 CTRLMMR_MCAN8_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.180 CTRLMMR_MCAN9_CLKSEL Register ( Offset = 84A4h) [reset = 0h]

CTRLMMR_MCAN9_CLKSEL is shown in Figure 5-514 and described in Table 5-1055.

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Controls the functional clock source MCAN9.

Table 5-1054 CTRLMMR_MCAN9_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 84A4h
Figure 5-514 CTRLMMR_MCAN9_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1055 CTRLMMR_MCAN9_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.181 CTRLMMR_MCAN10_CLKSEL Register ( Offset = 84A8h) [reset = 0h]

CTRLMMR_MCAN10_CLKSEL is shown in Figure 5-515 and described in Table 5-1057.

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Controls the functional clock source MCAN10.

Table 5-1056 CTRLMMR_MCAN10_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 84A8h
Figure 5-515 CTRLMMR_MCAN10_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1057 CTRLMMR_MCAN10_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.182 CTRLMMR_MCAN11_CLKSEL Register ( Offset = 84ACh) [reset = 0h]

CTRLMMR_MCAN11_CLKSEL is shown in Figure 5-516 and described in Table 5-1059.

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Controls the functional clock source MCAN11.

Table 5-1058 CTRLMMR_MCAN11_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 84ACh
Figure 5-516 CTRLMMR_MCAN11_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1059 CTRLMMR_MCAN11_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.183 CTRLMMR_MCAN12_CLKSEL Register ( Offset = 84B0h) [reset = 0h]

CTRLMMR_MCAN12_CLKSEL is shown in Figure 5-517 and described in Table 5-1061.

Return to Summary Table.

Controls the functional clock source MCAN12.

Table 5-1060 CTRLMMR_MCAN12_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 84B0h
Figure 5-517 CTRLMMR_MCAN12_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1061 CTRLMMR_MCAN12_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.184 CTRLMMR_MCAN13_CLKSEL Register ( Offset = 84B4h) [reset = 0h]

CTRLMMR_MCAN13_CLKSEL is shown in Figure 5-518 and described in Table 5-1063.

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Controls the functional clock source MCAN13.

Table 5-1062 CTRLMMR_MCAN13_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 84B4h
Figure 5-518 CTRLMMR_MCAN13_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1063 CTRLMMR_MCAN13_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.185 CTRLMMR_MCAN14_CLKSEL Register ( Offset = 84B8h) [reset = 0h]

CTRLMMR_MCAN14_CLKSEL is shown in Figure 5-519 and described in Table 5-1065.

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Controls the functional clock source MCAN14.

Table 5-1064 CTRLMMR_MCAN14_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 84B8h
Figure 5-519 CTRLMMR_MCAN14_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1065 CTRLMMR_MCAN14_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.186 CTRLMMR_MCAN15_CLKSEL Register ( Offset = 84BCh) [reset = 0h]

CTRLMMR_MCAN15_CLKSEL is shown in Figure 5-520 and described in Table 5-1067.

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Controls the functional clock source MCAN15.

Table 5-1066 CTRLMMR_MCAN15_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 84BCh
Figure 5-520 CTRLMMR_MCAN15_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1067 CTRLMMR_MCAN15_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.187 CTRLMMR_MCAN16_CLKSEL Register ( Offset = 84C0h) [reset = 0h]

CTRLMMR_MCAN16_CLKSEL is shown in Figure 5-521 and described in Table 5-1069.

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Controls the functional clock source MCAN16.

Table 5-1068 CTRLMMR_MCAN16_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 84C0h
Figure 5-521 CTRLMMR_MCAN16_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1069 CTRLMMR_MCAN16_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.188 CTRLMMR_MCAN17_CLKSEL Register ( Offset = 84C4h) [reset = 0h]

CTRLMMR_MCAN17_CLKSEL is shown in Figure 5-522 and described in Table 5-1071.

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Controls the functional clock source MCAN17.

Table 5-1070 CTRLMMR_MCAN17_CLKSEL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 84C4h
Figure 5-522 CTRLMMR_MCAN17_CLKSEL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCLK_SEL
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1071 CTRLMMR_MCAN17_CLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h

Reserved

1-0CLK_SELR/W0h

MAIN MCAN_CLK selection
0h - MAIN_PLL0_HSDIV4_CLKOUT
1h - MCU_EXT_REFCLK0 (pin)
2h - HFOSC1_CLKOUT
3h - HFOSC0_CLKOUT

1.3.4.189 CTRLMMR_LOCK2_KICK0 Register ( Offset = 9008h) [reset = 0h]

CTRLMMR_LOCK2_KICK0 is shown in Figure 5-523 and described in Table 5-1073.

Return to Summary Table.

Lower 32-bits of Partition2 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK2_KICK1 with its key value before write-protected Partition 2 registers can be written.

Table 5-1072 CTRLMMR_LOCK2_KICK0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 9008h
Figure 5-523 CTRLMMR_LOCK2_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1073 CTRLMMR_LOCK2_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition2 registers

0UNLOCKEDR0h

Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.3.4.190 CTRLMMR_LOCK2_KICK1 Register ( Offset = 900Ch) [reset = 0h]

CTRLMMR_LOCK2_KICK1 is shown in Figure 5-524 and described in Table 5-1075.

Return to Summary Table.

Upper 32-bits of Partition 2 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK2_KICK0 with its key value before write-protected Partition 2 registers can be written.

Table 5-1074 CTRLMMR_LOCK2_KICK1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 900Ch
Figure 5-524 CTRLMMR_LOCK2_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-1075 CTRLMMR_LOCK2_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition2 registers

1.3.4.191 CTRLMMR_MCU0_LBIST_CTRL Register ( Offset = C000h) [reset = 0h]

CTRLMMR_MCU0_LBIST_CTRL is shown in Figure 5-525 and described in Table 5-1077.

Return to Summary Table.

Configures and enables LBIST operation.

Table 5-1076 CTRLMMR_MCU0_LBIST_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C000h
Figure 5-525 CTRLMMR_MCU0_LBIST_CTRL Register
3130292827262524
BIST_RESETRESERVEDBIST_RUN
R/W-0hR-0hR/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RUNBIST_MODERESERVEDDC_DEF
R/W-0hR-0hR/W-0h
76543210
LOAD_DIVRESERVEDDIVIDE_RATIO
R/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1077 CTRLMMR_MCU0_LBIST_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31BIST_RESETR/W0h

Reset LBIST macro

30-28RESERVEDR0h

Reserved

27-24BIST_RUNR/W0h

Starts LBIST if all bits are 1

23-16RESERVEDR0h

Reserved

15-12RUNBIST_MODER/W0h

Runbist mode enable if all bits are 1

11-10RESERVEDR0h

Reserved

9-8DC_DEFR/W0h

Clock delay after scan_enable switching

7LOAD_DIVR/W0h

Loads LBIST clock divide ratio on transition from 0 to 1

6-5RESERVEDR0h

Reserved

4-0DIVIDE_RATIOR/W0h

LBIST clock divide ratio

1.3.4.192 CTRLMMR_MCU0_LBIST_PATCOUNT Register ( Offset = C004h) [reset = 0h]

CTRLMMR_MCU0_LBIST_PATCOUNT is shown in Figure 5-526 and described in Table 5-1079.

Return to Summary Table.

Specifies the number of LBIST patterns to run.

Table 5-1078 CTRLMMR_MCU0_LBIST_PATCOUNT Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C004h
Figure 5-526 CTRLMMR_MCU0_LBIST_PATCOUNT Register
3130292827262524
RESERVEDSTATIC_PC_DEF
R-0hR/W-0h
2322212019181716
STATIC_PC_DEF
R/W-0h
15141312111098
RESERVEDSET_PC_DEF
R-0hR/W-0h
76543210
RESET_PC_DEFSCAN_PC_DEF
R/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1079 CTRLMMR_MCU0_LBIST_PATCOUNT Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h

Reserved

29-16STATIC_PC_DEFR/W0h

Number of stuck-at patterns to run

15-12RESERVEDR0h

Reserved

11-8SET_PC_DEFR/W0h

Number of set patterns to run

7-4RESET_PC_DEFR/W0h

Number of reset patterns to run

3-0SCAN_PC_DEFR/W0h

Number of chain test patterns to run

1.3.4.193 CTRLMMR_MCU0_LBIST_SEED0 Register ( Offset = C008h) [reset = 0h]

CTRLMMR_MCU0_LBIST_SEED0 is shown in Figure 5-527 and described in Table 5-1081.

Return to Summary Table.

Specifies the 32 LSBs of the PRPG seed.

Table 5-1080 CTRLMMR_MCU0_LBIST_SEED0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C008h
Figure 5-527 CTRLMMR_MCU0_LBIST_SEED0 Register
313029282726252423222120191817161514131211109876543210
PRPG_DEF
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-1081 CTRLMMR_MCU0_LBIST_SEED0 Register Field Descriptions
BitFieldTypeResetDescription
31-0PRPG_DEFR/W0h

Initial seed for PRPG (bits 31:0)

1.3.4.194 CTRLMMR_MCU0_LBIST_SEED1 Register ( Offset = C00Ch) [reset = 0h]

CTRLMMR_MCU0_LBIST_SEED1 is shown in Figure 5-528 and described in Table 5-1083.

Return to Summary Table.

Specifies the 21 MSBs of the PRPG seed.

Table 5-1082 CTRLMMR_MCU0_LBIST_SEED1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C00Ch
Figure 5-528 CTRLMMR_MCU0_LBIST_SEED1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPRPG_DEF
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1083 CTRLMMR_MCU0_LBIST_SEED1 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h

Reserved

20-0PRPG_DEFR/W0h

Initial seed for PRPG (bits 52:32)

1.3.4.195 CTRLMMR_MCU0_LBIST_SPARE0 Register ( Offset = C010h) [reset = 0h]

CTRLMMR_MCU0_LBIST_SPARE0 is shown in Figure 5-529 and described in Table 5-1085.

Return to Summary Table.

Spare LBIST control bits.

Table 5-1084 CTRLMMR_MCU0_LBIST_SPARE0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C010h
Figure 5-529 CTRLMMR_MCU0_LBIST_SPARE0 Register
3130292827262524
SPARE0
R/W-0h
2322212019181716
SPARE0
R/W-0h
15141312111098
SPARE0
R/W-0h
76543210
SPARE0PBIST_SELFTEST_ENLBIST_SELFTEST_EN
R/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-1085 CTRLMMR_MCU0_LBIST_SPARE0 Register Field Descriptions
BitFieldTypeResetDescription
31-2SPARE0R/W0h

LBIST spare bits

1PBIST_SELFTEST_ENR/W0h

PBIST isolation control

0LBIST_SELFTEST_ENR/W0h

LBIST isolation control

1.3.4.196 CTRLMMR_MCU0_LBIST_SPARE1 Register ( Offset = C014h) [reset = 0h]

CTRLMMR_MCU0_LBIST_SPARE1 is shown in Figure 5-530 and described in Table 5-1087.

Return to Summary Table.

Spare LBIST control bits.

Table 5-1086 CTRLMMR_MCU0_LBIST_SPARE1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C014h
Figure 5-530 CTRLMMR_MCU0_LBIST_SPARE1 Register
313029282726252423222120191817161514131211109876543210
SPARE1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-1087 CTRLMMR_MCU0_LBIST_SPARE1 Register Field Descriptions
BitFieldTypeResetDescription
31-0SPARE1R/W0h

LBIST spare bits

1.3.4.197 CTRLMMR_MCU0_LBIST_STAT Register ( Offset = C018h) [reset = X]

CTRLMMR_MCU0_LBIST_STAT is shown in Figure 5-531 and described in Table 5-1089.

Return to Summary Table.

Indicates LBIST status and provides MISR selection control.

Table 5-1088 CTRLMMR_MCU0_LBIST_STAT Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C018h
Figure 5-531 CTRLMMR_MCU0_LBIST_STAT Register
3130292827262524
BIST_DONERESERVED
R-XR-0h
2322212019181716
RESERVED
R-0h
15141312111098
BIST_RUNNINGRESERVEDOUT_MUX_CTL
R-XR-0hR/W-0h
76543210
MISR_MUX_CTL
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1089 CTRLMMR_MCU0_LBIST_STAT Register Field Descriptions
BitFieldTypeResetDescription
31BIST_DONERX

LBIST is done

30-16RESERVEDR0h

Reserved

15BIST_RUNNINGRX

LBIST is running

14-10RESERVEDR0h

Reserved

9-8OUT_MUX_CTLR/W0h

Selects source of LBIST output
0h - LBIST IP CTRLMMR_PID value
1h - LBIST CTRL ID value
1x - MISR value

7-0MISR_MUX_CTLR/W0h

Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR.

1.3.4.198 CTRLMMR_MCU0_LBIST_MISR Register ( Offset = C01Ch) [reset = X]

CTRLMMR_MCU0_LBIST_MISR is shown in Figure 5-532 and described in Table 5-1091.

Return to Summary Table.

Contains LBIST MISR output value.

Table 5-1090 CTRLMMR_MCU0_LBIST_MISR Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C01Ch
Figure 5-532 CTRLMMR_MCU0_LBIST_MISR Register
313029282726252423222120191817161514131211109876543210
MISR_RESULT
R-X
LEGEND: R = Read Only; -n = value after reset
Table 5-1091 CTRLMMR_MCU0_LBIST_MISR Register Field Descriptions
BitFieldTypeResetDescription
31-0MISR_RESULTRX

32-bits of MISR value selected by misr_mux_ctl

1.3.4.199 CTRLMMR_MPU0_LBIST_CTRL Register ( Offset = C100h) [reset = 0h]

CTRLMMR_MPU0_LBIST_CTRL is shown in Figure 5-533 and described in Table 5-1093.

Return to Summary Table.

Configures and enables LBIST operation.

Table 5-1092 CTRLMMR_MPU0_LBIST_CTRL Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C100h
Figure 5-533 CTRLMMR_MPU0_LBIST_CTRL Register
3130292827262524
BIST_RESETRESERVEDBIST_RUN
R/W-0hR-0hR/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RUNBIST_MODERESERVEDDC_DEF
R/W-0hR-0hR/W-0h
76543210
LOAD_DIVRESERVEDDIVIDE_RATIO
R/W-0hR-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1093 CTRLMMR_MPU0_LBIST_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31BIST_RESETR/W0h

Reset LBIST macro

30-28RESERVEDR0h

Reserved

27-24BIST_RUNR/W0h

Starts LBIST if all bits are 1

23-16RESERVEDR0h

Reserved

15-12RUNBIST_MODER/W0h

Runbist mode enable if all bits are 1

11-10RESERVEDR0h

Reserved

9-8DC_DEFR/W0h

Clock delay after scan_enable switching

7LOAD_DIVR/W0h

Loads LBIST clock divide ratio on transition from 0 to 1

6-5RESERVEDR0h

Reserved

4-0DIVIDE_RATIOR/W0h

LBIST clock divide ratio

1.3.4.200 CTRLMMR_MPU0_LBIST_PATCOUNT Register ( Offset = C104h) [reset = 0h]

CTRLMMR_MPU0_LBIST_PATCOUNT is shown in Figure 5-534 and described in Table 5-1095.

Return to Summary Table.

Specifies the number of LBIST patterns to run.

Table 5-1094 CTRLMMR_MPU0_LBIST_PATCOUNT Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C104h
Figure 5-534 CTRLMMR_MPU0_LBIST_PATCOUNT Register
3130292827262524
RESERVEDSTATIC_PC_DEF
R-0hR/W-0h
2322212019181716
STATIC_PC_DEF
R/W-0h
15141312111098
RESERVEDSET_PC_DEF
R-0hR/W-0h
76543210
RESET_PC_DEFSCAN_PC_DEF
R/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1095 CTRLMMR_MPU0_LBIST_PATCOUNT Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h

Reserved

29-16STATIC_PC_DEFR/W0h

Number of stuck-at patterns to run

15-12RESERVEDR0h

Reserved

11-8SET_PC_DEFR/W0h

Number of set patterns to run

7-4RESET_PC_DEFR/W0h

Number of reset patterns to run

3-0SCAN_PC_DEFR/W0h

Number of chain test patterns to run

1.3.4.201 CTRLMMR_MPU0_LBIST_SEED0 Register ( Offset = C108h) [reset = 0h]

CTRLMMR_MPU0_LBIST_SEED0 is shown in Figure 5-535 and described in Table 5-1097.

Return to Summary Table.

Specifies the 32 LSBs of the PRPG seed.

Table 5-1096 CTRLMMR_MPU0_LBIST_SEED0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C108h
Figure 5-535 CTRLMMR_MPU0_LBIST_SEED0 Register
313029282726252423222120191817161514131211109876543210
PRPG_DEF
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-1097 CTRLMMR_MPU0_LBIST_SEED0 Register Field Descriptions
BitFieldTypeResetDescription
31-0PRPG_DEFR/W0h

Initial seed for PRPG (bits 31:0)

1.3.4.202 CTRLMMR_MPU0_LBIST_SEED1 Register ( Offset = C10Ch) [reset = 0h]

CTRLMMR_MPU0_LBIST_SEED1 is shown in Figure 5-536 and described in Table 5-1099.

Return to Summary Table.

Specifies the 21 MSBs of the PRPG seed.

Table 5-1098 CTRLMMR_MPU0_LBIST_SEED1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C10Ch
Figure 5-536 CTRLMMR_MPU0_LBIST_SEED1 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPRPG_DEF
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1099 CTRLMMR_MPU0_LBIST_SEED1 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h

Reserved

20-0PRPG_DEFR/W0h

Initial seed for PRPG (bits 52:32)

1.3.4.203 CTRLMMR_MPU0_LBIST_SPARE0 Register ( Offset = C110h) [reset = 0h]

CTRLMMR_MPU0_LBIST_SPARE0 is shown in Figure 5-537 and described in Table 5-1101.

Return to Summary Table.

Spare LBIST control bits.

Table 5-1100 CTRLMMR_MPU0_LBIST_SPARE0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C110h
Figure 5-537 CTRLMMR_MPU0_LBIST_SPARE0 Register
3130292827262524
SPARE0
R/W-0h
2322212019181716
SPARE0
R/W-0h
15141312111098
SPARE0
R/W-0h
76543210
SPARE0PBIST_SELFTEST_ENLBIST_SELFTEST_EN
R/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-1101 CTRLMMR_MPU0_LBIST_SPARE0 Register Field Descriptions
BitFieldTypeResetDescription
31-2SPARE0R/W0h

LBIST spare bits

1PBIST_SELFTEST_ENR/W0h

PBIST isolation control

0LBIST_SELFTEST_ENR/W0h

LBIST isolation control

1.3.4.204 CTRLMMR_MPU0_LBIST_SPARE1 Register ( Offset = C114h) [reset = 0h]

CTRLMMR_MPU0_LBIST_SPARE1 is shown in Figure 5-538 and described in Table 5-1103.

Return to Summary Table.

Spare LBIST control bits.

Table 5-1102 CTRLMMR_MPU0_LBIST_SPARE1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C114h
Figure 5-538 CTRLMMR_MPU0_LBIST_SPARE1 Register
313029282726252423222120191817161514131211109876543210
SPARE1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-1103 CTRLMMR_MPU0_LBIST_SPARE1 Register Field Descriptions
BitFieldTypeResetDescription
31-0SPARE1R/W0h

LBIST spare bits

1.3.4.205 CTRLMMR_MPU0_LBIST_STAT Register ( Offset = C118h) [reset = X]

CTRLMMR_MPU0_LBIST_STAT is shown in Figure 5-539 and described in Table 5-1105.

Return to Summary Table.

Indicates LBIST status and provides MISR selection control.

Table 5-1104 CTRLMMR_MPU0_LBIST_STAT Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C118h
Figure 5-539 CTRLMMR_MPU0_LBIST_STAT Register
3130292827262524
BIST_DONERESERVED
R-XR-0h
2322212019181716
RESERVED
R-0h
15141312111098
BIST_RUNNINGRESERVEDOUT_MUX_CTL
R-XR-0hR/W-0h
76543210
MISR_MUX_CTL
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1105 CTRLMMR_MPU0_LBIST_STAT Register Field Descriptions
BitFieldTypeResetDescription
31BIST_DONERX

LBIST is done

30-16RESERVEDR0h

Reserved

15BIST_RUNNINGRX

LBIST is running

14-10RESERVEDR0h

Reserved

9-8OUT_MUX_CTLR/W0h

Selects source of LBIST output
0h - LBIST IP CTRLMMR_PID value
1h - LBIST CTRL ID value
1x - MISR value

7-0MISR_MUX_CTLR/W0h

Selects block of 32 MISR bits to read. A value of 0 selects a compacted 32-bit version of the full MISR. A value of 1-32 select a 32-bit segment of the MISR.

1.3.4.206 CTRLMMR_MPU0_LBIST_MISR Register ( Offset = C11Ch) [reset = X]

CTRLMMR_MPU0_LBIST_MISR is shown in Figure 5-540 and described in Table 5-1107.

Return to Summary Table.

Contains LBIST MISR output value.

Table 5-1106 CTRLMMR_MPU0_LBIST_MISR Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C11Ch
Figure 5-540 CTRLMMR_MPU0_LBIST_MISR Register
313029282726252423222120191817161514131211109876543210
MISR_RESULT
R-X
LEGEND: R = Read Only; -n = value after reset
Table 5-1107 CTRLMMR_MPU0_LBIST_MISR Register Field Descriptions
BitFieldTypeResetDescription
31-0MISR_RESULTRX

32-bits of MISR value selected by misr_mux_ctl

1.3.4.207 CTRLMMR_MCU0_LBIST_SIG Register ( Offset = C280h) [reset = X]

CTRLMMR_MCU0_LBIST_SIG is shown in Figure 5-541 and described in Table 5-1109.

Return to Summary Table.

Contains expected MISR output value.

Table 5-1108 CTRLMMR_MCU0_LBIST_SIG Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C280h
Figure 5-541 CTRLMMR_MCU0_LBIST_SIG Register
313029282726252423222120191817161514131211109876543210
MISR_SIG
R-X
LEGEND: R = Read Only; -n = value after reset
Table 5-1109 CTRLMMR_MCU0_LBIST_SIG Register Field Descriptions
BitFieldTypeResetDescription
31-0MISR_SIGRX

MISR signature

1.3.4.208 CTRLMMR_MPU0_LBIST_SIG Register ( Offset = C2A0h) [reset = X]

CTRLMMR_MPU0_LBIST_SIG is shown in Figure 5-542 and described in Table 5-1111.

Return to Summary Table.

Contains expected MISR output value.

Table 5-1110 CTRLMMR_MPU0_LBIST_SIG Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C2A0h
Figure 5-542 CTRLMMR_MPU0_LBIST_SIG Register
313029282726252423222120191817161514131211109876543210
MISR_SIG
R-X
LEGEND: R = Read Only; -n = value after reset
Table 5-1111 CTRLMMR_MPU0_LBIST_SIG Register Field Descriptions
BitFieldTypeResetDescription
31-0MISR_SIGRX

MISR signature

1.3.4.209 CTRLMMR_FUSE_CRC_STAT Register ( Offset = C320h) [reset = X]

CTRLMMR_FUSE_CRC_STAT is shown in Figure 5-543 and described in Table 5-1113.

Return to Summary Table.

Indicates status of fuse chain CRC.

Table 5-1112 CTRLMMR_FUSE_CRC_STAT Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 C320h
Figure 5-543 CTRLMMR_FUSE_CRC_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CRC_ERR_7CRC_ERR_6CRC_ERR_5CRC_ERR_4CRC_ERR_3CRC_ERR_2CRC_ERR_1RESERVED
R-XR-XR-XR-XR-XR-XR-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 5-1113 CTRLMMR_FUSE_CRC_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved

7CRC_ERR_7RX

Indicates eFuse CRC error on chain 7

6CRC_ERR_6RX

Indicates eFuse CRC error on chain 6

5CRC_ERR_5RX

Indicates eFuse CRC error on chain 5

4CRC_ERR_4RX

Indicates eFuse CRC error on chain 4

3CRC_ERR_3RX

Indicates eFuse CRC error on chain 3

2CRC_ERR_2RX

Indicates eFuse CRC error on chain 2

1CRC_ERR_1RX

Indicates eFuse CRC error on chain 1

0RESERVEDR0h

Reserved

1.3.4.210 CTRLMMR_LOCK3_KICK0 Register ( Offset = D008h) [reset = 0h]

CTRLMMR_LOCK3_KICK0 is shown in Figure 5-544 and described in Table 5-1115.

Return to Summary Table.

Lower 32-bits of Partition3 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK3_KICK1 with its key value before write-protected Partition 3 registers can be written.

Table 5-1114 CTRLMMR_LOCK3_KICK0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 D008h
Figure 5-544 CTRLMMR_LOCK3_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1115 CTRLMMR_LOCK3_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition3 registers

0UNLOCKEDR0h

Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.3.4.211 CTRLMMR_LOCK3_KICK1 Register ( Offset = D00Ch) [reset = 0h]

CTRLMMR_LOCK3_KICK1 is shown in Figure 5-545 and described in Table 5-1117.

Return to Summary Table.

Upper 32-bits of Partition 3 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK3_KICK0 with its key value before write-protected Partition 3 registers can be written.

Table 5-1116 CTRLMMR_LOCK3_KICK1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00010 D00Ch
Figure 5-545 CTRLMMR_LOCK3_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-1117 CTRLMMR_LOCK3_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition3 registers

1.3.4.212 CTRLMMR_CHNG_DDR4_FSP_REQ Register ( Offset = 14000h) [reset = 0h]

CTRLMMR_CHNG_DDR4_FSP_REQ is shown in Figure 5-546 and described in Table 5-1119.

Return to Summary Table.

This register is used to initiate a LPDDR4 frequency set point change to the DDR Controller.

Table 5-1118 CTRLMMR_CHNG_DDR4_FSP_REQ Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 4000h
Figure 5-546 CTRLMMR_CHNG_DDR4_FSP_REQ Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDREQ
R-0hR/W-0h
76543210
RESERVEDREQ_TYPE
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1119 CTRLMMR_CHNG_DDR4_FSP_REQ Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h

Reserved

8REQR/W0h

Initiate FSP frequency change

7-2RESERVEDR0h

Reserved

1-0REQ_TYPER/W0h

Frequency request type.
Frequency request type which indicates which DDR4 frequency to select in the set point table in the SDRAM

1.3.4.213 CTRLMMR_CHNG_DDR4_FSP_ACK Register ( Offset = 14004h) [reset = X]

CTRLMMR_CHNG_DDR4_FSP_ACK is shown in Figure 5-547 and described in Table 5-1121.

Return to Summary Table.

This register is used by the DDR Controller to acknowledge the LPDDR4 frequency set point shange request.

Table 5-1120 CTRLMMR_CHNG_DDR4_FSP_ACK Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 4004h
Figure 5-547 CTRLMMR_CHNG_DDR4_FSP_ACK Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
ACKRESERVEDERROR
R-XR-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-1121 CTRLMMR_CHNG_DDR4_FSP_ACK Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved

7ACKRX

Frequency change acknowledge.
This bit is only valid when CHNG_DDR4_FSP_REQ_req = 1
Indication from the DDR Controller that the FSP change operation is complete
0h - FSP change operation in progress
1h - FSP change operation complete

6-1RESERVEDR0h

Reserved

0ERRORRX

Frequency change error
This bit is only valid when CHNG_DDR4_FSP_REQ_req = 1
0h - FSP change was sucessful
1h - FSP change was not sucessful

1.3.4.214 CTRLMMR_DDR4_FSP_CLKCHNG_REQ Register ( Offset = 14080h) [reset = X]

CTRLMMR_DDR4_FSP_CLKCHNG_REQ is shown in Figure 5-548 and described in Table 5-1123.

Return to Summary Table.

This register is used by the DDR Controller to request the DDR PLL clock frequency change. This can occur as part of DDR4 initialization and training or in response to a LPDDR4 FSP change request.

Table 5-1122 CTRLMMR_DDR4_FSP_CLKCHNG_REQ Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 4080h
Figure 5-548 CTRLMMR_DDR4_FSP_CLKCHNG_REQ Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
REQRESERVEDREQ_TYPE
R-XR-0hR-X
LEGEND: R = Read Only; -n = value after reset
Table 5-1123 CTRLMMR_DDR4_FSP_CLKCHNG_REQ Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h

Reserved

7REQRX

DDR Controller FSP clock change request
Indicates that the DDR controller needs the DDR clock changed to the frequency indicated by the req_type field. This bit is cleared when the DDR4_FSP_CLKCHNG_ACK_ack bit is set.

6-2RESERVEDR0h

Reserved

1-0REQ_TYPERX

Frequency request type
Indicates which LPDDR4 FSP (frequency set point) to which the DDR Controller wants the DDR clock set

1.3.4.215 CTRLMMR_DDR4_FSP_CLKCHNG_ACK Register ( Offset = 140C0h) [reset = 0h]

CTRLMMR_DDR4_FSP_CLKCHNG_ACK is shown in Figure 5-549 and described in Table 5-1125.

Return to Summary Table.

This register is used to acknowledge a DDR PLL clock frequency change to the DDR Controller.

Table 5-1124 CTRLMMR_DDR4_FSP_CLKCHNG_ACK Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 40C0h
Figure 5-549 CTRLMMR_DDR4_FSP_CLKCHNG_ACK Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDACK
R-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1125 CTRLMMR_DDR4_FSP_CLKCHNG_ACK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h

Reserved

0ACKR/W0h

DDR FSP clock change ackowledge
This bit should be set once the DDR clock has been sucessfully changed to the value requested by DDR4_FSP_CLKCHNG_REQ_req_type. Setting this bit will clear the DDR4_FSP_CLKCHNG_REQ_req bit and the associated change request interrupt.

1.3.4.216 CTRLMMR_LOCK5_KICK0 Register ( Offset = 15008h) [reset = 0h]

CTRLMMR_LOCK5_KICK0 is shown in Figure 5-550 and described in Table 5-1127.

Return to Summary Table.

Lower 32-bits of Partition5 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK5_KICK1 with its key value before write-protected Partition 5 registers can be written.

Table 5-1126 CTRLMMR_LOCK5_KICK0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 5008h
Figure 5-550 CTRLMMR_LOCK5_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1127 CTRLMMR_LOCK5_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition5 registers

0UNLOCKEDR0h

Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.3.4.217 CTRLMMR_LOCK5_KICK1 Register ( Offset = 1500Ch) [reset = 0h]

CTRLMMR_LOCK5_KICK1 is shown in Figure 5-551 and described in Table 5-1129.

Return to Summary Table.

Upper 32-bits of Partition 5 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK5_KICK0 with its key value before write-protected Partition 5 registers can be written.

Table 5-1128 CTRLMMR_LOCK5_KICK1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 500Ch
Figure 5-551 CTRLMMR_LOCK5_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-1129 CTRLMMR_LOCK5_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition5 registers

1.3.4.218 CTRLMMR_PADCONFIG0 Register ( Offset = 1C000h) [reset = 4007h]

CTRLMMR_PADCONFIG0 is shown in Figure 5-552 and described in Table 5-1131.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1130 CTRLMMR_PADCONFIG0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C000h
Figure 5-552 CTRLMMR_PADCONFIG0 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENRESERVEDDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVERESERVED
R/W-0hR/W-0hR/W-0hR-0hR/W-0hR-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1131 CTRLMMR_PADCONFIG0 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28-27RESERVEDR0h

Reserved

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17-16RESERVEDR0h

Reserved

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.219 CTRLMMR_PADCONFIG1 Register ( Offset = 1C004h) [reset = 8214007h]

CTRLMMR_PADCONFIG1 is shown in Figure 5-553 and described in Table 5-1133.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1132 CTRLMMR_PADCONFIG1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C004h
Figure 5-553 CTRLMMR_PADCONFIG1 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1133 CTRLMMR_PADCONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.220 CTRLMMR_PADCONFIG2 Register ( Offset = 1C008h) [reset = 8214007h]

CTRLMMR_PADCONFIG2 is shown in Figure 5-554 and described in Table 5-1135.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1134 CTRLMMR_PADCONFIG2 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C008h
Figure 5-554 CTRLMMR_PADCONFIG2 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1135 CTRLMMR_PADCONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.221 CTRLMMR_PADCONFIG3 Register ( Offset = 1C00Ch) [reset = 8214007h]

CTRLMMR_PADCONFIG3 is shown in Figure 5-555 and described in Table 5-1137.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1136 CTRLMMR_PADCONFIG3 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C00Ch
Figure 5-555 CTRLMMR_PADCONFIG3 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1137 CTRLMMR_PADCONFIG3 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.222 CTRLMMR_PADCONFIG4 Register ( Offset = 1C010h) [reset = 8214007h]

CTRLMMR_PADCONFIG4 is shown in Figure 5-556 and described in Table 5-1139.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1138 CTRLMMR_PADCONFIG4 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C010h
Figure 5-556 CTRLMMR_PADCONFIG4 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1139 CTRLMMR_PADCONFIG4 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.223 CTRLMMR_PADCONFIG5 Register ( Offset = 1C014h) [reset = 8214007h]

CTRLMMR_PADCONFIG5 is shown in Figure 5-557 and described in Table 5-1141.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1140 CTRLMMR_PADCONFIG5 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C014h
Figure 5-557 CTRLMMR_PADCONFIG5 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1141 CTRLMMR_PADCONFIG5 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.224 CTRLMMR_PADCONFIG6 Register ( Offset = 1C018h) [reset = 8214007h]

CTRLMMR_PADCONFIG6 is shown in Figure 5-558 and described in Table 5-1143.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1142 CTRLMMR_PADCONFIG6 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C018h
Figure 5-558 CTRLMMR_PADCONFIG6 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1143 CTRLMMR_PADCONFIG6 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.225 CTRLMMR_PADCONFIG7 Register ( Offset = 1C01Ch) [reset = 8214007h]

CTRLMMR_PADCONFIG7 is shown in Figure 5-559 and described in Table 5-1145.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1144 CTRLMMR_PADCONFIG7 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C01Ch
Figure 5-559 CTRLMMR_PADCONFIG7 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1145 CTRLMMR_PADCONFIG7 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.226 CTRLMMR_PADCONFIG8 Register ( Offset = 1C020h) [reset = 8214007h]

CTRLMMR_PADCONFIG8 is shown in Figure 5-560 and described in Table 5-1147.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1146 CTRLMMR_PADCONFIG8 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C020h
Figure 5-560 CTRLMMR_PADCONFIG8 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1147 CTRLMMR_PADCONFIG8 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.227 CTRLMMR_PADCONFIG9 Register ( Offset = 1C024h) [reset = 8214007h]

CTRLMMR_PADCONFIG9 is shown in Figure 5-561 and described in Table 5-1149.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1148 CTRLMMR_PADCONFIG9 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C024h
Figure 5-561 CTRLMMR_PADCONFIG9 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1149 CTRLMMR_PADCONFIG9 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.228 CTRLMMR_PADCONFIG10 Register ( Offset = 1C028h) [reset = 8214007h]

CTRLMMR_PADCONFIG10 is shown in Figure 5-562 and described in Table 5-1151.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1150 CTRLMMR_PADCONFIG10 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C028h
Figure 5-562 CTRLMMR_PADCONFIG10 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1151 CTRLMMR_PADCONFIG10 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.229 CTRLMMR_PADCONFIG11 Register ( Offset = 1C02Ch) [reset = 8214007h]

CTRLMMR_PADCONFIG11 is shown in Figure 5-563 and described in Table 5-1153.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1152 CTRLMMR_PADCONFIG11 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C02Ch
Figure 5-563 CTRLMMR_PADCONFIG11 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1153 CTRLMMR_PADCONFIG11 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.230 CTRLMMR_PADCONFIG12 Register ( Offset = 1C030h) [reset = 8214007h]

CTRLMMR_PADCONFIG12 is shown in Figure 5-564 and described in Table 5-1155.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1154 CTRLMMR_PADCONFIG12 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C030h
Figure 5-564 CTRLMMR_PADCONFIG12 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1155 CTRLMMR_PADCONFIG12 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.231 CTRLMMR_PADCONFIG13 Register ( Offset = 1C034h) [reset = 8214007h]

CTRLMMR_PADCONFIG13 is shown in Figure 5-565 and described in Table 5-1157.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1156 CTRLMMR_PADCONFIG13 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C034h
Figure 5-565 CTRLMMR_PADCONFIG13 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1157 CTRLMMR_PADCONFIG13 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.232 CTRLMMR_PADCONFIG14 Register ( Offset = 1C038h) [reset = 8214007h]

CTRLMMR_PADCONFIG14 is shown in Figure 5-566 and described in Table 5-1159.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1158 CTRLMMR_PADCONFIG14 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C038h
Figure 5-566 CTRLMMR_PADCONFIG14 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1159 CTRLMMR_PADCONFIG14 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.233 CTRLMMR_PADCONFIG15 Register ( Offset = 1C03Ch) [reset = 8214007h]

CTRLMMR_PADCONFIG15 is shown in Figure 5-567 and described in Table 5-1161.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1160 CTRLMMR_PADCONFIG15 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C03Ch
Figure 5-567 CTRLMMR_PADCONFIG15 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1161 CTRLMMR_PADCONFIG15 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.234 CTRLMMR_PADCONFIG16 Register ( Offset = 1C040h) [reset = 8214007h]

CTRLMMR_PADCONFIG16 is shown in Figure 5-568 and described in Table 5-1163.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1162 CTRLMMR_PADCONFIG16 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C040h
Figure 5-568 CTRLMMR_PADCONFIG16 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1163 CTRLMMR_PADCONFIG16 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.235 CTRLMMR_PADCONFIG17 Register ( Offset = 1C044h) [reset = 8214007h]

CTRLMMR_PADCONFIG17 is shown in Figure 5-569 and described in Table 5-1165.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1164 CTRLMMR_PADCONFIG17 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C044h
Figure 5-569 CTRLMMR_PADCONFIG17 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1165 CTRLMMR_PADCONFIG17 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.236 CTRLMMR_PADCONFIG18 Register ( Offset = 1C048h) [reset = 8214007h]

CTRLMMR_PADCONFIG18 is shown in Figure 5-570 and described in Table 5-1167.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1166 CTRLMMR_PADCONFIG18 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C048h
Figure 5-570 CTRLMMR_PADCONFIG18 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1167 CTRLMMR_PADCONFIG18 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.237 CTRLMMR_PADCONFIG19 Register ( Offset = 1C04Ch) [reset = 8214007h]

CTRLMMR_PADCONFIG19 is shown in Figure 5-571 and described in Table 5-1169.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1168 CTRLMMR_PADCONFIG19 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C04Ch
Figure 5-571 CTRLMMR_PADCONFIG19 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1169 CTRLMMR_PADCONFIG19 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.238 CTRLMMR_PADCONFIG20 Register ( Offset = 1C050h) [reset = 8214007h]

CTRLMMR_PADCONFIG20 is shown in Figure 5-572 and described in Table 5-1171.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1170 CTRLMMR_PADCONFIG20 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C050h
Figure 5-572 CTRLMMR_PADCONFIG20 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1171 CTRLMMR_PADCONFIG20 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.239 CTRLMMR_PADCONFIG21 Register ( Offset = 1C054h) [reset = 8214007h]

CTRLMMR_PADCONFIG21 is shown in Figure 5-573 and described in Table 5-1173.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1172 CTRLMMR_PADCONFIG21 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C054h
Figure 5-573 CTRLMMR_PADCONFIG21 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1173 CTRLMMR_PADCONFIG21 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.240 CTRLMMR_PADCONFIG22 Register ( Offset = 1C058h) [reset = 8214007h]

CTRLMMR_PADCONFIG22 is shown in Figure 5-574 and described in Table 5-1175.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1174 CTRLMMR_PADCONFIG22 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C058h
Figure 5-574 CTRLMMR_PADCONFIG22 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1175 CTRLMMR_PADCONFIG22 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.241 CTRLMMR_PADCONFIG23 Register ( Offset = 1C05Ch) [reset = 8214007h]

CTRLMMR_PADCONFIG23 is shown in Figure 5-575 and described in Table 5-1177.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1176 CTRLMMR_PADCONFIG23 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C05Ch
Figure 5-575 CTRLMMR_PADCONFIG23 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1177 CTRLMMR_PADCONFIG23 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.242 CTRLMMR_PADCONFIG24 Register ( Offset = 1C060h) [reset = 8214007h]

CTRLMMR_PADCONFIG24 is shown in Figure 5-576 and described in Table 5-1179.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1178 CTRLMMR_PADCONFIG24 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C060h
Figure 5-576 CTRLMMR_PADCONFIG24 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1179 CTRLMMR_PADCONFIG24 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.243 CTRLMMR_PADCONFIG25 Register ( Offset = 1C064h) [reset = 8214007h]

CTRLMMR_PADCONFIG25 is shown in Figure 5-577 and described in Table 5-1181.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1180 CTRLMMR_PADCONFIG25 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C064h
Figure 5-577 CTRLMMR_PADCONFIG25 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1181 CTRLMMR_PADCONFIG25 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.244 CTRLMMR_PADCONFIG26 Register ( Offset = 1C068h) [reset = 8214007h]

CTRLMMR_PADCONFIG26 is shown in Figure 5-578 and described in Table 5-1183.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1182 CTRLMMR_PADCONFIG26 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C068h
Figure 5-578 CTRLMMR_PADCONFIG26 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1183 CTRLMMR_PADCONFIG26 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.245 CTRLMMR_PADCONFIG27 Register ( Offset = 1C06Ch) [reset = 8214007h]

CTRLMMR_PADCONFIG27 is shown in Figure 5-579 and described in Table 5-1185.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1184 CTRLMMR_PADCONFIG27 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C06Ch
Figure 5-579 CTRLMMR_PADCONFIG27 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1185 CTRLMMR_PADCONFIG27 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.246 CTRLMMR_PADCONFIG28 Register ( Offset = 1C070h) [reset = 8214007h]

CTRLMMR_PADCONFIG28 is shown in Figure 5-580 and described in Table 5-1187.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1186 CTRLMMR_PADCONFIG28 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C070h
Figure 5-580 CTRLMMR_PADCONFIG28 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1187 CTRLMMR_PADCONFIG28 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.247 CTRLMMR_PADCONFIG29 Register ( Offset = 1C074h) [reset = 8214007h]

CTRLMMR_PADCONFIG29 is shown in Figure 5-581 and described in Table 5-1189.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1188 CTRLMMR_PADCONFIG29 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C074h
Figure 5-581 CTRLMMR_PADCONFIG29 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1189 CTRLMMR_PADCONFIG29 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.248 CTRLMMR_PADCONFIG30 Register ( Offset = 1C078h) [reset = 8214007h]

CTRLMMR_PADCONFIG30 is shown in Figure 5-582 and described in Table 5-1191.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1190 CTRLMMR_PADCONFIG30 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C078h
Figure 5-582 CTRLMMR_PADCONFIG30 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1191 CTRLMMR_PADCONFIG30 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.249 CTRLMMR_PADCONFIG31 Register ( Offset = 1C07Ch) [reset = 8214007h]

CTRLMMR_PADCONFIG31 is shown in Figure 5-583 and described in Table 5-1193.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1192 CTRLMMR_PADCONFIG31 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C07Ch
Figure 5-583 CTRLMMR_PADCONFIG31 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1193 CTRLMMR_PADCONFIG31 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.250 CTRLMMR_PADCONFIG32 Register ( Offset = 1C080h) [reset = 8214007h]

CTRLMMR_PADCONFIG32 is shown in Figure 5-584 and described in Table 5-1195.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1194 CTRLMMR_PADCONFIG32 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C080h
Figure 5-584 CTRLMMR_PADCONFIG32 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1195 CTRLMMR_PADCONFIG32 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.251 CTRLMMR_PADCONFIG33 Register ( Offset = 1C084h) [reset = 8214007h]

CTRLMMR_PADCONFIG33 is shown in Figure 5-585 and described in Table 5-1197.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1196 CTRLMMR_PADCONFIG33 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C084h
Figure 5-585 CTRLMMR_PADCONFIG33 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1197 CTRLMMR_PADCONFIG33 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.252 CTRLMMR_PADCONFIG34 Register ( Offset = 1C088h) [reset = 8214007h]

CTRLMMR_PADCONFIG34 is shown in Figure 5-586 and described in Table 5-1199.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1198 CTRLMMR_PADCONFIG34 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C088h
Figure 5-586 CTRLMMR_PADCONFIG34 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1199 CTRLMMR_PADCONFIG34 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.253 CTRLMMR_PADCONFIG35 Register ( Offset = 1C08Ch) [reset = 8214007h]

CTRLMMR_PADCONFIG35 is shown in Figure 5-587 and described in Table 5-1201.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1200 CTRLMMR_PADCONFIG35 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C08Ch
Figure 5-587 CTRLMMR_PADCONFIG35 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1201 CTRLMMR_PADCONFIG35 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.254 CTRLMMR_PADCONFIG36 Register ( Offset = 1C090h) [reset = 8214007h]

CTRLMMR_PADCONFIG36 is shown in Figure 5-588 and described in Table 5-1203.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1202 CTRLMMR_PADCONFIG36 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C090h
Figure 5-588 CTRLMMR_PADCONFIG36 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1203 CTRLMMR_PADCONFIG36 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.255 CTRLMMR_PADCONFIG37 Register ( Offset = 1C094h) [reset = 8214007h]

CTRLMMR_PADCONFIG37 is shown in Figure 5-589 and described in Table 5-1205.

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Register to control pin configuration and muxing.

Table 5-1204 CTRLMMR_PADCONFIG37 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C094h
Figure 5-589 CTRLMMR_PADCONFIG37 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1205 CTRLMMR_PADCONFIG37 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.256 CTRLMMR_PADCONFIG38 Register ( Offset = 1C098h) [reset = 8214007h]

CTRLMMR_PADCONFIG38 is shown in Figure 5-590 and described in Table 5-1207.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1206 CTRLMMR_PADCONFIG38 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C098h
Figure 5-590 CTRLMMR_PADCONFIG38 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1207 CTRLMMR_PADCONFIG38 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.257 CTRLMMR_PADCONFIG39 Register ( Offset = 1C09Ch) [reset = 8214007h]

CTRLMMR_PADCONFIG39 is shown in Figure 5-591 and described in Table 5-1209.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1208 CTRLMMR_PADCONFIG39 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C09Ch
Figure 5-591 CTRLMMR_PADCONFIG39 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1209 CTRLMMR_PADCONFIG39 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.258 CTRLMMR_PADCONFIG40 Register ( Offset = 1C0A0h) [reset = 8214007h]

CTRLMMR_PADCONFIG40 is shown in Figure 5-592 and described in Table 5-1211.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1210 CTRLMMR_PADCONFIG40 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0A0h
Figure 5-592 CTRLMMR_PADCONFIG40 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1211 CTRLMMR_PADCONFIG40 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.259 CTRLMMR_PADCONFIG41 Register ( Offset = 1C0A4h) [reset = 8214007h]

CTRLMMR_PADCONFIG41 is shown in Figure 5-593 and described in Table 5-1213.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1212 CTRLMMR_PADCONFIG41 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0A4h
Figure 5-593 CTRLMMR_PADCONFIG41 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1213 CTRLMMR_PADCONFIG41 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.260 CTRLMMR_PADCONFIG42 Register ( Offset = 1C0A8h) [reset = 8214007h]

CTRLMMR_PADCONFIG42 is shown in Figure 5-594 and described in Table 5-1215.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1214 CTRLMMR_PADCONFIG42 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0A8h
Figure 5-594 CTRLMMR_PADCONFIG42 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1215 CTRLMMR_PADCONFIG42 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.261 CTRLMMR_PADCONFIG43 Register ( Offset = 1C0ACh) [reset = 8054007h]

CTRLMMR_PADCONFIG43 is shown in Figure 5-595 and described in Table 5-1217.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1216 CTRLMMR_PADCONFIG43 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0ACh
Figure 5-595 CTRLMMR_PADCONFIG43 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1217 CTRLMMR_PADCONFIG43 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.262 CTRLMMR_PADCONFIG44 Register ( Offset = 1C0B0h) [reset = 8214007h]

CTRLMMR_PADCONFIG44 is shown in Figure 5-596 and described in Table 5-1219.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1218 CTRLMMR_PADCONFIG44 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0B0h
Figure 5-596 CTRLMMR_PADCONFIG44 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1219 CTRLMMR_PADCONFIG44 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.263 CTRLMMR_PADCONFIG45 Register ( Offset = 1C0B4h) [reset = 8214007h]

CTRLMMR_PADCONFIG45 is shown in Figure 5-597 and described in Table 5-1221.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1220 CTRLMMR_PADCONFIG45 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0B4h
Figure 5-597 CTRLMMR_PADCONFIG45 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1221 CTRLMMR_PADCONFIG45 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.264 CTRLMMR_PADCONFIG46 Register ( Offset = 1C0B8h) [reset = 8214007h]

CTRLMMR_PADCONFIG46 is shown in Figure 5-598 and described in Table 5-1223.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1222 CTRLMMR_PADCONFIG46 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0B8h
Figure 5-598 CTRLMMR_PADCONFIG46 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1223 CTRLMMR_PADCONFIG46 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.265 CTRLMMR_PADCONFIG47 Register ( Offset = 1C0BCh) [reset = 8214007h]

CTRLMMR_PADCONFIG47 is shown in Figure 5-599 and described in Table 5-1225.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1224 CTRLMMR_PADCONFIG47 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0BCh
Figure 5-599 CTRLMMR_PADCONFIG47 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1225 CTRLMMR_PADCONFIG47 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.266 CTRLMMR_PADCONFIG48 Register ( Offset = 1C0C0h) [reset = 8214007h]

CTRLMMR_PADCONFIG48 is shown in Figure 5-600 and described in Table 5-1227.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1226 CTRLMMR_PADCONFIG48 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0C0h
Figure 5-600 CTRLMMR_PADCONFIG48 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1227 CTRLMMR_PADCONFIG48 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.267 CTRLMMR_PADCONFIG49 Register ( Offset = 1C0C4h) [reset = 8214007h]

CTRLMMR_PADCONFIG49 is shown in Figure 5-601 and described in Table 5-1229.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1228 CTRLMMR_PADCONFIG49 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0C4h
Figure 5-601 CTRLMMR_PADCONFIG49 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1229 CTRLMMR_PADCONFIG49 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.268 CTRLMMR_PADCONFIG50 Register ( Offset = 1C0C8h) [reset = 8214007h]

CTRLMMR_PADCONFIG50 is shown in Figure 5-602 and described in Table 5-1231.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1230 CTRLMMR_PADCONFIG50 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0C8h
Figure 5-602 CTRLMMR_PADCONFIG50 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1231 CTRLMMR_PADCONFIG50 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.269 CTRLMMR_PADCONFIG51 Register ( Offset = 1C0CCh) [reset = 8214007h]

CTRLMMR_PADCONFIG51 is shown in Figure 5-603 and described in Table 5-1233.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1232 CTRLMMR_PADCONFIG51 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0CCh
Figure 5-603 CTRLMMR_PADCONFIG51 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1233 CTRLMMR_PADCONFIG51 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.270 CTRLMMR_PADCONFIG52 Register ( Offset = 1C0D0h) [reset = 8214007h]

CTRLMMR_PADCONFIG52 is shown in Figure 5-604 and described in Table 5-1235.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1234 CTRLMMR_PADCONFIG52 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0D0h
Figure 5-604 CTRLMMR_PADCONFIG52 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1235 CTRLMMR_PADCONFIG52 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.271 CTRLMMR_PADCONFIG53 Register ( Offset = 1C0D4h) [reset = 44007h]

CTRLMMR_PADCONFIG53 is shown in Figure 5-605 and described in Table 5-1237.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1236 CTRLMMR_PADCONFIG53 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0D4h
Figure 5-605 CTRLMMR_PADCONFIG53 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENRESERVEDDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVERESERVED
R/W-0hR/W-0hR/W-0hR-0hR/W-1hR-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1237 CTRLMMR_PADCONFIG53 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28-27RESERVEDR0h

Reserved

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17-16RESERVEDR0h

Reserved

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.272 CTRLMMR_PADCONFIG54 Register ( Offset = 1C0D8h) [reset = 44007h]

CTRLMMR_PADCONFIG54 is shown in Figure 5-606 and described in Table 5-1239.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1238 CTRLMMR_PADCONFIG54 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0D8h
Figure 5-606 CTRLMMR_PADCONFIG54 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENRESERVEDDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVERESERVED
R/W-0hR/W-0hR/W-0hR-0hR/W-1hR-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1239 CTRLMMR_PADCONFIG54 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28-27RESERVEDR0h

Reserved

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17-16RESERVEDR0h

Reserved

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.273 CTRLMMR_PADCONFIG55 Register ( Offset = 1C0DCh) [reset = 8214007h]

CTRLMMR_PADCONFIG55 is shown in Figure 5-607 and described in Table 5-1241.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1240 CTRLMMR_PADCONFIG55 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0DCh
Figure 5-607 CTRLMMR_PADCONFIG55 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1241 CTRLMMR_PADCONFIG55 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.274 CTRLMMR_PADCONFIG56 Register ( Offset = 1C0E0h) [reset = 8214007h]

CTRLMMR_PADCONFIG56 is shown in Figure 5-608 and described in Table 5-1243.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1242 CTRLMMR_PADCONFIG56 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0E0h
Figure 5-608 CTRLMMR_PADCONFIG56 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1243 CTRLMMR_PADCONFIG56 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.275 CTRLMMR_PADCONFIG57 Register ( Offset = 1C0E4h) [reset = 8214007h]

CTRLMMR_PADCONFIG57 is shown in Figure 5-609 and described in Table 5-1245.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1244 CTRLMMR_PADCONFIG57 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0E4h
Figure 5-609 CTRLMMR_PADCONFIG57 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1245 CTRLMMR_PADCONFIG57 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.276 CTRLMMR_PADCONFIG58 Register ( Offset = 1C0E8h) [reset = 8214007h]

CTRLMMR_PADCONFIG58 is shown in Figure 5-610 and described in Table 5-1247.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1246 CTRLMMR_PADCONFIG58 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0E8h
Figure 5-610 CTRLMMR_PADCONFIG58 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1247 CTRLMMR_PADCONFIG58 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.277 CTRLMMR_PADCONFIG59 Register ( Offset = 1C0ECh) [reset = 8214007h]

CTRLMMR_PADCONFIG59 is shown in Figure 5-611 and described in Table 5-1249.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1248 CTRLMMR_PADCONFIG59 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0ECh
Figure 5-611 CTRLMMR_PADCONFIG59 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1249 CTRLMMR_PADCONFIG59 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.278 CTRLMMR_PADCONFIG60 Register ( Offset = 1C0F0h) [reset = 8214007h]

CTRLMMR_PADCONFIG60 is shown in Figure 5-612 and described in Table 5-1251.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1250 CTRLMMR_PADCONFIG60 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0F0h
Figure 5-612 CTRLMMR_PADCONFIG60 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1251 CTRLMMR_PADCONFIG60 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.279 CTRLMMR_PADCONFIG61 Register ( Offset = 1C0F4h) [reset = 8214007h]

CTRLMMR_PADCONFIG61 is shown in Figure 5-613 and described in Table 5-1253.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1252 CTRLMMR_PADCONFIG61 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0F4h
Figure 5-613 CTRLMMR_PADCONFIG61 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1253 CTRLMMR_PADCONFIG61 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.280 CTRLMMR_PADCONFIG62 Register ( Offset = 1C0F8h) [reset = 8214007h]

CTRLMMR_PADCONFIG62 is shown in Figure 5-614 and described in Table 5-1255.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1254 CTRLMMR_PADCONFIG62 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0F8h
Figure 5-614 CTRLMMR_PADCONFIG62 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1255 CTRLMMR_PADCONFIG62 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.281 CTRLMMR_PADCONFIG63 Register ( Offset = 1C0FCh) [reset = 8214000h]

CTRLMMR_PADCONFIG63 is shown in Figure 5-615 and described in Table 5-1257.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1256 CTRLMMR_PADCONFIG63 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C0FCh
Figure 5-615 CTRLMMR_PADCONFIG63 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1257 CTRLMMR_PADCONFIG63 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.282 CTRLMMR_PADCONFIG64 Register ( Offset = 1C100h) [reset = 8214007h]

CTRLMMR_PADCONFIG64 is shown in Figure 5-616 and described in Table 5-1259.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1258 CTRLMMR_PADCONFIG64 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C100h
Figure 5-616 CTRLMMR_PADCONFIG64 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1259 CTRLMMR_PADCONFIG64 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.283 CTRLMMR_PADCONFIG65 Register ( Offset = 1C104h) [reset = 8214007h]

CTRLMMR_PADCONFIG65 is shown in Figure 5-617 and described in Table 5-1261.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1260 CTRLMMR_PADCONFIG65 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C104h
Figure 5-617 CTRLMMR_PADCONFIG65 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISRESERVEDRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1261 CTRLMMR_PADCONFIG65 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19RESERVEDR0h

Reserved

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.284 CTRLMMR_PADCONFIG66 Register ( Offset = 1C108h) [reset = 8014000h]

CTRLMMR_PADCONFIG66 is shown in Figure 5-618 and described in Table 5-1263.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1262 CTRLMMR_PADCONFIG66 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C108h
Figure 5-618 CTRLMMR_PADCONFIG66 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1263 CTRLMMR_PADCONFIG66 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.285 CTRLMMR_PADCONFIG68 Register ( Offset = 1C110h) [reset = 44000h]

CTRLMMR_PADCONFIG68 is shown in Figure 5-619 and described in Table 5-1265.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1264 CTRLMMR_PADCONFIG68 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C110h
Figure 5-619 CTRLMMR_PADCONFIG68 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1265 CTRLMMR_PADCONFIG68 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W0h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.286 CTRLMMR_PADCONFIG71 Register ( Offset = 1C11Ch) [reset = 10264000h]

CTRLMMR_PADCONFIG71 is shown in Figure 5-620 and described in Table 5-1267.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1266 CTRLMMR_PADCONFIG71 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C11Ch
Figure 5-620 CTRLMMR_PADCONFIG71 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-1hR/W-1hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1267 CTRLMMR_PADCONFIG71 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W1h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W1h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W1h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W0h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.287 CTRLMMR_PADCONFIG72 Register ( Offset = 1C120h) [reset = 204007h]

CTRLMMR_PADCONFIG72 is shown in Figure 5-621 and described in Table 5-1269.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1268 CTRLMMR_PADCONFIG72 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C120h
Figure 5-621 CTRLMMR_PADCONFIG72 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1269 CTRLMMR_PADCONFIG72 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W0h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W0h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.288 CTRLMMR_PADCONFIG73 Register ( Offset = 1C124h) [reset = 8214007h]

CTRLMMR_PADCONFIG73 is shown in Figure 5-622 and described in Table 5-1271.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1270 CTRLMMR_PADCONFIG73 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C124h
Figure 5-622 CTRLMMR_PADCONFIG73 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1271 CTRLMMR_PADCONFIG73 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.289 CTRLMMR_PADCONFIG89 Register ( Offset = 1C164h) [reset = 8214007h]

CTRLMMR_PADCONFIG89 is shown in Figure 5-623 and described in Table 5-1273.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1272 CTRLMMR_PADCONFIG89 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C164h
Figure 5-623 CTRLMMR_PADCONFIG89 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1273 CTRLMMR_PADCONFIG89 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.290 CTRLMMR_PADCONFIG90 Register ( Offset = 1C168h) [reset = 8214007h]

CTRLMMR_PADCONFIG90 is shown in Figure 5-624 and described in Table 5-1275.

Return to Summary Table.

Register to control pin configuration and muxing.

Table 5-1274 CTRLMMR_PADCONFIG90 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 C168h
Figure 5-624 CTRLMMR_PADCONFIG90 Register
3130292827262524
LOCKWKUP_EVTWKUP_ENDS_PULLTYPE_SELDS_PULLUD_ENDSOUT_VALDSOUT_DISDS_EN
R/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0h
2322212019181716
ISO_BYPISO_OVRTX_DISDRV_STRRXACTIVEPULLTYPESELPULLUDEN
R/W-0hR/W-0hR/W-1hR/W-0hR/W-0hR/W-0hR/W-1h
15141312111098
FORCE_DS_ENST_ENDEBOUNCE_SELRESERVEDWK_LVL_POL
R/W-0hR/W-1hR/W-0hR-0hR/W-0h
76543210
WK_LVL_ENRESERVEDVGPIO_SELMUXMODE
R/W-0hR-0hR/W-0hR/W-7h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1275 CTRLMMR_PADCONFIG90 Register Field Descriptions
BitFieldTypeResetDescription
31LOCKR/W0h

Lock
0h - Padconfig register is unlocked
1h - Padconfig register is locked from further writes

30WKUP_EVTR0h

Wakeup event status
0h - No wake event on pin
1h - Wake event occurred on pin

29WKUP_ENR/W0h

Wakeup enable. Supported for CANUART IOs domain.
0h - Wakeup operation disabled
1h - Wakeup operation enabled

28DS_PULLTYPE_SELR/W0h

Deep Sleep pull-up/down selection
0h - Offmode pulldown selected
1h - Offmode pullup selected

27DS_PULLUD_ENR/W1h

Deep Sleep pull-up/down enable (active low)
0h - Pullup / pulldown is enabled
1h - Pullup / pulldown is disabled

26DSOUT_VALR/W0h

Deep Sleep output value
0h - Output value is 0
1h - Output value is 1

25DSOUT_DISR/W0h

Deep Sleep output disable
0h - Output enabled
1h - Output disabled

24DS_ENR/W0h

Deep Sleep override control
0h - IO keeps its previous state when Deep Sleep mode is active
1h - IO state is forced to OFF mode value when Deep Sleep mode is active

23ISO_BYPR/W0h

Isolation Bypass
0h - IO isolation is preserved
1h - IO isolation is bypassed

22ISO_OVRR/W0h

Isolation Override
0h - IO isolation is preserved
1h - IO isolation is overridden

21TX_DISR/W1h

Driver Disable
0h - Driver is enabled
1h - Driver is disabled

20-19DRV_STRR/W0h

Drive Strength Control . Selects the drive strength value for LVCMOS pins. (Does not apply to other pin types)

18RXACTIVER/W0h

Input enable for the Pad
0h - Receiver disabled
1h - Receiver enabled

17PULLTYPESELR/W0h

Pad Pullup / Pulldown type selection
0h - Pulldown selected
1h - Pullup selected

16PULLUDENR/W1h

Pad Pullup / Pulldown enable. This is an active low signal.
0h - Pullup / Pulldown enabled
1h - Pullup / Pulldown disabled

15FORCE_DS_ENR/W0h

Enable pad Deep Sleep controls by overriding DMSC gating
0h - Deep Sleep pad controls are gated by the DMSC
1h - Activate Deep Sleep pad controls (override DMSC gating logic)

14ST_ENR/W1h

Receiver Schmitt Trigger enable
0h - Schmitt trigger input disabled
1h - Schmitt trigger input enabled

13-11DEBOUNCE_SELR/W0h

Selects the debouce period for the pad.

10-9RESERVEDR0h

Reserved

8WK_LVL_POLR/W0h

Level Sensitive Wakeup Polarity
This bit is not relevant unless wk_lvl_en is set to 1h.
0h - Low. A low (0) value on the pin causes a wakeup
1h - High. A high (1) value on the pin causes a wakeup

7WK_LVL_ENR/W0h

Level Sensitive Wakeup Enable
0h - Disabled. Wakeup is triggered by change of the pin input value
1h - Enabled. Wakeup is triggered when the pin matches the value specified by wk_lvl_pol. The chosen polarity must be maintained. (e.g. until wakeup completion is confirmed)

6RESERVEDR0h

Reserved

5-4VGPIO_SELR/W0h

Virtual MAIN_GPIO instance select.
These bits select which instance of GPIO is used for this I/O pad. This allows protection between two different Processor virtual worlds. These bits have no effect if GPIO mode (muxmode=7) is not selected for the PAD.

0h - Implement GPIO in GPIO0 instance

1h - Implement GPIO in GPIO2 instance

2h - Implement GPIO in GPIO4 instance

3h - Implement GPIO in GPIO6 instance

3-0MUXMODER/W7h

Pad functional signal mux selection

0h - Mux Mode 0

1h - Mux Mode 1

2h - Mux Mode 2

3h - Mux Mode 3

4h - Mux Mode 4

5h - Mux Mode 5

6h - Mux Mode 6

7h - Mux Mode 7

8h - Mux Mode 8

9h - Mux Mode 9

Ah - Mux Mode 10

Bh - Mux Mode 11

Ch - Mux Mode 12

Dh - Mux Mode 13

Eh - Mux Mode 14

Fh - Mux Mode 15

1.3.4.291 CTRLMMR_LOCK7_KICK0 Register ( Offset = 1D008h) [reset = 0h]

CTRLMMR_LOCK7_KICK0 is shown in Figure 5-625 and described in Table 5-1277.

Return to Summary Table.

Lower 32-bits of Partition7 write lock key. This register must be written with the designated key value followed by a write to CTRLMMR_LOCK7_KICK1 with its key value before write-protected Partition 7 registers can be written.

Table 5-1276 CTRLMMR_LOCK7_KICK0 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 D008h
Figure 5-625 CTRLMMR_LOCK7_KICK0 Register
3130292827262524
KEY
R/W-0h
2322212019181716
KEY
R/W-0h
15141312111098
KEY
R/W-0h
76543210
KEYUNLOCKED
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 5-1277 CTRLMMR_LOCK7_KICK0 Register Field Descriptions
BitFieldTypeResetDescription
31-1KEYR/W0h

Write the kick0 unlock value followed by the kick1 unlock value to unlock the write-protected Partition7 registers

0UNLOCKEDR0h

Unlock status. When set indicates that the proper unlock sequence has been performed and the partition is unlocked for writing.

1.3.4.292 CTRLMMR_LOCK7_KICK1 Register ( Offset = 1D00Ch) [reset = 0h]

CTRLMMR_LOCK7_KICK1 is shown in Figure 5-626 and described in Table 5-1279.

Return to Summary Table.

Upper 32-bits of Partition 7 write lock key. This register must be written with the designated key value after a write to CTRLMMR_LOCK7_KICK0 with its key value before write-protected Partition 7 registers can be written.

Table 5-1278 CTRLMMR_LOCK7_KICK1 Instances
InstancePhysical Address
CTRL_MMR0_CFG00011 D00Ch
Figure 5-626 CTRLMMR_LOCK7_KICK1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 5-1279 CTRLMMR_LOCK7_KICK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Write the kick1 unlock value after the kick0 unlock value to unlock the write-protected Partition7 registers