SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Octal SPI flash memories support various protocols, and the OSPI boot mode of the device only supports a specific protocol defined below. Additionally, if the flash memory is complaint with JEDEC xSPI standards JESD251 and JESD216D, refer to Section 4.3.8. The OSPI protocol is described according to bit-width (1 or 8) and data rate (S or D for *S*ingle Data rate or *D*ouble Data rate) for the Command/Address/Data segments of the protocol. The OSPI boot mode supports 1S-1S-8S mode. The Command and Address issued are 8 bits and 24 bits, respectively. The Read Command issued for OSPI mode is 0x8b, followed by zero for address and 8 dummy cycles. The frequency of operation is 33 MHz.
The following boot mode pin configuration and corresponding pin usage and mux configuration are shown below. This is the OSPI boot mode.
Primary boot mode B must be set to 0 if MCU only is set to 0.
Table 4-15 shows configuration pins assignment to functions when boot mode is the Octal SPI.
BOOTMODE Pins | Field | Value | Description | MCU Only=1 Value |
---|---|---|---|---|
6 | Speed | 0 | 33 MHz using manual tap selection | 0 |
1 | Reserved | |||
5 | Iclk | 0 | Iclock source external | 0 |
1 | Iclock source internal | |||
4 | Csel | 0 | Boot Flash is on CS 0 | 0 |
1 | Boot Flash is on CS 1 |
Table 4-16 summarizes the OSPI pin configuration done by ROM code for OSPI boot device.
Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Tx En/Dis | Pinmux Sel |
---|---|---|---|---|---|---|---|
MCU_OSPI0_CLK0 | MCU_OSPI0_CLK | Disable | Up | 0 | Disable | Enable | 0 |
MCU_OSPI0_LBCLK0 | MCU_OSPI0_LBCLK0 | Disable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_DQS | MCU_OSPI0_DQS | Disable | Up | 0 | Enable | Disable | 0 |
MCU_OSPI0_D0 | MCU_OSPI0_D0 | Enable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_D1 | MCU_OSPI0_D1 | Enable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_D2 | MCU_OSPI0_D2 | Enable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_D3 | MCU_OSPI0_D3 | Enable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_D4 | MCU_OSPI0_D4 | Enable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_D5 | MCU_OSPI0_D5 | Enable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_D6 | MCU_OSPI0_D6 | Enable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_D7 | MCU_OSPI0_D7 | Enable | Up | 0 | Enable | Enable | 0 |
MCU_OSPI0_CSn0 | MCU_OSPI0_CSn0 | Enable | Up | 0 | Disable | Enable | 0 |
MCU_OSPI0_CSn1 | MCU_OSPI0_CSn1 | Enable | Up | 0 | Disable | Enable | 0 |