SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5709 lists the memory-mapped registers for the NAVSS0_MCRC. All register offset addresses not listed in Table 12-5709 should be considered as reserved locations and the register contents should not be modified.
This is the MMR register region for the mcrc64_regs component
Instance | Base Address |
---|---|
NAVSS0_MCRC | 31F7 0000h |
MCU_NAVSS0_MCRC | 2A26 4000h |
Offset | Acronym | Register Name | NAVSS0_MCRC Physical Address | MCU_NAVSS0_MCRC Physical Address |
---|---|---|---|---|
0h | MCRC_CRC_CTRL0 | CRC Global Control Register 0 | 31F7 0000h | 2A26 4000h |
8h | MCRC_CRC_CTRL1 | CRC Global Control Register 1 | 31F7 0008h | 2A26 4008h |
10h | MCRC_CRC_CTRL2 | CRC Global Control Register 2 | 31F7 0010h | 2A26 4010h |
18h | MCRC_CRC_INTS | CRC Interrupt Enable Set Register | 31F7 0018h | 2A26 4018h |
20h | MCRC_CRC_INTR | CRC Interrupt Enable Reset Register | 31F7 0020h | 2A26 4020h |
28h | MCRC_CRC_STATUS | CRC Interrupt Status Register | 31F7 0028h | 2A26 4028h |
30h | MCRC_CRC_INT_OFFSET_REG | CRC Interrupt Offset | 31F7 0030h | 2A26 4030h |
38h | MCRC_CRC_BUSY | CRC Busy Register | 31F7 0038h | 2A26 4038h |
40h | MCRC_CRC_PCOUNT_REG1 | CRC Pattern Counter Preload Register1 | 31F7 0040h | 2A26 4040h |
44h | MCRC_CRC_SCOUNT_REG1 | CRC Sector Counter Preload Register1 | 31F7 0044h | 2A26 4044h |
48h | MCRC_CRC_CURSEC_REG1 | CRC Current Sector Register 1 | 31F7 0048h | 2A26 4048h |
4Ch | MCRC_CRC_WDTOPLD1 | CRC channel 1 Watchdog Timeout Preload Register A | 31F7 004Ch | 2A26 404Ch |
50h | MCRC_CRC_BCTOPLD1 | CRC channel 1 Block Complete Timeout Preload Register B | 31F7 0050h | 2A26 4050h |
60h | MCRC_PSA_SIGREGL1 | Channel 1 PSA signature low register | 31F7 0060h | 2A26 4060h |
64h | MCRC_PSA_SIGREGH1 | Channel 1 PSA signature high register | 31F7 0064h | 2A26 4064h |
68h | MCRC_CRC_REGL1 | Channel 1 CRC value low register | 31F7 0068h | 2A26 4068h |
6Ch | MCRC_CRC_REGH1 | Channel 1 CRC value high register | 31F7 006Ch | 2A26 406Ch |
70h | MCRC_PSA_SECSIGREGL1 | Channel 1 PSA sector signature low register | 31F7 0070h | 2A26 4070h |
74h | MCRC_PSA_SECSIGREGH1 | Channel 1 PSA sector signature high register | 31F7 0074h | 2A26 4074h |
78h | MCRC_RAW_DATAREGL1 | Channel 1 Raw Data Low Register | 31F7 0078h | 2A26 4078h |
7Ch | MCRC_RAW_DATAREGH1 | Channel 1 Raw Data High Register | 31F7 007Ch | 2A26 407Ch |
80h | MCRC_CRC_PCOUNT_REG2 | CRC Pattern Counter Preload Register2 | 31F7 0080h | 2A26 4080h |
84h | MCRC_CRC_SCOUNT_REG2 | CRC Sector Counter Preload Register2 | 31F7 0084h | 2A26 4084h |
88h | MCRC_CRC_CURSEC_REG2 | CRC Current Sector Register 2 | 31F7 0088h | 2A26 4088h |
8Ch | MCRC_CRC_WDTOPLD2 | CRC channel 2 Watchdog Timeout Preload Register | 31F7 008Ch | 2A26 408Ch |
90h | MCRC_CRC_BCTOPLD2 | CRC channel 2 Block Complete Timeout Preload Register | 31F7 0090h | 2A26 4090h |
A0h | MCRC_PSA_SIGREGL2 | Channel 2 PSA signature low register | 31F7 00A0h | 2A26 40A0h |
A4h | MCRC_PSA_SIGREGH2 | Channel 2 PSA signature high register | 31F7 00A4h | 2A26 40A4h |
A8h | MCRC_CRC_REGL2 | Channel 2 CRC value low register | 31F7 00A8h | 2A26 40A8h |
ACh | MCRC_CRC_REGH2 | Channel 2 CRC value high register | 31F7 00ACh | 2A26 40ACh |
B0h | MCRC_PSA_SECSIGREGL2 | Channel 2 PSA sector signature low register | 31F7 00B0h | 2A26 40B0h |
B4h | MCRC_PSA_SECSIGREGH2 | Channel 2 PSA sector signature high register | 31F7 00B4h | 2A26 40B4h |
B8h | MCRC_RAW_DATAREGL2 | Channel 2 Raw Data Low Register | 31F7 00B8h | 2A26 40B8h |
BCh | MCRC_RAW_DATAREGH2 | Channel 2 Raw Data High Register | 31F7 00BCh | 2A26 40BCh |
C0h | MCRC_CRC_PCOUNT_REG3 | CRC Pattern Counter Preload Register3 | 31F7 00C0h | 2A26 40C0h |
C4h | MCRC_CRC_SCOUNT_REG3 | CRC Sector Counter Preload Register3 | 31F7 00C4h | 2A26 40C4h |
C8h | MCRC_CRC_CURSEC_REG3 | CRC Current Sector Register 3 | 31F7 00C8h | 2A26 40C8h |
CCh | MCRC_CRC_WDTOPLD3 | CRC channel 3 Watchdog Timeout Preload Register | 31F7 00CCh | 2A26 40CCh |
D0h | MCRC_CRC_BCTOPLD3 | CRC channel 3 Block Complete Timeout Preload Register | 31F7 00D0h | 2A26 40D0h |
E0h | MCRC_PSA_SIGREGL3 | Channel 3 PSA signature low register | 31F7 00E0h | 2A26 40E0h |
E4h | MCRC_PSA_SIGREGH3 | Channel 3 PSA signature high register | 31F7 00E4h | 2A26 40E4h |
E8h | MCRC_CRC_REGL3 | Channel 3 CRC value low register | 31F7 00E8h | 2A26 40E8h |
ECh | MCRC_CRC_REGH3 | Channel 3 CRC value high register | 31F7 00ECh | 2A26 40ECh |
F0h | MCRC_PSA_SECSIGREGL3 | Channel 3 PSA sector signature low register | 31F7 00F0h | 2A26 40F0h |
F4h | MCRC_PSA_SECSIGREGH3 | Channel 3 PSA sector signature high register | 31F7 00F4h | 2A26 40F4h |
F8h | MCRC_RAW_DATAREGL3 | Channel 3 Raw Data Low Register | 31F7 00F8h | 2A26 40F8h |
FCh | MCRC_RAW_DATAREGH3 | Channel 3 Raw Data High Register | 31F7 00FCh | 2A26 40FCh |
100h | MCRC_CRC_PCOUNT_REG4 | CRC Pattern Counter Preload Register4 | 31F7 0100h | 2A26 4100h |
104h | MCRC_CRC_SCOUNT_REG4 | CRC Sector Counter Preload Register4 | 31F7 0104h | 2A26 4104h |
108h | MCRC_CRC_CURSEC_REG4 | CRC Current Sector Register 4 | 31F7 0108h | 2A26 4108h |
10Ch | MCRC_CRC_WDTOPLD4 | CRC channel 4 Watchdog Timeout Preload Register | 31F7 010Ch | 2A26 410Ch |
110h | MCRC_CRC_BCTOPLD4 | CRC channel 4 Block Complete Timeout Preload Register | 31F7 0110h | 2A26 4110h |
120h | MCRC_PSA_SIGREGL4 | Channel 4 PSA signature low register | 31F7 0120h | 2A26 4120h |
124h | MCRC_PSA_SIGREGH4 | Channel 4 PSA signature high register | 31F7 0124h | 2A26 4124h |
128h | MCRC_CRC_REGL4 | Channel 4 CRC value low register | 31F7 0128h | 2A26 4128h |
12Ch | MCRC_CRC_REGH4 | Channel 4 CRC value high register | 31F7 012Ch | 2A26 412Ch |
130h | MCRC_PSA_SECSIGREGL4 | Channel 4 PSA sector signature low register | 31F7 0130h | 2A26 4130h |
134h | MCRC_PSA_SECSIGREGH4 | Channel 4 PSA sector signature high register | 31F7 0134h | 2A26 4134h |
138h | MCRC_RAW_DATAREGL4 | Channel 4 Raw Data Low Register | 31F7 0138h | 2A26 4138h |
13Ch | MCRC_RAW_DATAREGH4 | Channel 4 Raw Data High Register | 31F7 013Ch | 2A26 413Ch |
140h | MCRC_BUS_SEL | Data bus tracing selection | 31F7 0140h | 2A26 4140h |
200h + formula | MCRC_I0_PSA_SIGREG1_CPY_Y | Channel 1 PSA signature block region | 31F7 0200h + formula | 2A26 4200h + formula |
280h + formula | MCRC_I0_PSA_SIGREG2_CPY_Y | Channel 2 PSA signature block region | 31F7 0280h + formula | 2A26 4280h + formula |
300h + formula | MCRC_I0_PSA_SIGREG3_CPY_Y | Channel 3 PSA signature block region | 31F7 0300h + formula | 2A26 4300h + formula |
380h + formula | MCRC_I0_PSA_SIGREG4_CPY_Y | Channel 4 PSA signature block region | 31F7 0380h + formula | 2A26 4380h + formula |
MCRC_CRC_CTRL0 is shown in Figure 12-2985 and described in Table 12-5711.
Return to Summary Table.
CRC Global Control Register 0
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0000h |
MCU_NAVSS0_MCRC | 2A26 4000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CH4_PSA_SWRE | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CH3_PSA_SWRE | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CH2_PSA_SWRE | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1_PSA_SWRE | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | CH4_PSA_SWRE | R/W | 0h | Channel 4 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not reset 1 = PSA Signature Register reset |
23-17 | RESERVED | R/W | X | |
16 | CH3_PSA_SWRE | R/W | 0h | Channel 3 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not reset 1 = PSA Signature Register reset |
15-9 | RESERVED | R/W | X | |
8 | CH2_PSA_SWRE | R/W | 0h | Channel 2 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not reset 1 = PSA Signature Register reset |
7-1 | RESERVED | R/W | X | |
0 | CH1_PSA_SWRE | R/W | 0h | Channel 1 PSA Software Reset. When set, the PSA Signature Register is reset to all zero. Software reset does not reset software reset bit itself. Therefore, CPU is required to clear this bit by writing a 0 . 0 = PSA Signature Register not reset 1 = PSA Signature Register reset |
MCRC_CRC_CTRL1 is shown in Figure 12-2986 and described in Table 12-5713.
Return to Summary Table.
CRC Global Control Register 1
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0008h |
MCU_NAVSS0_MCRC | 2A26 4008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PWDN | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | PWDN | R/W | 0h | Power Down. When set, MCRC moduleMCRC Module is put in power down mode. 0 = MCRC is not in power down mode. 1 = MCRC is in power down mode. |
MCRC_CRC_CTRL2 is shown in Figure 12-2987 and described in Table 12-5715.
Return to Summary Table.
Channel Mode Control Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0010h |
MCU_NAVSS0_MCRC | 2A26 4010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CH4_MODE | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CH3_MODE | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CH2_MODE | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1_TRACEEN | RESERVED | CH1_MODE | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | X | |
25-24 | CH4_MODE | R/W | 0h | Channel 4 Mode. 00 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register. 01 = AUTO mode 10 = Semi-CPU mode 11 = Full-CPU mode For all four channels the seed value can be first planted into PSA register before the Channel Mode is switched to Full-CPU mode since host CPU controls the amount of data for compression. During AUTO mode, the PSA register is automatically reset to zero at the end of each sector compression. |
23-18 | RESERVED | R/W | X | |
17-16 | CH3_MODE | R/W | 0h | Channel 3 Mode. 00 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register. 01 = AUTO mode 10 = Semi-CPU mode 11 = Full-CPU mode |
15-10 | RESERVED | R/W | X | |
9-8 | CH2_MODE | R/W | 0h | Channel 2 Mode. 00 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register. 01 = AUTO mode 10 = Semi-CPU mode 11 = Full-CPU mode |
7-5 | RESERVED | R/W | X | |
4 | CH1_TRACEEN | R/W | 0h | Channel 1 Data Trace Enable When set, the channel is put into data trace mode. The channel snoops on the CPU VBUSM, ITCM, DTCM buses for any read transaction. Any read data on these buses is compressed by the PSA Signature Register. When suspend is on, the PSA Signature Register does not compress any read data on these buses. 0 = Data Trace disable 1 = Data Trace enable |
3-2 | RESERVED | R/W | X | |
1-0 | CH1_MODE | R/W | 0h | Channel 1 Mode. 00 = Data Capture mode. In this mode, the PSA Signature Register does not compress data when it is written. Any data written to PSA Signature Register is simply captured by PSA Signature Register without any compression. This mode can be used to plant seed value into the PSA register. 01 = AUTO mode 10 = Semi-CPU mode 11 = Full-CPU mode |
MCRC_CRC_INTS is shown in Figure 12-2988 and described in Table 12-5717.
Return to Summary Table.
CRC Interrupt Enable Set Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0018h |
MCU_NAVSS0_MCRC | 2A26 4018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CH4_TIME_OUT_ENS_ | CH4_UNDERENS | CH4_OVERENS | CH4_CRC_FAILENS | CH4_CCITENS | ||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CH3_TIME_OUT_ENS | CH3_UNDERENS | CH3_OVERENS | CH3_CRC_FAILENS | CH3_CCITENS | ||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CH2_TIME_OUT_ENS_ | CH2_UNDERENS | CH2_OVERENS | CH2_CRC_FAILENS | CH2_CCITENS | ||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1_TIME_OUT_ENS_ | CH1_UNDERENS | CH1_OVERENS | CH1_CRC_FAILENS | CH1_CCITENS | ||
R/W-X | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | ||
LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28 | CH4_TIME_OUT_ENS_ | R/W1S | 0h | Channel 4 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
27 | CH4_UNDERENS | R/W1S | 0h | Channel 4 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
26 | CH4_OVERENS | R/W1S | 0h | Channel 4 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
25 | CH4_CRC_FAILENS | R/W1S | 0h | Channel 4 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
24 | CH4_CCITENS | R/W1S | 0h | Channel 4 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt enable |
23-21 | RESERVED | R/W | X | |
20 | CH3_TIME_OUT_ENS | R/W1S | 0h | Channel 3 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
19 | CH3_UNDERENS | R/W1S | 0h | Channel 3 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
18 | CH3_OVERENS | R/W1S | 0h | Channel 3 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
17 | CH3_CRC_FAILENS | R/W1S | 0h | Channel 3 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
16 | CH3_CCITENS | R/W1S | 0h | Channel 3 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt enable |
15-13 | RESERVED | R/W | X | |
12 | CH2_TIME_OUT_ENS_ | R/W1S | 0h | Channel 2 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
11 | CH2_UNDERENS | R/W1S | 0h | Channel 2 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
10 | CH2_OVERENS | R/W1S | 0h | Channel 2 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
9 | CH2_CRC_FAILENS | R/W1S | 0h | Channel 2 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
8 | CH2_CCITENS | R/W1S | 0h | Channel 2 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt enable |
7-5 | RESERVED | R/W | X | |
4 | CH1_TIME_OUT_ENS_ | R/W1S | 0h | Channel 1 Timeout Interrupt Enable Bit Writing a one to this bit enable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
3 | CH1_UNDERENS | R/W1S | 0h | Channel 1 Underrun Interrupt Enable Bit Writing a one to this bit enable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
2 | CH1_OVERENS | R/W1S | 0h | Channel 1 Overrun Interrupt Enable Bit Writing a one to this bit enable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
1 | CH1_CRC_FAILENS | R/W1S | 0h | Channel 1 CRC Fail Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
0 | CH1_CCITENS | R/W1S | 0h | Channel 1 Compression Complete Interrupt Enable Bit. Writing a one to this bit enable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt enable |
MCRC_CRC_INTR is shown in Figure 12-2989 and described in Table 12-5719.
Return to Summary Table.
CRC Interrupt Enable Reset Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0020h |
MCU_NAVSS0_MCRC | 2A26 4020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CH4_TIME_OUT_ENR | CH4_UNDERENR | CH4_OVERENR | CH4_CRC_FAILENR | CH4_CCITENR | ||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CH3_TIME_OUT_ENR_ | CH3_UNDERENR | CH3_OVERENR | CH3_CRC_FAILENR | CH3_CCITENR | ||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CH2_TIME_OUT_ENR_ | CH2_UNDERENR | CH2_OVERENR | CH2_CRC_FAILENR | CH2_CCITENR | ||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1_TIME_OUT_ENR_ | CH1_UNDERENR | CH1_OVERENR | CH1_CRC_FAILENR | CH1_CCITENR | ||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28 | CH4_TIME_OUT_ENR | R/W1C | 0h | Channel 4 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
27 | CH4_UNDERENR | R/W1C | 0h | Channel 4 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
26 | CH4_OVERENR | R/W1C | 0h | Channel 4 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
25 | CH4_CRC_FAILENR | R/W1C | 0h | Channel 4 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
24 | CH4_CCITENR | R/W1C | 0h | Channel 4 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt disable |
23-21 | RESERVED | R/W | X | |
20 | CH3_TIME_OUT_ENR_ | R/W1C | 0h | Channel 3 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
19 | CH3_UNDERENR | R/W1C | 0h | Channel 3 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
18 | CH3_OVERENR | R/W1C | 0h | Channel 3 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
17 | CH3_CRC_FAILENR | R/W1C | 0h | Channel 3 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
16 | CH3_CCITENR | R/W1C | 0h | Channel 3 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt disable |
15-13 | RESERVED | R/W | X | |
12 | CH2_TIME_OUT_ENR_ | R/W1C | 0h | Channel 2 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
11 | CH2_UNDERENR | R/W1C | 0h | Channel 2 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
10 | CH2_OVERENR | R/W1C | 0h | Channel 2 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
9 | CH2_CRC_FAILENR | R/W1C | 0h | Channel 2 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
8 | CH2_CCITENR | R/W1C | 0h | Channel 2 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt disable |
7-5 | RESERVED | R/W | X | |
4 | CH1_TIME_OUT_ENR_ | R/W1C | 0h | Channel 1 Timeout Interrupt Disable Bit Writing a one to this bit disable the timeout interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Timeout Interrupt disable 1 = Timeout Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Timeout Interrupt enable |
3 | CH1_UNDERENR | R/W1C | 0h | Channel 1 Underrun Interrupt Disable Bit Writing a one to this bit disable the underrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Underrun Interrupt disable 1 = Underrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Underrun Interrupt enable |
2 | CH1_OVERENR | R/W1C | 0h | Channel 1 Overrun Interrupt Disable Bit Writing a one to this bit disable the overrun interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = Overrun Interrupt disable 1 = Overrun Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Overrun Interrupt enable |
1 | CH1_CRC_FAILENR | R/W1C | 0h | Channel 1 CRC Fail Interrupt Disable Bit. Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable). User and privileged mode read: 0 = CRC Fail Interrupt disable 1 = CRC Fail Interrupt enable User and privileged mode write: 0 = Has no effect 1 = CRC Fail Interrupt enable |
0 | CH1_CCITENR | R/W1C | 0h | Channel 1 Compression Complete Interrupt Disable Bit Writing a one to this bit disable the CRC fail interrupt. Writing a zero has no effect. Reading from this bit gives the status (interrupt enable/disable) User and privileged mode read: 0 = Compression Complete Interrupt disable 1 = Compression Complete Interrupt enable User and privileged mode write: 0 = Has no effect 1 = Compression Complete Interrupt disable |
MCRC_CRC_STATUS is shown in Figure 12-2990 and described in Table 12-5721.
Return to Summary Table.
CRC Interrupt Status Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0028h |
MCU_NAVSS0_MCRC | 2A26 4028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CH4_TIME_OUT | CH4_UNDER | CH4_OVER | CH4_CRC_FAIL | CH4_CCIT | ||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CH3_TIME_OUT | CH3_UNDER | CH3_OVER | CH3_CRC_FAIL | CH3_CCIT | ||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CH2_TIME_OUT | CH2_UNDER | CH2_OVER | CH2_CRC_FAIL | CH2_CCIT | ||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1_TIME_OUT | CH1_UNDER | CH1_OVER | CH1_CRC_FAIL | CH1_CCIT | ||
R/W-X | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | ||
LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28 | CH4_TIME_OUT | R/W1C | 0h | Channel 4 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
27 | CH4_UNDER | R/W1C | 0h | Channel 4 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
26 | CH4_OVER | R/W1C | 0h | Channel 4 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
25 | CH4_CRC_FAIL | R/W1C | 0h | Channel 4 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
24 | CH4_CCIT | R/W1C | 0h | Channel 4 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern compression complete interrupt is active |
23-21 | RESERVED | R/W | X | |
20 | CH3_TIME_OUT | R/W1C | 0h | Channel 3 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
19 | CH3_UNDER | R/W1C | 0h | Channel 3 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
18 | CH3_OVER | R/W1C | 0h | Channel 3 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
17 | CH3_CRC_FAIL | R/W1C | 0h | Channel 3 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
16 | CH3_CCIT | R/W1C | 0h | Channel 3 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern compression complete interrupt is active |
15-13 | RESERVED | R/W | X | |
12 | CH2_TIME_OUT | R/W1C | 0h | Channel 2 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
11 | CH2_UNDER | R/W1C | 0h | Channel 2 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
10 | CH2_OVER | R/W1C | 0h | Channel 2 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode. 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
9 | CH2_CRC_FAIL | R/W1C | 0h | Channel 2 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
8 | CH2_CCIT | R/W1C | 0h | Channel 2 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern compression complete interrupt is active |
7-5 | RESERVED | R/W | X | |
4 | CH1_TIME_OUT | R/W1C | 0h | Channel 1 CRC Timeout Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in both AUTO and Semi-CPU mode. 0 = No timeout interrupt is active 1 = Timeout interrupt is active |
3 | CH1_UNDER | R/W1C | 0h | Channel 1 CRC Underrun Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only 0 = No underrun interrupt is active 1 = Underrun interrupt is active |
2 | CH1_OVER | R/W1C | 0h | Channel 1 CRC Overrun Status Flag This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in either AUTO or Semi-CPU mode. 0 = No overrun interrupt is active 1 = Overrun interrupt is active |
1 | CH1_CRC_FAIL | R/W1C | 0h | Channel 1 CRC Compare Fail Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is set in AUTO mode only. 0 = No CRC compare fail interrupt is active 1 = CRC compare fail interrupt is active |
0 | CH1_CCIT | R/W1C | 0h | Channel 1 CRC Pattern Compression Complete Status Flag. This bit is cleared by writing a 1 to it only. Writing 0 has no effect. This bit is only set in Semi-CPU mode. 0 = No CRC pattern compression complete interrupt is active 1 = CRC pattern compression complete interrupt is active |
MCRC_CRC_INT_OFFSET_REG is shown in Figure 12-2991 and described in Table 12-5723.
Return to Summary Table.
CRC Interrupt Offset
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0030h |
MCU_NAVSS0_MCRC | 2A26 4030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | X | |
7-0 | CRC | R | 0h | Interrupt Offset. This register indicates the highest priority pending interrupt vector address. Reading the offset register automatically clears the respective interrupt flag. |
MCRC_CRC_BUSY is shown in Figure 12-2992 and described in Table 12-5725.
Return to Summary Table.
CRC Busy Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0038h |
MCU_NAVSS0_MCRC | 2A26 4038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CH4_BUSY | ||||||
R-X | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CH3_BUSY | ||||||
R-X | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CH2_BUSY | ||||||
R-X | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CH1_BUSY | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | X | |
24 | CH4_BUSY | R | 0h | During AUTO or Semi-CPU mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed. |
23-17 | RESERVED | R | X | |
16 | CH3_BUSY | R | 0h | During AUTO or Semi-CPU mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed. |
15-9 | RESERVED | R | X | |
8 | CH2_BUSY | R | 0h | During AUTO or Semi-CPU mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed. |
7-1 | RESERVED | R | X | |
0 | CH1_BUSY | R | 0h | During AUTO or Semi-CPU mode, the busy flag is set when the first data pattern of the block is compressed and remains set until the the last data pattern of the block is compressed. The flag is cleared when the last data pattern of the block is compressed. |
MCRC_CRC_PCOUNT_REG1 is shown in Figure 12-2993 and described in Table 12-5727.
Return to Summary Table.
CRC Pattern Counter Preload Register1
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0040h |
MCU_NAVSS0_MCRC | 2A26 4040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_PAT_COUNT1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19-0 | CRC_PAT_COUNT1 | R/W | 0h | Channel 1 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed. |
MCRC_CRC_SCOUNT_REG1 is shown in Figure 12-2994 and described in Table 12-5729.
Return to Summary Table.
CRC Sector Counter Preload Register1
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0044h |
MCU_NAVSS0_MCRC | 2A26 4044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_SEC_COUNT1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | CRC_SEC_COUNT1 | R/W | 0h | Channel 1 Sector Counter Preload Register. This register contains the number of sectors in one block of memory. |
MCRC_CRC_CURSEC_REG1 is shown in Figure 12-2995 and described in Table 12-5731.
Return to Summary Table.
CRC Current Sector Register 1
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0048h |
MCU_NAVSS0_MCRC | 2A26 4048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_CURSEC1 | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | CRC_CURSEC1 | R | 0h | Channel 1 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erroneous sector number. In Semi-CPU mode, this register is used to indicate the sector number for which the compression complete has last happened. |
MCRC_CRC_WDTOPLD1 is shown in Figure 12-2996 and described in Table 12-5733.
Return to Summary Table.
CRC channel 1 Watchdog Timeout Preload Register A
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 004Ch |
MCU_NAVSS0_MCRC | 2A26 404Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_WDTOPLD1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | CRC_WDTOPLD1 | R/W | 0h | Channel 1 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns. |
MCRC_CRC_BCTOPLD1 is shown in Figure 12-2997 and described in Table 12-5735.
Return to Summary Table.
CRC channel 1 Block Complete Timeout Preload Register B
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0050h |
MCU_NAVSS0_MCRC | 2A26 4050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_BCTOPLD1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | CRC_BCTOPLD1 | R/W | 0h | Channel 1 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC for an entire block needs to complete before a timeout interrupt is generated. |
MCRC_PSA_SIGREGL1 is shown in Figure 12-2998 and described in Table 12-5737.
Return to Summary Table.
Channel 1 PSA signature low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0060h |
MCU_NAVSS0_MCRC | 2A26 4060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASIG1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASIG1 | R/W | 0h | Channel 1 PSA Signature Low Register. This register contains the value stored at PSASIG1[31:0] register. |
MCRC_PSA_SIGREGH1 is shown in Figure 12-2999 and described in Table 12-5739.
Return to Summary Table.
Channel 1 PSA signature high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0064h |
MCU_NAVSS0_MCRC | 2A26 4064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASIG1_63_32 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASIG1_63_32 | R/W | 0h | Channel 1 PSA Signature High Register. This register contains the value stored at PSASIG1[63:32] register. |
MCRC_CRC_REGL1 is shown in Figure 12-3000 and described in Table 12-5741.
Return to Summary Table.
Channel 1 CRC value low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0068h |
MCU_NAVSS0_MCRC | 2A26 4068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC1 | R/W | 0h | Channel 1 CRC Value Low Register. This register contains the current known good signature value stored at CRC1[31:0] register. |
MCRC_CRC_REGH1 is shown in Figure 12-3001 and described in Table 12-5743.
Return to Summary Table.
Channel 1 CRC value high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 006Ch |
MCU_NAVSS0_MCRC | 2A26 406Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC1_47_32 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC1_47_32 | R/W | 0h | Channel 1 CRC Value High Register. This register contains the current known good signature value stored at CRC1[63:32] register. |
MCRC_PSA_SECSIGREGL1 is shown in Figure 12-3002 and described in Table 12-5745.
Return to Summary Table.
Channel 1 PSA sector signature low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0070h |
MCU_NAVSS0_MCRC | 2A26 4070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASECSIG1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASECSIG1 | R | 0h | Channel 1 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG1[31:0] register. |
MCRC_PSA_SECSIGREGH1 is shown in Figure 12-3003 and described in Table 12-5747.
Return to Summary Table.
Channel 1 PSA sector signature high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0074h |
MCU_NAVSS0_MCRC | 2A26 4074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASECSIG1_63_32 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASECSIG1_63_32 | R | 0h | Channel 1 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG1[63:32] register. |
MCRC_RAW_DATAREGL1 is shown in Figure 12-3004 and described in Table 12-5749.
Return to Summary Table.
Channel 1 Raw Data Low Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0078h |
MCU_NAVSS0_MCRC | 2A26 4078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAW_DATA1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RAW_DATA1 | R | 0h | Channel 1 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data. |
MCRC_RAW_DATAREGH1 is shown in Figure 12-3005 and described in Table 12-5751.
Return to Summary Table.
Channel 1 Raw Data High Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 007Ch |
MCU_NAVSS0_MCRC | 2A26 407Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAW_DATA1_47_32 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RAW_DATA1_47_32 | R | 0h | Channel 1 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data. |
MCRC_CRC_PCOUNT_REG2 is shown in Figure 12-3006 and described in Table 12-5753.
Return to Summary Table.
CRC Pattern Counter Preload Register2
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0080h |
MCU_NAVSS0_MCRC | 2A26 4080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_PAT_COUNT2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19-0 | CRC_PAT_COUNT2 | R/W | 0h | CRC Pattern Counter Preload Register 2 This register contains the number of data patterns in one sector to be compressed before a CRC is performed. |
MCRC_CRC_SCOUNT_REG2 is shown in Figure 12-3007 and described in Table 12-5755.
Return to Summary Table.
CRC Sector Counter Preload Register2
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0084h |
MCU_NAVSS0_MCRC | 2A26 4084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_SEC_COUNT2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | CRC_SEC_COUNT2 | R/W | 0h | Channel 2 Sector Counter Preload Register. This register contains the number of sectors in one block of memory. |
MCRC_CRC_CURSEC_REG2 is shown in Figure 12-3008 and described in Table 12-5757.
Return to Summary Table.
CRC Current Sector Register 2
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0088h |
MCU_NAVSS0_MCRC | 2A26 4088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_CURSEC2 | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | CRC_CURSEC2 | R | 0h | Channel 2 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erroneous sector number. In Semi-CPU mode, this register is used to indicate the sector number for which the compression complete has last happened. |
MCRC_CRC_WDTOPLD2 is shown in Figure 12-3009 and described in Table 12-5759.
Return to Summary Table.
CRC channel 2 Watchdog Timeout Preload Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 008Ch |
MCU_NAVSS0_MCRC | 2A26 408Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_WDTOPLD2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | CRC_WDTOPLD2 | R/W | 0h | Channel 2 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns. |
MCRC_CRC_BCTOPLD2 is shown in Figure 12-3010 and described in Table 12-5761.
Return to Summary Table.
CRC channel 2 Block Complete Timeout Preload Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0090h |
MCU_NAVSS0_MCRC | 2A26 4090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_BCTOPLD2 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | CRC_BCTOPLD2 | R/W | 0h | Channel 2 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated. |
MCRC_PSA_SIGREGL2 is shown in Figure 12-3011 and described in Table 12-5763.
Return to Summary Table.
Channel 2 PSA signature low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00A0h |
MCU_NAVSS0_MCRC | 2A26 40A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASIG2 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASIG2 | R/W | 0h | Channel 2 PSA Signature Low Register. This register contains the value stored at PSASIG2[31:0] register. |
MCRC_PSA_SIGREGH2 is shown in Figure 12-3012 and described in Table 12-5765.
Return to Summary Table.
Channel 2 PSA signature high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00A4h |
MCU_NAVSS0_MCRC | 2A26 40A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASIG2_63_32 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASIG2_63_32 | R/W | 0h | Channel 2 PSA Signature High Register. This register contains the value stored at PSASIG2[63:32] register. |
MCRC_CRC_REGL2 is shown in Figure 12-3013 and described in Table 12-5767.
Return to Summary Table.
Channel 2 CRC value low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00A8h |
MCU_NAVSS0_MCRC | 2A26 40A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC2 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC2 | R/W | 0h | Channel 2 CRC Value Low Register. This register contains the current known good signature value stored at CRC2[31:0] register. |
MCRC_CRC_REGH2 is shown in Figure 12-3014 and described in Table 12-5769.
Return to Summary Table.
Channel 2 CRC value high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00ACh |
MCU_NAVSS0_MCRC | 2A26 40ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC2_63_32 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC2_63_32 | R/W | 0h | Channel 2 CRC Value High Register. This register contains the current known good signature value stored at CRC2[63:32] register. |
MCRC_PSA_SECSIGREGL2 is shown in Figure 12-3015 and described in Table 12-5771.
Return to Summary Table.
Channel 2 PSA sector signature low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00B0h |
MCU_NAVSS0_MCRC | 2A26 40B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASECSIG2 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASECSIG2 | R | 0h | Channel 2 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG2[31:0] register. |
MCRC_PSA_SECSIGREGH2 is shown in Figure 12-3016 and described in Table 12-5773.
Return to Summary Table.
Channel 2 PSA sector signature high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00B4h |
MCU_NAVSS0_MCRC | 2A26 40B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASECSIG2_63_32 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASECSIG2_63_32 | R | 0h | Channel 2 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG2[63:32] register. |
MCRC_RAW_DATAREGL2 is shown in Figure 12-3017 and described in Table 12-5775.
Return to Summary Table.
Channel 2 Raw Data Low Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00B8h |
MCU_NAVSS0_MCRC | 2A26 40B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAW_DATA2 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RAW_DATA2 | R | 0h | Channel 2 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data. |
MCRC_RAW_DATAREGH2 is shown in Figure 12-3018 and described in Table 12-5777.
Return to Summary Table.
Channel 2 Raw Data High Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00BCh |
MCU_NAVSS0_MCRC | 2A26 40BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAW_DATA2_63_32 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RAW_DATA2_63_32 | R | 0h | Channel 2 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data. |
MCRC_CRC_PCOUNT_REG3 is shown in Figure 12-3019 and described in Table 12-5779.
Return to Summary Table.
CRC Pattern Counter Preload Register3
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00C0h |
MCU_NAVSS0_MCRC | 2A26 40C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_PAT_COUNT3 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19-0 | CRC_PAT_COUNT3 | R/W | 0h | Channel 3 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed. |
MCRC_CRC_SCOUNT_REG3 is shown in Figure 12-3020 and described in Table 12-5781.
Return to Summary Table.
CRC Sector Counter Preload Register3
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00C4h |
MCU_NAVSS0_MCRC | 2A26 40C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_SEC_COUNT3 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | CRC_SEC_COUNT3 | R/W | 0h | Channel 3 Sector Counter Preload Register. This register contains the number of sectors in one block of memory. |
MCRC_CRC_CURSEC_REG3 is shown in Figure 12-3021 and described in Table 12-5783.
Return to Summary Table.
CRC Current Sector Register 3
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00C8h |
MCU_NAVSS0_MCRC | 2A26 40C8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_CURSEC3 | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | CRC_CURSEC3 | R | 0h | Channel 3 Current Sector ID Register. In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erroneous sector number. In Semi-CPU mode, this register is used to indicate the sector number for which the compression complete has last happened. |
MCRC_CRC_WDTOPLD3 is shown in Figure 12-3022 and described in Table 12-5785.
Return to Summary Table.
CRC channel 3 Watchdog Timeout Preload Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00CCh |
MCU_NAVSS0_MCRC | 2A26 40CCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_WDTOPLD3 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | CRC_WDTOPLD3 | R/W | 0h | Channel 3 Watchdog Timeout Counter Preload Register. This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns. |
MCRC_CRC_BCTOPLD3 is shown in Figure 12-3023 and described in Table 12-5787.
Return to Summary Table.
CRC channel 3 Block Complete Timeout Preload Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00D0h |
MCU_NAVSS0_MCRC | 2A26 40D0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_BCTOPLD3 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | CRC_BCTOPLD3 | R/W | 0h | Channel 3 Block Complete Timeout Counter Preload Register. This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated. |
MCRC_PSA_SIGREGL3 is shown in Figure 12-3024 and described in Table 12-5789.
Return to Summary Table.
Channel 3 PSA signature low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00E0h |
MCU_NAVSS0_MCRC | 2A26 40E0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASIG3 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASIG3 | R/W | 0h | Channel 3 PSA Signature Low Register. This register contains the value stored at PSASIG3[31:0] register. |
MCRC_PSA_SIGREGH3 is shown in Figure 12-3025 and described in Table 12-5791.
Return to Summary Table.
Channel 3 PSA signature high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00E4h |
MCU_NAVSS0_MCRC | 2A26 40E4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASIG3_63_32 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASIG3_63_32 | R/W | 0h | Channel 3 PSA Signature High Register. This register contains the value stored at PSASIG3[63:32] register. |
MCRC_CRC_REGL3 is shown in Figure 12-3026 and described in Table 12-5793.
Return to Summary Table.
Channel 3 CRC value low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00E8h |
MCU_NAVSS0_MCRC | 2A26 40E8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC3 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC3 | R/W | 0h | Channel 3 CRC Value Low Register. This register contains the current known good signature value stored at CRC3[31:0] register. |
MCRC_CRC_REGH3 is shown in Figure 12-3027 and described in Table 12-5795.
Return to Summary Table.
Channel 3 CRC value high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00ECh |
MCU_NAVSS0_MCRC | 2A26 40ECh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC3_63_32 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC3_63_32 | R/W | 0h | Channel 3 CRC Value High Register. This register contains the current known good signature value stored at CRC3[63:32] register. |
MCRC_PSA_SECSIGREGL3 is shown in Figure 12-3028 and described in Table 12-5797.
Return to Summary Table.
Channel 3 PSA sector signature low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00F0h |
MCU_NAVSS0_MCRC | 2A26 40F0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASECSIG3 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASECSIG3 | R | 0h | Channel 3 PSA Sector Signature Low Register. This register contains the value stored at PSASECSIG3[31:0] register. |
MCRC_PSA_SECSIGREGH3 is shown in Figure 12-3029 and described in Table 12-5799.
Return to Summary Table.
Channel 3 PSA sector signature high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00F4h |
MCU_NAVSS0_MCRC | 2A26 40F4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASECSIG3_63_32 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASECSIG3_63_32 | R | 0h | Channel 3 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG3[63:32] register. |
MCRC_RAW_DATAREGL3 is shown in Figure 12-3030 and described in Table 12-5801.
Return to Summary Table.
Channel 3 Raw Data Low Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00F8h |
MCU_NAVSS0_MCRC | 2A26 40F8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAW_DATA3 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RAW_DATA3 | R | 0h | Channel 3 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data. |
MCRC_RAW_DATAREGH3 is shown in Figure 12-3031 and described in Table 12-5803.
Return to Summary Table.
Channel 3 Raw Data High Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 00FCh |
MCU_NAVSS0_MCRC | 2A26 40FCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAW_DATA3_63_32 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RAW_DATA3_63_32 | R | 0h | Channel 3 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data. |
MCRC_CRC_PCOUNT_REG4 is shown in Figure 12-3032 and described in Table 12-5805.
Return to Summary Table.
CRC Pattern Counter Preload Register4
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0100h |
MCU_NAVSS0_MCRC | 2A26 4100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_PAT_COUNT4 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19-0 | CRC_PAT_COUNT4 | R/W | 0h | Channel 4 Pattern Counter Preload Register. This register contains the number of data patterns in one sector to be compressed before a CRC is performed. |
MCRC_CRC_SCOUNT_REG4 is shown in Figure 12-3033 and described in Table 12-5807.
Return to Summary Table.
CRC Sector Counter Preload Register4
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0104h |
MCU_NAVSS0_MCRC | 2A26 4104h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_SEC_COUNT4 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | CRC_SEC_COUNT4 | R/W | 0h | Channel 4 Sector Counter Preload Register. This register contains the number of sectors in one block of memory. |
MCRC_CRC_CURSEC_REG4 is shown in Figure 12-3034 and described in Table 12-5809.
Return to Summary Table.
CRC Current Sector Register 4
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0108h |
MCU_NAVSS0_MCRC | 2A26 4108h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_CURSEC4 | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | CRC_CURSEC4 | R | 0h | In AUTO mode, this register contains the current sector number of which the signature verification fails. The sector counter is a free running up counter. When a sector fails, the erroneous sector number is logged into current sector ID register and the CRC fail interrupt is generated The sector ID register is frozen until it is read and the CRC fail status bit is cleared by CPU. While it is frozen, it does not capture another erroneous sector number. When this condition happens, an overrun interrupt is generated instead. Once the register is read and the CRC fail interrupt flag is cleared it can capture new erroneous sector number. In Semi-CPU mode, this register is used to indicate the sector number for which the compression complete has last happened. |
MCRC_CRC_WDTOPLD4 is shown in Figure 12-3035 and described in Table 12-5811.
Return to Summary Table.
CRC channel 4 Watchdog Timeout Preload Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 010Ch |
MCU_NAVSS0_MCRC | 2A26 410Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_WDTOPLD4 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | CRC_WDTOPLD4 | R/W | 0h | This register contains the number of clock cycles within which the DMA must transfer the next block of data patterns. |
MCRC_CRC_BCTOPLD4 is shown in Figure 12-3036 and described in Table 12-5813.
Return to Summary Table.
CRC channel 4 Block Complete Timeout Preload Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0110h |
MCU_NAVSS0_MCRC | 2A26 4110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CRC_BCTOPLD4 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | CRC_BCTOPLD4 | R/W | 0h | This register contains the number of clock cycles within which the CRC of an entire block needs to complete before a timeout interrupt is generated. |
MCRC_PSA_SIGREGL4 is shown in Figure 12-3037 and described in Table 12-5815.
Return to Summary Table.
Channel 4 PSA signature low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0120h |
MCU_NAVSS0_MCRC | 2A26 4120h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASIG4 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASIG4 | R/W | 0h | This register contains the value stored at PSASIG4[31:0] register. |
MCRC_PSA_SIGREGH4 is shown in Figure 12-3038 and described in Table 12-5817.
Return to Summary Table.
Channel 4 PSA signature high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0124h |
MCU_NAVSS0_MCRC | 2A26 4124h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASIG4_63_32 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASIG4_63_32 | R/W | 0h | This register contains the value stored at PSASIG4[63:32] register. |
MCRC_CRC_REGL4 is shown in Figure 12-3039 and described in Table 12-5819.
Return to Summary Table.
Channel 4 CRC value low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0128h |
MCU_NAVSS0_MCRC | 2A26 4128h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC4 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC4 | R/W | 0h | Channel 4 CRC Value Low Register. |
MCRC_CRC_REGH4 is shown in Figure 12-3040 and described in Table 12-5821.
Return to Summary Table.
Channel 4 CRC value high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 012Ch |
MCU_NAVSS0_MCRC | 2A26 412Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC4_63_32 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC4_63_32 | R/W | 0h | Channel 4 CRC Value High Register. |
MCRC_PSA_SECSIGREGL4 is shown in Figure 12-3041 and described in Table 12-5823.
Return to Summary Table.
Channel 4 PSA sector signature low register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0130h |
MCU_NAVSS0_MCRC | 2A26 4130h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASECSIG4 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASECSIG4 | R | 0h | Channel 4 PSA Sector Signature Low Register. |
MCRC_PSA_SECSIGREGH4 is shown in Figure 12-3042 and described in Table 12-5825.
Return to Summary Table.
Channel 4 PSA sector signature high register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0134h |
MCU_NAVSS0_MCRC | 2A26 4134h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PSASECSIG4_63_32 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PSASECSIG4_63_32 | R | 0h | Channel 4 PSA Sector Signature High Register. This register contains the value stored at PSASECSIG4[63:32] register. |
MCRC_RAW_DATAREGL4 is shown in Figure 12-3043 and described in Table 12-5827.
Return to Summary Table.
Channel 4 Raw Data Low Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0138h |
MCU_NAVSS0_MCRC | 2A26 4138h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAW_DATA4 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RAW_DATA4 | R | 0h | Channel 4 Raw Data Low Register. This register contains bit 31:0 of the uncompressed raw data. |
MCRC_RAW_DATAREGH4 is shown in Figure 12-3044 and described in Table 12-5829.
Return to Summary Table.
Channel 4 Raw Data High Register
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 013Ch |
MCU_NAVSS0_MCRC | 2A26 413Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RAW_DATA4_63_32 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RAW_DATA4_63_32 | R | 0h | Channel 4 Raw Data High Register. This register contains bit 63:32 of the uncompressed raw data. |
MCRC_BUS_SEL is shown in Figure 12-3045 and described in Table 12-5831.
Return to Summary Table.
Data bus tracing selection
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0140h |
MCU_NAVSS0_MCRC | 2A26 4140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MEN | DTC_MEN | ITC_MEN | ||||
R/W-X | R/W-1h | R/W-1h | R/W-1h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2 | MEN | R/W | 1h | Enable/disables the tracing of VBUSM 0: Tracing of VBUSM master bus has been disabled 1: Tracing of VBUSM master bus has been enabled |
1 | DTC_MEN | R/W | 1h | Enable/disables the tracing of data TCM 0: Tracing of DTCM_ODD and DTCM_EVEN buses have been disabled 1: Tracing of DTCM_ODD and DTCM_EVEN buses have been enabled |
0 | ITC_MEN | R/W | 1h | Enable/disables the tracing of instruction TCM 0: Tracing of ITCM bus has been disabled 1: Tracing of ITCM bus has been enabled Please refer the description of CPU Data trace at page 1-21 for the priority between different data buses. |
MCRC_I0_PSA_SIGREG1_CPY_Y is shown in Figure 12-3046 and described in Table 12-5833.
Return to Summary Table.
Channel 1 PSA signature block region
Offset = 200h + (y * 4h); where y = 0h to 1Fh
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0200h + formula |
MCU_NAVSS0_MCRC | 2A26 4200h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I0_PSASIG1_CPY0 | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | I0_PSASIG1_CPY0 | W | 0h | This register is a 128 byte block copy of the PSASIG1 register for DMA destination, it is write only, the result can be found in the PSASIG1 register. |
MCRC_I0_PSA_SIGREG2_CPY_Y is shown in Figure 12-3047 and described in Table 12-5835.
Return to Summary Table.
Channel 2 PSA signature block region
Offset = 280h + (y * 4h); where y = 0h to 1Fh
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0280h + formula |
MCU_NAVSS0_MCRC | 2A26 4280h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I0_PSASIG2_CPY0 | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | I0_PSASIG2_CPY0 | W | 0h | This register is a 128 byte block copy of the PSASIG2 register for DMA destination, it is write only, the result can be found in the PSASIG2 register. |
MCRC_I0_PSA_SIGREG3_CPY_Y is shown in Figure 12-3048 and described in Table 12-5837.
Return to Summary Table.
Channel 3 PSA signature block region
Offset = 300h + (y * 4h); where y = 0h to 1Fh
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0300h + formula |
MCU_NAVSS0_MCRC | 2A26 4300h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I0_PSASIG3_CPY0 | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | I0_PSASIG3_CPY0 | W | 0h | This register is a 128 byte block copy of the PSASIG3 register for DMA destination, it is write only, the result can be found in the PSASIG3 register. |
MCRC_I0_PSA_SIGREG4_CPY_Y is shown in Figure 12-3049 and described in Table 12-5839.
Return to Summary Table.
Channel 4 PSA signature block region
Offset = 380h + (y * 4h); where y = 0h to 1Fh
Instance | Physical Address |
---|---|
NAVSS0_MCRC | 31F7 0380h + formula |
MCU_NAVSS0_MCRC | 2A26 4380h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
I0_PSASIG4_CPY0 | |||||||||||||||||||||||||||||||
W-0h | |||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | I0_PSASIG4_CPY0 | W | 0h | This register is a 128 byte block copy of the PSASIG4 register for DMA destination, it is write only, the result can be found in the PSASIG4 register. |