Each MMCSD Host Controller supports:
- Integrated DMA controller supporting SD Advanced DMA - ADMA2 and ADMA3 (for more information about ADMA support, see Section 12.3.6.4.5, Advanced DMA)
- System Bus Interface:
- 64-bit data width (master interface)
- 64-bit address
- Clock asynchronous to MMCSD clock (MMCi_CLK)
- Little endian only
- Configuration Bus Interface:
- 32-bit data width (slave interface)
- Linear incrementing addressing mode
- 32-bit aligned accesses only
- Little endian only
- Muxing of other LVCMOS interfaces onto the MMCSD interface at the SoC level (MMCSD1 only)
MMCSD0 Host Controller (eMMC interface):
MultiMedia Card Support:
- eMMC Electrical Standard 5.1 (JESD84-B51)
- Backward compatible with earlier eMMC standards
- Legacy MMC SDR:
- 1.8 V, 8-bit bus width, 0-25 MHz, 25 MBps
- 1.8 V, 4-bit bus width, 0-25 MHz, 12.5 MBps
- 1.8 V, 1-bit bus width, 0-25 MHz, 3.125 MBps
- High Speed SDR:
- 1.8 V, 8-bit bus width, 0-50 MHz, 50 MBps
- 1.8 V, 4-bit bus width, 0-50 MHz, 25 MBps
- 1.8 V, 1-bit bus width, 0-50 MHz, 6.25 MBps
- High Speed DDR:
- 1.8 V, 8-bit bus width, 0-50 MHz, 100 MBps
- 1.8 V, 4-bit bus width, 0-50 MHz, 50 MBps
- HS200 SDR:
- 1.8 V, 0-200 MHz, 8-bit bus width, 200 MBps
- 1.8 V, 0-200 MHz, 4-bit bus width, 100 MBps
- HS400 DDR:
- 1.8 V, 0-200 MHz, 8-bit bus width, 400 MBps
MMCSD1 Host Controller (SD/SDIO interface):