SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section describes module integration in the device, including information about clocks, resets, and hardware requests.
Figure 7-5 shows the Spinlock integration.
Table 7-16 and Table 7-17 summarize the integration of the module in the device.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
SPINLOCK0 | PSC0 | GP | LPSC0 | MODSS_CBASS |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
SPINLOCK0 | SPINLOCK0_FICLK | MODSS_VBUS_D2_CLK | MAIN_SYSCLK0 | Spinlock clock. This clock is used for all interface and functional operations. |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
SPINLOCK0 | SPINLOCK0_RST | MODSS_RST | LPSC0 | Spinlock hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
SPINLOCK0 | - | - | - | No interrupts to external processors | - |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
SPINLOCK0 | - | - | - | No PDMA channels to external DMA engines | - |