SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 8-1686 lists the memory-mapped registers for the DDR PHY. All register offset addresses not listed in Table 8-1686 should be considered as reserved locations and the register contents should not be modified.
| Instance | Base Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 0000h |
| Offset | Acronym | Register Name | COMPUTE_CLUSTER0_CTL_CFG_PHY Physical Address |
|---|---|---|---|
| 4000h | DDRSS_PHY_0 | DDR PHY Register 0 | 0299 4000h |
| 4004h | DDRSS_PHY_1 | DDR PHY Register 1 | 0299 4004h |
| 4008h | DDRSS_PHY_2 | DDR PHY Register 2 | 0299 4008h |
| 400Ch | DDRSS_PHY_3 | DDR PHY Register 3 | 0299 400Ch |
| 4010h | DDRSS_PHY_4 | DDR PHY Register 4 | 0299 4010h |
| 4014h | DDRSS_PHY_5 | DDR PHY Register 5 | 0299 4014h |
| 4018h | DDRSS_PHY_6 | DDR PHY Register 6 | 0299 4018h |
| 401Ch | DDRSS_PHY_7 | DDR PHY Register 7 | 0299 401Ch |
| 4020h | DDRSS_PHY_8 | DDR PHY Register 8 | 0299 4020h |
| 4024h | DDRSS_PHY_9 | DDR PHY Register 9 | 0299 4024h |
| 4028h | DDRSS_PHY_10 | DDR PHY Register 10 | 0299 4028h |
| 402Ch | DDRSS_PHY_11 | DDR PHY Register 11 | 0299 402Ch |
| 4030h | DDRSS_PHY_12 | DDR PHY Register 12 | 0299 4030h |
| 4034h | DDRSS_PHY_13 | DDR PHY Register 13 | 0299 4034h |
| 4038h | DDRSS_PHY_14 | DDR PHY Register 14 | 0299 4038h |
| 403Ch | DDRSS_PHY_15 | DDR PHY Register 15 | 0299 403Ch |
| 4040h | DDRSS_PHY_16 | DDR PHY Register 16 | 0299 4040h |
| 4044h | DDRSS_PHY_17 | DDR PHY Register 17 | 0299 4044h |
| 4048h | DDRSS_PHY_18 | DDR PHY Register 18 | 0299 4048h |
| 404Ch | DDRSS_PHY_19 | DDR PHY Register 19 | 0299 404Ch |
| 4050h | DDRSS_PHY_20 | DDR PHY Register 20 | 0299 4050h |
| 4054h | DDRSS_PHY_21 | DDR PHY Register 21 | 0299 4054h |
| 4058h | DDRSS_PHY_22 | DDR PHY Register 22 | 0299 4058h |
| 405Ch | DDRSS_PHY_23 | DDR PHY Register 23 | 0299 405Ch |
| 4060h | DDRSS_PHY_24 | DDR PHY Register 24 | 0299 4060h |
| 4064h | DDRSS_PHY_25 | DDR PHY Register 25 | 0299 4064h |
| 4068h | DDRSS_PHY_26 | DDR PHY Register 26 | 0299 4068h |
| 406Ch | DDRSS_PHY_27 | DDR PHY Register 27 | 0299 406Ch |
| 4070h | DDRSS_PHY_28 | DDR PHY Register 28 | 0299 4070h |
| 4074h | DDRSS_PHY_29 | DDR PHY Register 29 | 0299 4074h |
| 4078h | DDRSS_PHY_30 | DDR PHY Register 30 | 0299 4078h |
| 407Ch | DDRSS_PHY_31 | DDR PHY Register 31 | 0299 407Ch |
| 4080h | DDRSS_PHY_32 | DDR PHY Register 32 | 0299 4080h |
| 4084h | DDRSS_PHY_33 | DDR PHY Register 33 | 0299 4084h |
| 4088h | DDRSS_PHY_34 | DDR PHY Register 34 | 0299 4088h |
| 408Ch | DDRSS_PHY_35 | DDR PHY Register 35 | 0299 408Ch |
| 4090h | DDRSS_PHY_36 | DDR PHY Register 36 | 0299 4090h |
| 4094h | DDRSS_PHY_37 | DDR PHY Register 37 | 0299 4094h |
| 4098h | DDRSS_PHY_38 | DDR PHY Register 38 | 0299 4098h |
| 409Ch | DDRSS_PHY_39 | DDR PHY Register 39 | 0299 409Ch |
| 40A0h | DDRSS_PHY_40 | DDR PHY Register 40 | 0299 40A0h |
| 40A4h | DDRSS_PHY_41 | DDR PHY Register 41 | 0299 40A4h |
| 40A8h | DDRSS_PHY_42 | DDR PHY Register 42 | 0299 40A8h |
| 40ACh | DDRSS_PHY_43 | DDR PHY Register 43 | 0299 40ACh |
| 40B0h | DDRSS_PHY_44 | DDR PHY Register 44 | 0299 40B0h |
| 40B4h | DDRSS_PHY_45 | DDR PHY Register 45 | 0299 40B4h |
| 40B8h | DDRSS_PHY_46 | DDR PHY Register 46 | 0299 40B8h |
| 40BCh | DDRSS_PHY_47 | DDR PHY Register 47 | 0299 40BCh |
| 40C0h | DDRSS_PHY_48 | DDR PHY Register 48 | 0299 40C0h |
| 40C4h | DDRSS_PHY_49 | DDR PHY Register 49 | 0299 40C4h |
| 40C8h | DDRSS_PHY_50 | DDR PHY Register 50 | 0299 40C8h |
| 40CCh | DDRSS_PHY_51 | DDR PHY Register 51 | 0299 40CCh |
| 40D0h | DDRSS_PHY_52 | DDR PHY Register 52 | 0299 40D0h |
| 40D4h | DDRSS_PHY_53 | DDR PHY Register 53 | 0299 40D4h |
| 40D8h | DDRSS_PHY_54 | DDR PHY Register 54 | 0299 40D8h |
| 40DCh | DDRSS_PHY_55 | DDR PHY Register 55 | 0299 40DCh |
| 40E0h | DDRSS_PHY_56 | DDR PHY Register 56 | 0299 40E0h |
| 40E4h | DDRSS_PHY_57 | DDR PHY Register 57 | 0299 40E4h |
| 40E8h | DDRSS_PHY_58 | DDR PHY Register 58 | 0299 40E8h |
| 40ECh | DDRSS_PHY_59 | DDR PHY Register 59 | 0299 40ECh |
| 40F0h | DDRSS_PHY_60 | DDR PHY Register 60 | 0299 40F0h |
| 40F4h | DDRSS_PHY_61 | DDR PHY Register 61 | 0299 40F4h |
| 40F8h | DDRSS_PHY_62 | DDR PHY Register 62 | 0299 40F8h |
| 40FCh | DDRSS_PHY_63 | DDR PHY Register 63 | 0299 40FCh |
| 4100h | DDRSS_PHY_64 | DDR PHY Register 64 | 0299 4100h |
| 4104h | DDRSS_PHY_65 | DDR PHY Register 65 | 0299 4104h |
| 4108h | DDRSS_PHY_66 | DDR PHY Register 66 | 0299 4108h |
| 410Ch | DDRSS_PHY_67 | DDR PHY Register 67 | 0299 410Ch |
| 4110h | DDRSS_PHY_68 | DDR PHY Register 68 | 0299 4110h |
| 4114h | DDRSS_PHY_69 | DDR PHY Register 69 | 0299 4114h |
| 4118h | DDRSS_PHY_70 | DDR PHY Register 70 | 0299 4118h |
| 411Ch | DDRSS_PHY_71 | DDR PHY Register 71 | 0299 411Ch |
| 4120h | DDRSS_PHY_72 | DDR PHY Register 72 | 0299 4120h |
| 4124h | DDRSS_PHY_73 | DDR PHY Register 73 | 0299 4124h |
| 4128h | DDRSS_PHY_74 | DDR PHY Register 74 | 0299 4128h |
| 412Ch | DDRSS_PHY_75 | DDR PHY Register 75 | 0299 412Ch |
| 4130h | DDRSS_PHY_76 | DDR PHY Register 76 | 0299 4130h |
| 4134h | DDRSS_PHY_77 | DDR PHY Register 77 | 0299 4134h |
| 4138h | DDRSS_PHY_78 | DDR PHY Register 78 | 0299 4138h |
| 413Ch | DDRSS_PHY_79 | DDR PHY Register 79 | 0299 413Ch |
| 4140h | DDRSS_PHY_80 | DDR PHY Register 80 | 0299 4140h |
| 4144h | DDRSS_PHY_81 | DDR PHY Register 81 | 0299 4144h |
| 4148h | DDRSS_PHY_82 | DDR PHY Register 82 | 0299 4148h |
| 414Ch | DDRSS_PHY_83 | DDR PHY Register 83 | 0299 414Ch |
| 4150h | DDRSS_PHY_84 | DDR PHY Register 84 | 0299 4150h |
| 4154h | DDRSS_PHY_85 | DDR PHY Register 85 | 0299 4154h |
| 4158h | DDRSS_PHY_86 | DDR PHY Register 86 | 0299 4158h |
| 415Ch | DDRSS_PHY_87 | DDR PHY Register 87 | 0299 415Ch |
| 4160h | DDRSS_PHY_88 | DDR PHY Register 88 | 0299 4160h |
| 4164h | DDRSS_PHY_89 | DDR PHY Register 89 | 0299 4164h |
| 4168h | DDRSS_PHY_90 | DDR PHY Register 90 | 0299 4168h |
| 416Ch | DDRSS_PHY_91 | DDR PHY Register 91 | 0299 416Ch |
| 4170h | DDRSS_PHY_92 | DDR PHY Register 92 | 0299 4170h |
| 4174h | DDRSS_PHY_93 | DDR PHY Register 93 | 0299 4174h |
| 4178h | DDRSS_PHY_94 | DDR PHY Register 94 | 0299 4178h |
| 417Ch | DDRSS_PHY_95 | DDR PHY Register 95 | 0299 417Ch |
| 4180h | DDRSS_PHY_96 | DDR PHY Register 96 | 0299 4180h |
| 4184h | DDRSS_PHY_97 | DDR PHY Register 97 | 0299 4184h |
| 4188h | DDRSS_PHY_98 | DDR PHY Register 98 | 0299 4188h |
| 418Ch | DDRSS_PHY_99 | DDR PHY Register 99 | 0299 418Ch |
| 4190h | DDRSS_PHY_100 | DDR PHY Register 100 | 0299 4190h |
| 4194h | DDRSS_PHY_101 | DDR PHY Register 101 | 0299 4194h |
| 4198h | DDRSS_PHY_102 | DDR PHY Register 102 | 0299 4198h |
| 419Ch | DDRSS_PHY_103 | DDR PHY Register 103 | 0299 419Ch |
| 41A0h | DDRSS_PHY_104 | DDR PHY Register 104 | 0299 41A0h |
| 41A4h | DDRSS_PHY_105 | DDR PHY Register 105 | 0299 41A4h |
| 41A8h | DDRSS_PHY_106 | DDR PHY Register 106 | 0299 41A8h |
| 41ACh | DDRSS_PHY_107 | DDR PHY Register 107 | 0299 41ACh |
| 41B0h | DDRSS_PHY_108 | DDR PHY Register 108 | 0299 41B0h |
| 41B4h | DDRSS_PHY_109 | DDR PHY Register 109 | 0299 41B4h |
| 41B8h | DDRSS_PHY_110 | DDR PHY Register 110 | 0299 41B8h |
| 41BCh | DDRSS_PHY_111 | DDR PHY Register 111 | 0299 41BCh |
| 41C0h | DDRSS_PHY_112 | DDR PHY Register 112 | 0299 41C0h |
| 41C4h | DDRSS_PHY_113 | DDR PHY Register 113 | 0299 41C4h |
| 41C8h | DDRSS_PHY_114 | DDR PHY Register 114 | 0299 41C8h |
| 41CCh | DDRSS_PHY_115 | DDR PHY Register 115 | 0299 41CCh |
| 41D0h | DDRSS_PHY_116 | DDR PHY Register 116 | 0299 41D0h |
| 41D4h | DDRSS_PHY_117 | DDR PHY Register 117 | 0299 41D4h |
| 41D8h | DDRSS_PHY_118 | DDR PHY Register 118 | 0299 41D8h |
| 41DCh | DDRSS_PHY_119 | DDR PHY Register 119 | 0299 41DCh |
| 41E0h | DDRSS_PHY_120 | DDR PHY Register 120 | 0299 41E0h |
| 41E4h | DDRSS_PHY_121 | DDR PHY Register 121 | 0299 41E4h |
| 41E8h | DDRSS_PHY_122 | DDR PHY Register 122 | 0299 41E8h |
| 41ECh | DDRSS_PHY_123 | DDR PHY Register 123 | 0299 41ECh |
| 41F0h | DDRSS_PHY_124 | DDR PHY Register 124 | 0299 41F0h |
| 41F4h | DDRSS_PHY_125 | DDR PHY Register 125 | 0299 41F4h |
| 41F8h | DDRSS_PHY_126 | DDR PHY Register 126 | 0299 41F8h |
| 41FCh | DDRSS_PHY_127 | DDR PHY Register 127 | 0299 41FCh |
| 4200h | DDRSS_PHY_128 | DDR PHY Register 128 | 0299 4200h |
| 4204h | DDRSS_PHY_129 | DDR PHY Register 129 | 0299 4204h |
| 4208h | DDRSS_PHY_130 | DDR PHY Register 130 | 0299 4208h |
| 420Ch | DDRSS_PHY_131 | DDR PHY Register 131 | 0299 420Ch |
| 4210h | DDRSS_PHY_132 | DDR PHY Register 132 | 0299 4210h |
| 4214h | DDRSS_PHY_133 | DDR PHY Register 133 | 0299 4214h |
| 4218h | DDRSS_PHY_134 | DDR PHY Register 134 | 0299 4218h |
| 421Ch | DDRSS_PHY_135 | DDR PHY Register 135 | 0299 421Ch |
| 4220h | DDRSS_PHY_136 | DDR PHY Register 136 | 0299 4220h |
| 4224h | DDRSS_PHY_137 | DDR PHY Register 137 | 0299 4224h |
| 4228h | DDRSS_PHY_138 | DDR PHY Register 138 | 0299 4228h |
| 422Ch | DDRSS_PHY_139 | DDR PHY Register 139 | 0299 422Ch |
| 4400h | DDRSS_PHY_256 | DDR PHY Register 256 | 0299 4400h |
| 4404h | DDRSS_PHY_257 | DDR PHY Register 257 | 0299 4404h |
| 4408h | DDRSS_PHY_258 | DDR PHY Register 258 | 0299 4408h |
| 440Ch | DDRSS_PHY_259 | DDR PHY Register 259 | 0299 440Ch |
| 4410h | DDRSS_PHY_260 | DDR PHY Register 260 | 0299 4410h |
| 4414h | DDRSS_PHY_261 | DDR PHY Register 261 | 0299 4414h |
| 4418h | DDRSS_PHY_262 | DDR PHY Register 262 | 0299 4418h |
| 441Ch | DDRSS_PHY_263 | DDR PHY Register 263 | 0299 441Ch |
| 4420h | DDRSS_PHY_264 | DDR PHY Register 264 | 0299 4420h |
| 4424h | DDRSS_PHY_265 | DDR PHY Register 265 | 0299 4424h |
| 4428h | DDRSS_PHY_266 | DDR PHY Register 266 | 0299 4428h |
| 442Ch | DDRSS_PHY_267 | DDR PHY Register 267 | 0299 442Ch |
| 4430h | DDRSS_PHY_268 | DDR PHY Register 268 | 0299 4430h |
| 4434h | DDRSS_PHY_269 | DDR PHY Register 269 | 0299 4434h |
| 4438h | DDRSS_PHY_270 | DDR PHY Register 270 | 0299 4438h |
| 443Ch | DDRSS_PHY_271 | DDR PHY Register 271 | 0299 443Ch |
| 4440h | DDRSS_PHY_272 | DDR PHY Register 272 | 0299 4440h |
| 4444h | DDRSS_PHY_273 | DDR PHY Register 273 | 0299 4444h |
| 4448h | DDRSS_PHY_274 | DDR PHY Register 274 | 0299 4448h |
| 444Ch | DDRSS_PHY_275 | DDR PHY Register 275 | 0299 444Ch |
| 4450h | DDRSS_PHY_276 | DDR PHY Register 276 | 0299 4450h |
| 4454h | DDRSS_PHY_277 | DDR PHY Register 277 | 0299 4454h |
| 4458h | DDRSS_PHY_278 | DDR PHY Register 278 | 0299 4458h |
| 445Ch | DDRSS_PHY_279 | DDR PHY Register 279 | 0299 445Ch |
| 4460h | DDRSS_PHY_280 | DDR PHY Register 280 | 0299 4460h |
| 4464h | DDRSS_PHY_281 | DDR PHY Register 281 | 0299 4464h |
| 4468h | DDRSS_PHY_282 | DDR PHY Register 282 | 0299 4468h |
| 446Ch | DDRSS_PHY_283 | DDR PHY Register 283 | 0299 446Ch |
| 4470h | DDRSS_PHY_284 | DDR PHY Register 284 | 0299 4470h |
| 4474h | DDRSS_PHY_285 | DDR PHY Register 285 | 0299 4474h |
| 4478h | DDRSS_PHY_286 | DDR PHY Register 286 | 0299 4478h |
| 447Ch | DDRSS_PHY_287 | DDR PHY Register 287 | 0299 447Ch |
| 4480h | DDRSS_PHY_288 | DDR PHY Register 288 | 0299 4480h |
| 4484h | DDRSS_PHY_289 | DDR PHY Register 289 | 0299 4484h |
| 4488h | DDRSS_PHY_290 | DDR PHY Register 290 | 0299 4488h |
| 448Ch | DDRSS_PHY_291 | DDR PHY Register 291 | 0299 448Ch |
| 4490h | DDRSS_PHY_292 | DDR PHY Register 292 | 0299 4490h |
| 4494h | DDRSS_PHY_293 | DDR PHY Register 293 | 0299 4494h |
| 4498h | DDRSS_PHY_294 | DDR PHY Register 294 | 0299 4498h |
| 449Ch | DDRSS_PHY_295 | DDR PHY Register 295 | 0299 449Ch |
| 44A0h | DDRSS_PHY_296 | DDR PHY Register 296 | 0299 44A0h |
| 44A4h | DDRSS_PHY_297 | DDR PHY Register 297 | 0299 44A4h |
| 44A8h | DDRSS_PHY_298 | DDR PHY Register 298 | 0299 44A8h |
| 44ACh | DDRSS_PHY_299 | DDR PHY Register 299 | 0299 44ACh |
| 44B0h | DDRSS_PHY_300 | DDR PHY Register 300 | 0299 44B0h |
| 44B4h | DDRSS_PHY_301 | DDR PHY Register 301 | 0299 44B4h |
| 44B8h | DDRSS_PHY_302 | DDR PHY Register 302 | 0299 44B8h |
| 44BCh | DDRSS_PHY_303 | DDR PHY Register 303 | 0299 44BCh |
| 44C0h | DDRSS_PHY_304 | DDR PHY Register 304 | 0299 44C0h |
| 44C4h | DDRSS_PHY_305 | DDR PHY Register 305 | 0299 44C4h |
| 44C8h | DDRSS_PHY_306 | DDR PHY Register 306 | 0299 44C8h |
| 44CCh | DDRSS_PHY_307 | DDR PHY Register 307 | 0299 44CCh |
| 44D0h | DDRSS_PHY_308 | DDR PHY Register 308 | 0299 44D0h |
| 44D4h | DDRSS_PHY_309 | DDR PHY Register 309 | 0299 44D4h |
| 44D8h | DDRSS_PHY_310 | DDR PHY Register 310 | 0299 44D8h |
| 44DCh | DDRSS_PHY_311 | DDR PHY Register 311 | 0299 44DCh |
| 44E0h | DDRSS_PHY_312 | DDR PHY Register 312 | 0299 44E0h |
| 44E4h | DDRSS_PHY_313 | DDR PHY Register 313 | 0299 44E4h |
| 44E8h | DDRSS_PHY_314 | DDR PHY Register 314 | 0299 44E8h |
| 44ECh | DDRSS_PHY_315 | DDR PHY Register 315 | 0299 44ECh |
| 44F0h | DDRSS_PHY_316 | DDR PHY Register 316 | 0299 44F0h |
| 44F4h | DDRSS_PHY_317 | DDR PHY Register 317 | 0299 44F4h |
| 44F8h | DDRSS_PHY_318 | DDR PHY Register 318 | 0299 44F8h |
| 44FCh | DDRSS_PHY_319 | DDR PHY Register 319 | 0299 44FCh |
| 4500h | DDRSS_PHY_320 | DDR PHY Register 320 | 0299 4500h |
| 4504h | DDRSS_PHY_321 | DDR PHY Register 321 | 0299 4504h |
| 4508h | DDRSS_PHY_322 | DDR PHY Register 322 | 0299 4508h |
| 450Ch | DDRSS_PHY_323 | DDR PHY Register 323 | 0299 450Ch |
| 4510h | DDRSS_PHY_324 | DDR PHY Register 324 | 0299 4510h |
| 4514h | DDRSS_PHY_325 | DDR PHY Register 325 | 0299 4514h |
| 4518h | DDRSS_PHY_326 | DDR PHY Register 326 | 0299 4518h |
| 451Ch | DDRSS_PHY_327 | DDR PHY Register 327 | 0299 451Ch |
| 4520h | DDRSS_PHY_328 | DDR PHY Register 328 | 0299 4520h |
| 4524h | DDRSS_PHY_329 | DDR PHY Register 329 | 0299 4524h |
| 4528h | DDRSS_PHY_330 | DDR PHY Register 330 | 0299 4528h |
| 452Ch | DDRSS_PHY_331 | DDR PHY Register 331 | 0299 452Ch |
| 4530h | DDRSS_PHY_332 | DDR PHY Register 332 | 0299 4530h |
| 4534h | DDRSS_PHY_333 | DDR PHY Register 333 | 0299 4534h |
| 4538h | DDRSS_PHY_334 | DDR PHY Register 334 | 0299 4538h |
| 453Ch | DDRSS_PHY_335 | DDR PHY Register 335 | 0299 453Ch |
| 4540h | DDRSS_PHY_336 | DDR PHY Register 336 | 0299 4540h |
| 4544h | DDRSS_PHY_337 | DDR PHY Register 337 | 0299 4544h |
| 4548h | DDRSS_PHY_338 | DDR PHY Register 338 | 0299 4548h |
| 454Ch | DDRSS_PHY_339 | DDR PHY Register 339 | 0299 454Ch |
| 4550h | DDRSS_PHY_340 | DDR PHY Register 340 | 0299 4550h |
| 4554h | DDRSS_PHY_341 | DDR PHY Register 341 | 0299 4554h |
| 4558h | DDRSS_PHY_342 | DDR PHY Register 342 | 0299 4558h |
| 455Ch | DDRSS_PHY_343 | DDR PHY Register 343 | 0299 455Ch |
| 4560h | DDRSS_PHY_344 | DDR PHY Register 344 | 0299 4560h |
| 4564h | DDRSS_PHY_345 | DDR PHY Register 345 | 0299 4564h |
| 4568h | DDRSS_PHY_346 | DDR PHY Register 346 | 0299 4568h |
| 456Ch | DDRSS_PHY_347 | DDR PHY Register 347 | 0299 456Ch |
| 4570h | DDRSS_PHY_348 | DDR PHY Register 348 | 0299 4570h |
| 4574h | DDRSS_PHY_349 | DDR PHY Register 349 | 0299 4574h |
| 4578h | DDRSS_PHY_350 | DDR PHY Register 350 | 0299 4578h |
| 457Ch | DDRSS_PHY_351 | DDR PHY Register 351 | 0299 457Ch |
| 4580h | DDRSS_PHY_352 | DDR PHY Register 352 | 0299 4580h |
| 4584h | DDRSS_PHY_353 | DDR PHY Register 353 | 0299 4584h |
| 4588h | DDRSS_PHY_354 | DDR PHY Register 354 | 0299 4588h |
| 458Ch | DDRSS_PHY_355 | DDR PHY Register 355 | 0299 458Ch |
| 4590h | DDRSS_PHY_356 | DDR PHY Register 356 | 0299 4590h |
| 4594h | DDRSS_PHY_357 | DDR PHY Register 357 | 0299 4594h |
| 4598h | DDRSS_PHY_358 | DDR PHY Register 358 | 0299 4598h |
| 459Ch | DDRSS_PHY_359 | DDR PHY Register 359 | 0299 459Ch |
| 45A0h | DDRSS_PHY_360 | DDR PHY Register 360 | 0299 45A0h |
| 45A4h | DDRSS_PHY_361 | DDR PHY Register 361 | 0299 45A4h |
| 45A8h | DDRSS_PHY_362 | DDR PHY Register 362 | 0299 45A8h |
| 45ACh | DDRSS_PHY_363 | DDR PHY Register 363 | 0299 45ACh |
| 45B0h | DDRSS_PHY_364 | DDR PHY Register 364 | 0299 45B0h |
| 45B4h | DDRSS_PHY_365 | DDR PHY Register 365 | 0299 45B4h |
| 45B8h | DDRSS_PHY_366 | DDR PHY Register 366 | 0299 45B8h |
| 45BCh | DDRSS_PHY_367 | DDR PHY Register 367 | 0299 45BCh |
| 45C0h | DDRSS_PHY_368 | DDR PHY Register 368 | 0299 45C0h |
| 45C4h | DDRSS_PHY_369 | DDR PHY Register 369 | 0299 45C4h |
| 45C8h | DDRSS_PHY_370 | DDR PHY Register 370 | 0299 45C8h |
| 45CCh | DDRSS_PHY_371 | DDR PHY Register 371 | 0299 45CCh |
| 45D0h | DDRSS_PHY_372 | DDR PHY Register 372 | 0299 45D0h |
| 45D4h | DDRSS_PHY_373 | DDR PHY Register 373 | 0299 45D4h |
| 45D8h | DDRSS_PHY_374 | DDR PHY Register 374 | 0299 45D8h |
| 45DCh | DDRSS_PHY_375 | DDR PHY Register 375 | 0299 45DCh |
| 45E0h | DDRSS_PHY_376 | DDR PHY Register 376 | 0299 45E0h |
| 45E4h | DDRSS_PHY_377 | DDR PHY Register 377 | 0299 45E4h |
| 45E8h | DDRSS_PHY_378 | DDR PHY Register 378 | 0299 45E8h |
| 45ECh | DDRSS_PHY_379 | DDR PHY Register 379 | 0299 45ECh |
| 45F0h | DDRSS_PHY_380 | DDR PHY Register 380 | 0299 45F0h |
| 45F4h | DDRSS_PHY_381 | DDR PHY Register 381 | 0299 45F4h |
| 45F8h | DDRSS_PHY_382 | DDR PHY Register 382 | 0299 45F8h |
| 45FCh | DDRSS_PHY_383 | DDR PHY Register 383 | 0299 45FCh |
| 4600h | DDRSS_PHY_384 | DDR PHY Register 384 | 0299 4600h |
| 4604h | DDRSS_PHY_385 | DDR PHY Register 385 | 0299 4604h |
| 4608h | DDRSS_PHY_386 | DDR PHY Register 386 | 0299 4608h |
| 460Ch | DDRSS_PHY_387 | DDR PHY Register 387 | 0299 460Ch |
| 4610h | DDRSS_PHY_388 | DDR PHY Register 388 | 0299 4610h |
| 4614h | DDRSS_PHY_389 | DDR PHY Register 389 | 0299 4614h |
| 4618h | DDRSS_PHY_390 | DDR PHY Register 390 | 0299 4618h |
| 461Ch | DDRSS_PHY_391 | DDR PHY Register 391 | 0299 461Ch |
| 4620h | DDRSS_PHY_392 | DDR PHY Register 392 | 0299 4620h |
| 4624h | DDRSS_PHY_393 | DDR PHY Register 393 | 0299 4624h |
| 4628h | DDRSS_PHY_394 | DDR PHY Register 394 | 0299 4628h |
| 462Ch | DDRSS_PHY_395 | DDR PHY Register 395 | 0299 462Ch |
| 4800h | DDRSS_PHY_512 | DDR PHY Register 512 | 0299 4800h |
| 4804h | DDRSS_PHY_513 | DDR PHY Register 513 | 0299 4804h |
| 4808h | DDRSS_PHY_514 | DDR PHY Register 514 | 0299 4808h |
| 480Ch | DDRSS_PHY_515 | DDR PHY Register 515 | 0299 480Ch |
| 4810h | DDRSS_PHY_516 | DDR PHY Register 516 | 0299 4810h |
| 4814h | DDRSS_PHY_517 | DDR PHY Register 517 | 0299 4814h |
| 4818h | DDRSS_PHY_518 | DDR PHY Register 518 | 0299 4818h |
| 481Ch | DDRSS_PHY_519 | DDR PHY Register 519 | 0299 481Ch |
| 4820h | DDRSS_PHY_520 | DDR PHY Register 520 | 0299 4820h |
| 4824h | DDRSS_PHY_521 | DDR PHY Register 521 | 0299 4824h |
| 4828h | DDRSS_PHY_522 | DDR PHY Register 522 | 0299 4828h |
| 482Ch | DDRSS_PHY_523 | DDR PHY Register 523 | 0299 482Ch |
| 4830h | DDRSS_PHY_524 | DDR PHY Register 524 | 0299 4830h |
| 4834h | DDRSS_PHY_525 | DDR PHY Register 525 | 0299 4834h |
| 4838h | DDRSS_PHY_526 | DDR PHY Register 526 | 0299 4838h |
| 483Ch | DDRSS_PHY_527 | DDR PHY Register 527 | 0299 483Ch |
| 4840h | DDRSS_PHY_528 | DDR PHY Register 528 | 0299 4840h |
| 4844h | DDRSS_PHY_529 | DDR PHY Register 529 | 0299 4844h |
| 4848h | DDRSS_PHY_530 | DDR PHY Register 530 | 0299 4848h |
| 484Ch | DDRSS_PHY_531 | DDR PHY Register 531 | 0299 484Ch |
| 4850h | DDRSS_PHY_532 | DDR PHY Register 532 | 0299 4850h |
| 4854h | DDRSS_PHY_533 | DDR PHY Register 533 | 0299 4854h |
| 4858h | DDRSS_PHY_534 | DDR PHY Register 534 | 0299 4858h |
| 485Ch | DDRSS_PHY_535 | DDR PHY Register 535 | 0299 485Ch |
| 4860h | DDRSS_PHY_536 | DDR PHY Register 536 | 0299 4860h |
| 4864h | DDRSS_PHY_537 | DDR PHY Register 537 | 0299 4864h |
| 4868h | DDRSS_PHY_538 | DDR PHY Register 538 | 0299 4868h |
| 486Ch | DDRSS_PHY_539 | DDR PHY Register 539 | 0299 486Ch |
| 4870h | DDRSS_PHY_540 | DDR PHY Register 540 | 0299 4870h |
| 4874h | DDRSS_PHY_541 | DDR PHY Register 541 | 0299 4874h |
| 4878h | DDRSS_PHY_542 | DDR PHY Register 542 | 0299 4878h |
| 487Ch | DDRSS_PHY_543 | DDR PHY Register 543 | 0299 487Ch |
| 4880h | DDRSS_PHY_544 | DDR PHY Register 544 | 0299 4880h |
| 4884h | DDRSS_PHY_545 | DDR PHY Register 545 | 0299 4884h |
| 4888h | DDRSS_PHY_546 | DDR PHY Register 546 | 0299 4888h |
| 488Ch | DDRSS_PHY_547 | DDR PHY Register 547 | 0299 488Ch |
| 4890h | DDRSS_PHY_548 | DDR PHY Register 548 | 0299 4890h |
| 4894h | DDRSS_PHY_549 | DDR PHY Register 549 | 0299 4894h |
| 4898h | DDRSS_PHY_550 | DDR PHY Register 550 | 0299 4898h |
| 489Ch | DDRSS_PHY_551 | DDR PHY Register 551 | 0299 489Ch |
| 48A0h | DDRSS_PHY_552 | DDR PHY Register 552 | 0299 48A0h |
| 48A4h | DDRSS_PHY_553 | DDR PHY Register 553 | 0299 48A4h |
| 48A8h | DDRSS_PHY_554 | DDR PHY Register 554 | 0299 48A8h |
| 48ACh | DDRSS_PHY_555 | DDR PHY Register 555 | 0299 48ACh |
| 48B0h | DDRSS_PHY_556 | DDR PHY Register 556 | 0299 48B0h |
| 48B4h | DDRSS_PHY_557 | DDR PHY Register 557 | 0299 48B4h |
| 48B8h | DDRSS_PHY_558 | DDR PHY Register 558 | 0299 48B8h |
| 48BCh | DDRSS_PHY_559 | DDR PHY Register 559 | 0299 48BCh |
| 48C0h | DDRSS_PHY_560 | DDR PHY Register 560 | 0299 48C0h |
| 48C4h | DDRSS_PHY_561 | DDR PHY Register 561 | 0299 48C4h |
| 48C8h | DDRSS_PHY_562 | DDR PHY Register 562 | 0299 48C8h |
| 48CCh | DDRSS_PHY_563 | DDR PHY Register 563 | 0299 48CCh |
| 48D0h | DDRSS_PHY_564 | DDR PHY Register 564 | 0299 48D0h |
| 48D4h | DDRSS_PHY_565 | DDR PHY Register 565 | 0299 48D4h |
| 48D8h | DDRSS_PHY_566 | DDR PHY Register 566 | 0299 48D8h |
| 48DCh | DDRSS_PHY_567 | DDR PHY Register 567 | 0299 48DCh |
| 48E0h | DDRSS_PHY_568 | DDR PHY Register 568 | 0299 48E0h |
| 48E4h | DDRSS_PHY_569 | DDR PHY Register 569 | 0299 48E4h |
| 48E8h | DDRSS_PHY_570 | DDR PHY Register 570 | 0299 48E8h |
| 48ECh | DDRSS_PHY_571 | DDR PHY Register 571 | 0299 48ECh |
| 48F0h | DDRSS_PHY_572 | DDR PHY Register 572 | 0299 48F0h |
| 48F4h | DDRSS_PHY_573 | DDR PHY Register 573 | 0299 48F4h |
| 48F8h | DDRSS_PHY_574 | DDR PHY Register 574 | 0299 48F8h |
| 48FCh | DDRSS_PHY_575 | DDR PHY Register 575 | 0299 48FCh |
| 4900h | DDRSS_PHY_576 | DDR PHY Register 576 | 0299 4900h |
| 4904h | DDRSS_PHY_577 | DDR PHY Register 577 | 0299 4904h |
| 4908h | DDRSS_PHY_578 | DDR PHY Register 578 | 0299 4908h |
| 490Ch | DDRSS_PHY_579 | DDR PHY Register 579 | 0299 490Ch |
| 4910h | DDRSS_PHY_580 | DDR PHY Register 580 | 0299 4910h |
| 4914h | DDRSS_PHY_581 | DDR PHY Register 581 | 0299 4914h |
| 4918h | DDRSS_PHY_582 | DDR PHY Register 582 | 0299 4918h |
| 491Ch | DDRSS_PHY_583 | DDR PHY Register 583 | 0299 491Ch |
| 4920h | DDRSS_PHY_584 | DDR PHY Register 584 | 0299 4920h |
| 4924h | DDRSS_PHY_585 | DDR PHY Register 585 | 0299 4924h |
| 4928h | DDRSS_PHY_586 | DDR PHY Register 586 | 0299 4928h |
| 492Ch | DDRSS_PHY_587 | DDR PHY Register 587 | 0299 492Ch |
| 4930h | DDRSS_PHY_588 | DDR PHY Register 588 | 0299 4930h |
| 4934h | DDRSS_PHY_589 | DDR PHY Register 589 | 0299 4934h |
| 4938h | DDRSS_PHY_590 | DDR PHY Register 590 | 0299 4938h |
| 493Ch | DDRSS_PHY_591 | DDR PHY Register 591 | 0299 493Ch |
| 4940h | DDRSS_PHY_592 | DDR PHY Register 592 | 0299 4940h |
| 4944h | DDRSS_PHY_593 | DDR PHY Register 593 | 0299 4944h |
| 4948h | DDRSS_PHY_594 | DDR PHY Register 594 | 0299 4948h |
| 494Ch | DDRSS_PHY_595 | DDR PHY Register 595 | 0299 494Ch |
| 4950h | DDRSS_PHY_596 | DDR PHY Register 596 | 0299 4950h |
| 4954h | DDRSS_PHY_597 | DDR PHY Register 597 | 0299 4954h |
| 4958h | DDRSS_PHY_598 | DDR PHY Register 598 | 0299 4958h |
| 495Ch | DDRSS_PHY_599 | DDR PHY Register 599 | 0299 495Ch |
| 4960h | DDRSS_PHY_600 | DDR PHY Register 600 | 0299 4960h |
| 4964h | DDRSS_PHY_601 | DDR PHY Register 601 | 0299 4964h |
| 4968h | DDRSS_PHY_602 | DDR PHY Register 602 | 0299 4968h |
| 496Ch | DDRSS_PHY_603 | DDR PHY Register 603 | 0299 496Ch |
| 4970h | DDRSS_PHY_604 | DDR PHY Register 604 | 0299 4970h |
| 4974h | DDRSS_PHY_605 | DDR PHY Register 605 | 0299 4974h |
| 4978h | DDRSS_PHY_606 | DDR PHY Register 606 | 0299 4978h |
| 497Ch | DDRSS_PHY_607 | DDR PHY Register 607 | 0299 497Ch |
| 4980h | DDRSS_PHY_608 | DDR PHY Register 608 | 0299 4980h |
| 4984h | DDRSS_PHY_609 | DDR PHY Register 609 | 0299 4984h |
| 4988h | DDRSS_PHY_610 | DDR PHY Register 610 | 0299 4988h |
| 498Ch | DDRSS_PHY_611 | DDR PHY Register 611 | 0299 498Ch |
| 4990h | DDRSS_PHY_612 | DDR PHY Register 612 | 0299 4990h |
| 4994h | DDRSS_PHY_613 | DDR PHY Register 613 | 0299 4994h |
| 4998h | DDRSS_PHY_614 | DDR PHY Register 614 | 0299 4998h |
| 499Ch | DDRSS_PHY_615 | DDR PHY Register 615 | 0299 499Ch |
| 49A0h | DDRSS_PHY_616 | DDR PHY Register 616 | 0299 49A0h |
| 49A4h | DDRSS_PHY_617 | DDR PHY Register 617 | 0299 49A4h |
| 49A8h | DDRSS_PHY_618 | DDR PHY Register 618 | 0299 49A8h |
| 49ACh | DDRSS_PHY_619 | DDR PHY Register 619 | 0299 49ACh |
| 49B0h | DDRSS_PHY_620 | DDR PHY Register 620 | 0299 49B0h |
| 49B4h | DDRSS_PHY_621 | DDR PHY Register 621 | 0299 49B4h |
| 49B8h | DDRSS_PHY_622 | DDR PHY Register 622 | 0299 49B8h |
| 49BCh | DDRSS_PHY_623 | DDR PHY Register 623 | 0299 49BCh |
| 49C0h | DDRSS_PHY_624 | DDR PHY Register 624 | 0299 49C0h |
| 49C4h | DDRSS_PHY_625 | DDR PHY Register 625 | 0299 49C4h |
| 49C8h | DDRSS_PHY_626 | DDR PHY Register 626 | 0299 49C8h |
| 49CCh | DDRSS_PHY_627 | DDR PHY Register 627 | 0299 49CCh |
| 49D0h | DDRSS_PHY_628 | DDR PHY Register 628 | 0299 49D0h |
| 49D4h | DDRSS_PHY_629 | DDR PHY Register 629 | 0299 49D4h |
| 49D8h | DDRSS_PHY_630 | DDR PHY Register 630 | 0299 49D8h |
| 49DCh | DDRSS_PHY_631 | DDR PHY Register 631 | 0299 49DCh |
| 49E0h | DDRSS_PHY_632 | DDR PHY Register 632 | 0299 49E0h |
| 49E4h | DDRSS_PHY_633 | DDR PHY Register 633 | 0299 49E4h |
| 49E8h | DDRSS_PHY_634 | DDR PHY Register 634 | 0299 49E8h |
| 49ECh | DDRSS_PHY_635 | DDR PHY Register 635 | 0299 49ECh |
| 49F0h | DDRSS_PHY_636 | DDR PHY Register 636 | 0299 49F0h |
| 49F4h | DDRSS_PHY_637 | DDR PHY Register 637 | 0299 49F4h |
| 49F8h | DDRSS_PHY_638 | DDR PHY Register 638 | 0299 49F8h |
| 49FCh | DDRSS_PHY_639 | DDR PHY Register 639 | 0299 49FCh |
| 4A00h | DDRSS_PHY_640 | DDR PHY Register 640 | 0299 4A00h |
| 4A04h | DDRSS_PHY_641 | DDR PHY Register 641 | 0299 4A04h |
| 4A08h | DDRSS_PHY_642 | DDR PHY Register 642 | 0299 4A08h |
| 4A0Ch | DDRSS_PHY_643 | DDR PHY Register 643 | 0299 4A0Ch |
| 4A10h | DDRSS_PHY_644 | DDR PHY Register 644 | 0299 4A10h |
| 4A14h | DDRSS_PHY_645 | DDR PHY Register 645 | 0299 4A14h |
| 4A18h | DDRSS_PHY_646 | DDR PHY Register 646 | 0299 4A18h |
| 4A1Ch | DDRSS_PHY_647 | DDR PHY Register 647 | 0299 4A1Ch |
| 4A20h | DDRSS_PHY_648 | DDR PHY Register 648 | 0299 4A20h |
| 4A24h | DDRSS_PHY_649 | DDR PHY Register 649 | 0299 4A24h |
| 4A28h | DDRSS_PHY_650 | DDR PHY Register 650 | 0299 4A28h |
| 4A2Ch | DDRSS_PHY_651 | DDR PHY Register 651 | 0299 4A2Ch |
| 4C00h | DDRSS_PHY_768 | DDR PHY Register 768 | 0299 4C00h |
| 4C04h | DDRSS_PHY_769 | DDR PHY Register 769 | 0299 4C04h |
| 4C08h | DDRSS_PHY_770 | DDR PHY Register 770 | 0299 4C08h |
| 4C0Ch | DDRSS_PHY_771 | DDR PHY Register 771 | 0299 4C0Ch |
| 4C10h | DDRSS_PHY_772 | DDR PHY Register 772 | 0299 4C10h |
| 4C14h | DDRSS_PHY_773 | DDR PHY Register 773 | 0299 4C14h |
| 4C18h | DDRSS_PHY_774 | DDR PHY Register 774 | 0299 4C18h |
| 4C1Ch | DDRSS_PHY_775 | DDR PHY Register 775 | 0299 4C1Ch |
| 4C20h | DDRSS_PHY_776 | DDR PHY Register 776 | 0299 4C20h |
| 4C24h | DDRSS_PHY_777 | DDR PHY Register 777 | 0299 4C24h |
| 4C28h | DDRSS_PHY_778 | DDR PHY Register 778 | 0299 4C28h |
| 4C2Ch | DDRSS_PHY_779 | DDR PHY Register 779 | 0299 4C2Ch |
| 4C30h | DDRSS_PHY_780 | DDR PHY Register 780 | 0299 4C30h |
| 4C34h | DDRSS_PHY_781 | DDR PHY Register 781 | 0299 4C34h |
| 4C38h | DDRSS_PHY_782 | DDR PHY Register 782 | 0299 4C38h |
| 4C3Ch | DDRSS_PHY_783 | DDR PHY Register 783 | 0299 4C3Ch |
| 4C40h | DDRSS_PHY_784 | DDR PHY Register 784 | 0299 4C40h |
| 4C44h | DDRSS_PHY_785 | DDR PHY Register 785 | 0299 4C44h |
| 4C48h | DDRSS_PHY_786 | DDR PHY Register 786 | 0299 4C48h |
| 4C4Ch | DDRSS_PHY_787 | DDR PHY Register 787 | 0299 4C4Ch |
| 4C50h | DDRSS_PHY_788 | DDR PHY Register 788 | 0299 4C50h |
| 4C54h | DDRSS_PHY_789 | DDR PHY Register 789 | 0299 4C54h |
| 4C58h | DDRSS_PHY_790 | DDR PHY Register 790 | 0299 4C58h |
| 4C5Ch | DDRSS_PHY_791 | DDR PHY Register 791 | 0299 4C5Ch |
| 4C60h | DDRSS_PHY_792 | DDR PHY Register 792 | 0299 4C60h |
| 4C64h | DDRSS_PHY_793 | DDR PHY Register 793 | 0299 4C64h |
| 4C68h | DDRSS_PHY_794 | DDR PHY Register 794 | 0299 4C68h |
| 4C6Ch | DDRSS_PHY_795 | DDR PHY Register 795 | 0299 4C6Ch |
| 4C70h | DDRSS_PHY_796 | DDR PHY Register 796 | 0299 4C70h |
| 4C74h | DDRSS_PHY_797 | DDR PHY Register 797 | 0299 4C74h |
| 4C78h | DDRSS_PHY_798 | DDR PHY Register 798 | 0299 4C78h |
| 4C7Ch | DDRSS_PHY_799 | DDR PHY Register 799 | 0299 4C7Ch |
| 4C80h | DDRSS_PHY_800 | DDR PHY Register 800 | 0299 4C80h |
| 4C84h | DDRSS_PHY_801 | DDR PHY Register 801 | 0299 4C84h |
| 4C88h | DDRSS_PHY_802 | DDR PHY Register 802 | 0299 4C88h |
| 4C8Ch | DDRSS_PHY_803 | DDR PHY Register 803 | 0299 4C8Ch |
| 4C90h | DDRSS_PHY_804 | DDR PHY Register 804 | 0299 4C90h |
| 4C94h | DDRSS_PHY_805 | DDR PHY Register 805 | 0299 4C94h |
| 4C98h | DDRSS_PHY_806 | DDR PHY Register 806 | 0299 4C98h |
| 4C9Ch | DDRSS_PHY_807 | DDR PHY Register 807 | 0299 4C9Ch |
| 4CA0h | DDRSS_PHY_808 | DDR PHY Register 808 | 0299 4CA0h |
| 4CA4h | DDRSS_PHY_809 | DDR PHY Register 809 | 0299 4CA4h |
| 4CA8h | DDRSS_PHY_810 | DDR PHY Register 810 | 0299 4CA8h |
| 4CACh | DDRSS_PHY_811 | DDR PHY Register 811 | 0299 4CACh |
| 4CB0h | DDRSS_PHY_812 | DDR PHY Register 812 | 0299 4CB0h |
| 4CB4h | DDRSS_PHY_813 | DDR PHY Register 813 | 0299 4CB4h |
| 4CB8h | DDRSS_PHY_814 | DDR PHY Register 814 | 0299 4CB8h |
| 4CBCh | DDRSS_PHY_815 | DDR PHY Register 815 | 0299 4CBCh |
| 4CC0h | DDRSS_PHY_816 | DDR PHY Register 816 | 0299 4CC0h |
| 4CC4h | DDRSS_PHY_817 | DDR PHY Register 817 | 0299 4CC4h |
| 4CC8h | DDRSS_PHY_818 | DDR PHY Register 818 | 0299 4CC8h |
| 4CCCh | DDRSS_PHY_819 | DDR PHY Register 819 | 0299 4CCCh |
| 4CD0h | DDRSS_PHY_820 | DDR PHY Register 820 | 0299 4CD0h |
| 4CD4h | DDRSS_PHY_821 | DDR PHY Register 821 | 0299 4CD4h |
| 4CD8h | DDRSS_PHY_822 | DDR PHY Register 822 | 0299 4CD8h |
| 4CDCh | DDRSS_PHY_823 | DDR PHY Register 823 | 0299 4CDCh |
| 4CE0h | DDRSS_PHY_824 | DDR PHY Register 824 | 0299 4CE0h |
| 4CE4h | DDRSS_PHY_825 | DDR PHY Register 825 | 0299 4CE4h |
| 4CE8h | DDRSS_PHY_826 | DDR PHY Register 826 | 0299 4CE8h |
| 4CECh | DDRSS_PHY_827 | DDR PHY Register 827 | 0299 4CECh |
| 4CF0h | DDRSS_PHY_828 | DDR PHY Register 828 | 0299 4CF0h |
| 4CF4h | DDRSS_PHY_829 | DDR PHY Register 829 | 0299 4CF4h |
| 4CF8h | DDRSS_PHY_830 | DDR PHY Register 830 | 0299 4CF8h |
| 4CFCh | DDRSS_PHY_831 | DDR PHY Register 831 | 0299 4CFCh |
| 4D00h | DDRSS_PHY_832 | DDR PHY Register 832 | 0299 4D00h |
| 4D04h | DDRSS_PHY_833 | DDR PHY Register 833 | 0299 4D04h |
| 4D08h | DDRSS_PHY_834 | DDR PHY Register 834 | 0299 4D08h |
| 4D0Ch | DDRSS_PHY_835 | DDR PHY Register 835 | 0299 4D0Ch |
| 4D10h | DDRSS_PHY_836 | DDR PHY Register 836 | 0299 4D10h |
| 4D14h | DDRSS_PHY_837 | DDR PHY Register 837 | 0299 4D14h |
| 4D18h | DDRSS_PHY_838 | DDR PHY Register 838 | 0299 4D18h |
| 4D1Ch | DDRSS_PHY_839 | DDR PHY Register 839 | 0299 4D1Ch |
| 4D20h | DDRSS_PHY_840 | DDR PHY Register 840 | 0299 4D20h |
| 4D24h | DDRSS_PHY_841 | DDR PHY Register 841 | 0299 4D24h |
| 4D28h | DDRSS_PHY_842 | DDR PHY Register 842 | 0299 4D28h |
| 4D2Ch | DDRSS_PHY_843 | DDR PHY Register 843 | 0299 4D2Ch |
| 4D30h | DDRSS_PHY_844 | DDR PHY Register 844 | 0299 4D30h |
| 4D34h | DDRSS_PHY_845 | DDR PHY Register 845 | 0299 4D34h |
| 4D38h | DDRSS_PHY_846 | DDR PHY Register 846 | 0299 4D38h |
| 4D3Ch | DDRSS_PHY_847 | DDR PHY Register 847 | 0299 4D3Ch |
| 4D40h | DDRSS_PHY_848 | DDR PHY Register 848 | 0299 4D40h |
| 4D44h | DDRSS_PHY_849 | DDR PHY Register 849 | 0299 4D44h |
| 4D48h | DDRSS_PHY_850 | DDR PHY Register 850 | 0299 4D48h |
| 4D4Ch | DDRSS_PHY_851 | DDR PHY Register 851 | 0299 4D4Ch |
| 4D50h | DDRSS_PHY_852 | DDR PHY Register 852 | 0299 4D50h |
| 4D54h | DDRSS_PHY_853 | DDR PHY Register 853 | 0299 4D54h |
| 4D58h | DDRSS_PHY_854 | DDR PHY Register 854 | 0299 4D58h |
| 4D5Ch | DDRSS_PHY_855 | DDR PHY Register 855 | 0299 4D5Ch |
| 4D60h | DDRSS_PHY_856 | DDR PHY Register 856 | 0299 4D60h |
| 4D64h | DDRSS_PHY_857 | DDR PHY Register 857 | 0299 4D64h |
| 4D68h | DDRSS_PHY_858 | DDR PHY Register 858 | 0299 4D68h |
| 4D6Ch | DDRSS_PHY_859 | DDR PHY Register 859 | 0299 4D6Ch |
| 4D70h | DDRSS_PHY_860 | DDR PHY Register 860 | 0299 4D70h |
| 4D74h | DDRSS_PHY_861 | DDR PHY Register 861 | 0299 4D74h |
| 4D78h | DDRSS_PHY_862 | DDR PHY Register 862 | 0299 4D78h |
| 4D7Ch | DDRSS_PHY_863 | DDR PHY Register 863 | 0299 4D7Ch |
| 4D80h | DDRSS_PHY_864 | DDR PHY Register 864 | 0299 4D80h |
| 4D84h | DDRSS_PHY_865 | DDR PHY Register 865 | 0299 4D84h |
| 4D88h | DDRSS_PHY_866 | DDR PHY Register 866 | 0299 4D88h |
| 4D8Ch | DDRSS_PHY_867 | DDR PHY Register 867 | 0299 4D8Ch |
| 4D90h | DDRSS_PHY_868 | DDR PHY Register 868 | 0299 4D90h |
| 4D94h | DDRSS_PHY_869 | DDR PHY Register 869 | 0299 4D94h |
| 4D98h | DDRSS_PHY_870 | DDR PHY Register 870 | 0299 4D98h |
| 4D9Ch | DDRSS_PHY_871 | DDR PHY Register 871 | 0299 4D9Ch |
| 4DA0h | DDRSS_PHY_872 | DDR PHY Register 872 | 0299 4DA0h |
| 4DA4h | DDRSS_PHY_873 | DDR PHY Register 873 | 0299 4DA4h |
| 4DA8h | DDRSS_PHY_874 | DDR PHY Register 874 | 0299 4DA8h |
| 4DACh | DDRSS_PHY_875 | DDR PHY Register 875 | 0299 4DACh |
| 4DB0h | DDRSS_PHY_876 | DDR PHY Register 876 | 0299 4DB0h |
| 4DB4h | DDRSS_PHY_877 | DDR PHY Register 877 | 0299 4DB4h |
| 4DB8h | DDRSS_PHY_878 | DDR PHY Register 878 | 0299 4DB8h |
| 4DBCh | DDRSS_PHY_879 | DDR PHY Register 879 | 0299 4DBCh |
| 4DC0h | DDRSS_PHY_880 | DDR PHY Register 880 | 0299 4DC0h |
| 4DC4h | DDRSS_PHY_881 | DDR PHY Register 881 | 0299 4DC4h |
| 4DC8h | DDRSS_PHY_882 | DDR PHY Register 882 | 0299 4DC8h |
| 4DCCh | DDRSS_PHY_883 | DDR PHY Register 883 | 0299 4DCCh |
| 4DD0h | DDRSS_PHY_884 | DDR PHY Register 884 | 0299 4DD0h |
| 4DD4h | DDRSS_PHY_885 | DDR PHY Register 885 | 0299 4DD4h |
| 4DD8h | DDRSS_PHY_886 | DDR PHY Register 886 | 0299 4DD8h |
| 4DDCh | DDRSS_PHY_887 | DDR PHY Register 887 | 0299 4DDCh |
| 4DE0h | DDRSS_PHY_888 | DDR PHY Register 888 | 0299 4DE0h |
| 4DE4h | DDRSS_PHY_889 | DDR PHY Register 889 | 0299 4DE4h |
| 4DE8h | DDRSS_PHY_890 | DDR PHY Register 890 | 0299 4DE8h |
| 4DECh | DDRSS_PHY_891 | DDR PHY Register 891 | 0299 4DECh |
| 4DF0h | DDRSS_PHY_892 | DDR PHY Register 892 | 0299 4DF0h |
| 4DF4h | DDRSS_PHY_893 | DDR PHY Register 893 | 0299 4DF4h |
| 4DF8h | DDRSS_PHY_894 | DDR PHY Register 894 | 0299 4DF8h |
| 4DFCh | DDRSS_PHY_895 | DDR PHY Register 895 | 0299 4DFCh |
| 4E00h | DDRSS_PHY_896 | DDR PHY Register 896 | 0299 4E00h |
| 4E04h | DDRSS_PHY_897 | DDR PHY Register 897 | 0299 4E04h |
| 4E08h | DDRSS_PHY_898 | DDR PHY Register 898 | 0299 4E08h |
| 4E0Ch | DDRSS_PHY_899 | DDR PHY Register 899 | 0299 4E0Ch |
| 4E10h | DDRSS_PHY_900 | DDR PHY Register 900 | 0299 4E10h |
| 4E14h | DDRSS_PHY_901 | DDR PHY Register 901 | 0299 4E14h |
| 4E18h | DDRSS_PHY_902 | DDR PHY Register 902 | 0299 4E18h |
| 4E1Ch | DDRSS_PHY_903 | DDR PHY Register 903 | 0299 4E1Ch |
| 4E20h | DDRSS_PHY_904 | DDR PHY Register 904 | 0299 4E20h |
| 4E24h | DDRSS_PHY_905 | DDR PHY Register 905 | 0299 4E24h |
| 4E28h | DDRSS_PHY_906 | DDR PHY Register 906 | 0299 4E28h |
| 4E2Ch | DDRSS_PHY_907 | DDR PHY Register 907 | 0299 4E2Ch |
| 5000h | DDRSS_PHY_1024 | DDR PHY Register 1024 | 0299 5000h |
| 5004h | DDRSS_PHY_1025 | DDR PHY Register 1025 | 0299 5004h |
| 5008h | DDRSS_PHY_1026 | DDR PHY Register 1026 | 0299 5008h |
| 500Ch | DDRSS_PHY_1027 | DDR PHY Register 1027 | 0299 500Ch |
| 5010h | DDRSS_PHY_1028 | DDR PHY Register 1028 | 0299 5010h |
| 5014h | DDRSS_PHY_1029 | DDR PHY Register 1029 | 0299 5014h |
| 5018h | DDRSS_PHY_1030 | DDR PHY Register 1030 | 0299 5018h |
| 501Ch | DDRSS_PHY_1031 | DDR PHY Register 1031 | 0299 501Ch |
| 5020h | DDRSS_PHY_1032 | DDR PHY Register 1032 | 0299 5020h |
| 5024h | DDRSS_PHY_1033 | DDR PHY Register 1033 | 0299 5024h |
| 5028h | DDRSS_PHY_1034 | DDR PHY Register 1034 | 0299 5028h |
| 502Ch | DDRSS_PHY_1035 | DDR PHY Register 1035 | 0299 502Ch |
| 5030h | DDRSS_PHY_1036 | DDR PHY Register 1036 | 0299 5030h |
| 5034h | DDRSS_PHY_1037 | DDR PHY Register 1037 | 0299 5034h |
| 5038h | DDRSS_PHY_1038 | DDR PHY Register 1038 | 0299 5038h |
| 503Ch | DDRSS_PHY_1039 | DDR PHY Register 1039 | 0299 503Ch |
| 5040h | DDRSS_PHY_1040 | DDR PHY Register 1040 | 0299 5040h |
| 5044h | DDRSS_PHY_1041 | DDR PHY Register 1041 | 0299 5044h |
| 5048h | DDRSS_PHY_1042 | DDR PHY Register 1042 | 0299 5048h |
| 504Ch | DDRSS_PHY_1043 | DDR PHY Register 1043 | 0299 504Ch |
| 5050h | DDRSS_PHY_1044 | DDR PHY Register 1044 | 0299 5050h |
| 5054h | DDRSS_PHY_1045 | DDR PHY Register 1045 | 0299 5054h |
| 5058h | DDRSS_PHY_1046 | DDR PHY Register 1046 | 0299 5058h |
| 505Ch | DDRSS_PHY_1047 | DDR PHY Register 1047 | 0299 505Ch |
| 5060h | DDRSS_PHY_1048 | DDR PHY Register 1048 | 0299 5060h |
| 5064h | DDRSS_PHY_1049 | DDR PHY Register 1049 | 0299 5064h |
| 5068h | DDRSS_PHY_1050 | DDR PHY Register 1050 | 0299 5068h |
| 506Ch | DDRSS_PHY_1051 | DDR PHY Register 1051 | 0299 506Ch |
| 5070h | DDRSS_PHY_1052 | DDR PHY Register 1052 | 0299 5070h |
| 5074h | DDRSS_PHY_1053 | DDR PHY Register 1053 | 0299 5074h |
| 5078h | DDRSS_PHY_1054 | DDR PHY Register 1054 | 0299 5078h |
| 507Ch | DDRSS_PHY_1055 | DDR PHY Register 1055 | 0299 507Ch |
| 5080h | DDRSS_PHY_1056 | DDR PHY Register 1056 | 0299 5080h |
| 5084h | DDRSS_PHY_1057 | DDR PHY Register 1057 | 0299 5084h |
| 5088h | DDRSS_PHY_1058 | DDR PHY Register 1058 | 0299 5088h |
| 508Ch | DDRSS_PHY_1059 | DDR PHY Register 1059 | 0299 508Ch |
| 5090h | DDRSS_PHY_1060 | DDR PHY Register 1060 | 0299 5090h |
| 5094h | DDRSS_PHY_1061 | DDR PHY Register 1061 | 0299 5094h |
| 5098h | DDRSS_PHY_1062 | DDR PHY Register 1062 | 0299 5098h |
| 509Ch | DDRSS_PHY_1063 | DDR PHY Register 1063 | 0299 509Ch |
| 50A0h | DDRSS_PHY_1064 | DDR PHY Register 1064 | 0299 50A0h |
| 50A4h | DDRSS_PHY_1065 | DDR PHY Register 1065 | 0299 50A4h |
| 50A8h | DDRSS_PHY_1066 | DDR PHY Register 1066 | 0299 50A8h |
| 50ACh | DDRSS_PHY_1067 | DDR PHY Register 1067 | 0299 50ACh |
| 50B0h | DDRSS_PHY_1068 | DDR PHY Register 1068 | 0299 50B0h |
| 50B4h | DDRSS_PHY_1069 | DDR PHY Register 1069 | 0299 50B4h |
| 50B8h | DDRSS_PHY_1070 | DDR PHY Register 1070 | 0299 50B8h |
| 50BCh | DDRSS_PHY_1071 | DDR PHY Register 1071 | 0299 50BCh |
| 50C0h | DDRSS_PHY_1072 | DDR PHY Register 1072 | 0299 50C0h |
| 50C4h | DDRSS_PHY_1073 | DDR PHY Register 1073 | 0299 50C4h |
| 50C8h | DDRSS_PHY_1074 | DDR PHY Register 1074 | 0299 50C8h |
| 50CCh | DDRSS_PHY_1075 | DDR PHY Register 1075 | 0299 50CCh |
| 5400h | DDRSS_PHY_1280 | DDR PHY Register 1280 | 0299 5400h |
| 5404h | DDRSS_PHY_1281 | DDR PHY Register 1281 | 0299 5404h |
| 5408h | DDRSS_PHY_1282 | DDR PHY Register 1282 | 0299 5408h |
| 540Ch | DDRSS_PHY_1283 | DDR PHY Register 1283 | 0299 540Ch |
| 5410h | DDRSS_PHY_1284 | DDR PHY Register 1284 | 0299 5410h |
| 5414h | DDRSS_PHY_1285 | DDR PHY Register 1285 | 0299 5414h |
| 5418h | DDRSS_PHY_1286 | DDR PHY Register 1286 | 0299 5418h |
| 541Ch | DDRSS_PHY_1287 | DDR PHY Register 1287 | 0299 541Ch |
| 5420h | DDRSS_PHY_1288 | DDR PHY Register 1288 | 0299 5420h |
| 5424h | DDRSS_PHY_1289 | DDR PHY Register 1289 | 0299 5424h |
| 5428h | DDRSS_PHY_1290 | DDR PHY Register 1290 | 0299 5428h |
| 542Ch | DDRSS_PHY_1291 | DDR PHY Register 1291 | 0299 542Ch |
| 5430h | DDRSS_PHY_1292 | DDR PHY Register 1292 | 0299 5430h |
| 5434h | DDRSS_PHY_1293 | DDR PHY Register 1293 | 0299 5434h |
| 5438h | DDRSS_PHY_1294 | DDR PHY Register 1294 | 0299 5438h |
| 543Ch | DDRSS_PHY_1295 | DDR PHY Register 1295 | 0299 543Ch |
| 5440h | DDRSS_PHY_1296 | DDR PHY Register 1296 | 0299 5440h |
| 5444h | DDRSS_PHY_1297 | DDR PHY Register 1297 | 0299 5444h |
| 5448h | DDRSS_PHY_1298 | DDR PHY Register 1298 | 0299 5448h |
| 544Ch | DDRSS_PHY_1299 | DDR PHY Register 1299 | 0299 544Ch |
| 5450h | DDRSS_PHY_1300 | DDR PHY Register 1300 | 0299 5450h |
| 5454h | DDRSS_PHY_1301 | DDR PHY Register 1301 | 0299 5454h |
| 5458h | DDRSS_PHY_1302 | DDR PHY Register 1302 | 0299 5458h |
| 545Ch | DDRSS_PHY_1303 | DDR PHY Register 1303 | 0299 545Ch |
| 5460h | DDRSS_PHY_1304 | DDR PHY Register 1304 | 0299 5460h |
| 5464h | DDRSS_PHY_1305 | DDR PHY Register 1305 | 0299 5464h |
| 5468h | DDRSS_PHY_1306 | DDR PHY Register 1306 | 0299 5468h |
| 546Ch | DDRSS_PHY_1307 | DDR PHY Register 1307 | 0299 546Ch |
| 5470h | DDRSS_PHY_1308 | DDR PHY Register 1308 | 0299 5470h |
| 5474h | DDRSS_PHY_1309 | DDR PHY Register 1309 | 0299 5474h |
| 5478h | DDRSS_PHY_1310 | DDR PHY Register 1310 | 0299 5478h |
| 547Ch | DDRSS_PHY_1311 | DDR PHY Register 1311 | 0299 547Ch |
| 5480h | DDRSS_PHY_1312 | DDR PHY Register 1312 | 0299 5480h |
| 5484h | DDRSS_PHY_1313 | DDR PHY Register 1313 | 0299 5484h |
| 5488h | DDRSS_PHY_1314 | DDR PHY Register 1314 | 0299 5488h |
| 548Ch | DDRSS_PHY_1315 | DDR PHY Register 1315 | 0299 548Ch |
| 5490h | DDRSS_PHY_1316 | DDR PHY Register 1316 | 0299 5490h |
| 5494h | DDRSS_PHY_1317 | DDR PHY Register 1317 | 0299 5494h |
| 5498h | DDRSS_PHY_1318 | DDR PHY Register 1318 | 0299 5498h |
| 549Ch | DDRSS_PHY_1319 | DDR PHY Register 1319 | 0299 549Ch |
| 54A0h | DDRSS_PHY_1320 | DDR PHY Register 1320 | 0299 54A0h |
| 54A4h | DDRSS_PHY_1321 | DDR PHY Register 1321 | 0299 54A4h |
| 54A8h | DDRSS_PHY_1322 | DDR PHY Register 1322 | 0299 54A8h |
| 54ACh | DDRSS_PHY_1323 | DDR PHY Register 1323 | 0299 54ACh |
| 54B0h | DDRSS_PHY_1324 | DDR PHY Register 1324 | 0299 54B0h |
| 54B4h | DDRSS_PHY_1325 | DDR PHY Register 1325 | 0299 54B4h |
| 54B8h | DDRSS_PHY_1326 | DDR PHY Register 1326 | 0299 54B8h |
| 54BCh | DDRSS_PHY_1327 | DDR PHY Register 1327 | 0299 54BCh |
| 54C0h | DDRSS_PHY_1328 | DDR PHY Register 1328 | 0299 54C0h |
| 54C4h | DDRSS_PHY_1329 | DDR PHY Register 1329 | 0299 54C4h |
| 54C8h | DDRSS_PHY_1330 | DDR PHY Register 1330 | 0299 54C8h |
| 54CCh | DDRSS_PHY_1331 | DDR PHY Register 1331 | 0299 54CCh |
| 54D0h | DDRSS_PHY_1332 | DDR PHY Register 1332 | 0299 54D0h |
| 54D4h | DDRSS_PHY_1333 | DDR PHY Register 1333 | 0299 54D4h |
| 54D8h | DDRSS_PHY_1334 | DDR PHY Register 1334 | 0299 54D8h |
| 54DCh | DDRSS_PHY_1335 | DDR PHY Register 1335 | 0299 54DCh |
| 54E0h | DDRSS_PHY_1336 | DDR PHY Register 1336 | 0299 54E0h |
| 54E4h | DDRSS_PHY_1337 | DDR PHY Register 1337 | 0299 54E4h |
| 54E8h | DDRSS_PHY_1338 | DDR PHY Register 1338 | 0299 54E8h |
| 54ECh | DDRSS_PHY_1339 | DDR PHY Register 1339 | 0299 54ECh |
| 54F0h | DDRSS_PHY_1340 | DDR PHY Register 1340 | 0299 54F0h |
| 54F4h | DDRSS_PHY_1341 | DDR PHY Register 1341 | 0299 54F4h |
| 54F8h | DDRSS_PHY_1342 | DDR PHY Register 1342 | 0299 54F8h |
| 54FCh | DDRSS_PHY_1343 | DDR PHY Register 1343 | 0299 54FCh |
| 5500h | DDRSS_PHY_1344 | DDR PHY Register 1344 | 0299 5500h |
| 5504h | DDRSS_PHY_1345 | DDR PHY Register 1345 | 0299 5504h |
| 5508h | DDRSS_PHY_1346 | DDR PHY Register 1346 | 0299 5508h |
| 550Ch | DDRSS_PHY_1347 | DDR PHY Register 1347 | 0299 550Ch |
| 5510h | DDRSS_PHY_1348 | DDR PHY Register 1348 | 0299 5510h |
| 5514h | DDRSS_PHY_1349 | DDR PHY Register 1349 | 0299 5514h |
| 5518h | DDRSS_PHY_1350 | DDR PHY Register 1350 | 0299 5518h |
| 551Ch | DDRSS_PHY_1351 | DDR PHY Register 1351 | 0299 551Ch |
| 5520h | DDRSS_PHY_1352 | DDR PHY Register 1352 | 0299 5520h |
| 5524h | DDRSS_PHY_1353 | DDR PHY Register 1353 | 0299 5524h |
| 5528h | DDRSS_PHY_1354 | DDR PHY Register 1354 | 0299 5528h |
| 552Ch | DDRSS_PHY_1355 | DDR PHY Register 1355 | 0299 552Ch |
| 5530h | DDRSS_PHY_1356 | DDR PHY Register 1356 | 0299 5530h |
| 5534h | DDRSS_PHY_1357 | DDR PHY Register 1357 | 0299 5534h |
| 5538h | DDRSS_PHY_1358 | DDR PHY Register 1358 | 0299 5538h |
| 553Ch | DDRSS_PHY_1359 | DDR PHY Register 1359 | 0299 553Ch |
| 5540h | DDRSS_PHY_1360 | DDR PHY Register 1360 | 0299 5540h |
| 5544h | DDRSS_PHY_1361 | DDR PHY Register 1361 | 0299 5544h |
| 5548h | DDRSS_PHY_1362 | DDR PHY Register 1362 | 0299 5548h |
| 554Ch | DDRSS_PHY_1363 | DDR PHY Register 1363 | 0299 554Ch |
| 5550h | DDRSS_PHY_1364 | DDR PHY Register 1364 | 0299 5550h |
| 5554h | DDRSS_PHY_1365 | DDR PHY Register 1365 | 0299 5554h |
| 5558h | DDRSS_PHY_1366 | DDR PHY Register 1366 | 0299 5558h |
| 555Ch | DDRSS_PHY_1367 | DDR PHY Register 1367 | 0299 555Ch |
| 5560h | DDRSS_PHY_1368 | DDR PHY Register 1368 | 0299 5560h |
| 5564h | DDRSS_PHY_1369 | DDR PHY Register 1369 | 0299 5564h |
| 5568h | DDRSS_PHY_1370 | DDR PHY Register 1370 | 0299 5568h |
| 556Ch | DDRSS_PHY_1371 | DDR PHY Register 1371 | 0299 556Ch |
| 5570h | DDRSS_PHY_1372 | DDR PHY Register 1372 | 0299 5570h |
| 5574h | DDRSS_PHY_1373 | DDR PHY Register 1373 | 0299 5574h |
| 5578h | DDRSS_PHY_1374 | DDR PHY Register 1374 | 0299 5578h |
| 557Ch | DDRSS_PHY_1375 | DDR PHY Register 1375 | 0299 557Ch |
| 5580h | DDRSS_PHY_1376 | DDR PHY Register 1376 | 0299 5580h |
| 5584h | DDRSS_PHY_1377 | DDR PHY Register 1377 | 0299 5584h |
| 5588h | DDRSS_PHY_1378 | DDR PHY Register 1378 | 0299 5588h |
| 558Ch | DDRSS_PHY_1379 | DDR PHY Register 1379 | 0299 558Ch |
| 5590h | DDRSS_PHY_1380 | DDR PHY Register 1380 | 0299 5590h |
| 5594h | DDRSS_PHY_1381 | DDR PHY Register 1381 | 0299 5594h |
| 5598h | DDRSS_PHY_1382 | DDR PHY Register 1382 | 0299 5598h |
| 559Ch | DDRSS_PHY_1383 | DDR PHY Register 1383 | 0299 559Ch |
| 55A0h | DDRSS_PHY_1384 | DDR PHY Register 1384 | 0299 55A0h |
| 55A4h | DDRSS_PHY_1385 | DDR PHY Register 1385 | 0299 55A4h |
| 55A8h | DDRSS_PHY_1386 | DDR PHY Register 1386 | 0299 55A8h |
| 55ACh | DDRSS_PHY_1387 | DDR PHY Register 1387 | 0299 55ACh |
| 55B0h | DDRSS_PHY_1388 | DDR PHY Register 1388 | 0299 55B0h |
| 55B4h | DDRSS_PHY_1389 | DDR PHY Register 1389 | 0299 55B4h |
| 55B8h | DDRSS_PHY_1390 | DDR PHY Register 1390 | 0299 55B8h |
| 55BCh | DDRSS_PHY_1391 | DDR PHY Register 1391 | 0299 55BCh |
| 55C0h | DDRSS_PHY_1392 | DDR PHY Register 1392 | 0299 55C0h |
| 55C4h | DDRSS_PHY_1393 | DDR PHY Register 1393 | 0299 55C4h |
| 55C8h | DDRSS_PHY_1394 | DDR PHY Register 1394 | 0299 55C8h |
| 55CCh | DDRSS_PHY_1395 | DDR PHY Register 1395 | 0299 55CCh |
| 55D0h | DDRSS_PHY_1396 | DDR PHY Register 1396 | 0299 55D0h |
| 55D4h | DDRSS_PHY_1397 | DDR PHY Register 1397 | 0299 55D4h |
| 55D8h | DDRSS_PHY_1398 | DDR PHY Register 1398 | 0299 55D8h |
| 55DCh | DDRSS_PHY_1399 | DDR PHY Register 1399 | 0299 55DCh |
| 55E0h | DDRSS_PHY_1400 | DDR PHY Register 1400 | 0299 55E0h |
| 55E4h | DDRSS_PHY_1401 | DDR PHY Register 1401 | 0299 55E4h |
| 55E8h | DDRSS_PHY_1402 | DDR PHY Register 1402 | 0299 55E8h |
| 55ECh | DDRSS_PHY_1403 | DDR PHY Register 1403 | 0299 55ECh |
| 55F0h | DDRSS_PHY_1404 | DDR PHY Register 1404 | 0299 55F0h |
| 55F4h | DDRSS_PHY_1405 | DDR PHY Register 1405 | 0299 55F4h |
| 55F8h | DDRSS_PHY_1406 | DDR PHY Register 1406 | 0299 55F8h |
| 55FCh | DDRSS_PHY_1407 | DDR PHY Register 1407 | 0299 55FCh |
| 5600h | DDRSS_PHY_1408 | DDR PHY Register 1408 | 0299 5600h |
| 5604h | DDRSS_PHY_1409 | DDR PHY Register 1409 | 0299 5604h |
| 5608h | DDRSS_PHY_1410 | DDR PHY Register 1410 | 0299 5608h |
| 560Ch | DDRSS_PHY_1411 | DDR PHY Register 1411 | 0299 560Ch |
| 5610h | DDRSS_PHY_1412 | DDR PHY Register 1412 | 0299 5610h |
| 5614h | DDRSS_PHY_1413 | DDR PHY Register 1413 | 0299 5614h |
| 5618h | DDRSS_PHY_1414 | DDR PHY Register 1414 | 0299 5618h |
| 561Ch | DDRSS_PHY_1415 | DDR PHY Register 1415 | 0299 561Ch |
| 5620h | DDRSS_PHY_1416 | DDR PHY Register 1416 | 0299 5620h |
| 5624h | DDRSS_PHY_1417 | DDR PHY Register 1417 | 0299 5624h |
| 5628h | DDRSS_PHY_1418 | DDR PHY Register 1418 | 0299 5628h |
| 562Ch | DDRSS_PHY_1419 | DDR PHY Register 1419 | 0299 562Ch |
| 5630h | DDRSS_PHY_1420 | DDR PHY Register 1420 | 0299 5630h |
| 5634h | DDRSS_PHY_1421 | DDR PHY Register 1421 | 0299 5634h |
| 5638h | DDRSS_PHY_1422 | DDR PHY Register 1422 | 0299 5638h |
DDRSS_PHY_0 is shown in Figure 8-838 and described in Table 8-1688.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_IO_PAD_DELAY_TIMING_BYPASS_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CLK_WR_BYPASS_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CLK_WR_BYPASS_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-16 | PHY_IO_PAD_DELAY_TIMING_BYPASS_0 | R/W | 0h | Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WR_BYPASS_SLAVE_DELAY_0 | R/W | 0h | Write data clock bypass mode slave delay setting for slice 0.} PADDING_BEFORE |
DDRSS_PHY_1 is shown in Figure 8-839 and described in Table 8-1690.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRITE_PATH_LAT_ADD_BYPASS_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R/W | X | |
| 18-16 | PHY_WRITE_PATH_LAT_ADD_BYPASS_0 | R/W | 0h | Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0 | R/W | 0h | Write DQS bypass mode slave delay setting for slice 0. |
DDRSS_PHY_2 is shown in Figure 8-840 and described in Table 8-1692.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CLK_BYPASS_OVERRIDE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_BYPASS_TWO_CYC_PREAMBLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_CLK_BYPASS_OVERRIDE_0 | R/W | 0h | Bypass mode override setting for slice 0. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_BYPASS_TWO_CYC_PREAMBLE_0 | R/W | 0h | Two_cycle_preamble for bypass mode for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0 | R/W | 0h | Read DQS bypass mode slave delay setting for slice 0. |
DDRSS_PHY_3 is shown in Figure 8-841 and described in Table 8-1694.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 400Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WRDQ3_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_WRDQ2_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQ1_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDQ0_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_SW_WRDQ3_SHIFT_0 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 0. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_SW_WRDQ2_SHIFT_0 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 0. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_SW_WRDQ1_SHIFT_0 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 0. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDQ0_SHIFT_0 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 0. |
DDRSS_PHY_4 is shown in Figure 8-842 and described in Table 8-1696.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WRDQ7_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_WRDQ6_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQ5_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDQ4_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_SW_WRDQ7_SHIFT_0 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 0. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_SW_WRDQ6_SHIFT_0 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 0. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_SW_WRDQ5_SHIFT_0 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 0. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDQ4_SHIFT_0 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 0. |
DDRSS_PHY_5 is shown in Figure 8-843 and described in Table 8-1698.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PER_CS_TRAINING_MULTICAST_EN_0 | ||||||
| R/W-X | R/W-1h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PER_RANK_CS_MAP_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQS_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDM_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_PER_CS_TRAINING_MULTICAST_EN_0 | R/W | 1h | When set, a register write will update parameters for all ranks at the same time in slice 0. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_PER_RANK_CS_MAP_0 | R/W | 0h | Per-rank CS map for slice 0. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_SW_WRDQS_SHIFT_0 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 0. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDM_SHIFT_0 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 0. |
DDRSS_PHY_6 is shown in Figure 8-844 and described in Table 8-1700.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_DLY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PER_CS_TRAINING_INDEX_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_LP4_BOOT_RDDATA_EN_DLY_0 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is early for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_PER_CS_TRAINING_INDEX_0 | R/W | 0h | For per-rank training, indicates which rank's paramters are read/written for slice 0. |
DDRSS_PHY_7 is shown in Figure 8-845 and described in Table 8-1702.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 401Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LP4_BOOT_RPTR_UPDATE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 0. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0 | R/W | 0h | For LPDDR4 boot frequency, write path clock gating disable for slice 0. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_LP4_BOOT_RPTR_UPDATE_0 | R/W | 0h | For LPDDR4 boot frequency, the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 0. |
DDRSS_PHY_8 is shown in Figure 8-846 and described in Table 8-1704.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LPBK_DFX_TIMEOUT_EN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LPBK_CONTROL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_LPBK_CONTROL_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CTRL_LPBK_EN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_LPBK_DFX_TIMEOUT_EN_0 | R/W | 0h | Loopback read only test timeout mechanism enable for slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16-8 | PHY_LPBK_CONTROL_0 | R/W | 0h | Loopback control bits for slice 0. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_CTRL_LPBK_EN_0 | R/W | 0h | Loopback control en for slice 0. |
DDRSS_PHY_9 is shown in Figure 8-847 and described in Table 8-1706.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4024h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_AUTO_TIMING_MARGIN_CONTROL_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_AUTO_TIMING_MARGIN_CONTROL_0 | R/W | 0h | Auto timing marging control bits for slice 0. |
DDRSS_PHY_10 is shown in Figure 8-848 and described in Table 8-1708.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4028h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_AUTO_TIMING_MARGIN_OBS_0 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R | X | |
| 27-0 | PHY_AUTO_TIMING_MARGIN_OBS_0 | R | 0h | Observation register for the auto_timing_margin for slice 0. |
DDRSS_PHY_11 is shown in Figure 8-849 and described in Table 8-1710.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 402Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_MULTI_PATT_ENABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PRBS_PATTERN_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PRBS_PATTERN_MASK_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PRBS_PATTERN_START_0 | ||||||
| R/W-X | R/W-1h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RDLVL_MULTI_PATT_ENABLE_0 | R/W | 0h | Read Leveling Multi-pattern enable for slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16-8 | PHY_PRBS_PATTERN_MASK_0 | R/W | 0h | PRBS7 mask signal for slice 0. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_PRBS_PATTERN_START_0 | R/W | 1h | PRBS7 start pattern for slice 0. |
DDRSS_PHY_12 is shown in Figure 8-850 and described in Table 8-1712.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_VREF_TRAIN_OBS_0 | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_VREF_INITIAL_STEPSIZE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_MULTI_PATT_RST_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-23 | RESERVED | R/W | X | |
| 22-16 | PHY_VREF_TRAIN_OBS_0 | R | 0h | Observation register for best vref value for slice 0. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_VREF_INITIAL_STEPSIZE_0 | R/W | 0h | Data slice initial VREF training step size for slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_RDLVL_MULTI_PATT_RST_DISABLE_0 | R/W | 0h | Read Leveling read level windows disable reset for slice 0. |
DDRSS_PHY_13 is shown in Figure 8-851 and described in Table 8-1714.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4034h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_SNAP_OBS_REGS_0 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GATE_ERROR_DELAY_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | SC_PHY_SNAP_OBS_REGS_0 | W | 0h | Initiates a snapshot of the internal observation registers for slice 0. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GATE_ERROR_DELAY_SELECT_0 | R/W | 0h | Number of cycles to wait for the DQS gate to close before flagging an error for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0 | R/W | 0h | Read DQS data clock bypass mode slave delay setting for slice 0. |
DDRSS_PHY_14 is shown in Figure 8-852 and described in Table 8-1716.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4038h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_MEM_CLASS_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LPDDR_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL1_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL1_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_MEM_CLASS_0 | R/W | 0h | Indicates the type of DRAM for slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_LPDDR_0 | R/W | 0h | Adds a cycle of delay for the slice 0 to match the address slice. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_GATE_SMPL1_SLAVE_DELAY_0 | R/W | 0h | Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 0. |
DDRSS_PHY_15 is shown in Figure 8-853 and described in Table 8-1718.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 403Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | ON_FLY_GATE_ADJUST_EN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL2_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL2_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | ON_FLY_GATE_ADJUST_EN_0 | R/W | 0h | Control the on-the-fly gate adjustment for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_GATE_SMPL2_SLAVE_DELAY_0 | R/W | 0h | Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 0. |
DDRSS_PHY_16 is shown in Figure 8-854 and described in Table 8-1720.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_TRACKING_OBS_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_GATE_TRACKING_OBS_0 | R | 0h | Report the on-the-fly gate measurement result for slice 0. |
DDRSS_PHY_17 is shown in Figure 8-855 and described in Table 8-1722.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4044h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_PST_AMBLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DFI40_POLARITY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-8 | PHY_LP4_PST_AMBLE_0 | R/W | 0h | Controls the read postamble extension for LPDDR4 for slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DFI40_POLARITY_0 | R/W | 0h | Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 0. |
DDRSS_PHY_18 is shown in Figure 8-856 and described in Table 8-1724.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4048h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT8_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT8_0 | R/W | 0h | Read leveling pattern 8 data for slice 0. |
DDRSS_PHY_19 is shown in Figure 8-857 and described in Table 8-1726.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 404Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT9_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT9_0 | R/W | 0h | Read leveling pattern 9 data for slice 0. |
DDRSS_PHY_20 is shown in Figure 8-858 and described in Table 8-1728.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4050h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT10_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT10_0 | R/W | 0h | Read leveling pattern 10 data for slice 0. |
DDRSS_PHY_21 is shown in Figure 8-859 and described in Table 8-1730.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4054h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT11_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT11_0 | R/W | 0h | Read leveling pattern 11 data for slice 0. |
DDRSS_PHY_22 is shown in Figure 8-860 and described in Table 8-1732.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4058h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT12_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT12_0 | R/W | 0h | Read leveling pattern 12 data for slice 0. |
DDRSS_PHY_23 is shown in Figure 8-861 and described in Table 8-1734.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 405Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT13_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT13_0 | R/W | 0h | Read leveling pattern 13 data for slice 0. |
DDRSS_PHY_24 is shown in Figure 8-862 and described in Table 8-1736.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4060h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT14_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT14_0 | R/W | 0h | Read leveling pattern 14 data for slice 0. |
DDRSS_PHY_25 is shown in Figure 8-863 and described in Table 8-1738.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4064h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT15_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT15_0 | R/W | 0h | Read leveling pattern 15 data for slice 0. |
DDRSS_PHY_26 is shown in Figure 8-864 and described in Table 8-1740.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4068h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQ_ENC_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DLY_LOCK_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_FIFO_PTR_RST_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SLAVE_LOOP_CNT_UPDATE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_RDDQ_ENC_OBS_SELECT_0 | R/W | 0h | Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 0. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_MASTER_DLY_LOCK_OBS_SELECT_0 | R/W | 0h | Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_SW_FIFO_PTR_RST_DISABLE_0 | R/W | 0h | Disables automatic reset of the read entry FIFO pointers for slice 0. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_SLAVE_LOOP_CNT_UPDATE_0 | R/W | 0h | Reserved for future use for slice 0. |
DDRSS_PHY_27 is shown in Figure 8-865 and described in Table 8-1742.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 406Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_FIFO_PTR_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WR_SHIFT_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WR_ENC_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQS_DQ_ENC_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_FIFO_PTR_OBS_SELECT_0 | R/W | 0h | Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 0. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_WR_SHIFT_OBS_SELECT_0 | R/W | 0h | Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 0. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WR_ENC_OBS_SELECT_0 | R/W | 0h | Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 0. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_RDDQS_DQ_ENC_OBS_SELECT_0 | R/W | 0h | Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 0. |
DDRSS_PHY_28 is shown in Figure 8-866 and described in Table 8-1744.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4070h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_WRLVL_PER_START_0 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_ALGO_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_LVL_DEBUG_CONT_0 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LVL_DEBUG_MODE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_WRLVL_PER_START_0 | R/W | 0h | Observation register for write leveling status for slice 0. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_WRLVL_ALGO_0 | R/W | 0h | Write leveling algorithm selection for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8 | SC_PHY_LVL_DEBUG_CONT_0 | W | 0h | Allows the leveling state machine to advance (when in debug mode) for slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_LVL_DEBUG_MODE_0 | R/W | 0h | Enables leveling debug mode for slice 0. |
DDRSS_PHY_29 is shown in Figure 8-867 and described in Table 8-1746.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4074h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQ_MASK_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_UPDT_WAIT_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_CAPTURE_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | X | |
| 23-16 | PHY_DQ_MASK_0 | R/W | 0h | For ECC slice, should set this register to do DQ bit mask for slice 0. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WRLVL_UPDT_WAIT_CNT_0 | R/W | 0h | Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 0. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_WRLVL_CAPTURE_CNT_0 | R/W | 0h | Number of samples to take at each DQS slave delay setting during write leveling for slice 0. |
DDRSS_PHY_30 is shown in Figure 8-868 and described in Table 8-1748.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4078h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GTLVL_UPDT_WAIT_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_CAPTURE_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GTLVL_PER_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_PER_START_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_GTLVL_UPDT_WAIT_CNT_0 | R/W | 0h | Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 0. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_GTLVL_CAPTURE_CNT_0 | R/W | 0h | Number of samples to take at each DQS slave delay setting during gate training for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_PER_START_0 | R/W | 0h | Value to be added to the current gate delay position as the staring point for periodic gate training for slice 0. |
DDRSS_PHY_31 is shown in Figure 8-869 and described in Table 8-1750.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 407Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDLVL_OP_MODE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_UPDT_WAIT_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_CAPTURE_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 0. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_RDLVL_OP_MODE_0 | R/W | 0h | Read leveling algorithm select for slice 0. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_RDLVL_UPDT_WAIT_CNT_0 | R/W | 0h | Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 0. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_RDLVL_CAPTURE_CNT_0 | R/W | 0h | Number of samples to take at each DQS slave delay setting during read leveling for slice 0. |
DDRSS_PHY_32 is shown in Figure 8-870 and described in Table 8-1752.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4080h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_BURST_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_WDQLVL_CLK_JITTER_TOLERANCE_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDLVL_DATA_MASK_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PERIODIC_OBS_SELECT_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_WDQLVL_BURST_CNT_0 | R/W | 0h | Defines the write/read burst length in bytes during the write data leveling sequence for slice 0. |
| 23-16 | PHY_WDQLVL_CLK_JITTER_TOLERANCE_0 | R/W | 0h | Defines the minimum gap requirment for the LE and TE window for slice 0. |
| 15-8 | PHY_RDLVL_DATA_MASK_0 | R/W | 0h | Per-bit mask for read leveling for slice 0. |
| 7-0 | PHY_RDLVL_PERIODIC_OBS_SELECT_0 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 0. |
DDRSS_PHY_33 is shown in Figure 8-871 and described in Table 8-1754.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4084h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_UPDT_WAIT_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_PATT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_WDQLVL_UPDT_WAIT_CNT_0 | R/W | 0h | Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 0. |
| 23-19 | RESERVED | R/W | X | |
| 18-8 | PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0 | R/W | 0h | Defines the write/read burst length in bytes during the write data leveling sequence for slice 0. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_WDQLVL_PATT_0 | R/W | 0h | Defines the training patterns to be used during the write data leveling sequence for slice 0. |
DDRSS_PHY_34 is shown in Figure 8-872 and described in Table 8-1756.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4088h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_WDQLVL_CLR_PREV_RESULTS_0 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_PERIODIC_OBS_SELECT_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DQDM_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | SC_PHY_WDQLVL_CLR_PREV_RESULTS_0 | W | 0h | Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 0. |
| 15-8 | PHY_WDQLVL_PERIODIC_OBS_SELECT_0 | R/W | 0h | Select value to map specific information during or post periodic write data leveling for slice 0. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_WDQLVL_DQDM_OBS_SELECT_0 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 0. |
DDRSS_PHY_35 is shown in Figure 8-873 and described in Table 8-1758.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 408Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DATADM_MASK_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R/W | X | |
| 8-0 | PHY_WDQLVL_DATADM_MASK_0 | R/W | 0h | Per-bit mask for write data leveling for slice 0. |
DDRSS_PHY_36 is shown in Figure 8-874 and described in Table 8-1760.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4090h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT0_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT0_0 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 0. |
DDRSS_PHY_37 is shown in Figure 8-875 and described in Table 8-1762.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4094h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT1_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT1_0 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 0. |
DDRSS_PHY_38 is shown in Figure 8-876 and described in Table 8-1764.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4098h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT2_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT2_0 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 0. |
DDRSS_PHY_39 is shown in Figure 8-877 and described in Table 8-1766.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 409Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT3_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT3_0 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 0. |
DDRSS_PHY_40 is shown in Figure 8-878 and described in Table 8-1768.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_MULT_TRAIN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_USER_PATT4_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT4_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_NTP_MULT_TRAIN_0 | R/W | 0h | Control for single pass only No-Topology training for slice 0. |
| 15-0 | PHY_USER_PATT4_0 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 0. |
DDRSS_PHY_41 is shown in Figure 8-879 and described in Table 8-1770.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_EARLY_THRESHOLD_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_NTP_PERIOD_THRESHOLD_0 | R/W | 0h | Threshold Criteria of period threshold after No-Topology training is completed for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_NTP_EARLY_THRESHOLD_0 | R/W | 0h | Threshold Criteria of early threshold after No-Topology training is completed for slice 0. |
DDRSS_PHY_42 is shown in Figure 8-880 and described in Table 8-1772.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40A8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_MAX_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_MIN_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_NTP_PERIOD_THRESHOLD_MAX_0 | R/W | 0h | Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary, to set period threshold/early threshold after No-Topology training is completed for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_NTP_PERIOD_THRESHOLD_MIN_0 | R/W | 0h | Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary, to set period threshold/early threshold after No-Topology training is completed for slice 0. |
DDRSS_PHY_43 is shown in Figure 8-881 and described in Table 8-1774.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40ACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_FIFO_PTR_OBS_0 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_MANUAL_CLEAR_0 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CALVL_VREF_DRIVING_SLICE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | X | |
| 23-16 | PHY_FIFO_PTR_OBS_0 | R | 0h | Observation register containing read entry FIFO pointers for slice 0. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | SC_PHY_MANUAL_CLEAR_0 | W | 0h | Manual reset/clear of internal logic for slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_CALVL_VREF_DRIVING_SLICE_0 | R/W | 0h | Indicates if slice 0 is used to drive the VREF value to the device during CA training. |
DDRSS_PHY_44 is shown in Figure 8-882 and described in Table 8-1776.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40B0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LPBK_RESULT_OBS_0 | |||||||||||||||||||||||||||||||
| R-00100000h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_LPBK_RESULT_OBS_0 | R | 00100000h | Observation register containing loopback status/results for slice 0. |
DDRSS_PHY_45 is shown in Figure 8-883 and described in Table 8-1778.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DLY_LOCK_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LPBK_ERROR_COUNT_OBS_0 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R | X | |
| 26-16 | PHY_MASTER_DLY_LOCK_OBS_0 | R | 0h | Observation register containing master delay results for slice 0. |
| 15-0 | PHY_LPBK_ERROR_COUNT_OBS_0 | R | 0h | Observation register containing total number of loopback error data for slice 0. |
DDRSS_PHY_46 is shown in Figure 8-884 and described in Table 8-1780.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0 | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_MEAS_DLY_STEP_VALUE_0 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ_SLV_DLY_ENC_OBS_0 | ||||||
| R-X | R-0h | ||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 0. |
| 23-16 | PHY_MEAS_DLY_STEP_VALUE_0 | R | 0h | Observation register containing fraction of the cycle in 1 delay element, numerator with demominator of 512, for slice 0. |
| 15 | RESERVED | R | X | |
| 14-8 | PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing read DQS base slave delay encoded value for slice 0. |
| 7 | RESERVED | R | X | |
| 6-0 | PHY_RDDQ_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing read DQ slave delay encoded values for slice 0. |
DDRSS_PHY_47 is shown in Figure 8-885 and described in Table 8-1782.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0 | ||||||
| R-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R | X | |
| 30-24 | PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing write DQS base slave delay encoded value for slice 0. |
| 23-19 | RESERVED | R | X | |
| 18-8 | PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing read DQS gate slave delay encoded value for slice 0. |
| 7-0 | PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 0. |
DDRSS_PHY_48 is shown in Figure 8-886 and described in Table 8-1784.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WR_SHIFT_OBS_0 | ||||||
| R-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WR_ADDER_SLV_DLY_ENC_OBS_0 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R | X | |
| 18-16 | PHY_WR_SHIFT_OBS_0 | R | 0h | Observation register containing automatic half cycle and cycle shift values for slice 0. |
| 15-8 | PHY_WR_ADDER_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing write adder slave delay encoded value for slice 0. |
| 7-0 | PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing write DQ base slave delay encoded value for slice 0. |
DDRSS_PHY_49 is shown in Figure 8-887 and described in Table 8-1786.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40C4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_HARD1_DELAY_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_HARD0_DELAY_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_WRLVL_HARD1_DELAY_OBS_0 | R | 0h | Observation register containing write leveling first hard 1 DQS slave delay for slice 0. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_WRLVL_HARD0_DELAY_OBS_0 | R | 0h | Observation register containing write leveling last hard 0 DQS slave delay for slice 0. |
DDRSS_PHY_50 is shown in Figure 8-888 and described in Table 8-1788.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40C8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_STATUS_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_STATUS_OBS_0 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R | X | |
| 16-0 | PHY_WRLVL_STATUS_OBS_0 | R | 0h | Observation register containing write leveling status for slice 0. |
DDRSS_PHY_51 is shown in Figure 8-889 and described in Table 8-1790.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing gate sample2 slave delay encoded values for slice 0. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing gate sample1 slave delay encoded values for slice 0. |
DDRSS_PHY_52 is shown in Figure 8-890 and described in Table 8-1792.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40D0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_HARD0_DELAY_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_ERROR_OBS_0 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R | X | |
| 29-16 | PHY_GTLVL_HARD0_DELAY_OBS_0 | R | 0h | Observation register containing gate training first hard 0 DQS slave delay for slice 0. |
| 15-0 | PHY_WRLVL_ERROR_OBS_0 | R | 0h | Observation register containing write leveling error status for slice 0. |
DDRSS_PHY_53 is shown in Figure 8-891 and described in Table 8-1794.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40D4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GTLVL_HARD1_DELAY_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-14 | RESERVED | R | X | |
| 13-0 | PHY_GTLVL_HARD1_DELAY_OBS_0 | R | 0h | Observation register containing gate training last hard 1 DQS slave delay for slice 0. |
DDRSS_PHY_54 is shown in Figure 8-892 and described in Table 8-1796.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40D8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_STATUS_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_STATUS_OBS_0 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R | X | |
| 17-0 | PHY_GTLVL_STATUS_OBS_0 | R | 0h | Observation register containing gate training status for slice 0. |
DDRSS_PHY_55 is shown in Figure 8-893 and described in Table 8-1798.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40DCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0 | R | 0h | Observation register containing read leveling data window trailing edge slave delay setting for slice 0. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0 | R | 0h | Observation register containing read leveling data window leading edge slave delay setting for slice 0. |
DDRSS_PHY_56 is shown in Figure 8-894 and described in Table 8-1800.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0 | ||||||
| R-X | R-0h | ||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | X | |
| 1-0 | PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0 | R | 0h | Observation register containing read leveling number of windows found for slice 0. |
DDRSS_PHY_57 is shown in Figure 8-895 and described in Table 8-1802.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_STATUS_OBS_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_STATUS_OBS_0 | R | 0h | Observation register containing read leveling status for slice 0. |
DDRSS_PHY_58 is shown in Figure 8-896 and described in Table 8-1804.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40E8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PERIODIC_OBS_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PERIODIC_OBS_0 | R | 0h | Observation register containing periodic read leveling status for slice 0. |
DDRSS_PHY_59 is shown in Figure 8-897 and described in Table 8-1806.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40ECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DQDM_TE_DLY_OBS_0 | ||||||||||||||
| R-X | R-7FFh | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DQDM_LE_DLY_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R | X | |
| 26-16 | PHY_WDQLVL_DQDM_TE_DLY_OBS_0 | R | 7FFh | Observation register containing write data leveling data window trailing edge slave delay setting for slice 0. |
| 15-11 | RESERVED | R | X | |
| 10-0 | PHY_WDQLVL_DQDM_LE_DLY_OBS_0 | R | 0h | Observation register containing write data leveling data window leading edge slave delay setting for slice 0. |
DDRSS_PHY_60 is shown in Figure 8-898 and described in Table 8-1808.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_STATUS_OBS_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_WDQLVL_STATUS_OBS_0 | R | 0h | Observation register containing write data leveling status for slice 0. |
DDRSS_PHY_61 is shown in Figure 8-899 and described in Table 8-1810.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40F4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_PERIODIC_OBS_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_WDQLVL_PERIODIC_OBS_0 | R | 0h | Observation register containing periodic write data leveling status for slice 0. |
DDRSS_PHY_62 is shown in Figure 8-900 and described in Table 8-1812.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40F8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DDL_MODE_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-0 | PHY_DDL_MODE_0 | R/W | 0h | DDL mode for slice 0. |
DDRSS_PHY_63 is shown in Figure 8-901 and described in Table 8-1814.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 40FCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DDL_MASK_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DDL_MASK_0 | R/W | 0h | DDL mask for slice 0. |
DDRSS_PHY_64 is shown in Figure 8-902 and described in Table 8-1816.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4100h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TEST_OBS_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DDL_TEST_OBS_0 | R | 0h | DDL test observation for slice 0. |
DDRSS_PHY_65 is shown in Figure 8-903 and described in Table 8-1818.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4104h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TEST_MSTR_DLY_OBS_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DDL_TEST_MSTR_DLY_OBS_0 | R | 0h | DDL test observation delays for slice 0 master DDL. |
DDRSS_PHY_66 is shown in Figure 8-904 and described in Table 8-1820.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4108h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_OVERRIDE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_RX_CAL_START_0 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_WDQS_OE_EXTEND_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TRACK_UPD_THRESHOLD_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RX_CAL_OVERRIDE_0 | R/W | 0h | Manual setting of RX Calibration enable for slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | SC_PHY_RX_CAL_START_0 | W | 0h | Manual RX Calibration start for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_LP4_WDQS_OE_EXTEND_0 | R/W | 0h | LPDDR4 write preamble extension enable for slice 0. |
| 7-0 | PHY_DDL_TRACK_UPD_THRESHOLD_0 | R/W | 0h | Specify threshold value for PHY init update tracking for slice 0. |
DDRSS_PHY_67 is shown in Figure 8-905 and described in Table 8-1822.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 410Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_DQ0_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RX_CAL_DQ0_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RX_CAL_SAMPLE_WAIT_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ0_0 | R/W | 0h | RX Calibration codes for DQ0 for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0 | R/W | 0h | Data slice power reduction disable for slice 0. |
| 7-0 | PHY_RX_CAL_SAMPLE_WAIT_0 | R/W | 0h | RX Calibration state machine wait count for slice 0. |
DDRSS_PHY_68 is shown in Figure 8-906 and described in Table 8-1824.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4110h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ2_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ1_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ2_0 | R/W | 0h | RX Calibration codes for DQ2 for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ1_0 | R/W | 0h | RX Calibration codes for DQ1 for slice 0. |
DDRSS_PHY_69 is shown in Figure 8-907 and described in Table 8-1826.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4114h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ4_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ3_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ4_0 | R/W | 0h | RX Calibration codes for DQ4 for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ3_0 | R/W | 0h | RX Calibration codes for DQ3 for slice 0. |
DDRSS_PHY_70 is shown in Figure 8-908 and described in Table 8-1828.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4118h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ6_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ5_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ6_0 | R/W | 0h | RX Calibration codes for DQ6 for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ5_0 | R/W | 0h | RX Calibration codes for DQ5 for slice 0. |
DDRSS_PHY_71 is shown in Figure 8-909 and described in Table 8-1830.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 411Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ7_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ7_0 | R/W | 0h | RX Calibration codes for DQ7 for slice 0. |
DDRSS_PHY_72 is shown in Figure 8-910 and described in Table 8-1832.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4120h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DM_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_RX_CAL_DM_0 | R/W | 0h | RX Calibration codes for DM for slice 0. |
DDRSS_PHY_73 is shown in Figure 8-911 and described in Table 8-1834.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4124h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_FDBK_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQS_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_FDBK_0 | R/W | 0h | RX Calibration codes for FDBK for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQS_0 | R/W | 0h | RX Calibration codes for DQS for slice 0. |
DDRSS_PHY_74 is shown in Figure 8-912 and described in Table 8-1836.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4128h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_LOCK_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R | X | |
| 24-16 | PHY_RX_CAL_LOCK_OBS_0 | R | 0h | RX Calibration lock results for slice 0. |
| 15-11 | RESERVED | R | X | |
| 10-0 | PHY_RX_CAL_OBS_0 | R | 0h | RX Calibration results for slice 0. |
DDRSS_PHY_75 is shown in Figure 8-913 and described in Table 8-1838.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 412Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_COMP_VAL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DIFF_ADJUST_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RX_CAL_SE_ADJUST_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DISABLE_0 | ||||||
| R/W-X | R/W-1h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RX_CAL_COMP_VAL_0 | R/W | 0h | Expected C value from RX pad for slice 0. |
| 23 | RESERVED | R/W | X | |
| 22-16 | PHY_RX_CAL_DIFF_ADJUST_0 | R/W | 0h | Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 0. |
| 15 | RESERVED | R/W | X | |
| 14-8 | PHY_RX_CAL_SE_ADJUST_0 | R/W | 0h | Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_RX_CAL_DISABLE_0 | R/W | 1h | RX CAL disable signal for slice 0, set 1 to bypass the rx calibration |
DDRSS_PHY_76 is shown in Figure 8-914 and described in Table 8-1840.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4130h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_BIAS_EN_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_INDEX_MASK_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_PAD_RX_BIAS_EN_0 | R/W | 0h | Controls RX_BIAS_EN pin for each pad for slice 0. |
| 15-12 | RESERVED | R/W | X | |
| 11-0 | PHY_RX_CAL_INDEX_MASK_0 | R/W | 0h | RX offset calibration mask of all RX pad for slice 0. |
DDRSS_PHY_77 is shown in Figure 8-915 and described in Table 8-1842.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4134h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_WEIGHT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_CAL_TIMEOUT_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_CAL_SAMPLE_WAIT_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_STATIC_TOG_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_DATA_DC_WEIGHT_0 | R/W | 0h | Determines weight of average calculating for slice 0. |
| 23-16 | PHY_DATA_DC_CAL_TIMEOUT_0 | R/W | 0h | Determines timeout number of iteration for slice 0. |
| 15-8 | PHY_DATA_DC_CAL_SAMPLE_WAIT_0 | R/W | 0h | Determines number of cycles to wait for each sample for slice 0. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_STATIC_TOG_DISABLE_0 | R/W | 0h | Control to disable toggle during static activity for slice 0. |
DDRSS_PHY_78 is shown in Figure 8-916 and described in Table 8-1844.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4138h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_ADJUST_DIRECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_ADJUST_THRSHLD_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_ADJUST_SAMPLE_CNT_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_ADJUST_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_DATA_DC_ADJUST_DIRECT_0 | R/W | 0h | Adjust direction for slice 0. |
| 23-16 | PHY_DATA_DC_ADJUST_THRSHLD_0 | R/W | 0h | Duty cycle adjust threshold around the mid-point for slice 0. |
| 15-8 | PHY_DATA_DC_ADJUST_SAMPLE_CNT_0 | R/W | 0h | Duty cycle adjust sample count for slice 0. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DATA_DC_ADJUST_START_0 | R/W | 0h | Duty cycle adjust starting value for slice 0. |
DDRSS_PHY_79 is shown in Figure 8-917 and described in Table 8-1846.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 413Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_FDBK_PWR_CTRL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_SW_RANK_0 | ||||||
| R/W-X | R/W-1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_CAL_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_CAL_POLARITY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_FDBK_PWR_CTRL_0 | R/W | 0h | Shutoff gate feedback IO to reduce power for slice 0. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DATA_DC_SW_RANK_0 | R/W | 1h | Rank selection for software based duty cycle correction for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DATA_DC_CAL_START_0 | R/W | 0h | Manual trigger for DCC for slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DATA_DC_CAL_POLARITY_0 | R/W | 0h | Calibration polarity for slice 0. |
DDRSS_PHY_80 is shown in Figure 8-918 and described in Table 8-1848.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4140h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SLICE_PWR_RDC_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDPATH_GATE_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SLV_DLY_CTRL_GATE_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_SLICE_PWR_RDC_DISABLE_0 | R/W | 0h | Data slice power reduction disable for slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0 | R/W | 0h | Data slice DCC and RX_CAL block power reduction disable for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_RDPATH_GATE_DISABLE_0 | R/W | 0h | Data slice read path power reduction disable for slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_SLV_DLY_CTRL_GATE_DISABLE_0 | R/W | 0h | Data slice slv_dly_control block power reduction disable for slice 0. |
DDRSS_PHY_81 is shown in Figure 8-919 and described in Table 8-1850.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4144h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DS_FSM_ERROR_INFO_0 | ||||||||||||||
| R/W-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PARITY_ERROR_REGIF_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | PHY_DS_FSM_ERROR_INFO_0 | R | 0h | Data slice level FSM Error Info for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_PARITY_ERROR_REGIF_0 | R/W | 0h | Inject parity error to register interface signals for slice 0. |
DDRSS_PHY_82 is shown in Figure 8-920 and described in Table 8-1852.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4148h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0 | |||||||
| W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DS_FSM_ERROR_INFO_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DS_FSM_ERROR_INFO_MASK_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0 | W | 0h | Data slice level FSM Error Info for slice 0. |
| 15-14 | RESERVED | R/W | X | |
| 13-0 | PHY_DS_FSM_ERROR_INFO_MASK_0 | R/W | 0h | Data slice level FSM Error Info Mask for slice 0. |
DDRSS_PHY_83 is shown in Figure 8-921 and described in Table 8-1854.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 414Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DS_TRAIN_CALIB_ERROR_INFO_0 | ||||||
| R/W-X | R-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0 | W | 0h | Data slice level training/calibration Error Info for slice 0. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_0 | R/W | 0h | Data slice level training/calibration Error Info Mask for slice 0. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_DS_TRAIN_CALIB_ERROR_INFO_0 | R | 0h | Data slice level training/calibration Error Info for slice 0. |
DDRSS_PHY_84 is shown in Figure 8-922 and described in Table 8-1856.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4150h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DQS_TSEL_ENABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQ_TSEL_SELECT_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_TSEL_SELECT_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DQ_TSEL_ENABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_DQS_TSEL_ENABLE_0 | R/W | 0h | Operation type tsel enables for DQS signals for slice 0. |
| 23-8 | PHY_DQ_TSEL_SELECT_0 | R/W | 0h | Operation type tsel select values for DQ/DM signals for slice 0. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_DQ_TSEL_ENABLE_0 | R/W | 0h | Operation type tsel enables for DQ/DM signals for slice 0. |
DDRSS_PHY_85 is shown in Figure 8-923 and described in Table 8-1858.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4154h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_VREF_INITIAL_START_POINT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TWO_CYC_PREAMBLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQS_TSEL_SELECT_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQS_TSEL_SELECT_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-24 | PHY_VREF_INITIAL_START_POINT_0 | R/W | 0h | Data slice initial VREF training start value for slice 0. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_TWO_CYC_PREAMBLE_0 | R/W | 0h | 2 cycle preamble support for slice 0. |
| 15-0 | PHY_DQS_TSEL_SELECT_0 | R/W | 0h | Operation type tsel select values for DQS signals for slice 0. |
DDRSS_PHY_86 is shown in Figure 8-924 and described in Table 8-1860.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4158h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_NTP_WDQ_STEP_SIZE_0 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_TRAIN_EN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_VREF_TRAINING_CTRL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_VREF_INITIAL_STOP_POINT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_NTP_WDQ_STEP_SIZE_0 | R/W | 0h | Step size of WR DQ slave delay during No-Topology training for slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_NTP_TRAIN_EN_0 | R/W | 0h | Enable for No-Topology training for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_VREF_TRAINING_CTRL_0 | R/W | 0h | Data slice vref training enable control for slice 0. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_VREF_INITIAL_STOP_POINT_0 | R/W | 0h | Data slice initial VREF training stop value for slice 0. |
DDRSS_PHY_87 is shown in Figure 8-925 and described in Table 8-1862.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 415Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_WDQ_STOP_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_WDQ_START_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_NTP_WDQ_STOP_0 | R/W | 0h | End of WR DQ slave delay in No-Topology training for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_NTP_WDQ_START_0 | R/W | 0h | Starting WR DQ slave delay in No-Topology training for slice 0. |
DDRSS_PHY_88 is shown in Figure 8-926 and described in Table 8-1864.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4160h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WDQLVL_DVW_MIN_EN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DVW_MIN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_DVW_MIN_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_NTP_WDQ_BIT_EN_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_SW_WDQLVL_DVW_MIN_EN_0 | R/W | 0h | SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 0. |
| 23-18 | RESERVED | R/W | X | |
| 17-8 | PHY_WDQLVL_DVW_MIN_0 | R/W | 0h | Minimum data valid window across DQs and ranks for slice 0. |
| 7-0 | PHY_NTP_WDQ_BIT_EN_0 | R/W | 0h | Enable Bit for WR DQ during No-Topology training for slice 0. |
DDRSS_PHY_89 is shown in Figure 8-927 and described in Table 8-1866.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4164h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_RX_DCD_0_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_TX_DCD_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_FAST_LVL_EN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_PER_START_OFFSET_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_RX_DCD_0_0 | R/W | 0h | Controls RX_DCD pin for each pad for slice 0. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_TX_DCD_0 | R/W | 0h | Controls TX_DCD pin for each pad for slice 0. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_FAST_LVL_EN_0 | R/W | 0h | Enable for fast multi-pattern window search for slice 0. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_WDQLVL_PER_START_OFFSET_0 | R/W | 0h | Peridic training start point offset for slice 0. |
DDRSS_PHY_90 is shown in Figure 8-928 and described in Table 8-1868.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4168h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_RX_DCD_4_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_DCD_3_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_RX_DCD_2_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RX_DCD_1_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_RX_DCD_4_0 | R/W | 0h | Controls RX_DCD pin for each pad for slice 0. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_RX_DCD_3_0 | R/W | 0h | Controls RX_DCD pin for each pad for slice 0. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_RX_DCD_2_0 | R/W | 0h | Controls RX_DCD pin for each pad for slice 0. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_RX_DCD_1_0 | R/W | 0h | Controls RX_DCD pin for each pad for slice 0. |
DDRSS_PHY_91 is shown in Figure 8-929 and described in Table 8-1870.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 416Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_DM_RX_DCD_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_DCD_7_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_RX_DCD_6_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RX_DCD_5_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_DM_RX_DCD_0 | R/W | 0h | Controls RX_DCD pin for dm pad for slice 0. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_RX_DCD_7_0 | R/W | 0h | Controls RX_DCD pin for each pad for slice 0. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_RX_DCD_6_0 | R/W | 0h | Controls RX_DCD pin for each pad for slice 0. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_RX_DCD_5_0 | R/W | 0h | Controls RX_DCD pin for each pad for slice 0. |
DDRSS_PHY_92 is shown in Figure 8-930 and described in Table 8-1872.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4170h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_DSLICE_IO_CFG_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_FDBK_RX_DCD_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_DQS_RX_DCD_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-22 | RESERVED | R/W | X | |
| 21-16 | PHY_PAD_DSLICE_IO_CFG_0 | R/W | 0h | Controls PCLK/PARK pin for pad for slice 0. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_FDBK_RX_DCD_0 | R/W | 0h | Controls RX_DCD pin for fdbk pad for slice 0. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_DQS_RX_DCD_0 | R/W | 0h | Controls RX_DCD pin for dqs pad for slice 0. |
DDRSS_PHY_93 is shown in Figure 8-931 and described in Table 8-1874.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4174h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ1_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ0_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ1_SLAVE_DELAY_0 | R/W | 0h | Read DQ1 slave delay setting for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ0_SLAVE_DELAY_0 | R/W | 0h | Read DQ0 slave delay setting for slice 0. |
DDRSS_PHY_94 is shown in Figure 8-932 and described in Table 8-1876.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4178h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ3_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ2_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ3_SLAVE_DELAY_0 | R/W | 0h | Read DQ3 slave delay setting for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ2_SLAVE_DELAY_0 | R/W | 0h | Read DQ2 slave delay setting for slice 0. |
DDRSS_PHY_95 is shown in Figure 8-933 and described in Table 8-1878.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 417Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ5_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ4_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ5_SLAVE_DELAY_0 | R/W | 0h | Read DQ5 slave delay setting for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ4_SLAVE_DELAY_0 | R/W | 0h | Read DQ4 slave delay setting for slice 0. |
DDRSS_PHY_96 is shown in Figure 8-934 and described in Table 8-1880.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4180h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ7_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ6_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ7_SLAVE_DELAY_0 | R/W | 0h | Read DQ7 slave delay setting for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ6_SLAVE_DELAY_0 | R/W | 0h | Read DQ6 slave delay setting for slice 0. |
DDRSS_PHY_97 is shown in Figure 8-935 and described in Table 8-1882.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4184h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_CAL_CLK_SEL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDM_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDM_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R/W | X | |
| 18-16 | PHY_DATA_DC_CAL_CLK_SEL_0 | R/W | 0h | Determines DCC CAL clock for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDM_SLAVE_DELAY_0 | R/W | 0h | Read DM/DBI slave delay setting for slice 0. |
DDRSS_PHY_98 is shown in Figure 8-936 and described in Table 8-1884.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4188h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_OE_TIMING_0 | PHY_DQ_TSEL_WR_TIMING_0 | ||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQ_TSEL_RD_TIMING_0 | PHY_DQ_OE_TIMING_0 | ||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DQS_OE_TIMING_0 | R/W | 0h | Start/end timing values for DQS output enable signals for slice 0. |
| 23-16 | PHY_DQ_TSEL_WR_TIMING_0 | R/W | 0h | Start/end timing values for DQ/DM write based termination enable and select signals for slice 0. |
| 15-8 | PHY_DQ_TSEL_RD_TIMING_0 | R/W | 0h | Start/end timing values for DQ/DM read based termination enable and select signals for slice 0. |
| 7-0 | PHY_DQ_OE_TIMING_0 | R/W | 0h | Start/end timing values for DQ/DM output enable signals for slice 0. |
DDRSS_PHY_99 is shown in Figure 8-937 and described in Table 8-1886.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 418Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DQS_TSEL_WR_TIMING_0 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_OE_RD_TIMING_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQS_TSEL_RD_TIMING_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_IO_PAD_DELAY_TIMING_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DQS_TSEL_WR_TIMING_0 | R/W | 0h | Start/end timing values for DQS write based termination enable and select signals for slice 0. |
| 23-16 | PHY_DQS_OE_RD_TIMING_0 | R/W | 0h | Start/end timing values for DQS read based OE extension for slice 0. |
| 15-8 | PHY_DQS_TSEL_RD_TIMING_0 | R/W | 0h | Start/end timing values for DQS read based termination enable and select signals for slice 0. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_IO_PAD_DELAY_TIMING_0 | R/W | 0h | Feedback pad's OPAD and IPAD delay timing for slice 0. |
DDRSS_PHY_100 is shown in Figure 8-938 and described in Table 8-1888.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4190h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_VREF_CTRL_DQ_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_VREF_SETTING_TIME_0 | |||||||||||||||
| R/W-0h | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-16 | PHY_PAD_VREF_CTRL_DQ_0 | R/W | 0h | Pad VREF control settings for DQ slice 0.
|
| 15-0 | PHY_VREF_SETTING_TIME_0 | R/W | 0h | Number of cycles for vref settle after setting is changed for slice 0. |
DDRSS_PHY_101 is shown in Figure 8-939 and described in Table 8-1890.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4194h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDATA_EN_IE_DLY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_IE_TIMING_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_IE_TIMING_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PER_CS_TRAINING_EN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_RDDATA_EN_IE_DLY_0 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0. |
| 23-16 | PHY_DQS_IE_TIMING_0 | R/W | 0h | Start/end timing values for DQS input enable signals for slice 0. |
| 15-8 | PHY_DQ_IE_TIMING_0 | R/W | 0h | Start/end timing values for DQ/DM input enable signals for slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_PER_CS_TRAINING_EN_0 | R/W | 0h | Enables the per-rank training and read/write timing capabilities for slice 0. |
DDRSS_PHY_102 is shown in Figure 8-940 and described in Table 8-1892.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4198h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDATA_EN_OE_DLY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDATA_EN_TSEL_DLY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DBI_MODE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_IE_MODE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_RDDATA_EN_OE_DLY_0 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 0. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_RDDATA_EN_TSEL_DLY_0 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DBI_MODE_0 | R/W | 0h | DBI mode for slice 0. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_IE_MODE_0 | R/W | 0h | Input enable mode bits for slice 0. |
DDRSS_PHY_103 is shown in Figure 8-941 and described in Table 8-1894.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 419Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_MASTER_DELAY_STEP_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DELAY_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_MASTER_DELAY_START_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_MASTER_MODE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_MASTER_DELAY_STEP_0 | R/W | 0h | Incremental step size for master delay line locking algorithm for slice 0. |
| 23-19 | RESERVED | R/W | X | |
| 18-8 | PHY_MASTER_DELAY_START_0 | R/W | 0h | Start value for master delay line locking algorithm for slice 0. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_SW_MASTER_MODE_0 | R/W | 0h | Master delay line override settings for slice 0. |
DDRSS_PHY_104 is shown in Figure 8-942 and described in Table 8-1896.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_WRLVL_DLY_STEP_0 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RPTR_UPDATE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_MASTER_DELAY_HALF_MEASURE_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_MASTER_DELAY_WAIT_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_WRLVL_DLY_STEP_0 | R/W | 0h | DQS slave delay step size during write leveling for slice 0. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_RPTR_UPDATE_0 | R/W | 0h | Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 0. |
| 15-8 | PHY_MASTER_DELAY_HALF_MEASURE_0 | R/W | 0h | Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 0. |
| 7-0 | PHY_MASTER_DELAY_WAIT_0 | R/W | 0h | Wait cycles for master delay line locking algorithm for slice 0. |
DDRSS_PHY_105 is shown in Figure 8-943 and described in Table 8-1898.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GTLVL_RESP_WAIT_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_DLY_STEP_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_RESP_WAIT_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_DLY_FINE_STEP_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_GTLVL_RESP_WAIT_CNT_0 | R/W | 0h | Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 0. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GTLVL_DLY_STEP_0 | R/W | 0h | DQS slave delay step size during gate training for slice 0. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_WRLVL_RESP_WAIT_CNT_0 | R/W | 0h | Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 0. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_WRLVL_DLY_FINE_STEP_0 | R/W | 0h | DQS slave delay fine step size during write leveling for slice 0. |
DDRSS_PHY_106 is shown in Figure 8-944 and described in Table 8-1900.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41A8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_FINAL_STEP_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GTLVL_BACK_STEP_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_GTLVL_FINAL_STEP_0 | R/W | 0h | Final backup step delay used in gate training algorithm for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_BACK_STEP_0 | R/W | 0h | Interim backup step delay used in gate training algorithm for slice 0. |
DDRSS_PHY_107 is shown in Figure 8-945 and described in Table 8-1902.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41ACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_DLY_STEP_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TOGGLE_PRE_SUPPORT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_QTR_DLY_STEP_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_DLY_STEP_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_RDLVL_DLY_STEP_0 | R/W | 0h | DQS slave delay step size during read leveling for slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_TOGGLE_PRE_SUPPORT_0 | R/W | 0h | Support the toggle read preamble for LPDDR4 for slice 0. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WDQLVL_QTR_DLY_STEP_0 | R/W | 0h | Defines the step granularity for the logic to use once an edge is found for slice 0. |
| 7-0 | PHY_WDQLVL_DLY_STEP_0 | R/W | 0h | DQ slave delay step size during write data leveling for slice 0. |
DDRSS_PHY_108 is shown in Figure 8-946 and described in Table 8-1904.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41B0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_MAX_EDGE_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_MAX_EDGE_0 | R/W | 0h | The maximun rdlvl slave delay search window for read eye training for slice 0. |
DDRSS_PHY_109 is shown in Figure 8-947 and described in Table 8-1906.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_PER_START_OFFSET_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_RDLVL_DVW_MIN_EN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_DVW_MIN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_DVW_MIN_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_RDLVL_PER_START_OFFSET_0 | R/W | 0h | Peridic training start point offset for slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_SW_RDLVL_DVW_MIN_EN_0 | R/W | 0h | SW override to enable use of PHY_RDLVL_DVW_MIN for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_DVW_MIN_0 | R/W | 0h | Minimum data valid window across DQs and ranks for slice 0. |
DDRSS_PHY_110 is shown in Figure 8-948 and described in Table 8-1908.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_INIT_DISABLE_0 | ||||||
| R/W-X | R/W-3h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRPATH_GATE_TIMING_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRPATH_GATE_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DATA_DC_INIT_DISABLE_0 | R/W | 3h | Disable duty cycle adjust at initialization for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_WRPATH_GATE_TIMING_0 | R/W | 0h | Write path clock gating timing for slice 0. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_WRPATH_GATE_DISABLE_0 | R/W | 0h | Write path clock gating disable for slice 0. |
DDRSS_PHY_111 is shown in Figure 8-949 and described in Table 8-1910.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_DQ_INIT_SLV_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ_INIT_SLV_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_DQS_INIT_SLV_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQS_INIT_SLV_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_DATA_DC_DQ_INIT_SLV_DELAY_0 | R/W | 0h | Initial value of write DQ slave delay for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_DATA_DC_DQS_INIT_SLV_DELAY_0 | R/W | 0h | Initial value of write DQS slave delay for slice 0. |
DDRSS_PHY_112 is shown in Figure 8-950 and described in Table 8-1912.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DM_CLK_SE_THRSHLD_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_WDQLVL_ENABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_WRLVL_ENABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0 | R/W | 0h | Clock measurement cell threshold offset for differential signals for slice 0. |
| 23-16 | PHY_DATA_DC_DM_CLK_SE_THRSHLD_0 | R/W | 0h | Clock measurement cell threshold offset for single ended signals for slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DATA_DC_WDQLVL_ENABLE_0 | R/W | 0h | Enable duty cycle adjust during write DQ training for slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DATA_DC_WRLVL_ENABLE_0 | R/W | 0h | Enable duty cycle adjust during write leveling for slice 0. |
DDRSS_PHY_113 is shown in Figure 8-951 and described in Table 8-1914.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41C4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDATA_EN_DLY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_MEAS_DLY_STEP_ENABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQ_OSC_DELTA_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | PHY_RDDATA_EN_DLY_0 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is early for slice 0. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_MEAS_DLY_STEP_ENABLE_0 | R/W | 0h | Data slice training step definition using phy_meas_dly_step_value for slice 0. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_WDQ_OSC_DELTA_0 | R/W | 0h | Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 0. |
DDRSS_PHY_114 is shown in Figure 8-952 and described in Table 8-1916.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41C8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQ_DM_SWIZZLE0_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DQ_DM_SWIZZLE0_0 | R/W | 0h | DQ/DM bit swizzling 0 for slice 0. |
DDRSS_PHY_115 is shown in Figure 8-953 and described in Table 8-1918.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DQ_DM_SWIZZLE1_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R/W | X | |
| 3-0 | PHY_DQ_DM_SWIZZLE1_0 | R/W | 0h | DQ/DM bit swizzling 1 for slice 0. |
DDRSS_PHY_116 is shown in Figure 8-954 and described in Table 8-1920.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41D0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ1_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ0_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ1_SLAVE_DELAY_0 | R/W | 0h | Write clock slave delay setting for DQ1 for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ0_SLAVE_DELAY_0 | R/W | 0h | Write clock slave delay setting for DQ0 for slice 0. |
DDRSS_PHY_117 is shown in Figure 8-955 and described in Table 8-1922.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41D4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ3_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ2_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ3_SLAVE_DELAY_0 | R/W | 0h | Write clock slave delay setting for DQ3 for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ2_SLAVE_DELAY_0 | R/W | 0h | Write clock slave delay setting for DQ2 for slice 0. |
DDRSS_PHY_118 is shown in Figure 8-956 and described in Table 8-1924.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41D8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ5_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ4_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ5_SLAVE_DELAY_0 | R/W | 0h | Write clock slave delay setting for DQ5 for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ4_SLAVE_DELAY_0 | R/W | 0h | Write clock slave delay setting for DQ4 for slice 0. |
DDRSS_PHY_119 is shown in Figure 8-957 and described in Table 8-1926.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41DCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ7_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ6_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ7_SLAVE_DELAY_0 | R/W | 0h | Write clock slave delay setting for DQ7 for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ6_SLAVE_DELAY_0 | R/W | 0h | Write clock slave delay setting for DQ6 for slice 0. |
DDRSS_PHY_120 is shown in Figure 8-958 and described in Table 8-1928.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQS_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDM_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_CLK_WRDQS_SLAVE_DELAY_0 | R/W | 0h | Write clock slave delay setting for DQS for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDM_SLAVE_DELAY_0 | R/W | 0h | Write clock slave delay setting for DM for slice 0. |
DDRSS_PHY_121 is shown in Figure 8-959 and described in Table 8-1930.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_THRESHOLD_ADJUST_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-8 | PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0 | R/W | 0h | Rising edge read DQS slave delay setting for DQ0 for slice 0. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_WRLVL_THRESHOLD_ADJUST_0 | R/W | 0h | Write level threshold adjust value based on those thresholds for DQS for slice 0. |
DDRSS_PHY_122 is shown in Figure 8-960 and described in Table 8-1932.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41E8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0 | R/W | 0h | Rising edge read DQS slave delay setting for DQ1 for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0 | R/W | 0h | Falling edge read DQS slave delay setting for DQ0 for slice 0. |
DDRSS_PHY_123 is shown in Figure 8-961 and described in Table 8-1934.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41ECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0 | R/W | 0h | Rising edge read DQS slave delay setting for DQ2 for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0 | R/W | 0h | Falling edge read DQS slave delay setting for DQ1 for slice 0. |
DDRSS_PHY_124 is shown in Figure 8-962 and described in Table 8-1936.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0 | R/W | 0h | Rising edge read DQS slave delay setting for DQ3 for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0 | R/W | 0h | Falling edge read DQS slave delay setting for DQ2 for slice 0. |
DDRSS_PHY_125 is shown in Figure 8-963 and described in Table 8-1938.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41F4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0 | R/W | 0h | Rising edge read DQS slave delay setting for DQ4 for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0 | R/W | 0h | Falling edge read DQS slave delay setting for DQ3 for slice 0. |
DDRSS_PHY_126 is shown in Figure 8-964 and described in Table 8-1940.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41F8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0 | R/W | 0h | Rising edge read DQS slave delay setting for DQ5 for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0 | R/W | 0h | Falling edge read DQS slave delay setting for DQ4 for slice 0. |
DDRSS_PHY_127 is shown in Figure 8-965 and described in Table 8-1942.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 41FCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0 | R/W | 0h | Rising edge read DQS slave delay setting for DQ6 for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0 | R/W | 0h | Falling edge read DQS slave delay setting for DQ5 for slice 0. |
DDRSS_PHY_128 is shown in Figure 8-966 and described in Table 8-1944.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4200h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0 | R/W | 0h | Rising edge read DQS slave delay setting for DQ7 for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0 | R/W | 0h | Falling edge read DQS slave delay setting for DQ6 for slice 0. |
DDRSS_PHY_129 is shown in Figure 8-967 and described in Table 8-1946.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4204h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DM_RISE_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DM_RISE_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DM_RISE_SLAVE_DELAY_0 | R/W | 0h | Rising edge read DQS slave delay setting for DM for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0 | R/W | 0h | Falling edge read DQS slave delay setting for DQ7 for slice 0. |
DDRSS_PHY_130 is shown in Figure 8-968 and described in Table 8-1948.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4208h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_GATE_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_GATE_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DM_FALL_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DM_FALL_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_GATE_SLAVE_DELAY_0 | R/W | 0h | Read DQS slave delay setting for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DM_FALL_SLAVE_DELAY_0 | R/W | 0h | Falling edge read DQS slave delay setting for DM for slice 0. |
DDRSS_PHY_131 is shown in Figure 8-969 and described in Table 8-1950.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 420Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRITE_PATH_LAT_ADD_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQS_LATENCY_ADJUST_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 | R/W | 0h | Write level delay threshold above which will be considered in previous cycle for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_WRITE_PATH_LAT_ADD_0 | R/W | 0h | Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 0. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_RDDQS_LATENCY_ADJUST_0 | R/W | 0h | Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0. |
DDRSS_PHY_132 is shown in Figure 8-970 and described in Table 8-1952.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4210h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_EARLY_FORCE_ZERO_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_WRLVL_EARLY_FORCE_ZERO_0 | R/W | 0h | Force the final write level delay value (that meets the early threshold) to 0 for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0 | R/W | 0h | Write level delay threshold below which will add a cycle of write path latency for slice 0. |
DDRSS_PHY_133 is shown in Figure 8-971 and described in Table 8-1954.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4214h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_LAT_ADJ_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GTLVL_RDDQS_SLV_DLY_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_RDDQS_SLV_DLY_START_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GTLVL_LAT_ADJ_START_0 | R/W | 0h | Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_RDDQS_SLV_DLY_START_0 | R/W | 0h | Initial read DQS gate slave delay setting during gate training for slice 0. |
DDRSS_PHY_134 is shown in Figure 8-972 and described in Table 8-1956.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4218h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_NTP_PASS_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_WRLAT_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_DQDM_SLV_DLY_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_DQDM_SLV_DLY_START_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_NTP_PASS_0 | R/W | 0h | Indicates if No-topology training found a passing result for slice 0. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_NTP_WRLAT_START_0 | R/W | 0h | Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_WDQLVL_DQDM_SLV_DLY_START_0 | R/W | 0h | Initial DQ/DM slave delay setting during write data leveling for slice 0. |
DDRSS_PHY_135 is shown in Figure 8-973 and described in Table 8-1958.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 421Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0 | R/W | 0h | Read leveling starting value for the DQS/DQ slave delay settings for slice 0. |
DDRSS_PHY_136 is shown in Figure 8-974 and described in Table 8-1960.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4220h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DQ2_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ1_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DQ0_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQS_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DQ2_CLK_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 0. |
| 23-16 | PHY_DATA_DC_DQ1_CLK_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 0. |
| 15-8 | PHY_DATA_DC_DQ0_CLK_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 0. |
| 7-0 | PHY_DATA_DC_DQS_CLK_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 0. |
DDRSS_PHY_137 is shown in Figure 8-975 and described in Table 8-1962.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4224h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DQ6_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ5_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DQ4_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQ3_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DQ6_CLK_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 0. |
| 23-16 | PHY_DATA_DC_DQ5_CLK_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 0. |
| 15-8 | PHY_DATA_DC_DQ4_CLK_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 0. |
| 7-0 | PHY_DATA_DC_DQ3_CLK_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 0. |
DDRSS_PHY_138 is shown in Figure 8-976 and described in Table 8-1964.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4228h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DSLICE_PAD_BOOSTPN_SETTING_0 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DSLICE_PAD_BOOSTPN_SETTING_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DM_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQ7_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | PHY_DSLICE_PAD_BOOSTPN_SETTING_0 | R/W | 0h | Setting for boost P/N of pad for slice 0. |
| 15-8 | PHY_DATA_DC_DM_CLK_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 0. |
| 7-0 | PHY_DATA_DC_DQ7_CLK_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 0. |
DDRSS_PHY_139 is shown in Figure 8-977 and described in Table 8-1966.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 422Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DQS_FFE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DQ_FFE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DSLICE_PAD_RX_CTLE_SETTING_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DQS_FFE_0 | R/W | 0h | TX_FFE setting for DQS pad for slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_DQ_FFE_0 | R/W | 0h | TX_FFE setting for DQ/DM pad for slice 0. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DSLICE_PAD_RX_CTLE_SETTING_0 | R/W | 0h | Setting for RX ctle P/N of pad for slice 0. |
DDRSS_PHY_256 is shown in Figure 8-978 and described in Table 8-1968.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4400h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_IO_PAD_DELAY_TIMING_BYPASS_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CLK_WR_BYPASS_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CLK_WR_BYPASS_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-16 | PHY_IO_PAD_DELAY_TIMING_BYPASS_1 | R/W | 0h | Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WR_BYPASS_SLAVE_DELAY_1 | R/W | 0h | Write data clock bypass mode slave delay setting for slice 1.} PADDING_BEFORE |
DDRSS_PHY_257 is shown in Figure 8-979 and described in Table 8-1970.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4404h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRITE_PATH_LAT_ADD_BYPASS_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R/W | X | |
| 18-16 | PHY_WRITE_PATH_LAT_ADD_BYPASS_1 | R/W | 0h | Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1 | R/W | 0h | Write DQS bypass mode slave delay setting for slice 1. |
DDRSS_PHY_258 is shown in Figure 8-980 and described in Table 8-1972.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4408h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CLK_BYPASS_OVERRIDE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_BYPASS_TWO_CYC_PREAMBLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_CLK_BYPASS_OVERRIDE_1 | R/W | 0h | Bypass mode override setting for slice 1. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_BYPASS_TWO_CYC_PREAMBLE_1 | R/W | 0h | Two_cycle_preamble for bypass mode for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1 | R/W | 0h | Read DQS bypass mode slave delay setting for slice 1. |
DDRSS_PHY_259 is shown in Figure 8-981 and described in Table 8-1974.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 440Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WRDQ3_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_WRDQ2_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQ1_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDQ0_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_SW_WRDQ3_SHIFT_1 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 1. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_SW_WRDQ2_SHIFT_1 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 1. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_SW_WRDQ1_SHIFT_1 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 1. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDQ0_SHIFT_1 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 1. |
DDRSS_PHY_260 is shown in Figure 8-982 and described in Table 8-1976.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4410h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WRDQ7_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_WRDQ6_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQ5_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDQ4_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_SW_WRDQ7_SHIFT_1 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 1. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_SW_WRDQ6_SHIFT_1 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 1. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_SW_WRDQ5_SHIFT_1 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 1. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDQ4_SHIFT_1 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 1. |
DDRSS_PHY_261 is shown in Figure 8-983 and described in Table 8-1978.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4414h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PER_CS_TRAINING_MULTICAST_EN_1 | ||||||
| R/W-X | R/W-1h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PER_RANK_CS_MAP_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQS_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDM_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_PER_CS_TRAINING_MULTICAST_EN_1 | R/W | 1h | When set, a register write will update parameters for all ranks at the same time in slice 1. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_PER_RANK_CS_MAP_1 | R/W | 0h | Per-rank CS map for slice 1. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_SW_WRDQS_SHIFT_1 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 1. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDM_SHIFT_1 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 1. |
DDRSS_PHY_262 is shown in Figure 8-984 and described in Table 8-1980.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4418h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_DLY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PER_CS_TRAINING_INDEX_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_LP4_BOOT_RDDATA_EN_DLY_1 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is early for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 1. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_PER_CS_TRAINING_INDEX_1 | R/W | 0h | For per-rank training, indicates which rank's paramters are read/written for slice 1. |
DDRSS_PHY_263 is shown in Figure 8-985 and described in Table 8-1982.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 441Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LP4_BOOT_RPTR_UPDATE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 1. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1 | R/W | 0h | For LPDDR4 boot frequency, write path clock gating disable for slice 1. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 1. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_LP4_BOOT_RPTR_UPDATE_1 | R/W | 0h | For LPDDR4 boot frequency, the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 1. |
DDRSS_PHY_264 is shown in Figure 8-986 and described in Table 8-1984.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4420h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LPBK_DFX_TIMEOUT_EN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LPBK_CONTROL_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_LPBK_CONTROL_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CTRL_LPBK_EN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_LPBK_DFX_TIMEOUT_EN_1 | R/W | 0h | Loopback read only test timeout mechanism enable for slice 1. |
| 23-17 | RESERVED | R/W | X | |
| 16-8 | PHY_LPBK_CONTROL_1 | R/W | 0h | Loopback control bits for slice 1. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_CTRL_LPBK_EN_1 | R/W | 0h | Loopback control en for slice 1. |
DDRSS_PHY_265 is shown in Figure 8-987 and described in Table 8-1986.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4424h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_AUTO_TIMING_MARGIN_CONTROL_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_AUTO_TIMING_MARGIN_CONTROL_1 | R/W | 0h | Auto timing marging control bits for slice 1. |
DDRSS_PHY_266 is shown in Figure 8-988 and described in Table 8-1988.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4428h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_AUTO_TIMING_MARGIN_OBS_1 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R | X | |
| 27-0 | PHY_AUTO_TIMING_MARGIN_OBS_1 | R | 0h | Observation register for the auto_timing_margin for slice 1. |
DDRSS_PHY_267 is shown in Figure 8-989 and described in Table 8-1990.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 442Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_MULTI_PATT_ENABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PRBS_PATTERN_MASK_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PRBS_PATTERN_MASK_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PRBS_PATTERN_START_1 | ||||||
| R/W-X | R/W-1h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RDLVL_MULTI_PATT_ENABLE_1 | R/W | 0h | Read Leveling Multi-pattern enable for slice 1. |
| 23-17 | RESERVED | R/W | X | |
| 16-8 | PHY_PRBS_PATTERN_MASK_1 | R/W | 0h | PRBS7 mask signal for slice 1. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_PRBS_PATTERN_START_1 | R/W | 1h | PRBS7 start pattern for slice 1. |
DDRSS_PHY_268 is shown in Figure 8-990 and described in Table 8-1992.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4430h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_VREF_TRAIN_OBS_1 | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_VREF_INITIAL_STEPSIZE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_MULTI_PATT_RST_DISABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-23 | RESERVED | R/W | X | |
| 22-16 | PHY_VREF_TRAIN_OBS_1 | R | 0h | Observation register for best vref value for slice 1. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_VREF_INITIAL_STEPSIZE_1 | R/W | 0h | Data slice initial VREF training step size for slice 1. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_RDLVL_MULTI_PATT_RST_DISABLE_1 | R/W | 0h | Read Leveling read level windows disable reset for slice 1. |
DDRSS_PHY_269 is shown in Figure 8-991 and described in Table 8-1994.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4434h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_SNAP_OBS_REGS_1 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GATE_ERROR_DELAY_SELECT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | SC_PHY_SNAP_OBS_REGS_1 | W | 0h | Initiates a snapshot of the internal observation registers for slice 1. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GATE_ERROR_DELAY_SELECT_1 | R/W | 0h | Number of cycles to wait for the DQS gate to close before flagging an error for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1 | R/W | 0h | Read DQS data clock bypass mode slave delay setting for slice 1. |
DDRSS_PHY_270 is shown in Figure 8-992 and described in Table 8-1996.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4438h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_MEM_CLASS_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LPDDR_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL1_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL1_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_MEM_CLASS_1 | R/W | 0h | Indicates the type of DRAM for slice 1. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_LPDDR_1 | R/W | 0h | Adds a cycle of delay for the slice 1 to match the address slice. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_GATE_SMPL1_SLAVE_DELAY_1 | R/W | 0h | Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 1. |
DDRSS_PHY_271 is shown in Figure 8-993 and described in Table 8-1998.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 443Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | ON_FLY_GATE_ADJUST_EN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL2_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL2_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | ON_FLY_GATE_ADJUST_EN_1 | R/W | 0h | Control the on-the-fly gate adjustment for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_GATE_SMPL2_SLAVE_DELAY_1 | R/W | 0h | Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 1. |
DDRSS_PHY_272 is shown in Figure 8-994 and described in Table 8-2000.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4440h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_TRACKING_OBS_1 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_GATE_TRACKING_OBS_1 | R | 0h | Report the on-the-fly gate measurement result for slice 1. |
DDRSS_PHY_273 is shown in Figure 8-995 and described in Table 8-2002.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4444h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_PST_AMBLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DFI40_POLARITY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-8 | PHY_LP4_PST_AMBLE_1 | R/W | 0h | Controls the read postamble extension for LPDDR4 for slice 1. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DFI40_POLARITY_1 | R/W | 0h | Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 1. |
DDRSS_PHY_274 is shown in Figure 8-996 and described in Table 8-2004.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4448h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT8_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT8_1 | R/W | 0h | Read leveling pattern 8 data for slice 1. |
DDRSS_PHY_275 is shown in Figure 8-997 and described in Table 8-2006.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 444Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT9_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT9_1 | R/W | 0h | Read leveling pattern 9 data for slice 1. |
DDRSS_PHY_276 is shown in Figure 8-998 and described in Table 8-2008.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4450h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT10_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT10_1 | R/W | 0h | Read leveling pattern 10 data for slice 1. |
DDRSS_PHY_277 is shown in Figure 8-999 and described in Table 8-2010.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4454h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT11_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT11_1 | R/W | 0h | Read leveling pattern 11 data for slice 1. |
DDRSS_PHY_278 is shown in Figure 8-1000 and described in Table 8-2012.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4458h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT12_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT12_1 | R/W | 0h | Read leveling pattern 12 data for slice 1. |
DDRSS_PHY_279 is shown in Figure 8-1001 and described in Table 8-2014.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 445Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT13_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT13_1 | R/W | 0h | Read leveling pattern 13 data for slice 1. |
DDRSS_PHY_280 is shown in Figure 8-1002 and described in Table 8-2016.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4460h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT14_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT14_1 | R/W | 0h | Read leveling pattern 14 data for slice 1. |
DDRSS_PHY_281 is shown in Figure 8-1003 and described in Table 8-2018.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4464h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT15_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT15_1 | R/W | 0h | Read leveling pattern 15 data for slice 1. |
DDRSS_PHY_282 is shown in Figure 8-1004 and described in Table 8-2020.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4468h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQ_ENC_OBS_SELECT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DLY_LOCK_OBS_SELECT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_FIFO_PTR_RST_DISABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SLAVE_LOOP_CNT_UPDATE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_RDDQ_ENC_OBS_SELECT_1 | R/W | 0h | Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 1. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_MASTER_DLY_LOCK_OBS_SELECT_1 | R/W | 0h | Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_SW_FIFO_PTR_RST_DISABLE_1 | R/W | 0h | Disables automatic reset of the read entry FIFO pointers for slice 1. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_SLAVE_LOOP_CNT_UPDATE_1 | R/W | 0h | Reserved for future use for slice 1. |
DDRSS_PHY_283 is shown in Figure 8-1005 and described in Table 8-2022.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 446Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_FIFO_PTR_OBS_SELECT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WR_SHIFT_OBS_SELECT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WR_ENC_OBS_SELECT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQS_DQ_ENC_OBS_SELECT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_FIFO_PTR_OBS_SELECT_1 | R/W | 0h | Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 1. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_WR_SHIFT_OBS_SELECT_1 | R/W | 0h | Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 1. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WR_ENC_OBS_SELECT_1 | R/W | 0h | Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 1. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_RDDQS_DQ_ENC_OBS_SELECT_1 | R/W | 0h | Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 1. |
DDRSS_PHY_284 is shown in Figure 8-1006 and described in Table 8-2024.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4470h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_WRLVL_PER_START_1 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_ALGO_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_LVL_DEBUG_CONT_1 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LVL_DEBUG_MODE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_WRLVL_PER_START_1 | R/W | 0h | Observation register for write leveling status for slice 1. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_WRLVL_ALGO_1 | R/W | 0h | Write leveling algorithm selection for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8 | SC_PHY_LVL_DEBUG_CONT_1 | W | 0h | Allows the leveling state machine to advance (when in debug mode) for slice 1. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_LVL_DEBUG_MODE_1 | R/W | 0h | Enables leveling debug mode for slice 1. |
DDRSS_PHY_285 is shown in Figure 8-1007 and described in Table 8-2026.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4474h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQ_MASK_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_UPDT_WAIT_CNT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_CAPTURE_CNT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | X | |
| 23-16 | PHY_DQ_MASK_1 | R/W | 0h | For ECC slice, should set this register to do DQ bit mask for slice 1. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WRLVL_UPDT_WAIT_CNT_1 | R/W | 0h | Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 1. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_WRLVL_CAPTURE_CNT_1 | R/W | 0h | Number of samples to take at each DQS slave delay setting during write leveling for slice 1. |
DDRSS_PHY_286 is shown in Figure 8-1008 and described in Table 8-2028.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4478h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GTLVL_UPDT_WAIT_CNT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_CAPTURE_CNT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GTLVL_PER_START_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_PER_START_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_GTLVL_UPDT_WAIT_CNT_1 | R/W | 0h | Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 1. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_GTLVL_CAPTURE_CNT_1 | R/W | 0h | Number of samples to take at each DQS slave delay setting during gate training for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_PER_START_1 | R/W | 0h | Value to be added to the current gate delay position as the staring point for periodic gate training for slice 1. |
DDRSS_PHY_287 is shown in Figure 8-1009 and described in Table 8-2030.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 447Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDLVL_OP_MODE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_UPDT_WAIT_CNT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_CAPTURE_CNT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 1. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_RDLVL_OP_MODE_1 | R/W | 0h | Read leveling algorithm select for slice 1. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_RDLVL_UPDT_WAIT_CNT_1 | R/W | 0h | Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 1. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_RDLVL_CAPTURE_CNT_1 | R/W | 0h | Number of samples to take at each DQS slave delay setting during read leveling for slice 1. |
DDRSS_PHY_288 is shown in Figure 8-1010 and described in Table 8-2032.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4480h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_BURST_CNT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_WDQLVL_CLK_JITTER_TOLERANCE_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDLVL_DATA_MASK_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PERIODIC_OBS_SELECT_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_WDQLVL_BURST_CNT_1 | R/W | 0h | Defines the write/read burst length in bytes during the write data leveling sequence for slice 1. |
| 23-16 | PHY_WDQLVL_CLK_JITTER_TOLERANCE_1 | R/W | 0h | Defines the minimum gap requirment for the LE and TE window for slice 1. |
| 15-8 | PHY_RDLVL_DATA_MASK_1 | R/W | 0h | Per-bit mask for read leveling for slice 1. |
| 7-0 | PHY_RDLVL_PERIODIC_OBS_SELECT_1 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 1. |
DDRSS_PHY_289 is shown in Figure 8-1011 and described in Table 8-2034.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4484h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_UPDT_WAIT_CNT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_PATT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_WDQLVL_UPDT_WAIT_CNT_1 | R/W | 0h | Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 1. |
| 23-19 | RESERVED | R/W | X | |
| 18-8 | PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1 | R/W | 0h | Defines the write/read burst length in bytes during the write data leveling sequence for slice 1. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_WDQLVL_PATT_1 | R/W | 0h | Defines the training patterns to be used during the write data leveling sequence for slice 1. |
DDRSS_PHY_290 is shown in Figure 8-1012 and described in Table 8-2036.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4488h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_WDQLVL_CLR_PREV_RESULTS_1 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_PERIODIC_OBS_SELECT_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DQDM_OBS_SELECT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | SC_PHY_WDQLVL_CLR_PREV_RESULTS_1 | W | 0h | Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 1. |
| 15-8 | PHY_WDQLVL_PERIODIC_OBS_SELECT_1 | R/W | 0h | Select value to map specific information during or post periodic write data leveling for slice 1. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_WDQLVL_DQDM_OBS_SELECT_1 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 1. |
DDRSS_PHY_291 is shown in Figure 8-1013 and described in Table 8-2038.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 448Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DATADM_MASK_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R/W | X | |
| 8-0 | PHY_WDQLVL_DATADM_MASK_1 | R/W | 0h | Per-bit mask for write data leveling for slice 1. |
DDRSS_PHY_292 is shown in Figure 8-1014 and described in Table 8-2040.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4490h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT0_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT0_1 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 1. |
DDRSS_PHY_293 is shown in Figure 8-1015 and described in Table 8-2042.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4494h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT1_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT1_1 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 1. |
DDRSS_PHY_294 is shown in Figure 8-1016 and described in Table 8-2044.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4498h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT2_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT2_1 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 1. |
DDRSS_PHY_295 is shown in Figure 8-1017 and described in Table 8-2046.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 449Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT3_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT3_1 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 1. |
DDRSS_PHY_296 is shown in Figure 8-1018 and described in Table 8-2048.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_MULT_TRAIN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_USER_PATT4_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT4_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_NTP_MULT_TRAIN_1 | R/W | 0h | Control for single pass only No-Topology training for slice 1. |
| 15-0 | PHY_USER_PATT4_1 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 1. |
DDRSS_PHY_297 is shown in Figure 8-1019 and described in Table 8-2050.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_EARLY_THRESHOLD_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_NTP_PERIOD_THRESHOLD_1 | R/W | 0h | Threshold Criteria of period threshold after No-Topology training is completed for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_NTP_EARLY_THRESHOLD_1 | R/W | 0h | Threshold Criteria of early threshold after No-Topology training is completed for slice 1. |
DDRSS_PHY_298 is shown in Figure 8-1020 and described in Table 8-2052.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44A8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_MAX_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_MIN_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_NTP_PERIOD_THRESHOLD_MAX_1 | R/W | 0h | Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary, to set period threshold/early threshold after No-Topology training is completed for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_NTP_PERIOD_THRESHOLD_MIN_1 | R/W | 0h | Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary, to set period threshold/early threshold after No-Topology training is completed for slice 1. |
DDRSS_PHY_299 is shown in Figure 8-1021 and described in Table 8-2054.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44ACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_FIFO_PTR_OBS_1 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_MANUAL_CLEAR_1 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CALVL_VREF_DRIVING_SLICE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | X | |
| 23-16 | PHY_FIFO_PTR_OBS_1 | R | 0h | Observation register containing read entry FIFO pointers for slice 1. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | SC_PHY_MANUAL_CLEAR_1 | W | 0h | Manual reset/clear of internal logic for slice 1. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_CALVL_VREF_DRIVING_SLICE_1 | R/W | 0h | Indicates if slice 1 is used to drive the VREF value to the device during CA training. |
DDRSS_PHY_300 is shown in Figure 8-1022 and described in Table 8-2056.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44B0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LPBK_RESULT_OBS_1 | |||||||||||||||||||||||||||||||
| R-00100000h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_LPBK_RESULT_OBS_1 | R | 00100000h | Observation register containing loopback status/results for slice 1. |
DDRSS_PHY_301 is shown in Figure 8-1023 and described in Table 8-2058.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DLY_LOCK_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LPBK_ERROR_COUNT_OBS_1 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R | X | |
| 26-16 | PHY_MASTER_DLY_LOCK_OBS_1 | R | 0h | Observation register containing master delay results for slice 1. |
| 15-0 | PHY_LPBK_ERROR_COUNT_OBS_1 | R | 0h | Observation register containing total number of loopback error data for slice 1. |
DDRSS_PHY_302 is shown in Figure 8-1024 and described in Table 8-2060.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1 | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_MEAS_DLY_STEP_VALUE_1 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ_SLV_DLY_ENC_OBS_1 | ||||||
| R-X | R-0h | ||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1 | R | 0h | Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 1. |
| 23-16 | PHY_MEAS_DLY_STEP_VALUE_1 | R | 0h | Observation register containing fraction of the cycle in 1 delay element, numerator with demominator of 512, for slice 1. |
| 15 | RESERVED | R | X | |
| 14-8 | PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1 | R | 0h | Observation register containing read DQS base slave delay encoded value for slice 1. |
| 7 | RESERVED | R | X | |
| 6-0 | PHY_RDDQ_SLV_DLY_ENC_OBS_1 | R | 0h | Observation register containing read DQ slave delay encoded values for slice 1. |
DDRSS_PHY_303 is shown in Figure 8-1025 and described in Table 8-2062.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1 | ||||||
| R-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R | X | |
| 30-24 | PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1 | R | 0h | Observation register containing write DQS base slave delay encoded value for slice 1. |
| 23-19 | RESERVED | R | X | |
| 18-8 | PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1 | R | 0h | Observation register containing read DQS gate slave delay encoded value for slice 1. |
| 7-0 | PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1 | R | 0h | Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 1. |
DDRSS_PHY_304 is shown in Figure 8-1026 and described in Table 8-2064.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WR_SHIFT_OBS_1 | ||||||
| R-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WR_ADDER_SLV_DLY_ENC_OBS_1 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R | X | |
| 18-16 | PHY_WR_SHIFT_OBS_1 | R | 0h | Observation register containing automatic half cycle and cycle shift values for slice 1. |
| 15-8 | PHY_WR_ADDER_SLV_DLY_ENC_OBS_1 | R | 0h | Observation register containing write adder slave delay encoded value for slice 1. |
| 7-0 | PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1 | R | 0h | Observation register containing write DQ base slave delay encoded value for slice 1. |
DDRSS_PHY_305 is shown in Figure 8-1027 and described in Table 8-2066.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44C4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_HARD1_DELAY_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_HARD0_DELAY_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_WRLVL_HARD1_DELAY_OBS_1 | R | 0h | Observation register containing write leveling first hard 1 DQS slave delay for slice 1. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_WRLVL_HARD0_DELAY_OBS_1 | R | 0h | Observation register containing write leveling last hard 0 DQS slave delay for slice 1. |
DDRSS_PHY_306 is shown in Figure 8-1028 and described in Table 8-2068.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44C8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_STATUS_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_STATUS_OBS_1 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R | X | |
| 16-0 | PHY_WRLVL_STATUS_OBS_1 | R | 0h | Observation register containing write leveling status for slice 1. |
DDRSS_PHY_307 is shown in Figure 8-1029 and described in Table 8-2070.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1 | R | 0h | Observation register containing gate sample2 slave delay encoded values for slice 1. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1 | R | 0h | Observation register containing gate sample1 slave delay encoded values for slice 1. |
DDRSS_PHY_308 is shown in Figure 8-1030 and described in Table 8-2072.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44D0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_HARD0_DELAY_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_ERROR_OBS_1 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R | X | |
| 29-16 | PHY_GTLVL_HARD0_DELAY_OBS_1 | R | 0h | Observation register containing gate training first hard 0 DQS slave delay for slice 1. |
| 15-0 | PHY_WRLVL_ERROR_OBS_1 | R | 0h | Observation register containing write leveling error status for slice 1. |
DDRSS_PHY_309 is shown in Figure 8-1031 and described in Table 8-2074.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44D4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GTLVL_HARD1_DELAY_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-14 | RESERVED | R | X | |
| 13-0 | PHY_GTLVL_HARD1_DELAY_OBS_1 | R | 0h | Observation register containing gate training last hard 1 DQS slave delay for slice 1. |
DDRSS_PHY_310 is shown in Figure 8-1032 and described in Table 8-2076.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44D8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_STATUS_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_STATUS_OBS_1 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R | X | |
| 17-0 | PHY_GTLVL_STATUS_OBS_1 | R | 0h | Observation register containing gate training status for slice 1. |
DDRSS_PHY_311 is shown in Figure 8-1033 and described in Table 8-2078.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44DCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1 | R | 0h | Observation register containing read leveling data window trailing edge slave delay setting for slice 1. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1 | R | 0h | Observation register containing read leveling data window leading edge slave delay setting for slice 1. |
DDRSS_PHY_312 is shown in Figure 8-1034 and described in Table 8-2080.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1 | ||||||
| R-X | R-0h | ||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | X | |
| 1-0 | PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1 | R | 0h | Observation register containing read leveling number of windows found for slice 1. |
DDRSS_PHY_313 is shown in Figure 8-1035 and described in Table 8-2082.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_STATUS_OBS_1 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_STATUS_OBS_1 | R | 0h | Observation register containing read leveling status for slice 1. |
DDRSS_PHY_314 is shown in Figure 8-1036 and described in Table 8-2084.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44E8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PERIODIC_OBS_1 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PERIODIC_OBS_1 | R | 0h | Observation register containing periodic read leveling status for slice 1. |
DDRSS_PHY_315 is shown in Figure 8-1037 and described in Table 8-2086.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44ECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DQDM_TE_DLY_OBS_1 | ||||||||||||||
| R-X | R-7FFh | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DQDM_LE_DLY_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R | X | |
| 26-16 | PHY_WDQLVL_DQDM_TE_DLY_OBS_1 | R | 7FFh | Observation register containing write data leveling data window trailing edge slave delay setting for slice 1. |
| 15-11 | RESERVED | R | X | |
| 10-0 | PHY_WDQLVL_DQDM_LE_DLY_OBS_1 | R | 0h | Observation register containing write data leveling data window leading edge slave delay setting for slice 1. |
DDRSS_PHY_316 is shown in Figure 8-1038 and described in Table 8-2088.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_STATUS_OBS_1 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_WDQLVL_STATUS_OBS_1 | R | 0h | Observation register containing write data leveling status for slice 1. |
DDRSS_PHY_317 is shown in Figure 8-1039 and described in Table 8-2090.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44F4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_PERIODIC_OBS_1 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_WDQLVL_PERIODIC_OBS_1 | R | 0h | Observation register containing periodic write data leveling status for slice 1. |
DDRSS_PHY_318 is shown in Figure 8-1040 and described in Table 8-2092.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44F8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DDL_MODE_1 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-0 | PHY_DDL_MODE_1 | R/W | 0h | DDL mode for slice 1. |
DDRSS_PHY_319 is shown in Figure 8-1041 and described in Table 8-2094.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 44FCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DDL_MASK_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DDL_MASK_1 | R/W | 0h | DDL mask for slice 1. |
DDRSS_PHY_320 is shown in Figure 8-1042 and described in Table 8-2096.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4500h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TEST_OBS_1 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DDL_TEST_OBS_1 | R | 0h | DDL test observation for slice 1. |
DDRSS_PHY_321 is shown in Figure 8-1043 and described in Table 8-2098.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4504h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TEST_MSTR_DLY_OBS_1 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DDL_TEST_MSTR_DLY_OBS_1 | R | 0h | DDL test observation delays for slice 1 master DDL. |
DDRSS_PHY_322 is shown in Figure 8-1044 and described in Table 8-2100.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4508h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_OVERRIDE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_RX_CAL_START_1 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_WDQS_OE_EXTEND_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TRACK_UPD_THRESHOLD_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RX_CAL_OVERRIDE_1 | R/W | 0h | Manual setting of RX Calibration enable for slice 1. |
| 23-17 | RESERVED | R/W | X | |
| 16 | SC_PHY_RX_CAL_START_1 | W | 0h | Manual RX Calibration start for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_LP4_WDQS_OE_EXTEND_1 | R/W | 0h | LPDDR4 write preamble extension enable for slice 1. |
| 7-0 | PHY_DDL_TRACK_UPD_THRESHOLD_1 | R/W | 0h | Specify threshold value for PHY init update tracking for slice 1. |
DDRSS_PHY_323 is shown in Figure 8-1045 and described in Table 8-2102.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 450Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_DQ0_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RX_CAL_DQ0_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RX_CAL_SAMPLE_WAIT_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ0_1 | R/W | 0h | RX Calibration codes for DQ0 for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1 | R/W | 0h | Data slice power reduction disable for slice 1. |
| 7-0 | PHY_RX_CAL_SAMPLE_WAIT_1 | R/W | 0h | RX Calibration state machine wait count for slice 1. |
DDRSS_PHY_324 is shown in Figure 8-1046 and described in Table 8-2104.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4510h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ2_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ1_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ2_1 | R/W | 0h | RX Calibration codes for DQ2 for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ1_1 | R/W | 0h | RX Calibration codes for DQ1 for slice 1. |
DDRSS_PHY_325 is shown in Figure 8-1047 and described in Table 8-2106.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4514h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ4_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ3_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ4_1 | R/W | 0h | RX Calibration codes for DQ4 for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ3_1 | R/W | 0h | RX Calibration codes for DQ3 for slice 1. |
DDRSS_PHY_326 is shown in Figure 8-1048 and described in Table 8-2108.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4518h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ6_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ5_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ6_1 | R/W | 0h | RX Calibration codes for DQ6 for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ5_1 | R/W | 0h | RX Calibration codes for DQ5 for slice 1. |
DDRSS_PHY_327 is shown in Figure 8-1049 and described in Table 8-2110.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 451Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ7_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ7_1 | R/W | 0h | RX Calibration codes for DQ7 for slice 1. |
DDRSS_PHY_328 is shown in Figure 8-1050 and described in Table 8-2112.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4520h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DM_1 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_RX_CAL_DM_1 | R/W | 0h | RX Calibration codes for DM for slice 1. |
DDRSS_PHY_329 is shown in Figure 8-1051 and described in Table 8-2114.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4524h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_FDBK_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQS_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_FDBK_1 | R/W | 0h | RX Calibration codes for FDBK for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQS_1 | R/W | 0h | RX Calibration codes for DQS for slice 1. |
DDRSS_PHY_330 is shown in Figure 8-1052 and described in Table 8-2116.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4528h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_LOCK_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R | X | |
| 24-16 | PHY_RX_CAL_LOCK_OBS_1 | R | 0h | RX Calibration lock results for slice 1. |
| 15-11 | RESERVED | R | X | |
| 10-0 | PHY_RX_CAL_OBS_1 | R | 0h | RX Calibration results for slice 1. |
DDRSS_PHY_331 is shown in Figure 8-1053 and described in Table 8-2118.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 452Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_COMP_VAL_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DIFF_ADJUST_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RX_CAL_SE_ADJUST_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DISABLE_1 | ||||||
| R/W-X | R/W-1h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RX_CAL_COMP_VAL_1 | R/W | 0h | Expected C value from RX pad for slice 1. |
| 23 | RESERVED | R/W | X | |
| 22-16 | PHY_RX_CAL_DIFF_ADJUST_1 | R/W | 0h | Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 1. |
| 15 | RESERVED | R/W | X | |
| 14-8 | PHY_RX_CAL_SE_ADJUST_1 | R/W | 0h | Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 1. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_RX_CAL_DISABLE_1 | R/W | 1h | RX CAL disable signal for slice 1, set 1 to bypass the rx calibration |
DDRSS_PHY_332 is shown in Figure 8-1054 and described in Table 8-2120.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4530h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_BIAS_EN_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_INDEX_MASK_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_PAD_RX_BIAS_EN_1 | R/W | 0h | Controls RX_BIAS_EN pin for each pad for slice 1. |
| 15-12 | RESERVED | R/W | X | |
| 11-0 | PHY_RX_CAL_INDEX_MASK_1 | R/W | 0h | RX offset calibration mask of all RX pad for slice 1. |
DDRSS_PHY_333 is shown in Figure 8-1055 and described in Table 8-2122.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4534h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_WEIGHT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_CAL_TIMEOUT_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_CAL_SAMPLE_WAIT_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_STATIC_TOG_DISABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_DATA_DC_WEIGHT_1 | R/W | 0h | Determines weight of average calculating for slice 1. |
| 23-16 | PHY_DATA_DC_CAL_TIMEOUT_1 | R/W | 0h | Determines timeout number of iteration for slice 1. |
| 15-8 | PHY_DATA_DC_CAL_SAMPLE_WAIT_1 | R/W | 0h | Determines number of cycles to wait for each sample for slice 1. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_STATIC_TOG_DISABLE_1 | R/W | 0h | Control to disable toggle during static activity for slice 1. |
DDRSS_PHY_334 is shown in Figure 8-1056 and described in Table 8-2124.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4538h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_ADJUST_DIRECT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_ADJUST_THRSHLD_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_ADJUST_SAMPLE_CNT_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_ADJUST_START_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_DATA_DC_ADJUST_DIRECT_1 | R/W | 0h | Adjust direction for slice 1. |
| 23-16 | PHY_DATA_DC_ADJUST_THRSHLD_1 | R/W | 0h | Duty cycle adjust threshold around the mid-point for slice 1. |
| 15-8 | PHY_DATA_DC_ADJUST_SAMPLE_CNT_1 | R/W | 0h | Duty cycle adjust sample count for slice 1. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DATA_DC_ADJUST_START_1 | R/W | 0h | Duty cycle adjust starting value for slice 1. |
DDRSS_PHY_335 is shown in Figure 8-1057 and described in Table 8-2126.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 453Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_FDBK_PWR_CTRL_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_SW_RANK_1 | ||||||
| R/W-X | R/W-1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_CAL_START_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_CAL_POLARITY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_FDBK_PWR_CTRL_1 | R/W | 0h | Shutoff gate feedback IO to reduce power for slice 1. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DATA_DC_SW_RANK_1 | R/W | 1h | Rank selection for software based duty cycle correction for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DATA_DC_CAL_START_1 | R/W | 0h | Manual trigger for DCC for slice 1. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DATA_DC_CAL_POLARITY_1 | R/W | 0h | Calibration polarity for slice 1. |
DDRSS_PHY_336 is shown in Figure 8-1058 and described in Table 8-2128.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4540h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SLICE_PWR_RDC_DISABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDPATH_GATE_DISABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SLV_DLY_CTRL_GATE_DISABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_SLICE_PWR_RDC_DISABLE_1 | R/W | 0h | Data slice power reduction disable for slice 1. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1 | R/W | 0h | Data slice DCC and RX_CAL block power reduction disable for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_RDPATH_GATE_DISABLE_1 | R/W | 0h | Data slice read path power reduction disable for slice 1. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_SLV_DLY_CTRL_GATE_DISABLE_1 | R/W | 0h | Data slice slv_dly_control block power reduction disable for slice 1. |
DDRSS_PHY_337 is shown in Figure 8-1059 and described in Table 8-2130.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4544h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DS_FSM_ERROR_INFO_1 | ||||||||||||||
| R/W-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PARITY_ERROR_REGIF_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | PHY_DS_FSM_ERROR_INFO_1 | R | 0h | Data slice level FSM Error Info for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_PARITY_ERROR_REGIF_1 | R/W | 0h | Inject parity error to register interface signals for slice 1. |
DDRSS_PHY_338 is shown in Figure 8-1060 and described in Table 8-2132.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4548h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1 | |||||||
| W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DS_FSM_ERROR_INFO_MASK_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DS_FSM_ERROR_INFO_MASK_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1 | W | 0h | Data slice level FSM Error Info for slice 1. |
| 15-14 | RESERVED | R/W | X | |
| 13-0 | PHY_DS_FSM_ERROR_INFO_MASK_1 | R/W | 0h | Data slice level FSM Error Info Mask for slice 1. |
DDRSS_PHY_339 is shown in Figure 8-1061 and described in Table 8-2134.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 454Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DS_TRAIN_CALIB_ERROR_INFO_1 | ||||||
| R/W-X | R-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1 | W | 0h | Data slice level training/calibration Error Info for slice 1. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_1 | R/W | 0h | Data slice level training/calibration Error Info Mask for slice 1. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_DS_TRAIN_CALIB_ERROR_INFO_1 | R | 0h | Data slice level training/calibration Error Info for slice 1. |
DDRSS_PHY_340 is shown in Figure 8-1062 and described in Table 8-2136.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4550h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DQS_TSEL_ENABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQ_TSEL_SELECT_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_TSEL_SELECT_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DQ_TSEL_ENABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_DQS_TSEL_ENABLE_1 | R/W | 0h | Operation type tsel enables for DQS signals for slice 1. |
| 23-8 | PHY_DQ_TSEL_SELECT_1 | R/W | 0h | Operation type tsel select values for DQ/DM signals for slice 1. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_DQ_TSEL_ENABLE_1 | R/W | 0h | Operation type tsel enables for DQ/DM signals for slice 1. |
DDRSS_PHY_341 is shown in Figure 8-1063 and described in Table 8-2138.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4554h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_VREF_INITIAL_START_POINT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TWO_CYC_PREAMBLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQS_TSEL_SELECT_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQS_TSEL_SELECT_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-24 | PHY_VREF_INITIAL_START_POINT_1 | R/W | 0h | Data slice initial VREF training start value for slice 1. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_TWO_CYC_PREAMBLE_1 | R/W | 0h | 2 cycle preamble support for slice 1. |
| 15-0 | PHY_DQS_TSEL_SELECT_1 | R/W | 0h | Operation type tsel select values for DQS signals for slice 1. |
DDRSS_PHY_342 is shown in Figure 8-1064 and described in Table 8-2140.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4558h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_NTP_WDQ_STEP_SIZE_1 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_TRAIN_EN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_VREF_TRAINING_CTRL_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_VREF_INITIAL_STOP_POINT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_NTP_WDQ_STEP_SIZE_1 | R/W | 0h | Step size of WR DQ slave delay during No-Topology training for slice 1. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_NTP_TRAIN_EN_1 | R/W | 0h | Enable for No-Topology training for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_VREF_TRAINING_CTRL_1 | R/W | 0h | Data slice vref training enable control for slice 1. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_VREF_INITIAL_STOP_POINT_1 | R/W | 0h | Data slice initial VREF training stop value for slice 1. |
DDRSS_PHY_343 is shown in Figure 8-1065 and described in Table 8-2142.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 455Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_WDQ_STOP_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_WDQ_START_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_NTP_WDQ_STOP_1 | R/W | 0h | End of WR DQ slave delay in No-Topology training for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_NTP_WDQ_START_1 | R/W | 0h | Starting WR DQ slave delay in No-Topology training for slice 1. |
DDRSS_PHY_344 is shown in Figure 8-1066 and described in Table 8-2144.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4560h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WDQLVL_DVW_MIN_EN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DVW_MIN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_DVW_MIN_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_NTP_WDQ_BIT_EN_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_SW_WDQLVL_DVW_MIN_EN_1 | R/W | 0h | SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 1. |
| 23-18 | RESERVED | R/W | X | |
| 17-8 | PHY_WDQLVL_DVW_MIN_1 | R/W | 0h | Minimum data valid window across DQs and ranks for slice 1. |
| 7-0 | PHY_NTP_WDQ_BIT_EN_1 | R/W | 0h | Enable Bit for WR DQ during No-Topology training for slice 1. |
DDRSS_PHY_345 is shown in Figure 8-1067 and described in Table 8-2146.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4564h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_RX_DCD_0_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_TX_DCD_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_FAST_LVL_EN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_PER_START_OFFSET_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_RX_DCD_0_1 | R/W | 0h | Controls RX_DCD pin for each pad for slice 1. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_TX_DCD_1 | R/W | 0h | Controls TX_DCD pin for each pad for slice 1. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_FAST_LVL_EN_1 | R/W | 0h | Enable for fast multi-pattern window search for slice 1. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_WDQLVL_PER_START_OFFSET_1 | R/W | 0h | Peridic training start point offset for slice 1. |
DDRSS_PHY_346 is shown in Figure 8-1068 and described in Table 8-2148.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4568h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_RX_DCD_4_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_DCD_3_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_RX_DCD_2_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RX_DCD_1_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_RX_DCD_4_1 | R/W | 0h | Controls RX_DCD pin for each pad for slice 1. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_RX_DCD_3_1 | R/W | 0h | Controls RX_DCD pin for each pad for slice 1. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_RX_DCD_2_1 | R/W | 0h | Controls RX_DCD pin for each pad for slice 1. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_RX_DCD_1_1 | R/W | 0h | Controls RX_DCD pin for each pad for slice 1. |
DDRSS_PHY_347 is shown in Figure 8-1069 and described in Table 8-2150.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 456Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_DM_RX_DCD_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_DCD_7_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_RX_DCD_6_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RX_DCD_5_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_DM_RX_DCD_1 | R/W | 0h | Controls RX_DCD pin for dm pad for slice 1. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_RX_DCD_7_1 | R/W | 0h | Controls RX_DCD pin for each pad for slice 1. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_RX_DCD_6_1 | R/W | 0h | Controls RX_DCD pin for each pad for slice 1. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_RX_DCD_5_1 | R/W | 0h | Controls RX_DCD pin for each pad for slice 1. |
DDRSS_PHY_348 is shown in Figure 8-1070 and described in Table 8-2152.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4570h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_DSLICE_IO_CFG_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_FDBK_RX_DCD_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_DQS_RX_DCD_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-22 | RESERVED | R/W | X | |
| 21-16 | PHY_PAD_DSLICE_IO_CFG_1 | R/W | 0h | Controls PCLK/PARK pin for pad for slice 1. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_FDBK_RX_DCD_1 | R/W | 0h | Controls RX_DCD pin for fdbk pad for slice 1. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_DQS_RX_DCD_1 | R/W | 0h | Controls RX_DCD pin for dqs pad for slice 1. |
DDRSS_PHY_349 is shown in Figure 8-1071 and described in Table 8-2154.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4574h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ1_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ0_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ1_SLAVE_DELAY_1 | R/W | 0h | Read DQ1 slave delay setting for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ0_SLAVE_DELAY_1 | R/W | 0h | Read DQ0 slave delay setting for slice 1. |
DDRSS_PHY_350 is shown in Figure 8-1072 and described in Table 8-2156.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4578h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ3_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ2_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ3_SLAVE_DELAY_1 | R/W | 0h | Read DQ3 slave delay setting for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ2_SLAVE_DELAY_1 | R/W | 0h | Read DQ2 slave delay setting for slice 1. |
DDRSS_PHY_351 is shown in Figure 8-1073 and described in Table 8-2158.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 457Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ5_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ4_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ5_SLAVE_DELAY_1 | R/W | 0h | Read DQ5 slave delay setting for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ4_SLAVE_DELAY_1 | R/W | 0h | Read DQ4 slave delay setting for slice 1. |
DDRSS_PHY_352 is shown in Figure 8-1074 and described in Table 8-2160.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4580h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ7_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ6_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ7_SLAVE_DELAY_1 | R/W | 0h | Read DQ7 slave delay setting for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ6_SLAVE_DELAY_1 | R/W | 0h | Read DQ6 slave delay setting for slice 1. |
DDRSS_PHY_353 is shown in Figure 8-1075 and described in Table 8-2162.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4584h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_CAL_CLK_SEL_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDM_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDM_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R/W | X | |
| 18-16 | PHY_DATA_DC_CAL_CLK_SEL_1 | R/W | 0h | Determines DCC CAL clock for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDM_SLAVE_DELAY_1 | R/W | 0h | Read DM/DBI slave delay setting for slice 1. |
DDRSS_PHY_354 is shown in Figure 8-1076 and described in Table 8-2164.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4588h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_OE_TIMING_1 | PHY_DQ_TSEL_WR_TIMING_1 | ||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQ_TSEL_RD_TIMING_1 | PHY_DQ_OE_TIMING_1 | ||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DQS_OE_TIMING_1 | R/W | 0h | Start/end timing values for DQS output enable signals for slice 1. |
| 23-16 | PHY_DQ_TSEL_WR_TIMING_1 | R/W | 0h | Start/end timing values for DQ/DM write based termination enable and select signals for slice 1. |
| 15-8 | PHY_DQ_TSEL_RD_TIMING_1 | R/W | 0h | Start/end timing values for DQ/DM read based termination enable and select signals for slice 1. |
| 7-0 | PHY_DQ_OE_TIMING_1 | R/W | 0h | Start/end timing values for DQ/DM output enable signals for slice 1. |
DDRSS_PHY_355 is shown in Figure 8-1077 and described in Table 8-2166.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 458Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DQS_TSEL_WR_TIMING_1 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_OE_RD_TIMING_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQS_TSEL_RD_TIMING_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_IO_PAD_DELAY_TIMING_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DQS_TSEL_WR_TIMING_1 | R/W | 0h | Start/end timing values for DQS write based termination enable and select signals for slice 1. |
| 23-16 | PHY_DQS_OE_RD_TIMING_1 | R/W | 0h | Start/end timing values for DQS read based OE extension for slice 1. |
| 15-8 | PHY_DQS_TSEL_RD_TIMING_1 | R/W | 0h | Start/end timing values for DQS read based termination enable and select signals for slice 1. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_IO_PAD_DELAY_TIMING_1 | R/W | 0h | Feedback pad's OPAD and IPAD delay timing for slice 1. |
DDRSS_PHY_356 is shown in Figure 8-1078 and described in Table 8-2168.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4590h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_VREF_CTRL_DQ_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_VREF_SETTING_TIME_1 | |||||||||||||||
| R/W-0h | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-16 | PHY_PAD_VREF_CTRL_DQ_1 | R/W | 0h | Pad VREF control settings for DQ slice 1.
|
| 15-0 | PHY_VREF_SETTING_TIME_1 | R/W | 0h | Number of cycles for vref settle after setting is changed for slice 1. |
DDRSS_PHY_357 is shown in Figure 8-1079 and described in Table 8-2170.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4594h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDATA_EN_IE_DLY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_IE_TIMING_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_IE_TIMING_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PER_CS_TRAINING_EN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_RDDATA_EN_IE_DLY_1 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 1. |
| 23-16 | PHY_DQS_IE_TIMING_1 | R/W | 0h | Start/end timing values for DQS input enable signals for slice 1. |
| 15-8 | PHY_DQ_IE_TIMING_1 | R/W | 0h | Start/end timing values for DQ/DM input enable signals for slice 1. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_PER_CS_TRAINING_EN_1 | R/W | 0h | Enables the per-rank training and read/write timing capabilities for slice 1. |
DDRSS_PHY_358 is shown in Figure 8-1080 and described in Table 8-2172.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4598h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDATA_EN_OE_DLY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDATA_EN_TSEL_DLY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DBI_MODE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_IE_MODE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_RDDATA_EN_OE_DLY_1 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 1. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_RDDATA_EN_TSEL_DLY_1 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DBI_MODE_1 | R/W | 0h | DBI mode for slice 1. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_IE_MODE_1 | R/W | 0h | Input enable mode bits for slice 1. |
DDRSS_PHY_359 is shown in Figure 8-1081 and described in Table 8-2174.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 459Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_MASTER_DELAY_STEP_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DELAY_START_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_MASTER_DELAY_START_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_MASTER_MODE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_MASTER_DELAY_STEP_1 | R/W | 0h | Incremental step size for master delay line locking algorithm for slice 1. |
| 23-19 | RESERVED | R/W | X | |
| 18-8 | PHY_MASTER_DELAY_START_1 | R/W | 0h | Start value for master delay line locking algorithm for slice 1. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_SW_MASTER_MODE_1 | R/W | 0h | Master delay line override settings for slice 1. |
DDRSS_PHY_360 is shown in Figure 8-1082 and described in Table 8-2176.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_WRLVL_DLY_STEP_1 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RPTR_UPDATE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_MASTER_DELAY_HALF_MEASURE_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_MASTER_DELAY_WAIT_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_WRLVL_DLY_STEP_1 | R/W | 0h | DQS slave delay step size during write leveling for slice 1. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_RPTR_UPDATE_1 | R/W | 0h | Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 1. |
| 15-8 | PHY_MASTER_DELAY_HALF_MEASURE_1 | R/W | 0h | Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 1. |
| 7-0 | PHY_MASTER_DELAY_WAIT_1 | R/W | 0h | Wait cycles for master delay line locking algorithm for slice 1. |
DDRSS_PHY_361 is shown in Figure 8-1083 and described in Table 8-2178.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GTLVL_RESP_WAIT_CNT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_DLY_STEP_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_RESP_WAIT_CNT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_DLY_FINE_STEP_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_GTLVL_RESP_WAIT_CNT_1 | R/W | 0h | Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 1. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GTLVL_DLY_STEP_1 | R/W | 0h | DQS slave delay step size during gate training for slice 1. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_WRLVL_RESP_WAIT_CNT_1 | R/W | 0h | Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 1. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_WRLVL_DLY_FINE_STEP_1 | R/W | 0h | DQS slave delay fine step size during write leveling for slice 1. |
DDRSS_PHY_362 is shown in Figure 8-1084 and described in Table 8-2180.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45A8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_FINAL_STEP_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GTLVL_BACK_STEP_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_GTLVL_FINAL_STEP_1 | R/W | 0h | Final backup step delay used in gate training algorithm for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_BACK_STEP_1 | R/W | 0h | Interim backup step delay used in gate training algorithm for slice 1. |
DDRSS_PHY_363 is shown in Figure 8-1085 and described in Table 8-2182.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45ACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_DLY_STEP_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TOGGLE_PRE_SUPPORT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_QTR_DLY_STEP_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_DLY_STEP_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_RDLVL_DLY_STEP_1 | R/W | 0h | DQS slave delay step size during read leveling for slice 1. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_TOGGLE_PRE_SUPPORT_1 | R/W | 0h | Support the toggle read preamble for LPDDR4 for slice 1. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WDQLVL_QTR_DLY_STEP_1 | R/W | 0h | Defines the step granularity for the logic to use once an edge is found for slice 1. |
| 7-0 | PHY_WDQLVL_DLY_STEP_1 | R/W | 0h | DQ slave delay step size during write data leveling for slice 1. |
DDRSS_PHY_364 is shown in Figure 8-1086 and described in Table 8-2184.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45B0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_MAX_EDGE_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_MAX_EDGE_1 | R/W | 0h | The maximun rdlvl slave delay search window for read eye training for slice 1. |
DDRSS_PHY_365 is shown in Figure 8-1087 and described in Table 8-2186.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_PER_START_OFFSET_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_RDLVL_DVW_MIN_EN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_DVW_MIN_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_DVW_MIN_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_RDLVL_PER_START_OFFSET_1 | R/W | 0h | Peridic training start point offset for slice 1. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_SW_RDLVL_DVW_MIN_EN_1 | R/W | 0h | SW override to enable use of PHY_RDLVL_DVW_MIN for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_DVW_MIN_1 | R/W | 0h | Minimum data valid window across DQs and ranks for slice 1. |
DDRSS_PHY_366 is shown in Figure 8-1088 and described in Table 8-2188.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_INIT_DISABLE_1 | ||||||
| R/W-X | R/W-3h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRPATH_GATE_TIMING_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRPATH_GATE_DISABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DATA_DC_INIT_DISABLE_1 | R/W | 3h | Disable duty cycle adjust at initialization for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_WRPATH_GATE_TIMING_1 | R/W | 0h | Write path clock gating timing for slice 1. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_WRPATH_GATE_DISABLE_1 | R/W | 0h | Write path clock gating disable for slice 1. |
DDRSS_PHY_367 is shown in Figure 8-1089 and described in Table 8-2190.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_DQ_INIT_SLV_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ_INIT_SLV_DELAY_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_DQS_INIT_SLV_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQS_INIT_SLV_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_DATA_DC_DQ_INIT_SLV_DELAY_1 | R/W | 0h | Initial value of write DQ slave delay for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_DATA_DC_DQS_INIT_SLV_DELAY_1 | R/W | 0h | Initial value of write DQS slave delay for slice 1. |
DDRSS_PHY_368 is shown in Figure 8-1090 and described in Table 8-2192.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DM_CLK_SE_THRSHLD_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_WDQLVL_ENABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_WRLVL_ENABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1 | R/W | 0h | Clock measurement cell threshold offset for differential signals for slice 1. |
| 23-16 | PHY_DATA_DC_DM_CLK_SE_THRSHLD_1 | R/W | 0h | Clock measurement cell threshold offset for single ended signals for slice 1. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DATA_DC_WDQLVL_ENABLE_1 | R/W | 0h | Enable duty cycle adjust during write DQ training for slice 1. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DATA_DC_WRLVL_ENABLE_1 | R/W | 0h | Enable duty cycle adjust during write leveling for slice 1. |
DDRSS_PHY_369 is shown in Figure 8-1091 and described in Table 8-2194.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45C4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDATA_EN_DLY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_MEAS_DLY_STEP_ENABLE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQ_OSC_DELTA_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | PHY_RDDATA_EN_DLY_1 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is early for slice 1. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_MEAS_DLY_STEP_ENABLE_1 | R/W | 0h | Data slice training step definition using phy_meas_dly_step_value for slice 1. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_WDQ_OSC_DELTA_1 | R/W | 0h | Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 1. |
DDRSS_PHY_370 is shown in Figure 8-1092 and described in Table 8-2196.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45C8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQ_DM_SWIZZLE0_1 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DQ_DM_SWIZZLE0_1 | R/W | 0h | DQ/DM bit swizzling 0 for slice 1. |
DDRSS_PHY_371 is shown in Figure 8-1093 and described in Table 8-2198.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DQ_DM_SWIZZLE1_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R/W | X | |
| 3-0 | PHY_DQ_DM_SWIZZLE1_1 | R/W | 0h | DQ/DM bit swizzling 1 for slice 1. |
DDRSS_PHY_372 is shown in Figure 8-1094 and described in Table 8-2200.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45D0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ1_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ0_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ1_SLAVE_DELAY_1 | R/W | 0h | Write clock slave delay setting for DQ1 for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ0_SLAVE_DELAY_1 | R/W | 0h | Write clock slave delay setting for DQ0 for slice 1. |
DDRSS_PHY_373 is shown in Figure 8-1095 and described in Table 8-2202.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45D4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ3_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ2_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ3_SLAVE_DELAY_1 | R/W | 0h | Write clock slave delay setting for DQ3 for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ2_SLAVE_DELAY_1 | R/W | 0h | Write clock slave delay setting for DQ2 for slice 1. |
DDRSS_PHY_374 is shown in Figure 8-1096 and described in Table 8-2204.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45D8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ5_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ4_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ5_SLAVE_DELAY_1 | R/W | 0h | Write clock slave delay setting for DQ5 for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ4_SLAVE_DELAY_1 | R/W | 0h | Write clock slave delay setting for DQ4 for slice 1. |
DDRSS_PHY_375 is shown in Figure 8-1097 and described in Table 8-2206.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45DCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ7_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ6_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ7_SLAVE_DELAY_1 | R/W | 0h | Write clock slave delay setting for DQ7 for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ6_SLAVE_DELAY_1 | R/W | 0h | Write clock slave delay setting for DQ6 for slice 1. |
DDRSS_PHY_376 is shown in Figure 8-1098 and described in Table 8-2208.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQS_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDM_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_CLK_WRDQS_SLAVE_DELAY_1 | R/W | 0h | Write clock slave delay setting for DQS for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDM_SLAVE_DELAY_1 | R/W | 0h | Write clock slave delay setting for DM for slice 1. |
DDRSS_PHY_377 is shown in Figure 8-1099 and described in Table 8-2210.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_THRESHOLD_ADJUST_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-8 | PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1 | R/W | 0h | Rising edge read DQS slave delay setting for DQ0 for slice 1. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_WRLVL_THRESHOLD_ADJUST_1 | R/W | 0h | Write level threshold adjust value based on those thresholds for DQS for slice 1. |
DDRSS_PHY_378 is shown in Figure 8-1100 and described in Table 8-2212.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45E8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1 | R/W | 0h | Rising edge read DQS slave delay setting for DQ1 for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1 | R/W | 0h | Falling edge read DQS slave delay setting for DQ0 for slice 1. |
DDRSS_PHY_379 is shown in Figure 8-1101 and described in Table 8-2214.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45ECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1 | R/W | 0h | Rising edge read DQS slave delay setting for DQ2 for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1 | R/W | 0h | Falling edge read DQS slave delay setting for DQ1 for slice 1. |
DDRSS_PHY_380 is shown in Figure 8-1102 and described in Table 8-2216.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1 | R/W | 0h | Rising edge read DQS slave delay setting for DQ3 for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1 | R/W | 0h | Falling edge read DQS slave delay setting for DQ2 for slice 1. |
DDRSS_PHY_381 is shown in Figure 8-1103 and described in Table 8-2218.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45F4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1 | R/W | 0h | Rising edge read DQS slave delay setting for DQ4 for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1 | R/W | 0h | Falling edge read DQS slave delay setting for DQ3 for slice 1. |
DDRSS_PHY_382 is shown in Figure 8-1104 and described in Table 8-2220.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45F8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1 | R/W | 0h | Rising edge read DQS slave delay setting for DQ5 for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1 | R/W | 0h | Falling edge read DQS slave delay setting for DQ4 for slice 1. |
DDRSS_PHY_383 is shown in Figure 8-1105 and described in Table 8-2222.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 45FCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1 | R/W | 0h | Rising edge read DQS slave delay setting for DQ6 for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1 | R/W | 0h | Falling edge read DQS slave delay setting for DQ5 for slice 1. |
DDRSS_PHY_384 is shown in Figure 8-1106 and described in Table 8-2224.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4600h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1 | R/W | 0h | Rising edge read DQS slave delay setting for DQ7 for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1 | R/W | 0h | Falling edge read DQS slave delay setting for DQ6 for slice 1. |
DDRSS_PHY_385 is shown in Figure 8-1107 and described in Table 8-2226.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4604h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DM_RISE_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DM_RISE_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DM_RISE_SLAVE_DELAY_1 | R/W | 0h | Rising edge read DQS slave delay setting for DM for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1 | R/W | 0h | Falling edge read DQS slave delay setting for DQ7 for slice 1. |
DDRSS_PHY_386 is shown in Figure 8-1108 and described in Table 8-2228.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4608h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_GATE_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_GATE_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DM_FALL_SLAVE_DELAY_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DM_FALL_SLAVE_DELAY_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_GATE_SLAVE_DELAY_1 | R/W | 0h | Read DQS slave delay setting for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DM_FALL_SLAVE_DELAY_1 | R/W | 0h | Falling edge read DQS slave delay setting for DM for slice 1. |
DDRSS_PHY_387 is shown in Figure 8-1109 and described in Table 8-2230.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 460Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WRLVL_DELAY_EARLY_THRESHOLD_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_WRLVL_DELAY_EARLY_THRESHOLD_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRITE_PATH_LAT_ADD_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQS_LATENCY_ADJUST_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_WRLVL_DELAY_EARLY_THRESHOLD_1 | R/W | 0h | Write level delay threshold above which will be considered in previous cycle for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_WRITE_PATH_LAT_ADD_1 | R/W | 0h | Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 1. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_RDDQS_LATENCY_ADJUST_1 | R/W | 0h | Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 1. |
DDRSS_PHY_388 is shown in Figure 8-1110 and described in Table 8-2232.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4610h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_EARLY_FORCE_ZERO_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_WRLVL_EARLY_FORCE_ZERO_1 | R/W | 0h | Force the final write level delay value (that meets the early threshold) to 0 for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1 | R/W | 0h | Write level delay threshold below which will add a cycle of write path latency for slice 1. |
DDRSS_PHY_389 is shown in Figure 8-1111 and described in Table 8-2234.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4614h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_LAT_ADJ_START_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GTLVL_RDDQS_SLV_DLY_START_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_RDDQS_SLV_DLY_START_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GTLVL_LAT_ADJ_START_1 | R/W | 0h | Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_RDDQS_SLV_DLY_START_1 | R/W | 0h | Initial read DQS gate slave delay setting during gate training for slice 1. |
DDRSS_PHY_390 is shown in Figure 8-1112 and described in Table 8-2236.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4618h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_NTP_PASS_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_WRLAT_START_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_DQDM_SLV_DLY_START_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_DQDM_SLV_DLY_START_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_NTP_PASS_1 | R/W | 0h | Indicates if No-topology training found a passing result for slice 1. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_NTP_WRLAT_START_1 | R/W | 0h | Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_WDQLVL_DQDM_SLV_DLY_START_1 | R/W | 0h | Initial DQ/DM slave delay setting during write data leveling for slice 1. |
DDRSS_PHY_391 is shown in Figure 8-1113 and described in Table 8-2238.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 461Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1 | R/W | 0h | Read leveling starting value for the DQS/DQ slave delay settings for slice 1. |
DDRSS_PHY_392 is shown in Figure 8-1114 and described in Table 8-2240.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4620h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DQ2_CLK_ADJUST_1 | |||||||
| R/W-20h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ1_CLK_ADJUST_1 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DQ0_CLK_ADJUST_1 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQS_CLK_ADJUST_1 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DQ2_CLK_ADJUST_1 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 1. |
| 23-16 | PHY_DATA_DC_DQ1_CLK_ADJUST_1 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 1. |
| 15-8 | PHY_DATA_DC_DQ0_CLK_ADJUST_1 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 1. |
| 7-0 | PHY_DATA_DC_DQS_CLK_ADJUST_1 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 1. |
DDRSS_PHY_393 is shown in Figure 8-1115 and described in Table 8-2242.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4624h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DQ6_CLK_ADJUST_1 | |||||||
| R/W-20h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ5_CLK_ADJUST_1 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DQ4_CLK_ADJUST_1 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQ3_CLK_ADJUST_1 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DQ6_CLK_ADJUST_1 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 1. |
| 23-16 | PHY_DATA_DC_DQ5_CLK_ADJUST_1 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 1. |
| 15-8 | PHY_DATA_DC_DQ4_CLK_ADJUST_1 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 1. |
| 7-0 | PHY_DATA_DC_DQ3_CLK_ADJUST_1 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 1. |
DDRSS_PHY_394 is shown in Figure 8-1116 and described in Table 8-2244.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4628h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DSLICE_PAD_BOOSTPN_SETTING_1 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DSLICE_PAD_BOOSTPN_SETTING_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DM_CLK_ADJUST_1 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQ7_CLK_ADJUST_1 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | PHY_DSLICE_PAD_BOOSTPN_SETTING_1 | R/W | 0h | Setting for boost P/N of pad for slice 1. |
| 15-8 | PHY_DATA_DC_DM_CLK_ADJUST_1 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 1. |
| 7-0 | PHY_DATA_DC_DQ7_CLK_ADJUST_1 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 1. |
DDRSS_PHY_395 is shown in Figure 8-1117 and described in Table 8-2246.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 462Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DQS_FFE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DQ_FFE_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DSLICE_PAD_RX_CTLE_SETTING_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DQS_FFE_1 | R/W | 0h | TX_FFE setting for DQS pad for slice 1. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_DQ_FFE_1 | R/W | 0h | TX_FFE setting for DQ/DM pad for slice 1. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DSLICE_PAD_RX_CTLE_SETTING_1 | R/W | 0h | Setting for RX ctle P/N of pad for slice 1. |
DDRSS_PHY_512 is shown in Figure 8-1118 and described in Table 8-2248.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4800h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_IO_PAD_DELAY_TIMING_BYPASS_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CLK_WR_BYPASS_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CLK_WR_BYPASS_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-16 | PHY_IO_PAD_DELAY_TIMING_BYPASS_2 | R/W | 0h | Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WR_BYPASS_SLAVE_DELAY_2 | R/W | 0h | Write data clock bypass mode slave delay setting for slice 2.} PADDING_BEFORE |
DDRSS_PHY_513 is shown in Figure 8-1119 and described in Table 8-2250.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4804h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRITE_PATH_LAT_ADD_BYPASS_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R/W | X | |
| 18-16 | PHY_WRITE_PATH_LAT_ADD_BYPASS_2 | R/W | 0h | Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2 | R/W | 0h | Write DQS bypass mode slave delay setting for slice 2. |
DDRSS_PHY_514 is shown in Figure 8-1120 and described in Table 8-2252.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4808h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CLK_BYPASS_OVERRIDE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_BYPASS_TWO_CYC_PREAMBLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_CLK_BYPASS_OVERRIDE_2 | R/W | 0h | Bypass mode override setting for slice 2. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_BYPASS_TWO_CYC_PREAMBLE_2 | R/W | 0h | Two_cycle_preamble for bypass mode for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2 | R/W | 0h | Read DQS bypass mode slave delay setting for slice 2. |
DDRSS_PHY_515 is shown in Figure 8-1121 and described in Table 8-2254.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 480Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WRDQ3_SHIFT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_WRDQ2_SHIFT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQ1_SHIFT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDQ0_SHIFT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_SW_WRDQ3_SHIFT_2 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 2. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_SW_WRDQ2_SHIFT_2 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 2. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_SW_WRDQ1_SHIFT_2 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 2. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDQ0_SHIFT_2 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 2. |
DDRSS_PHY_516 is shown in Figure 8-1122 and described in Table 8-2256.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4810h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WRDQ7_SHIFT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_WRDQ6_SHIFT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQ5_SHIFT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDQ4_SHIFT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_SW_WRDQ7_SHIFT_2 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 2. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_SW_WRDQ6_SHIFT_2 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 2. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_SW_WRDQ5_SHIFT_2 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 2. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDQ4_SHIFT_2 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 2. |
DDRSS_PHY_517 is shown in Figure 8-1123 and described in Table 8-2258.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4814h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PER_CS_TRAINING_MULTICAST_EN_2 | ||||||
| R/W-X | R/W-1h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PER_RANK_CS_MAP_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQS_SHIFT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDM_SHIFT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_PER_CS_TRAINING_MULTICAST_EN_2 | R/W | 1h | When set, a register write will update parameters for all ranks at the same time in slice 2. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_PER_RANK_CS_MAP_2 | R/W | 0h | Per-rank CS map for slice 2. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_SW_WRDQS_SHIFT_2 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 2. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDM_SHIFT_2 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 2. |
DDRSS_PHY_518 is shown in Figure 8-1124 and described in Table 8-2260.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4818h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_DLY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PER_CS_TRAINING_INDEX_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 2. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_LP4_BOOT_RDDATA_EN_DLY_2 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is early for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 2. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_PER_CS_TRAINING_INDEX_2 | R/W | 0h | For per-rank training, indicates which rank's paramters are read/written for slice 2. |
DDRSS_PHY_519 is shown in Figure 8-1125 and described in Table 8-2262.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 481Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LP4_BOOT_RPTR_UPDATE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 2. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2 | R/W | 0h | For LPDDR4 boot frequency, write path clock gating disable for slice 2. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 2. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_LP4_BOOT_RPTR_UPDATE_2 | R/W | 0h | For LPDDR4 boot frequency, the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 2. |
DDRSS_PHY_520 is shown in Figure 8-1126 and described in Table 8-2264.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4820h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LPBK_DFX_TIMEOUT_EN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LPBK_CONTROL_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_LPBK_CONTROL_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CTRL_LPBK_EN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_LPBK_DFX_TIMEOUT_EN_2 | R/W | 0h | Loopback read only test timeout mechanism enable for slice 2. |
| 23-17 | RESERVED | R/W | X | |
| 16-8 | PHY_LPBK_CONTROL_2 | R/W | 0h | Loopback control bits for slice 2. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_CTRL_LPBK_EN_2 | R/W | 0h | Loopback control en for slice 2. |
DDRSS_PHY_521 is shown in Figure 8-1127 and described in Table 8-2266.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4824h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_AUTO_TIMING_MARGIN_CONTROL_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_AUTO_TIMING_MARGIN_CONTROL_2 | R/W | 0h | Auto timing marging control bits for slice 2. |
DDRSS_PHY_522 is shown in Figure 8-1128 and described in Table 8-2268.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4828h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_AUTO_TIMING_MARGIN_OBS_2 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R | X | |
| 27-0 | PHY_AUTO_TIMING_MARGIN_OBS_2 | R | 0h | Observation register for the auto_timing_margin for slice 2. |
DDRSS_PHY_523 is shown in Figure 8-1129 and described in Table 8-2270.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 482Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_MULTI_PATT_ENABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PRBS_PATTERN_MASK_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PRBS_PATTERN_MASK_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PRBS_PATTERN_START_2 | ||||||
| R/W-X | R/W-1h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RDLVL_MULTI_PATT_ENABLE_2 | R/W | 0h | Read Leveling Multi-pattern enable for slice 2. |
| 23-17 | RESERVED | R/W | X | |
| 16-8 | PHY_PRBS_PATTERN_MASK_2 | R/W | 0h | PRBS7 mask signal for slice 2. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_PRBS_PATTERN_START_2 | R/W | 1h | PRBS7 start pattern for slice 2. |
DDRSS_PHY_524 is shown in Figure 8-1130 and described in Table 8-2272.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4830h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_VREF_TRAIN_OBS_2 | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_VREF_INITIAL_STEPSIZE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_MULTI_PATT_RST_DISABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-23 | RESERVED | R/W | X | |
| 22-16 | PHY_VREF_TRAIN_OBS_2 | R | 0h | Observation register for best vref value for slice 2. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_VREF_INITIAL_STEPSIZE_2 | R/W | 0h | Data slice initial VREF training step size for slice 2. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_RDLVL_MULTI_PATT_RST_DISABLE_2 | R/W | 0h | Read Leveling read level windows disable reset for slice 2. |
DDRSS_PHY_525 is shown in Figure 8-1131 and described in Table 8-2274.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4834h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_SNAP_OBS_REGS_2 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GATE_ERROR_DELAY_SELECT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | SC_PHY_SNAP_OBS_REGS_2 | W | 0h | Initiates a snapshot of the internal observation registers for slice 2. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GATE_ERROR_DELAY_SELECT_2 | R/W | 0h | Number of cycles to wait for the DQS gate to close before flagging an error for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2 | R/W | 0h | Read DQS data clock bypass mode slave delay setting for slice 2. |
DDRSS_PHY_526 is shown in Figure 8-1132 and described in Table 8-2276.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4838h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_MEM_CLASS_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LPDDR_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL1_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL1_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_MEM_CLASS_2 | R/W | 0h | Indicates the type of DRAM for slice 2. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_LPDDR_2 | R/W | 0h | Adds a cycle of delay for the slice 2 to match the address slice. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_GATE_SMPL1_SLAVE_DELAY_2 | R/W | 0h | Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 2. |
DDRSS_PHY_527 is shown in Figure 8-1133 and described in Table 8-2278.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 483Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | ON_FLY_GATE_ADJUST_EN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL2_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL2_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | ON_FLY_GATE_ADJUST_EN_2 | R/W | 0h | Control the on-the-fly gate adjustment for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_GATE_SMPL2_SLAVE_DELAY_2 | R/W | 0h | Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 2. |
DDRSS_PHY_528 is shown in Figure 8-1134 and described in Table 8-2280.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4840h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_TRACKING_OBS_2 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_GATE_TRACKING_OBS_2 | R | 0h | Report the on-the-fly gate measurement result for slice 2. |
DDRSS_PHY_529 is shown in Figure 8-1135 and described in Table 8-2282.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4844h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_PST_AMBLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DFI40_POLARITY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-8 | PHY_LP4_PST_AMBLE_2 | R/W | 0h | Controls the read postamble extension for LPDDR4 for slice 2. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DFI40_POLARITY_2 | R/W | 0h | Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 2. |
DDRSS_PHY_530 is shown in Figure 8-1136 and described in Table 8-2284.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4848h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT8_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT8_2 | R/W | 0h | Read leveling pattern 8 data for slice 2. |
DDRSS_PHY_531 is shown in Figure 8-1137 and described in Table 8-2286.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 484Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT9_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT9_2 | R/W | 0h | Read leveling pattern 9 data for slice 2. |
DDRSS_PHY_532 is shown in Figure 8-1138 and described in Table 8-2288.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4850h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT10_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT10_2 | R/W | 0h | Read leveling pattern 10 data for slice 2. |
DDRSS_PHY_533 is shown in Figure 8-1139 and described in Table 8-2290.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4854h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT11_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT11_2 | R/W | 0h | Read leveling pattern 11 data for slice 2. |
DDRSS_PHY_534 is shown in Figure 8-1140 and described in Table 8-2292.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4858h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT12_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT12_2 | R/W | 0h | Read leveling pattern 12 data for slice 2. |
DDRSS_PHY_535 is shown in Figure 8-1141 and described in Table 8-2294.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 485Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT13_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT13_2 | R/W | 0h | Read leveling pattern 13 data for slice 2. |
DDRSS_PHY_536 is shown in Figure 8-1142 and described in Table 8-2296.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4860h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT14_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT14_2 | R/W | 0h | Read leveling pattern 14 data for slice 2. |
DDRSS_PHY_537 is shown in Figure 8-1143 and described in Table 8-2298.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4864h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT15_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT15_2 | R/W | 0h | Read leveling pattern 15 data for slice 2. |
DDRSS_PHY_538 is shown in Figure 8-1144 and described in Table 8-2300.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4868h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQ_ENC_OBS_SELECT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DLY_LOCK_OBS_SELECT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_FIFO_PTR_RST_DISABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SLAVE_LOOP_CNT_UPDATE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_RDDQ_ENC_OBS_SELECT_2 | R/W | 0h | Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 2. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_MASTER_DLY_LOCK_OBS_SELECT_2 | R/W | 0h | Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_SW_FIFO_PTR_RST_DISABLE_2 | R/W | 0h | Disables automatic reset of the read entry FIFO pointers for slice 2. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_SLAVE_LOOP_CNT_UPDATE_2 | R/W | 0h | Reserved for future use for slice 2. |
DDRSS_PHY_539 is shown in Figure 8-1145 and described in Table 8-2302.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 486Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_FIFO_PTR_OBS_SELECT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WR_SHIFT_OBS_SELECT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WR_ENC_OBS_SELECT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQS_DQ_ENC_OBS_SELECT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_FIFO_PTR_OBS_SELECT_2 | R/W | 0h | Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 2. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_WR_SHIFT_OBS_SELECT_2 | R/W | 0h | Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 2. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WR_ENC_OBS_SELECT_2 | R/W | 0h | Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 2. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_RDDQS_DQ_ENC_OBS_SELECT_2 | R/W | 0h | Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 2. |
DDRSS_PHY_540 is shown in Figure 8-1146 and described in Table 8-2304.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4870h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_WRLVL_PER_START_2 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_ALGO_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_LVL_DEBUG_CONT_2 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LVL_DEBUG_MODE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_WRLVL_PER_START_2 | R/W | 0h | Observation register for write leveling status for slice 2. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_WRLVL_ALGO_2 | R/W | 0h | Write leveling algorithm selection for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8 | SC_PHY_LVL_DEBUG_CONT_2 | W | 0h | Allows the leveling state machine to advance (when in debug mode) for slice 2. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_LVL_DEBUG_MODE_2 | R/W | 0h | Enables leveling debug mode for slice 2. |
DDRSS_PHY_541 is shown in Figure 8-1147 and described in Table 8-2306.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4874h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQ_MASK_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_UPDT_WAIT_CNT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_CAPTURE_CNT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | X | |
| 23-16 | PHY_DQ_MASK_2 | R/W | 0h | For ECC slice, should set this register to do DQ bit mask for slice 2. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WRLVL_UPDT_WAIT_CNT_2 | R/W | 0h | Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 2. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_WRLVL_CAPTURE_CNT_2 | R/W | 0h | Number of samples to take at each DQS slave delay setting during write leveling for slice 2. |
DDRSS_PHY_542 is shown in Figure 8-1148 and described in Table 8-2308.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4878h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GTLVL_UPDT_WAIT_CNT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_CAPTURE_CNT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GTLVL_PER_START_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_PER_START_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_GTLVL_UPDT_WAIT_CNT_2 | R/W | 0h | Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 2. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_GTLVL_CAPTURE_CNT_2 | R/W | 0h | Number of samples to take at each DQS slave delay setting during gate training for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_PER_START_2 | R/W | 0h | Value to be added to the current gate delay position as the staring point for periodic gate training for slice 2. |
DDRSS_PHY_543 is shown in Figure 8-1149 and described in Table 8-2310.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 487Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDLVL_OP_MODE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_UPDT_WAIT_CNT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_CAPTURE_CNT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 2. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_RDLVL_OP_MODE_2 | R/W | 0h | Read leveling algorithm select for slice 2. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_RDLVL_UPDT_WAIT_CNT_2 | R/W | 0h | Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 2. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_RDLVL_CAPTURE_CNT_2 | R/W | 0h | Number of samples to take at each DQS slave delay setting during read leveling for slice 2. |
DDRSS_PHY_544 is shown in Figure 8-1150 and described in Table 8-2312.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4880h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_BURST_CNT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_WDQLVL_CLK_JITTER_TOLERANCE_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDLVL_DATA_MASK_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PERIODIC_OBS_SELECT_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_WDQLVL_BURST_CNT_2 | R/W | 0h | Defines the write/read burst length in bytes during the write data leveling sequence for slice 2. |
| 23-16 | PHY_WDQLVL_CLK_JITTER_TOLERANCE_2 | R/W | 0h | Defines the minimum gap requirment for the LE and TE window for slice 2. |
| 15-8 | PHY_RDLVL_DATA_MASK_2 | R/W | 0h | Per-bit mask for read leveling for slice 2. |
| 7-0 | PHY_RDLVL_PERIODIC_OBS_SELECT_2 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 2. |
DDRSS_PHY_545 is shown in Figure 8-1151 and described in Table 8-2314.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4884h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_UPDT_WAIT_CNT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_PATT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_WDQLVL_UPDT_WAIT_CNT_2 | R/W | 0h | Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 2. |
| 23-19 | RESERVED | R/W | X | |
| 18-8 | PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2 | R/W | 0h | Defines the write/read burst length in bytes during the write data leveling sequence for slice 2. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_WDQLVL_PATT_2 | R/W | 0h | Defines the training patterns to be used during the write data leveling sequence for slice 2. |
DDRSS_PHY_546 is shown in Figure 8-1152 and described in Table 8-2316.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4888h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_WDQLVL_CLR_PREV_RESULTS_2 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_PERIODIC_OBS_SELECT_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DQDM_OBS_SELECT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | SC_PHY_WDQLVL_CLR_PREV_RESULTS_2 | W | 0h | Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 2. |
| 15-8 | PHY_WDQLVL_PERIODIC_OBS_SELECT_2 | R/W | 0h | Select value to map specific information during or post periodic write data leveling for slice 2. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_WDQLVL_DQDM_OBS_SELECT_2 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 2. |
DDRSS_PHY_547 is shown in Figure 8-1153 and described in Table 8-2318.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 488Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DATADM_MASK_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R/W | X | |
| 8-0 | PHY_WDQLVL_DATADM_MASK_2 | R/W | 0h | Per-bit mask for write data leveling for slice 2. |
DDRSS_PHY_548 is shown in Figure 8-1154 and described in Table 8-2320.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4890h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT0_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT0_2 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 2. |
DDRSS_PHY_549 is shown in Figure 8-1155 and described in Table 8-2322.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4894h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT1_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT1_2 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 2. |
DDRSS_PHY_550 is shown in Figure 8-1156 and described in Table 8-2324.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4898h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT2_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT2_2 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 2. |
DDRSS_PHY_551 is shown in Figure 8-1157 and described in Table 8-2326.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 489Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT3_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT3_2 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 2. |
DDRSS_PHY_552 is shown in Figure 8-1158 and described in Table 8-2328.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_MULT_TRAIN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_USER_PATT4_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT4_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_NTP_MULT_TRAIN_2 | R/W | 0h | Control for single pass only No-Topology training for slice 2. |
| 15-0 | PHY_USER_PATT4_2 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 2. |
DDRSS_PHY_553 is shown in Figure 8-1159 and described in Table 8-2330.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_EARLY_THRESHOLD_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_NTP_PERIOD_THRESHOLD_2 | R/W | 0h | Threshold Criteria of period threshold after No-Topology training is completed for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_NTP_EARLY_THRESHOLD_2 | R/W | 0h | Threshold Criteria of early threshold after No-Topology training is completed for slice 2. |
DDRSS_PHY_554 is shown in Figure 8-1160 and described in Table 8-2332.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48A8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_MAX_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_MIN_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_NTP_PERIOD_THRESHOLD_MAX_2 | R/W | 0h | Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary, to set period threshold/early threshold after No-Topology training is completed for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_NTP_PERIOD_THRESHOLD_MIN_2 | R/W | 0h | Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary, to set period threshold/early threshold after No-Topology training is completed for slice 2. |
DDRSS_PHY_555 is shown in Figure 8-1161 and described in Table 8-2334.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48ACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_FIFO_PTR_OBS_2 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_MANUAL_CLEAR_2 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CALVL_VREF_DRIVING_SLICE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | X | |
| 23-16 | PHY_FIFO_PTR_OBS_2 | R | 0h | Observation register containing read entry FIFO pointers for slice 2. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | SC_PHY_MANUAL_CLEAR_2 | W | 0h | Manual reset/clear of internal logic for slice 2. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_CALVL_VREF_DRIVING_SLICE_2 | R/W | 0h | Indicates if slice 2 is used to drive the VREF value to the device during CA training. |
DDRSS_PHY_556 is shown in Figure 8-1162 and described in Table 8-2336.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48B0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LPBK_RESULT_OBS_2 | |||||||||||||||||||||||||||||||
| R-00100000h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_LPBK_RESULT_OBS_2 | R | 00100000h | Observation register containing loopback status/results for slice 2. |
DDRSS_PHY_557 is shown in Figure 8-1163 and described in Table 8-2338.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DLY_LOCK_OBS_2 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LPBK_ERROR_COUNT_OBS_2 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R | X | |
| 26-16 | PHY_MASTER_DLY_LOCK_OBS_2 | R | 0h | Observation register containing master delay results for slice 2. |
| 15-0 | PHY_LPBK_ERROR_COUNT_OBS_2 | R | 0h | Observation register containing total number of loopback error data for slice 2. |
DDRSS_PHY_558 is shown in Figure 8-1164 and described in Table 8-2340.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2 | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_MEAS_DLY_STEP_VALUE_2 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ_SLV_DLY_ENC_OBS_2 | ||||||
| R-X | R-0h | ||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2 | R | 0h | Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 2. |
| 23-16 | PHY_MEAS_DLY_STEP_VALUE_2 | R | 0h | Observation register containing fraction of the cycle in 1 delay element, numerator with demominator of 512, for slice 2. |
| 15 | RESERVED | R | X | |
| 14-8 | PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2 | R | 0h | Observation register containing read DQS base slave delay encoded value for slice 2. |
| 7 | RESERVED | R | X | |
| 6-0 | PHY_RDDQ_SLV_DLY_ENC_OBS_2 | R | 0h | Observation register containing read DQ slave delay encoded values for slice 2. |
DDRSS_PHY_559 is shown in Figure 8-1165 and described in Table 8-2342.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2 | ||||||
| R-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R | X | |
| 30-24 | PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2 | R | 0h | Observation register containing write DQS base slave delay encoded value for slice 2. |
| 23-19 | RESERVED | R | X | |
| 18-8 | PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2 | R | 0h | Observation register containing read DQS gate slave delay encoded value for slice 2. |
| 7-0 | PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2 | R | 0h | Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 2. |
DDRSS_PHY_560 is shown in Figure 8-1166 and described in Table 8-2344.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WR_SHIFT_OBS_2 | ||||||
| R-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WR_ADDER_SLV_DLY_ENC_OBS_2 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R | X | |
| 18-16 | PHY_WR_SHIFT_OBS_2 | R | 0h | Observation register containing automatic half cycle and cycle shift values for slice 2. |
| 15-8 | PHY_WR_ADDER_SLV_DLY_ENC_OBS_2 | R | 0h | Observation register containing write adder slave delay encoded value for slice 2. |
| 7-0 | PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2 | R | 0h | Observation register containing write DQ base slave delay encoded value for slice 2. |
DDRSS_PHY_561 is shown in Figure 8-1167 and described in Table 8-2346.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48C4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_HARD1_DELAY_OBS_2 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_HARD0_DELAY_OBS_2 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_WRLVL_HARD1_DELAY_OBS_2 | R | 0h | Observation register containing write leveling first hard 1 DQS slave delay for slice 2. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_WRLVL_HARD0_DELAY_OBS_2 | R | 0h | Observation register containing write leveling last hard 0 DQS slave delay for slice 2. |
DDRSS_PHY_562 is shown in Figure 8-1168 and described in Table 8-2348.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48C8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_STATUS_OBS_2 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_STATUS_OBS_2 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R | X | |
| 16-0 | PHY_WRLVL_STATUS_OBS_2 | R | 0h | Observation register containing write leveling status for slice 2. |
DDRSS_PHY_563 is shown in Figure 8-1169 and described in Table 8-2350.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2 | R | 0h | Observation register containing gate sample2 slave delay encoded values for slice 2. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2 | R | 0h | Observation register containing gate sample1 slave delay encoded values for slice 2. |
DDRSS_PHY_564 is shown in Figure 8-1170 and described in Table 8-2352.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48D0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_HARD0_DELAY_OBS_2 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_ERROR_OBS_2 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R | X | |
| 29-16 | PHY_GTLVL_HARD0_DELAY_OBS_2 | R | 0h | Observation register containing gate training first hard 0 DQS slave delay for slice 2. |
| 15-0 | PHY_WRLVL_ERROR_OBS_2 | R | 0h | Observation register containing write leveling error status for slice 2. |
DDRSS_PHY_565 is shown in Figure 8-1171 and described in Table 8-2354.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48D4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GTLVL_HARD1_DELAY_OBS_2 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-14 | RESERVED | R | X | |
| 13-0 | PHY_GTLVL_HARD1_DELAY_OBS_2 | R | 0h | Observation register containing gate training last hard 1 DQS slave delay for slice 2. |
DDRSS_PHY_566 is shown in Figure 8-1172 and described in Table 8-2356.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48D8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_STATUS_OBS_2 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_STATUS_OBS_2 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R | X | |
| 17-0 | PHY_GTLVL_STATUS_OBS_2 | R | 0h | Observation register containing gate training status for slice 2. |
DDRSS_PHY_567 is shown in Figure 8-1173 and described in Table 8-2358.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48DCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2 | R | 0h | Observation register containing read leveling data window trailing edge slave delay setting for slice 2. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2 | R | 0h | Observation register containing read leveling data window leading edge slave delay setting for slice 2. |
DDRSS_PHY_568 is shown in Figure 8-1174 and described in Table 8-2360.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2 | ||||||
| R-X | R-0h | ||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | X | |
| 1-0 | PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2 | R | 0h | Observation register containing read leveling number of windows found for slice 2. |
DDRSS_PHY_569 is shown in Figure 8-1175 and described in Table 8-2362.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_STATUS_OBS_2 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_STATUS_OBS_2 | R | 0h | Observation register containing read leveling status for slice 2. |
DDRSS_PHY_570 is shown in Figure 8-1176 and described in Table 8-2364.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48E8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PERIODIC_OBS_2 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PERIODIC_OBS_2 | R | 0h | Observation register containing periodic read leveling status for slice 2. |
DDRSS_PHY_571 is shown in Figure 8-1177 and described in Table 8-2366.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48ECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DQDM_TE_DLY_OBS_2 | ||||||||||||||
| R-X | R-7FFh | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DQDM_LE_DLY_OBS_2 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R | X | |
| 26-16 | PHY_WDQLVL_DQDM_TE_DLY_OBS_2 | R | 7FFh | Observation register containing write data leveling data window trailing edge slave delay setting for slice 2. |
| 15-11 | RESERVED | R | X | |
| 10-0 | PHY_WDQLVL_DQDM_LE_DLY_OBS_2 | R | 0h | Observation register containing write data leveling data window leading edge slave delay setting for slice 2. |
DDRSS_PHY_572 is shown in Figure 8-1178 and described in Table 8-2368.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_STATUS_OBS_2 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_WDQLVL_STATUS_OBS_2 | R | 0h | Observation register containing write data leveling status for slice 2. |
DDRSS_PHY_573 is shown in Figure 8-1179 and described in Table 8-2370.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48F4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_PERIODIC_OBS_2 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_WDQLVL_PERIODIC_OBS_2 | R | 0h | Observation register containing periodic write data leveling status for slice 2. |
DDRSS_PHY_574 is shown in Figure 8-1180 and described in Table 8-2372.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48F8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DDL_MODE_2 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-0 | PHY_DDL_MODE_2 | R/W | 0h | DDL mode for slice 2. |
DDRSS_PHY_575 is shown in Figure 8-1181 and described in Table 8-2374.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 48FCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DDL_MASK_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DDL_MASK_2 | R/W | 0h | DDL mask for slice 2. |
DDRSS_PHY_576 is shown in Figure 8-1182 and described in Table 8-2376.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4900h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TEST_OBS_2 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DDL_TEST_OBS_2 | R | 0h | DDL test observation for slice 2. |
DDRSS_PHY_577 is shown in Figure 8-1183 and described in Table 8-2378.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4904h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TEST_MSTR_DLY_OBS_2 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DDL_TEST_MSTR_DLY_OBS_2 | R | 0h | DDL test observation delays for slice 2 master DDL. |
DDRSS_PHY_578 is shown in Figure 8-1184 and described in Table 8-2380.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4908h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_OVERRIDE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_RX_CAL_START_2 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_WDQS_OE_EXTEND_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TRACK_UPD_THRESHOLD_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RX_CAL_OVERRIDE_2 | R/W | 0h | Manual setting of RX Calibration enable for slice 2. |
| 23-17 | RESERVED | R/W | X | |
| 16 | SC_PHY_RX_CAL_START_2 | W | 0h | Manual RX Calibration start for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_LP4_WDQS_OE_EXTEND_2 | R/W | 0h | LPDDR4 write preamble extension enable for slice 2. |
| 7-0 | PHY_DDL_TRACK_UPD_THRESHOLD_2 | R/W | 0h | Specify threshold value for PHY init update tracking for slice 2. |
DDRSS_PHY_579 is shown in Figure 8-1185 and described in Table 8-2382.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 490Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_DQ0_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RX_CAL_DQ0_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RX_CAL_SAMPLE_WAIT_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ0_2 | R/W | 0h | RX Calibration codes for DQ0 for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2 | R/W | 0h | Data slice power reduction disable for slice 2. |
| 7-0 | PHY_RX_CAL_SAMPLE_WAIT_2 | R/W | 0h | RX Calibration state machine wait count for slice 2. |
DDRSS_PHY_580 is shown in Figure 8-1186 and described in Table 8-2384.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4910h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ2_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ1_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ2_2 | R/W | 0h | RX Calibration codes for DQ2 for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ1_2 | R/W | 0h | RX Calibration codes for DQ1 for slice 2. |
DDRSS_PHY_581 is shown in Figure 8-1187 and described in Table 8-2386.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4914h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ4_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ3_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ4_2 | R/W | 0h | RX Calibration codes for DQ4 for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ3_2 | R/W | 0h | RX Calibration codes for DQ3 for slice 2. |
DDRSS_PHY_582 is shown in Figure 8-1188 and described in Table 8-2388.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4918h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ6_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ5_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ6_2 | R/W | 0h | RX Calibration codes for DQ6 for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ5_2 | R/W | 0h | RX Calibration codes for DQ5 for slice 2. |
DDRSS_PHY_583 is shown in Figure 8-1189 and described in Table 8-2390.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 491Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ7_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ7_2 | R/W | 0h | RX Calibration codes for DQ7 for slice 2. |
DDRSS_PHY_584 is shown in Figure 8-1190 and described in Table 8-2392.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4920h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DM_2 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_RX_CAL_DM_2 | R/W | 0h | RX Calibration codes for DM for slice 2. |
DDRSS_PHY_585 is shown in Figure 8-1191 and described in Table 8-2394.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4924h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_FDBK_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQS_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_FDBK_2 | R/W | 0h | RX Calibration codes for FDBK for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQS_2 | R/W | 0h | RX Calibration codes for DQS for slice 2. |
DDRSS_PHY_586 is shown in Figure 8-1192 and described in Table 8-2396.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4928h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_LOCK_OBS_2 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_OBS_2 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R | X | |
| 24-16 | PHY_RX_CAL_LOCK_OBS_2 | R | 0h | RX Calibration lock results for slice 2. |
| 15-11 | RESERVED | R | X | |
| 10-0 | PHY_RX_CAL_OBS_2 | R | 0h | RX Calibration results for slice 2. |
DDRSS_PHY_587 is shown in Figure 8-1193 and described in Table 8-2398.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 492Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_COMP_VAL_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DIFF_ADJUST_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RX_CAL_SE_ADJUST_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DISABLE_2 | ||||||
| R/W-X | R/W-1h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RX_CAL_COMP_VAL_2 | R/W | 0h | Expected C value from RX pad for slice 2. |
| 23 | RESERVED | R/W | X | |
| 22-16 | PHY_RX_CAL_DIFF_ADJUST_2 | R/W | 0h | Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 2. |
| 15 | RESERVED | R/W | X | |
| 14-8 | PHY_RX_CAL_SE_ADJUST_2 | R/W | 0h | Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 2. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_RX_CAL_DISABLE_2 | R/W | 1h | RX CAL disable signal for slice 2, set 1 to bypass the rx calibration |
DDRSS_PHY_588 is shown in Figure 8-1194 and described in Table 8-2400.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4930h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_BIAS_EN_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_INDEX_MASK_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_PAD_RX_BIAS_EN_2 | R/W | 0h | Controls RX_BIAS_EN pin for each pad for slice 2. |
| 15-12 | RESERVED | R/W | X | |
| 11-0 | PHY_RX_CAL_INDEX_MASK_2 | R/W | 0h | RX offset calibration mask of all RX pad for slice 2. |
DDRSS_PHY_589 is shown in Figure 8-1195 and described in Table 8-2402.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4934h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_WEIGHT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_CAL_TIMEOUT_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_CAL_SAMPLE_WAIT_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_STATIC_TOG_DISABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_DATA_DC_WEIGHT_2 | R/W | 0h | Determines weight of average calculating for slice 2. |
| 23-16 | PHY_DATA_DC_CAL_TIMEOUT_2 | R/W | 0h | Determines timeout number of iteration for slice 2. |
| 15-8 | PHY_DATA_DC_CAL_SAMPLE_WAIT_2 | R/W | 0h | Determines number of cycles to wait for each sample for slice 2. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_STATIC_TOG_DISABLE_2 | R/W | 0h | Control to disable toggle during static activity for slice 2. |
DDRSS_PHY_590 is shown in Figure 8-1196 and described in Table 8-2404.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4938h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_ADJUST_DIRECT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_ADJUST_THRSHLD_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_ADJUST_SAMPLE_CNT_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_ADJUST_START_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_DATA_DC_ADJUST_DIRECT_2 | R/W | 0h | Adjust direction for slice 2. |
| 23-16 | PHY_DATA_DC_ADJUST_THRSHLD_2 | R/W | 0h | Duty cycle adjust threshold around the mid-point for slice 2. |
| 15-8 | PHY_DATA_DC_ADJUST_SAMPLE_CNT_2 | R/W | 0h | Duty cycle adjust sample count for slice 2. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DATA_DC_ADJUST_START_2 | R/W | 0h | Duty cycle adjust starting value for slice 2. |
DDRSS_PHY_591 is shown in Figure 8-1197 and described in Table 8-2406.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 493Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_FDBK_PWR_CTRL_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_SW_RANK_2 | ||||||
| R/W-X | R/W-1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_CAL_START_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_CAL_POLARITY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_FDBK_PWR_CTRL_2 | R/W | 0h | Shutoff gate feedback IO to reduce power for slice 2. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DATA_DC_SW_RANK_2 | R/W | 1h | Rank selection for software based duty cycle correction for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DATA_DC_CAL_START_2 | R/W | 0h | Manual trigger for DCC for slice 2. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DATA_DC_CAL_POLARITY_2 | R/W | 0h | Calibration polarity for slice 2. |
DDRSS_PHY_592 is shown in Figure 8-1198 and described in Table 8-2408.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4940h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SLICE_PWR_RDC_DISABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDPATH_GATE_DISABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SLV_DLY_CTRL_GATE_DISABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_SLICE_PWR_RDC_DISABLE_2 | R/W | 0h | Data slice power reduction disable for slice 2. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2 | R/W | 0h | Data slice DCC and RX_CAL block power reduction disable for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_RDPATH_GATE_DISABLE_2 | R/W | 0h | Data slice read path power reduction disable for slice 2. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_SLV_DLY_CTRL_GATE_DISABLE_2 | R/W | 0h | Data slice slv_dly_control block power reduction disable for slice 2. |
DDRSS_PHY_593 is shown in Figure 8-1199 and described in Table 8-2410.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4944h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DS_FSM_ERROR_INFO_2 | ||||||||||||||
| R/W-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PARITY_ERROR_REGIF_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | PHY_DS_FSM_ERROR_INFO_2 | R | 0h | Data slice level FSM Error Info for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_PARITY_ERROR_REGIF_2 | R/W | 0h | Inject parity error to register interface signals for slice 2. |
DDRSS_PHY_594 is shown in Figure 8-1200 and described in Table 8-2412.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4948h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2 | |||||||
| W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DS_FSM_ERROR_INFO_MASK_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DS_FSM_ERROR_INFO_MASK_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2 | W | 0h | Data slice level FSM Error Info for slice 2. |
| 15-14 | RESERVED | R/W | X | |
| 13-0 | PHY_DS_FSM_ERROR_INFO_MASK_2 | R/W | 0h | Data slice level FSM Error Info Mask for slice 2. |
DDRSS_PHY_595 is shown in Figure 8-1201 and described in Table 8-2414.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 494Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DS_TRAIN_CALIB_ERROR_INFO_2 | ||||||
| R/W-X | R-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2 | W | 0h | Data slice level training/calibration Error Info for slice 2. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_2 | R/W | 0h | Data slice level training/calibration Error Info Mask for slice 2. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_DS_TRAIN_CALIB_ERROR_INFO_2 | R | 0h | Data slice level training/calibration Error Info for slice 2. |
DDRSS_PHY_596 is shown in Figure 8-1202 and described in Table 8-2416.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4950h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DQS_TSEL_ENABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQ_TSEL_SELECT_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_TSEL_SELECT_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DQ_TSEL_ENABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_DQS_TSEL_ENABLE_2 | R/W | 0h | Operation type tsel enables for DQS signals for slice 2. |
| 23-8 | PHY_DQ_TSEL_SELECT_2 | R/W | 0h | Operation type tsel select values for DQ/DM signals for slice 2. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_DQ_TSEL_ENABLE_2 | R/W | 0h | Operation type tsel enables for DQ/DM signals for slice 2. |
DDRSS_PHY_597 is shown in Figure 8-1203 and described in Table 8-2418.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4954h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_VREF_INITIAL_START_POINT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TWO_CYC_PREAMBLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQS_TSEL_SELECT_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQS_TSEL_SELECT_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-24 | PHY_VREF_INITIAL_START_POINT_2 | R/W | 0h | Data slice initial VREF training start value for slice 2. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_TWO_CYC_PREAMBLE_2 | R/W | 0h | 2 cycle preamble support for slice 2. |
| 15-0 | PHY_DQS_TSEL_SELECT_2 | R/W | 0h | Operation type tsel select values for DQS signals for slice 2. |
DDRSS_PHY_598 is shown in Figure 8-1204 and described in Table 8-2420.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4958h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_NTP_WDQ_STEP_SIZE_2 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_TRAIN_EN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_VREF_TRAINING_CTRL_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_VREF_INITIAL_STOP_POINT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_NTP_WDQ_STEP_SIZE_2 | R/W | 0h | Step size of WR DQ slave delay during No-Topology training for slice 2. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_NTP_TRAIN_EN_2 | R/W | 0h | Enable for No-Topology training for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_VREF_TRAINING_CTRL_2 | R/W | 0h | Data slice vref training enable control for slice 2. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_VREF_INITIAL_STOP_POINT_2 | R/W | 0h | Data slice initial VREF training stop value for slice 2. |
DDRSS_PHY_599 is shown in Figure 8-1205 and described in Table 8-2422.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 495Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_WDQ_STOP_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_WDQ_START_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_NTP_WDQ_STOP_2 | R/W | 0h | End of WR DQ slave delay in No-Topology training for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_NTP_WDQ_START_2 | R/W | 0h | Starting WR DQ slave delay in No-Topology training for slice 2. |
DDRSS_PHY_600 is shown in Figure 8-1206 and described in Table 8-2424.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4960h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WDQLVL_DVW_MIN_EN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DVW_MIN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_DVW_MIN_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_NTP_WDQ_BIT_EN_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_SW_WDQLVL_DVW_MIN_EN_2 | R/W | 0h | SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 2. |
| 23-18 | RESERVED | R/W | X | |
| 17-8 | PHY_WDQLVL_DVW_MIN_2 | R/W | 0h | Minimum data valid window across DQs and ranks for slice 2. |
| 7-0 | PHY_NTP_WDQ_BIT_EN_2 | R/W | 0h | Enable Bit for WR DQ during No-Topology training for slice 2. |
DDRSS_PHY_601 is shown in Figure 8-1207 and described in Table 8-2426.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4964h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_RX_DCD_0_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_TX_DCD_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_FAST_LVL_EN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_PER_START_OFFSET_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_RX_DCD_0_2 | R/W | 0h | Controls RX_DCD pin for each pad for slice 2. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_TX_DCD_2 | R/W | 0h | Controls TX_DCD pin for each pad for slice 2. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_FAST_LVL_EN_2 | R/W | 0h | Enable for fast multi-pattern window search for slice 2. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_WDQLVL_PER_START_OFFSET_2 | R/W | 0h | Peridic training start point offset for slice 2. |
DDRSS_PHY_602 is shown in Figure 8-1208 and described in Table 8-2428.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4968h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_RX_DCD_4_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_DCD_3_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_RX_DCD_2_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RX_DCD_1_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_RX_DCD_4_2 | R/W | 0h | Controls RX_DCD pin for each pad for slice 2. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_RX_DCD_3_2 | R/W | 0h | Controls RX_DCD pin for each pad for slice 2. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_RX_DCD_2_2 | R/W | 0h | Controls RX_DCD pin for each pad for slice 2. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_RX_DCD_1_2 | R/W | 0h | Controls RX_DCD pin for each pad for slice 2. |
DDRSS_PHY_603 is shown in Figure 8-1209 and described in Table 8-2430.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 496Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_DM_RX_DCD_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_DCD_7_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_RX_DCD_6_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RX_DCD_5_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_DM_RX_DCD_2 | R/W | 0h | Controls RX_DCD pin for dm pad for slice 2. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_RX_DCD_7_2 | R/W | 0h | Controls RX_DCD pin for each pad for slice 2. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_RX_DCD_6_2 | R/W | 0h | Controls RX_DCD pin for each pad for slice 2. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_RX_DCD_5_2 | R/W | 0h | Controls RX_DCD pin for each pad for slice 2. |
DDRSS_PHY_604 is shown in Figure 8-1210 and described in Table 8-2432.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4970h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_DSLICE_IO_CFG_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_FDBK_RX_DCD_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_DQS_RX_DCD_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-22 | RESERVED | R/W | X | |
| 21-16 | PHY_PAD_DSLICE_IO_CFG_2 | R/W | 0h | Controls PCLK/PARK pin for pad for slice 2. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_FDBK_RX_DCD_2 | R/W | 0h | Controls RX_DCD pin for fdbk pad for slice 2. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_DQS_RX_DCD_2 | R/W | 0h | Controls RX_DCD pin for dqs pad for slice 2. |
DDRSS_PHY_605 is shown in Figure 8-1211 and described in Table 8-2434.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4974h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ1_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ0_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ1_SLAVE_DELAY_2 | R/W | 0h | Read DQ1 slave delay setting for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ0_SLAVE_DELAY_2 | R/W | 0h | Read DQ0 slave delay setting for slice 2. |
DDRSS_PHY_606 is shown in Figure 8-1212 and described in Table 8-2436.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4978h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ3_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ2_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ3_SLAVE_DELAY_2 | R/W | 0h | Read DQ3 slave delay setting for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ2_SLAVE_DELAY_2 | R/W | 0h | Read DQ2 slave delay setting for slice 2. |
DDRSS_PHY_607 is shown in Figure 8-1213 and described in Table 8-2438.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 497Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ5_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ4_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ5_SLAVE_DELAY_2 | R/W | 0h | Read DQ5 slave delay setting for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ4_SLAVE_DELAY_2 | R/W | 0h | Read DQ4 slave delay setting for slice 2. |
DDRSS_PHY_608 is shown in Figure 8-1214 and described in Table 8-2440.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4980h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ7_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ6_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ7_SLAVE_DELAY_2 | R/W | 0h | Read DQ7 slave delay setting for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ6_SLAVE_DELAY_2 | R/W | 0h | Read DQ6 slave delay setting for slice 2. |
DDRSS_PHY_609 is shown in Figure 8-1215 and described in Table 8-2442.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4984h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_CAL_CLK_SEL_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDM_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDM_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R/W | X | |
| 18-16 | PHY_DATA_DC_CAL_CLK_SEL_2 | R/W | 0h | Determines DCC CAL clock for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDM_SLAVE_DELAY_2 | R/W | 0h | Read DM/DBI slave delay setting for slice 2. |
DDRSS_PHY_610 is shown in Figure 8-1216 and described in Table 8-2444.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4988h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_OE_TIMING_2 | PHY_DQ_TSEL_WR_TIMING_2 | ||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQ_TSEL_RD_TIMING_2 | PHY_DQ_OE_TIMING_2 | ||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DQS_OE_TIMING_2 | R/W | 0h | Start/end timing values for DQS output enable signals for slice 2. |
| 23-16 | PHY_DQ_TSEL_WR_TIMING_2 | R/W | 0h | Start/end timing values for DQ/DM write based termination enable and select signals for slice 2. |
| 15-8 | PHY_DQ_TSEL_RD_TIMING_2 | R/W | 0h | Start/end timing values for DQ/DM read based termination enable and select signals for slice 2. |
| 7-0 | PHY_DQ_OE_TIMING_2 | R/W | 0h | Start/end timing values for DQ/DM output enable signals for slice 2. |
DDRSS_PHY_611 is shown in Figure 8-1217 and described in Table 8-2446.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 498Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DQS_TSEL_WR_TIMING_2 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_OE_RD_TIMING_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQS_TSEL_RD_TIMING_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_IO_PAD_DELAY_TIMING_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DQS_TSEL_WR_TIMING_2 | R/W | 0h | Start/end timing values for DQS write based termination enable and select signals for slice 2. |
| 23-16 | PHY_DQS_OE_RD_TIMING_2 | R/W | 0h | Start/end timing values for DQS read based OE extension for slice 2. |
| 15-8 | PHY_DQS_TSEL_RD_TIMING_2 | R/W | 0h | Start/end timing values for DQS read based termination enable and select signals for slice 2. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_IO_PAD_DELAY_TIMING_2 | R/W | 0h | Feedback pad's OPAD and IPAD delay timing for slice 2. |
DDRSS_PHY_612 is shown in Figure 8-1218 and described in Table 8-2448.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4990h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_VREF_CTRL_DQ_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_VREF_SETTING_TIME_2 | |||||||||||||||
| R/W-0h | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-16 | PHY_PAD_VREF_CTRL_DQ_2 | R/W | 0h | Pad VREF control settings for DQ slice 2.
|
| 15-0 | PHY_VREF_SETTING_TIME_2 | R/W | 0h | Number of cycles for vref settle after setting is changed for slice 2. |
DDRSS_PHY_613 is shown in Figure 8-1219 and described in Table 8-2450.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4994h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDATA_EN_IE_DLY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_IE_TIMING_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_IE_TIMING_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PER_CS_TRAINING_EN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_RDDATA_EN_IE_DLY_2 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 2. |
| 23-16 | PHY_DQS_IE_TIMING_2 | R/W | 0h | Start/end timing values for DQS input enable signals for slice 2. |
| 15-8 | PHY_DQ_IE_TIMING_2 | R/W | 0h | Start/end timing values for DQ/DM input enable signals for slice 2. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_PER_CS_TRAINING_EN_2 | R/W | 0h | Enables the per-rank training and read/write timing capabilities for slice 2. |
DDRSS_PHY_614 is shown in Figure 8-1220 and described in Table 8-2452.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4998h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDATA_EN_OE_DLY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDATA_EN_TSEL_DLY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DBI_MODE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_IE_MODE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_RDDATA_EN_OE_DLY_2 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 2. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_RDDATA_EN_TSEL_DLY_2 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DBI_MODE_2 | R/W | 0h | DBI mode for slice 2. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_IE_MODE_2 | R/W | 0h | Input enable mode bits for slice 2. |
DDRSS_PHY_615 is shown in Figure 8-1221 and described in Table 8-2454.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 499Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_MASTER_DELAY_STEP_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DELAY_START_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_MASTER_DELAY_START_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_MASTER_MODE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_MASTER_DELAY_STEP_2 | R/W | 0h | Incremental step size for master delay line locking algorithm for slice 2. |
| 23-19 | RESERVED | R/W | X | |
| 18-8 | PHY_MASTER_DELAY_START_2 | R/W | 0h | Start value for master delay line locking algorithm for slice 2. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_SW_MASTER_MODE_2 | R/W | 0h | Master delay line override settings for slice 2. |
DDRSS_PHY_616 is shown in Figure 8-1222 and described in Table 8-2456.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_WRLVL_DLY_STEP_2 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RPTR_UPDATE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_MASTER_DELAY_HALF_MEASURE_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_MASTER_DELAY_WAIT_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_WRLVL_DLY_STEP_2 | R/W | 0h | DQS slave delay step size during write leveling for slice 2. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_RPTR_UPDATE_2 | R/W | 0h | Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 2. |
| 15-8 | PHY_MASTER_DELAY_HALF_MEASURE_2 | R/W | 0h | Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 2. |
| 7-0 | PHY_MASTER_DELAY_WAIT_2 | R/W | 0h | Wait cycles for master delay line locking algorithm for slice 2. |
DDRSS_PHY_617 is shown in Figure 8-1223 and described in Table 8-2458.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GTLVL_RESP_WAIT_CNT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_DLY_STEP_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_RESP_WAIT_CNT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_DLY_FINE_STEP_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_GTLVL_RESP_WAIT_CNT_2 | R/W | 0h | Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 2. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GTLVL_DLY_STEP_2 | R/W | 0h | DQS slave delay step size during gate training for slice 2. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_WRLVL_RESP_WAIT_CNT_2 | R/W | 0h | Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 2. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_WRLVL_DLY_FINE_STEP_2 | R/W | 0h | DQS slave delay fine step size during write leveling for slice 2. |
DDRSS_PHY_618 is shown in Figure 8-1224 and described in Table 8-2460.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49A8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_FINAL_STEP_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GTLVL_BACK_STEP_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_GTLVL_FINAL_STEP_2 | R/W | 0h | Final backup step delay used in gate training algorithm for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_BACK_STEP_2 | R/W | 0h | Interim backup step delay used in gate training algorithm for slice 2. |
DDRSS_PHY_619 is shown in Figure 8-1225 and described in Table 8-2462.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49ACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_DLY_STEP_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TOGGLE_PRE_SUPPORT_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_QTR_DLY_STEP_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_DLY_STEP_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_RDLVL_DLY_STEP_2 | R/W | 0h | DQS slave delay step size during read leveling for slice 2. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_TOGGLE_PRE_SUPPORT_2 | R/W | 0h | Support the toggle read preamble for LPDDR4 for slice 2. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WDQLVL_QTR_DLY_STEP_2 | R/W | 0h | Defines the step granularity for the logic to use once an edge is found for slice 2. |
| 7-0 | PHY_WDQLVL_DLY_STEP_2 | R/W | 0h | DQ slave delay step size during write data leveling for slice 2. |
DDRSS_PHY_620 is shown in Figure 8-1226 and described in Table 8-2464.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49B0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_MAX_EDGE_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_MAX_EDGE_2 | R/W | 0h | The maximun rdlvl slave delay search window for read eye training for slice 2. |
DDRSS_PHY_621 is shown in Figure 8-1227 and described in Table 8-2466.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_PER_START_OFFSET_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_RDLVL_DVW_MIN_EN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_DVW_MIN_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_DVW_MIN_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_RDLVL_PER_START_OFFSET_2 | R/W | 0h | Peridic training start point offset for slice 2. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_SW_RDLVL_DVW_MIN_EN_2 | R/W | 0h | SW override to enable use of PHY_RDLVL_DVW_MIN for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_DVW_MIN_2 | R/W | 0h | Minimum data valid window across DQs and ranks for slice 2. |
DDRSS_PHY_622 is shown in Figure 8-1228 and described in Table 8-2468.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_INIT_DISABLE_2 | ||||||
| R/W-X | R/W-3h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRPATH_GATE_TIMING_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRPATH_GATE_DISABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DATA_DC_INIT_DISABLE_2 | R/W | 3h | Disable duty cycle adjust at initialization for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_WRPATH_GATE_TIMING_2 | R/W | 0h | Write path clock gating timing for slice 2. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_WRPATH_GATE_DISABLE_2 | R/W | 0h | Write path clock gating disable for slice 2. |
DDRSS_PHY_623 is shown in Figure 8-1229 and described in Table 8-2470.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_DQ_INIT_SLV_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ_INIT_SLV_DELAY_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_DQS_INIT_SLV_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQS_INIT_SLV_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_DATA_DC_DQ_INIT_SLV_DELAY_2 | R/W | 0h | Initial value of write DQ slave delay for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_DATA_DC_DQS_INIT_SLV_DELAY_2 | R/W | 0h | Initial value of write DQS slave delay for slice 2. |
DDRSS_PHY_624 is shown in Figure 8-1230 and described in Table 8-2472.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DM_CLK_SE_THRSHLD_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_WDQLVL_ENABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_WRLVL_ENABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2 | R/W | 0h | Clock measurement cell threshold offset for differential signals for slice 2. |
| 23-16 | PHY_DATA_DC_DM_CLK_SE_THRSHLD_2 | R/W | 0h | Clock measurement cell threshold offset for single ended signals for slice 2. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DATA_DC_WDQLVL_ENABLE_2 | R/W | 0h | Enable duty cycle adjust during write DQ training for slice 2. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DATA_DC_WRLVL_ENABLE_2 | R/W | 0h | Enable duty cycle adjust during write leveling for slice 2. |
DDRSS_PHY_625 is shown in Figure 8-1231 and described in Table 8-2474.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49C4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDATA_EN_DLY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_MEAS_DLY_STEP_ENABLE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQ_OSC_DELTA_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | PHY_RDDATA_EN_DLY_2 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is early for slice 2. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_MEAS_DLY_STEP_ENABLE_2 | R/W | 0h | Data slice training step definition using phy_meas_dly_step_value for slice 2. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_WDQ_OSC_DELTA_2 | R/W | 0h | Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 2. |
DDRSS_PHY_626 is shown in Figure 8-1232 and described in Table 8-2476.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49C8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQ_DM_SWIZZLE0_2 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DQ_DM_SWIZZLE0_2 | R/W | 0h | DQ/DM bit swizzling 0 for slice 2. |
DDRSS_PHY_627 is shown in Figure 8-1233 and described in Table 8-2478.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DQ_DM_SWIZZLE1_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R/W | X | |
| 3-0 | PHY_DQ_DM_SWIZZLE1_2 | R/W | 0h | DQ/DM bit swizzling 1 for slice 2. |
DDRSS_PHY_628 is shown in Figure 8-1234 and described in Table 8-2480.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49D0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ1_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ0_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ1_SLAVE_DELAY_2 | R/W | 0h | Write clock slave delay setting for DQ1 for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ0_SLAVE_DELAY_2 | R/W | 0h | Write clock slave delay setting for DQ0 for slice 2. |
DDRSS_PHY_629 is shown in Figure 8-1235 and described in Table 8-2482.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49D4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ3_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ2_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ3_SLAVE_DELAY_2 | R/W | 0h | Write clock slave delay setting for DQ3 for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ2_SLAVE_DELAY_2 | R/W | 0h | Write clock slave delay setting for DQ2 for slice 2. |
DDRSS_PHY_630 is shown in Figure 8-1236 and described in Table 8-2484.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49D8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ5_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ4_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ5_SLAVE_DELAY_2 | R/W | 0h | Write clock slave delay setting for DQ5 for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ4_SLAVE_DELAY_2 | R/W | 0h | Write clock slave delay setting for DQ4 for slice 2. |
DDRSS_PHY_631 is shown in Figure 8-1237 and described in Table 8-2486.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49DCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ7_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ6_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ7_SLAVE_DELAY_2 | R/W | 0h | Write clock slave delay setting for DQ7 for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ6_SLAVE_DELAY_2 | R/W | 0h | Write clock slave delay setting for DQ6 for slice 2. |
DDRSS_PHY_632 is shown in Figure 8-1238 and described in Table 8-2488.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQS_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDM_SLAVE_DELAY_2 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_CLK_WRDQS_SLAVE_DELAY_2 | R/W | 0h | Write clock slave delay setting for DQS for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDM_SLAVE_DELAY_2 | R/W | 0h | Write clock slave delay setting for DM for slice 2. |
DDRSS_PHY_633 is shown in Figure 8-1239 and described in Table 8-2490.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_THRESHOLD_ADJUST_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-8 | PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2 | R/W | 0h | Rising edge read DQS slave delay setting for DQ0 for slice 2. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_WRLVL_THRESHOLD_ADJUST_2 | R/W | 0h | Write level threshold adjust value based on those thresholds for DQS for slice 2. |
DDRSS_PHY_634 is shown in Figure 8-1240 and described in Table 8-2492.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49E8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2 | R/W | 0h | Rising edge read DQS slave delay setting for DQ1 for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2 | R/W | 0h | Falling edge read DQS slave delay setting for DQ0 for slice 2. |
DDRSS_PHY_635 is shown in Figure 8-1241 and described in Table 8-2494.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49ECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2 | R/W | 0h | Rising edge read DQS slave delay setting for DQ2 for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2 | R/W | 0h | Falling edge read DQS slave delay setting for DQ1 for slice 2. |
DDRSS_PHY_636 is shown in Figure 8-1242 and described in Table 8-2496.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2 | R/W | 0h | Rising edge read DQS slave delay setting for DQ3 for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2 | R/W | 0h | Falling edge read DQS slave delay setting for DQ2 for slice 2. |
DDRSS_PHY_637 is shown in Figure 8-1243 and described in Table 8-2498.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49F4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2 | R/W | 0h | Rising edge read DQS slave delay setting for DQ4 for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2 | R/W | 0h | Falling edge read DQS slave delay setting for DQ3 for slice 2. |
DDRSS_PHY_638 is shown in Figure 8-1244 and described in Table 8-2500.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49F8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2 | R/W | 0h | Rising edge read DQS slave delay setting for DQ5 for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2 | R/W | 0h | Falling edge read DQS slave delay setting for DQ4 for slice 2. |
DDRSS_PHY_639 is shown in Figure 8-1245 and described in Table 8-2502.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 49FCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2 | R/W | 0h | Rising edge read DQS slave delay setting for DQ6 for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2 | R/W | 0h | Falling edge read DQS slave delay setting for DQ5 for slice 2. |
DDRSS_PHY_640 is shown in Figure 8-1246 and described in Table 8-2504.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A00h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2 | R/W | 0h | Rising edge read DQS slave delay setting for DQ7 for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2 | R/W | 0h | Falling edge read DQS slave delay setting for DQ6 for slice 2. |
DDRSS_PHY_641 is shown in Figure 8-1247 and described in Table 8-2506.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A04h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DM_RISE_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DM_RISE_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DM_RISE_SLAVE_DELAY_2 | R/W | 0h | Rising edge read DQS slave delay setting for DM for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2 | R/W | 0h | Falling edge read DQS slave delay setting for DQ7 for slice 2. |
DDRSS_PHY_642 is shown in Figure 8-1248 and described in Table 8-2508.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A08h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_GATE_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_GATE_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DM_FALL_SLAVE_DELAY_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DM_FALL_SLAVE_DELAY_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_GATE_SLAVE_DELAY_2 | R/W | 0h | Read DQS slave delay setting for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DM_FALL_SLAVE_DELAY_2 | R/W | 0h | Falling edge read DQS slave delay setting for DM for slice 2. |
DDRSS_PHY_643 is shown in Figure 8-1249 and described in Table 8-2510.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A0Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WRLVL_DELAY_EARLY_THRESHOLD_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_WRLVL_DELAY_EARLY_THRESHOLD_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRITE_PATH_LAT_ADD_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQS_LATENCY_ADJUST_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_WRLVL_DELAY_EARLY_THRESHOLD_2 | R/W | 0h | Write level delay threshold above which will be considered in previous cycle for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_WRITE_PATH_LAT_ADD_2 | R/W | 0h | Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 2. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_RDDQS_LATENCY_ADJUST_2 | R/W | 0h | Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 2. |
DDRSS_PHY_644 is shown in Figure 8-1250 and described in Table 8-2512.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A10h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_EARLY_FORCE_ZERO_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_WRLVL_EARLY_FORCE_ZERO_2 | R/W | 0h | Force the final write level delay value (that meets the early threshold) to 0 for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2 | R/W | 0h | Write level delay threshold below which will add a cycle of write path latency for slice 2. |
DDRSS_PHY_645 is shown in Figure 8-1251 and described in Table 8-2514.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A14h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_LAT_ADJ_START_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GTLVL_RDDQS_SLV_DLY_START_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_RDDQS_SLV_DLY_START_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GTLVL_LAT_ADJ_START_2 | R/W | 0h | Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_RDDQS_SLV_DLY_START_2 | R/W | 0h | Initial read DQS gate slave delay setting during gate training for slice 2. |
DDRSS_PHY_646 is shown in Figure 8-1252 and described in Table 8-2516.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A18h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_NTP_PASS_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_WRLAT_START_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_DQDM_SLV_DLY_START_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_DQDM_SLV_DLY_START_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_NTP_PASS_2 | R/W | 0h | Indicates if No-topology training found a passing result for slice 2. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_NTP_WRLAT_START_2 | R/W | 0h | Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 2. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_WDQLVL_DQDM_SLV_DLY_START_2 | R/W | 0h | Initial DQ/DM slave delay setting during write data leveling for slice 2. |
DDRSS_PHY_647 is shown in Figure 8-1253 and described in Table 8-2518.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A1Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2 | R/W | 0h | Read leveling starting value for the DQS/DQ slave delay settings for slice 2. |
DDRSS_PHY_648 is shown in Figure 8-1254 and described in Table 8-2520.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A20h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DQ2_CLK_ADJUST_2 | |||||||
| R/W-20h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ1_CLK_ADJUST_2 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DQ0_CLK_ADJUST_2 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQS_CLK_ADJUST_2 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DQ2_CLK_ADJUST_2 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 2. |
| 23-16 | PHY_DATA_DC_DQ1_CLK_ADJUST_2 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 2. |
| 15-8 | PHY_DATA_DC_DQ0_CLK_ADJUST_2 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 2. |
| 7-0 | PHY_DATA_DC_DQS_CLK_ADJUST_2 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 2. |
DDRSS_PHY_649 is shown in Figure 8-1255 and described in Table 8-2522.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A24h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DQ6_CLK_ADJUST_2 | |||||||
| R/W-20h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ5_CLK_ADJUST_2 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DQ4_CLK_ADJUST_2 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQ3_CLK_ADJUST_2 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DQ6_CLK_ADJUST_2 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 2. |
| 23-16 | PHY_DATA_DC_DQ5_CLK_ADJUST_2 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 2. |
| 15-8 | PHY_DATA_DC_DQ4_CLK_ADJUST_2 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 2. |
| 7-0 | PHY_DATA_DC_DQ3_CLK_ADJUST_2 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 2. |
DDRSS_PHY_650 is shown in Figure 8-1256 and described in Table 8-2524.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A28h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DSLICE_PAD_BOOSTPN_SETTING_2 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DSLICE_PAD_BOOSTPN_SETTING_2 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DM_CLK_ADJUST_2 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQ7_CLK_ADJUST_2 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | PHY_DSLICE_PAD_BOOSTPN_SETTING_2 | R/W | 0h | Setting for boost P/N of pad for slice 2. |
| 15-8 | PHY_DATA_DC_DM_CLK_ADJUST_2 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 2. |
| 7-0 | PHY_DATA_DC_DQ7_CLK_ADJUST_2 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 2. |
DDRSS_PHY_651 is shown in Figure 8-1257 and described in Table 8-2526.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4A2Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DQS_FFE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DQ_FFE_2 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DSLICE_PAD_RX_CTLE_SETTING_2 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DQS_FFE_2 | R/W | 0h | TX_FFE setting for DQS pad for slice 2. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_DQ_FFE_2 | R/W | 0h | TX_FFE setting for DQ/DM pad for slice 2. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DSLICE_PAD_RX_CTLE_SETTING_2 | R/W | 0h | Setting for RX ctle P/N of pad for slice 2. |
DDRSS_PHY_768 is shown in Figure 8-1258 and described in Table 8-2528.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C00h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_IO_PAD_DELAY_TIMING_BYPASS_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CLK_WR_BYPASS_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CLK_WR_BYPASS_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-16 | PHY_IO_PAD_DELAY_TIMING_BYPASS_3 | R/W | 0h | Feedback pad's OPAD and IPAD delay timing on bypass mode for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WR_BYPASS_SLAVE_DELAY_3 | R/W | 0h | Write data clock bypass mode slave delay setting for slice 3.} PADDING_BEFORE |
DDRSS_PHY_769 is shown in Figure 8-1259 and described in Table 8-2530.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C04h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRITE_PATH_LAT_ADD_BYPASS_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R/W | X | |
| 18-16 | PHY_WRITE_PATH_LAT_ADD_BYPASS_3 | R/W | 0h | Number of cycles on bypass mode to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3 | R/W | 0h | Write DQS bypass mode slave delay setting for slice 3. |
DDRSS_PHY_770 is shown in Figure 8-1260 and described in Table 8-2532.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C08h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CLK_BYPASS_OVERRIDE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_BYPASS_TWO_CYC_PREAMBLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_CLK_BYPASS_OVERRIDE_3 | R/W | 0h | Bypass mode override setting for slice 3. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_BYPASS_TWO_CYC_PREAMBLE_3 | R/W | 0h | Two_cycle_preamble for bypass mode for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3 | R/W | 0h | Read DQS bypass mode slave delay setting for slice 3. |
DDRSS_PHY_771 is shown in Figure 8-1261 and described in Table 8-2534.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C0Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WRDQ3_SHIFT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_WRDQ2_SHIFT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQ1_SHIFT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDQ0_SHIFT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_SW_WRDQ3_SHIFT_3 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ3 for slice 3. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_SW_WRDQ2_SHIFT_3 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ2 for slice 3. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_SW_WRDQ1_SHIFT_3 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ1 for slice 3. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDQ0_SHIFT_3 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ0 for slice 3. |
DDRSS_PHY_772 is shown in Figure 8-1262 and described in Table 8-2536.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C10h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WRDQ7_SHIFT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_WRDQ6_SHIFT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQ5_SHIFT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDQ4_SHIFT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_SW_WRDQ7_SHIFT_3 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ7 for slice 3. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_SW_WRDQ6_SHIFT_3 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ6 for slice 3. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_SW_WRDQ5_SHIFT_3 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ5 for slice 3. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDQ4_SHIFT_3 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQ4 for slice 3. |
DDRSS_PHY_773 is shown in Figure 8-1263 and described in Table 8-2538.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C14h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PER_CS_TRAINING_MULTICAST_EN_3 | ||||||
| R/W-X | R/W-1h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PER_RANK_CS_MAP_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_WRDQS_SHIFT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_WRDM_SHIFT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_PER_CS_TRAINING_MULTICAST_EN_3 | R/W | 1h | When set, a register write will update parameters for all ranks at the same time in slice 3. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_PER_RANK_CS_MAP_3 | R/W | 0h | Per-rank CS map for slice 3. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_SW_WRDQS_SHIFT_3 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DQS for slice 3. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_SW_WRDM_SHIFT_3 | R/W | 0h | Manual override of automatic half_cycle_shift/cycle_shift for write DM for slice 3. |
DDRSS_PHY_774 is shown in Figure 8-1264 and described in Table 8-2540.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C18h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_DLY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PER_CS_TRAINING_INDEX_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 3. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_LP4_BOOT_RDDATA_EN_DLY_3 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is early for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 3. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_PER_CS_TRAINING_INDEX_3 | R/W | 0h | For per-rank training, indicates which rank's paramters are read/written for slice 3. |
DDRSS_PHY_775 is shown in Figure 8-1265 and described in Table 8-2542.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C1Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LP4_BOOT_RPTR_UPDATE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 3. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3 | R/W | 0h | For LPDDR4 boot frequency, write path clock gating disable for slice 3. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 3. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_LP4_BOOT_RPTR_UPDATE_3 | R/W | 0h | For LPDDR4 boot frequency, the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 3. |
DDRSS_PHY_776 is shown in Figure 8-1266 and described in Table 8-2544.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C20h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LPBK_DFX_TIMEOUT_EN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LPBK_CONTROL_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_LPBK_CONTROL_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CTRL_LPBK_EN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_LPBK_DFX_TIMEOUT_EN_3 | R/W | 0h | Loopback read only test timeout mechanism enable for slice 3. |
| 23-17 | RESERVED | R/W | X | |
| 16-8 | PHY_LPBK_CONTROL_3 | R/W | 0h | Loopback control bits for slice 3. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_CTRL_LPBK_EN_3 | R/W | 0h | Loopback control en for slice 3. |
DDRSS_PHY_777 is shown in Figure 8-1267 and described in Table 8-2546.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C24h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_AUTO_TIMING_MARGIN_CONTROL_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_AUTO_TIMING_MARGIN_CONTROL_3 | R/W | 0h | Auto timing marging control bits for slice 3. |
DDRSS_PHY_778 is shown in Figure 8-1268 and described in Table 8-2548.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C28h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_AUTO_TIMING_MARGIN_OBS_3 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R | X | |
| 27-0 | PHY_AUTO_TIMING_MARGIN_OBS_3 | R | 0h | Observation register for the auto_timing_margin for slice 3. |
DDRSS_PHY_779 is shown in Figure 8-1269 and described in Table 8-2550.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C2Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_MULTI_PATT_ENABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PRBS_PATTERN_MASK_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PRBS_PATTERN_MASK_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PRBS_PATTERN_START_3 | ||||||
| R/W-X | R/W-1h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RDLVL_MULTI_PATT_ENABLE_3 | R/W | 0h | Read Leveling Multi-pattern enable for slice 3. |
| 23-17 | RESERVED | R/W | X | |
| 16-8 | PHY_PRBS_PATTERN_MASK_3 | R/W | 0h | PRBS7 mask signal for slice 3. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_PRBS_PATTERN_START_3 | R/W | 1h | PRBS7 start pattern for slice 3. |
DDRSS_PHY_780 is shown in Figure 8-1270 and described in Table 8-2552.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C30h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_VREF_TRAIN_OBS_3 | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_VREF_INITIAL_STEPSIZE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_MULTI_PATT_RST_DISABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-23 | RESERVED | R/W | X | |
| 22-16 | PHY_VREF_TRAIN_OBS_3 | R | 0h | Observation register for best vref value for slice 3. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_VREF_INITIAL_STEPSIZE_3 | R/W | 0h | Data slice initial VREF training step size for slice 3. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_RDLVL_MULTI_PATT_RST_DISABLE_3 | R/W | 0h | Read Leveling read level windows disable reset for slice 3. |
DDRSS_PHY_781 is shown in Figure 8-1271 and described in Table 8-2554.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C34h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_SNAP_OBS_REGS_3 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GATE_ERROR_DELAY_SELECT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | SC_PHY_SNAP_OBS_REGS_3 | W | 0h | Initiates a snapshot of the internal observation registers for slice 3. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GATE_ERROR_DELAY_SELECT_3 | R/W | 0h | Number of cycles to wait for the DQS gate to close before flagging an error for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3 | R/W | 0h | Read DQS data clock bypass mode slave delay setting for slice 3. |
DDRSS_PHY_782 is shown in Figure 8-1272 and described in Table 8-2556.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C38h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_MEM_CLASS_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LPDDR_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL1_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL1_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_MEM_CLASS_3 | R/W | 0h | Indicates the type of DRAM for slice 3. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_LPDDR_3 | R/W | 0h | Adds a cycle of delay for the slice 3 to match the address slice. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_GATE_SMPL1_SLAVE_DELAY_3 | R/W | 0h | Number of cycles to delay the read DQS gate signal to generate gate1 signal for on-the-fly read DQS training for slice 3. |
DDRSS_PHY_783 is shown in Figure 8-1273 and described in Table 8-2558.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C3Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | ON_FLY_GATE_ADJUST_EN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL2_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL2_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | ON_FLY_GATE_ADJUST_EN_3 | R/W | 0h | Control the on-the-fly gate adjustment for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_GATE_SMPL2_SLAVE_DELAY_3 | R/W | 0h | Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 3. |
DDRSS_PHY_784 is shown in Figure 8-1274 and described in Table 8-2560.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C40h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_TRACKING_OBS_3 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_GATE_TRACKING_OBS_3 | R | 0h | Report the on-the-fly gate measurement result for slice 3. |
DDRSS_PHY_785 is shown in Figure 8-1275 and described in Table 8-2562.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C44h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_PST_AMBLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DFI40_POLARITY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-8 | PHY_LP4_PST_AMBLE_3 | R/W | 0h | Controls the read postamble extension for LPDDR4 for slice 3. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DFI40_POLARITY_3 | R/W | 0h | Indicates the dfi_wrdata_cs_n and dfi_rddata_cs_n is low active or high active for slice 3. |
DDRSS_PHY_786 is shown in Figure 8-1276 and described in Table 8-2564.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C48h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT8_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT8_3 | R/W | 0h | Read leveling pattern 8 data for slice 3. |
DDRSS_PHY_787 is shown in Figure 8-1277 and described in Table 8-2566.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C4Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT9_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT9_3 | R/W | 0h | Read leveling pattern 9 data for slice 3. |
DDRSS_PHY_788 is shown in Figure 8-1278 and described in Table 8-2568.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C50h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT10_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT10_3 | R/W | 0h | Read leveling pattern 10 data for slice 3. |
DDRSS_PHY_789 is shown in Figure 8-1279 and described in Table 8-2570.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C54h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT11_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT11_3 | R/W | 0h | Read leveling pattern 11 data for slice 3. |
DDRSS_PHY_790 is shown in Figure 8-1280 and described in Table 8-2572.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C58h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT12_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT12_3 | R/W | 0h | Read leveling pattern 12 data for slice 3. |
DDRSS_PHY_791 is shown in Figure 8-1281 and described in Table 8-2574.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C5Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT13_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT13_3 | R/W | 0h | Read leveling pattern 13 data for slice 3. |
DDRSS_PHY_792 is shown in Figure 8-1282 and described in Table 8-2576.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C60h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT14_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT14_3 | R/W | 0h | Read leveling pattern 14 data for slice 3. |
DDRSS_PHY_793 is shown in Figure 8-1283 and described in Table 8-2578.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C64h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PATT15_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PATT15_3 | R/W | 0h | Read leveling pattern 15 data for slice 3. |
DDRSS_PHY_794 is shown in Figure 8-1284 and described in Table 8-2580.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C68h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQ_ENC_OBS_SELECT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DLY_LOCK_OBS_SELECT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_FIFO_PTR_RST_DISABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SLAVE_LOOP_CNT_UPDATE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_RDDQ_ENC_OBS_SELECT_3 | R/W | 0h | Select value to map the internal read DQ slave delay encoded settings to the accessible read DQ encoded slave delay observation register for slice 3. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_MASTER_DLY_LOCK_OBS_SELECT_3 | R/W | 0h | Select value to map the internal master delay observation registers to the accessible master delay observation register for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_SW_FIFO_PTR_RST_DISABLE_3 | R/W | 0h | Disables automatic reset of the read entry FIFO pointers for slice 3. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_SLAVE_LOOP_CNT_UPDATE_3 | R/W | 0h | Reserved for future use for slice 3. |
DDRSS_PHY_795 is shown in Figure 8-1285 and described in Table 8-2582.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C6Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_FIFO_PTR_OBS_SELECT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WR_SHIFT_OBS_SELECT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WR_ENC_OBS_SELECT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQS_DQ_ENC_OBS_SELECT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_FIFO_PTR_OBS_SELECT_3 | R/W | 0h | Select value to map the internal read entry FIFO read/write pointers to the accessible read entry FIFO pointer observation register for slice 3. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_WR_SHIFT_OBS_SELECT_3 | R/W | 0h | Select value to map the internal write DQ/DQS automatic cycle/half_cycle shift settings to the accessible write DQ/DQS shift observation register for slice 3. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WR_ENC_OBS_SELECT_3 | R/W | 0h | Select value to map the internal write DQ slave delay encoded settings to the accessible write DQ encoded slave delay observation register for slice 3. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_RDDQS_DQ_ENC_OBS_SELECT_3 | R/W | 0h | Select value to map the internal read DQS DQ rise/fall slave delay encoded settings to the accessible read DQS DQ rise/fall encoded slave delay observation registers for slice 3. |
DDRSS_PHY_796 is shown in Figure 8-1286 and described in Table 8-2584.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C70h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_WRLVL_PER_START_3 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_ALGO_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_LVL_DEBUG_CONT_3 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LVL_DEBUG_MODE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_WRLVL_PER_START_3 | R/W | 0h | Observation register for write leveling status for slice 3. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_WRLVL_ALGO_3 | R/W | 0h | Write leveling algorithm selection for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8 | SC_PHY_LVL_DEBUG_CONT_3 | W | 0h | Allows the leveling state machine to advance (when in debug mode) for slice 3. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_LVL_DEBUG_MODE_3 | R/W | 0h | Enables leveling debug mode for slice 3. |
DDRSS_PHY_797 is shown in Figure 8-1287 and described in Table 8-2586.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C74h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQ_MASK_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_UPDT_WAIT_CNT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_CAPTURE_CNT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | X | |
| 23-16 | PHY_DQ_MASK_3 | R/W | 0h | For ECC slice, should set this register to do DQ bit mask for slice 3. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WRLVL_UPDT_WAIT_CNT_3 | R/W | 0h | Number of cycles to wait after changing DQS slave delay setting during write leveling for slice 3. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_WRLVL_CAPTURE_CNT_3 | R/W | 0h | Number of samples to take at each DQS slave delay setting during write leveling for slice 3. |
DDRSS_PHY_798 is shown in Figure 8-1288 and described in Table 8-2588.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C78h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GTLVL_UPDT_WAIT_CNT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_CAPTURE_CNT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GTLVL_PER_START_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_PER_START_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_GTLVL_UPDT_WAIT_CNT_3 | R/W | 0h | Number of cycles + 4 to wait after changing DQS slave delay setting during gate training for slice 3. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_GTLVL_CAPTURE_CNT_3 | R/W | 0h | Number of samples to take at each DQS slave delay setting during gate training for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_PER_START_3 | R/W | 0h | Value to be added to the current gate delay position as the staring point for periodic gate training for slice 3. |
DDRSS_PHY_799 is shown in Figure 8-1289 and described in Table 8-2590.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C7Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDLVL_OP_MODE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_UPDT_WAIT_CNT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_CAPTURE_CNT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during read leveling for slice 3. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_RDLVL_OP_MODE_3 | R/W | 0h | Read leveling algorithm select for slice 3. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_RDLVL_UPDT_WAIT_CNT_3 | R/W | 0h | Number of cycles to wait after changing DQS slave delay setting during read leveling for slice 3. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_RDLVL_CAPTURE_CNT_3 | R/W | 0h | Number of samples to take at each DQS slave delay setting during read leveling for slice 3. |
DDRSS_PHY_800 is shown in Figure 8-1290 and described in Table 8-2592.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C80h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_BURST_CNT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_WDQLVL_CLK_JITTER_TOLERANCE_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDLVL_DATA_MASK_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PERIODIC_OBS_SELECT_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_WDQLVL_BURST_CNT_3 | R/W | 0h | Defines the write/read burst length in bytes during the write data leveling sequence for slice 3. |
| 23-16 | PHY_WDQLVL_CLK_JITTER_TOLERANCE_3 | R/W | 0h | Defines the minimum gap requirment for the LE and TE window for slice 3. |
| 15-8 | PHY_RDLVL_DATA_MASK_3 | R/W | 0h | Per-bit mask for read leveling for slice 3. |
| 7-0 | PHY_RDLVL_PERIODIC_OBS_SELECT_3 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during periodic read leveling for slice 3. |
DDRSS_PHY_801 is shown in Figure 8-1291 and described in Table 8-2594.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C84h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_UPDT_WAIT_CNT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_PATT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_WDQLVL_UPDT_WAIT_CNT_3 | R/W | 0h | Number of cycles to wait after changing the DQ slave delay setting during write data leveling for slice 3. |
| 23-19 | RESERVED | R/W | X | |
| 18-8 | PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3 | R/W | 0h | Defines the write/read burst length in bytes during the write data leveling sequence for slice 3. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_WDQLVL_PATT_3 | R/W | 0h | Defines the training patterns to be used during the write data leveling sequence for slice 3. |
DDRSS_PHY_802 is shown in Figure 8-1292 and described in Table 8-2596.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C88h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_WDQLVL_CLR_PREV_RESULTS_3 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_PERIODIC_OBS_SELECT_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DQDM_OBS_SELECT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | SC_PHY_WDQLVL_CLR_PREV_RESULTS_3 | W | 0h | Clears the previous result value to allow a clean slate comparison for future write DQ leveling results for slice 3. |
| 15-8 | PHY_WDQLVL_PERIODIC_OBS_SELECT_3 | R/W | 0h | Select value to map specific information during or post periodic write data leveling for slice 3. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_WDQLVL_DQDM_OBS_SELECT_3 | R/W | 0h | Select value to map an individual DQ data window leading/trailing edge to the leading/trailing edge observation registers during write data leveling for slice 3. |
DDRSS_PHY_803 is shown in Figure 8-1293 and described in Table 8-2598.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C8Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DATADM_MASK_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R/W | X | |
| 8-0 | PHY_WDQLVL_DATADM_MASK_3 | R/W | 0h | Per-bit mask for write data leveling for slice 3. |
DDRSS_PHY_804 is shown in Figure 8-1294 and described in Table 8-2600.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C90h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT0_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT0_3 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 3. |
DDRSS_PHY_805 is shown in Figure 8-1295 and described in Table 8-2602.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C94h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT1_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT1_3 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 3. |
DDRSS_PHY_806 is shown in Figure 8-1296 and described in Table 8-2604.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C98h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT2_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT2_3 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 3. |
DDRSS_PHY_807 is shown in Figure 8-1297 and described in Table 8-2606.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4C9Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT3_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_USER_PATT3_3 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 3. |
DDRSS_PHY_808 is shown in Figure 8-1298 and described in Table 8-2608.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CA0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_MULT_TRAIN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_USER_PATT4_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_USER_PATT4_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_NTP_MULT_TRAIN_3 | R/W | 0h | Control for single pass only No-Topology training for slice 3. |
| 15-0 | PHY_USER_PATT4_3 | R/W | 0h | User-defined pattern to be used during write data leveling for slice 3. |
DDRSS_PHY_809 is shown in Figure 8-1299 and described in Table 8-2610.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CA4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_EARLY_THRESHOLD_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_NTP_PERIOD_THRESHOLD_3 | R/W | 0h | Threshold Criteria of period threshold after No-Topology training is completed for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_NTP_EARLY_THRESHOLD_3 | R/W | 0h | Threshold Criteria of early threshold after No-Topology training is completed for slice 3. |
DDRSS_PHY_810 is shown in Figure 8-1300 and described in Table 8-2612.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CA8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_MAX_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_PERIOD_THRESHOLD_MIN_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_NTP_PERIOD_THRESHOLD_MAX_3 | R/W | 0h | Maximum Threshold that phy_clk_wrdqs_slave_delay could cross boundary, to set period threshold/early threshold after No-Topology training is completed for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_NTP_PERIOD_THRESHOLD_MIN_3 | R/W | 0h | Minimum Threshold that phy_clk_wrdqs_slave_delay could cross boundary, to set period threshold/early threshold after No-Topology training is completed for slice 3. |
DDRSS_PHY_811 is shown in Figure 8-1301 and described in Table 8-2614.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_FIFO_PTR_OBS_3 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_MANUAL_CLEAR_3 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CALVL_VREF_DRIVING_SLICE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | X | |
| 23-16 | PHY_FIFO_PTR_OBS_3 | R | 0h | Observation register containing read entry FIFO pointers for slice 3. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | SC_PHY_MANUAL_CLEAR_3 | W | 0h | Manual reset/clear of internal logic for slice 3. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_CALVL_VREF_DRIVING_SLICE_3 | R/W | 0h | Indicates if slice 3 is used to drive the VREF value to the device during CA training. |
DDRSS_PHY_812 is shown in Figure 8-1302 and described in Table 8-2616.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CB0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LPBK_RESULT_OBS_3 | |||||||||||||||||||||||||||||||
| R-00100000h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_LPBK_RESULT_OBS_3 | R | 00100000h | Observation register containing loopback status/results for slice 3. |
DDRSS_PHY_813 is shown in Figure 8-1303 and described in Table 8-2618.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CB4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DLY_LOCK_OBS_3 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LPBK_ERROR_COUNT_OBS_3 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R | X | |
| 26-16 | PHY_MASTER_DLY_LOCK_OBS_3 | R | 0h | Observation register containing master delay results for slice 3. |
| 15-0 | PHY_LPBK_ERROR_COUNT_OBS_3 | R | 0h | Observation register containing total number of loopback error data for slice 3. |
DDRSS_PHY_814 is shown in Figure 8-1304 and described in Table 8-2620.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CB8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3 | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_MEAS_DLY_STEP_VALUE_3 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ_SLV_DLY_ENC_OBS_3 | ||||||
| R-X | R-0h | ||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3 | R | 0h | Observation register containing read DQS DQ rising edge adder slave delay encoded value for slice 3. |
| 23-16 | PHY_MEAS_DLY_STEP_VALUE_3 | R | 0h | Observation register containing fraction of the cycle in 1 delay element, numerator with demominator of 512, for slice 3. |
| 15 | RESERVED | R | X | |
| 14-8 | PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3 | R | 0h | Observation register containing read DQS base slave delay encoded value for slice 3. |
| 7 | RESERVED | R | X | |
| 6-0 | PHY_RDDQ_SLV_DLY_ENC_OBS_3 | R | 0h | Observation register containing read DQ slave delay encoded values for slice 3. |
DDRSS_PHY_815 is shown in Figure 8-1305 and described in Table 8-2622.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CBCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3 | ||||||
| R-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R | X | |
| 30-24 | PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3 | R | 0h | Observation register containing write DQS base slave delay encoded value for slice 3. |
| 23-19 | RESERVED | R | X | |
| 18-8 | PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3 | R | 0h | Observation register containing read DQS gate slave delay encoded value for slice 3. |
| 7-0 | PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3 | R | 0h | Observation register containing read DQS DQ falling edge adder slave delay encoded value for slice 3. |
DDRSS_PHY_816 is shown in Figure 8-1306 and described in Table 8-2624.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CC0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WR_SHIFT_OBS_3 | ||||||
| R-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WR_ADDER_SLV_DLY_ENC_OBS_3 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R | X | |
| 18-16 | PHY_WR_SHIFT_OBS_3 | R | 0h | Observation register containing automatic half cycle and cycle shift values for slice 3. |
| 15-8 | PHY_WR_ADDER_SLV_DLY_ENC_OBS_3 | R | 0h | Observation register containing write adder slave delay encoded value for slice 3. |
| 7-0 | PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3 | R | 0h | Observation register containing write DQ base slave delay encoded value for slice 3. |
DDRSS_PHY_817 is shown in Figure 8-1307 and described in Table 8-2626.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CC4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_HARD1_DELAY_OBS_3 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_HARD0_DELAY_OBS_3 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_WRLVL_HARD1_DELAY_OBS_3 | R | 0h | Observation register containing write leveling first hard 1 DQS slave delay for slice 3. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_WRLVL_HARD0_DELAY_OBS_3 | R | 0h | Observation register containing write leveling last hard 0 DQS slave delay for slice 3. |
DDRSS_PHY_818 is shown in Figure 8-1308 and described in Table 8-2628.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CC8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_STATUS_OBS_3 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_STATUS_OBS_3 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R | X | |
| 16-0 | PHY_WRLVL_STATUS_OBS_3 | R | 0h | Observation register containing write leveling status for slice 3. |
DDRSS_PHY_819 is shown in Figure 8-1309 and described in Table 8-2630.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CCCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3 | R | 0h | Observation register containing gate sample2 slave delay encoded values for slice 3. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3 | R | 0h | Observation register containing gate sample1 slave delay encoded values for slice 3. |
DDRSS_PHY_820 is shown in Figure 8-1310 and described in Table 8-2632.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CD0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_HARD0_DELAY_OBS_3 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_ERROR_OBS_3 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R | X | |
| 29-16 | PHY_GTLVL_HARD0_DELAY_OBS_3 | R | 0h | Observation register containing gate training first hard 0 DQS slave delay for slice 3. |
| 15-0 | PHY_WRLVL_ERROR_OBS_3 | R | 0h | Observation register containing write leveling error status for slice 3. |
DDRSS_PHY_821 is shown in Figure 8-1311 and described in Table 8-2634.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CD4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GTLVL_HARD1_DELAY_OBS_3 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-14 | RESERVED | R | X | |
| 13-0 | PHY_GTLVL_HARD1_DELAY_OBS_3 | R | 0h | Observation register containing gate training last hard 1 DQS slave delay for slice 3. |
DDRSS_PHY_822 is shown in Figure 8-1312 and described in Table 8-2636.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CD8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_STATUS_OBS_3 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_STATUS_OBS_3 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R | X | |
| 17-0 | PHY_GTLVL_STATUS_OBS_3 | R | 0h | Observation register containing gate training status for slice 3. |
DDRSS_PHY_823 is shown in Figure 8-1313 and described in Table 8-2638.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CDCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3 | ||||||
| R-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | X | |
| 25-16 | PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3 | R | 0h | Observation register containing read leveling data window trailing edge slave delay setting for slice 3. |
| 15-10 | RESERVED | R | X | |
| 9-0 | PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3 | R | 0h | Observation register containing read leveling data window leading edge slave delay setting for slice 3. |
DDRSS_PHY_824 is shown in Figure 8-1314 and described in Table 8-2640.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CE0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3 | ||||||
| R-X | R-0h | ||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R | X | |
| 1-0 | PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3 | R | 0h | Observation register containing read leveling number of windows found for slice 3. |
DDRSS_PHY_825 is shown in Figure 8-1315 and described in Table 8-2642.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CE4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_STATUS_OBS_3 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_STATUS_OBS_3 | R | 0h | Observation register containing read leveling status for slice 3. |
DDRSS_PHY_826 is shown in Figure 8-1316 and described in Table 8-2644.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CE8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_PERIODIC_OBS_3 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_RDLVL_PERIODIC_OBS_3 | R | 0h | Observation register containing periodic read leveling status for slice 3. |
DDRSS_PHY_827 is shown in Figure 8-1317 and described in Table 8-2646.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DQDM_TE_DLY_OBS_3 | ||||||||||||||
| R-X | R-7FFh | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_DQDM_LE_DLY_OBS_3 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R | X | |
| 26-16 | PHY_WDQLVL_DQDM_TE_DLY_OBS_3 | R | 7FFh | Observation register containing write data leveling data window trailing edge slave delay setting for slice 3. |
| 15-11 | RESERVED | R | X | |
| 10-0 | PHY_WDQLVL_DQDM_LE_DLY_OBS_3 | R | 0h | Observation register containing write data leveling data window leading edge slave delay setting for slice 3. |
DDRSS_PHY_828 is shown in Figure 8-1318 and described in Table 8-2648.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CF0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_STATUS_OBS_3 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_WDQLVL_STATUS_OBS_3 | R | 0h | Observation register containing write data leveling status for slice 3. |
DDRSS_PHY_829 is shown in Figure 8-1319 and described in Table 8-2650.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CF4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_PERIODIC_OBS_3 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_WDQLVL_PERIODIC_OBS_3 | R | 0h | Observation register containing periodic write data leveling status for slice 3. |
DDRSS_PHY_830 is shown in Figure 8-1320 and described in Table 8-2652.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CF8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DDL_MODE_3 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-0 | PHY_DDL_MODE_3 | R/W | 0h | DDL mode for slice 3. |
DDRSS_PHY_831 is shown in Figure 8-1321 and described in Table 8-2654.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4CFCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DDL_MASK_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DDL_MASK_3 | R/W | 0h | DDL mask for slice 3. |
DDRSS_PHY_832 is shown in Figure 8-1322 and described in Table 8-2656.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D00h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TEST_OBS_3 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DDL_TEST_OBS_3 | R | 0h | DDL test observation for slice 3. |
DDRSS_PHY_833 is shown in Figure 8-1323 and described in Table 8-2658.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D04h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TEST_MSTR_DLY_OBS_3 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DDL_TEST_MSTR_DLY_OBS_3 | R | 0h | DDL test observation delays for slice 3 master DDL. |
DDRSS_PHY_834 is shown in Figure 8-1324 and described in Table 8-2660.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D08h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_OVERRIDE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_RX_CAL_START_3 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_WDQS_OE_EXTEND_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_TRACK_UPD_THRESHOLD_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RX_CAL_OVERRIDE_3 | R/W | 0h | Manual setting of RX Calibration enable for slice 3. |
| 23-17 | RESERVED | R/W | X | |
| 16 | SC_PHY_RX_CAL_START_3 | W | 0h | Manual RX Calibration start for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_LP4_WDQS_OE_EXTEND_3 | R/W | 0h | LPDDR4 write preamble extension enable for slice 3. |
| 7-0 | PHY_DDL_TRACK_UPD_THRESHOLD_3 | R/W | 0h | Specify threshold value for PHY init update tracking for slice 3. |
DDRSS_PHY_835 is shown in Figure 8-1325 and described in Table 8-2662.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D0Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_DQ0_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RX_CAL_DQ0_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RX_CAL_SAMPLE_WAIT_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ0_3 | R/W | 0h | RX Calibration codes for DQ0 for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3 | R/W | 0h | Data slice power reduction disable for slice 3. |
| 7-0 | PHY_RX_CAL_SAMPLE_WAIT_3 | R/W | 0h | RX Calibration state machine wait count for slice 3. |
DDRSS_PHY_836 is shown in Figure 8-1326 and described in Table 8-2664.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D10h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ2_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ1_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ2_3 | R/W | 0h | RX Calibration codes for DQ2 for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ1_3 | R/W | 0h | RX Calibration codes for DQ1 for slice 3. |
DDRSS_PHY_837 is shown in Figure 8-1327 and described in Table 8-2666.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D14h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ4_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ3_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ4_3 | R/W | 0h | RX Calibration codes for DQ4 for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ3_3 | R/W | 0h | RX Calibration codes for DQ3 for slice 3. |
DDRSS_PHY_838 is shown in Figure 8-1328 and described in Table 8-2668.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D18h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DQ6_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ5_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_DQ6_3 | R/W | 0h | RX Calibration codes for DQ6 for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ5_3 | R/W | 0h | RX Calibration codes for DQ5 for slice 3. |
DDRSS_PHY_839 is shown in Figure 8-1329 and described in Table 8-2670.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D1Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQ7_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQ7_3 | R/W | 0h | RX Calibration codes for DQ7 for slice 3. |
DDRSS_PHY_840 is shown in Figure 8-1330 and described in Table 8-2672.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D20h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DM_3 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_RX_CAL_DM_3 | R/W | 0h | RX Calibration codes for DM for slice 3. |
DDRSS_PHY_841 is shown in Figure 8-1331 and described in Table 8-2674.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D24h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_FDBK_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DQS_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_RX_CAL_FDBK_3 | R/W | 0h | RX Calibration codes for FDBK for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_RX_CAL_DQS_3 | R/W | 0h | RX Calibration codes for DQS for slice 3. |
DDRSS_PHY_842 is shown in Figure 8-1332 and described in Table 8-2676.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D28h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_LOCK_OBS_3 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_OBS_3 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R | X | |
| 24-16 | PHY_RX_CAL_LOCK_OBS_3 | R | 0h | RX Calibration lock results for slice 3. |
| 15-11 | RESERVED | R | X | |
| 10-0 | PHY_RX_CAL_OBS_3 | R | 0h | RX Calibration results for slice 3. |
DDRSS_PHY_843 is shown in Figure 8-1333 and described in Table 8-2678.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D2Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RX_CAL_COMP_VAL_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RX_CAL_DIFF_ADJUST_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RX_CAL_SE_ADJUST_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_DISABLE_3 | ||||||
| R/W-X | R/W-1h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_RX_CAL_COMP_VAL_3 | R/W | 0h | Expected C value from RX pad for slice 3. |
| 23 | RESERVED | R/W | X | |
| 22-16 | PHY_RX_CAL_DIFF_ADJUST_3 | R/W | 0h | Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 3. |
| 15 | RESERVED | R/W | X | |
| 14-8 | PHY_RX_CAL_SE_ADJUST_3 | R/W | 0h | Fine adjustment for Single-Ended RX pad of RX CAL V2 for slice 3. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_RX_CAL_DISABLE_3 | R/W | 1h | RX CAL disable signal for slice 3, set 1 to bypass the rx calibration |
DDRSS_PHY_844 is shown in Figure 8-1334 and described in Table 8-2680.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D30h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_BIAS_EN_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RX_CAL_INDEX_MASK_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_PAD_RX_BIAS_EN_3 | R/W | 0h | Controls RX_BIAS_EN pin for each pad for slice 3. |
| 15-12 | RESERVED | R/W | X | |
| 11-0 | PHY_RX_CAL_INDEX_MASK_3 | R/W | 0h | RX offset calibration mask of all RX pad for slice 3. |
DDRSS_PHY_845 is shown in Figure 8-1335 and described in Table 8-2682.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D34h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_WEIGHT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_CAL_TIMEOUT_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_CAL_SAMPLE_WAIT_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_STATIC_TOG_DISABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_DATA_DC_WEIGHT_3 | R/W | 0h | Determines weight of average calculating for slice 3. |
| 23-16 | PHY_DATA_DC_CAL_TIMEOUT_3 | R/W | 0h | Determines timeout number of iteration for slice 3. |
| 15-8 | PHY_DATA_DC_CAL_SAMPLE_WAIT_3 | R/W | 0h | Determines number of cycles to wait for each sample for slice 3. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_STATIC_TOG_DISABLE_3 | R/W | 0h | Control to disable toggle during static activity for slice 3. |
DDRSS_PHY_846 is shown in Figure 8-1336 and described in Table 8-2684.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D38h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_ADJUST_DIRECT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_ADJUST_THRSHLD_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_ADJUST_SAMPLE_CNT_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_ADJUST_START_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_DATA_DC_ADJUST_DIRECT_3 | R/W | 0h | Adjust direction for slice 3. |
| 23-16 | PHY_DATA_DC_ADJUST_THRSHLD_3 | R/W | 0h | Duty cycle adjust threshold around the mid-point for slice 3. |
| 15-8 | PHY_DATA_DC_ADJUST_SAMPLE_CNT_3 | R/W | 0h | Duty cycle adjust sample count for slice 3. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DATA_DC_ADJUST_START_3 | R/W | 0h | Duty cycle adjust starting value for slice 3. |
DDRSS_PHY_847 is shown in Figure 8-1337 and described in Table 8-2686.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D3Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_FDBK_PWR_CTRL_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_SW_RANK_3 | ||||||
| R/W-X | R/W-1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_CAL_START_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_CAL_POLARITY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_FDBK_PWR_CTRL_3 | R/W | 0h | Shutoff gate feedback IO to reduce power for slice 3. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DATA_DC_SW_RANK_3 | R/W | 1h | Rank selection for software based duty cycle correction for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DATA_DC_CAL_START_3 | R/W | 0h | Manual trigger for DCC for slice 3. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DATA_DC_CAL_POLARITY_3 | R/W | 0h | Calibration polarity for slice 3. |
DDRSS_PHY_848 is shown in Figure 8-1338 and described in Table 8-2688.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D40h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SLICE_PWR_RDC_DISABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDPATH_GATE_DISABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SLV_DLY_CTRL_GATE_DISABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_SLICE_PWR_RDC_DISABLE_3 | R/W | 0h | Data slice power reduction disable for slice 3. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3 | R/W | 0h | Data slice DCC and RX_CAL block power reduction disable for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_RDPATH_GATE_DISABLE_3 | R/W | 0h | Data slice read path power reduction disable for slice 3. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_SLV_DLY_CTRL_GATE_DISABLE_3 | R/W | 0h | Data slice slv_dly_control block power reduction disable for slice 3. |
DDRSS_PHY_849 is shown in Figure 8-1339 and described in Table 8-2690.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D44h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DS_FSM_ERROR_INFO_3 | ||||||||||||||
| R/W-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PARITY_ERROR_REGIF_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | PHY_DS_FSM_ERROR_INFO_3 | R | 0h | Data slice level FSM Error Info for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_PARITY_ERROR_REGIF_3 | R/W | 0h | Inject parity error to register interface signals for slice 3. |
DDRSS_PHY_850 is shown in Figure 8-1340 and described in Table 8-2692.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D48h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3 | |||||||
| W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DS_FSM_ERROR_INFO_MASK_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DS_FSM_ERROR_INFO_MASK_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3 | W | 0h | Data slice level FSM Error Info for slice 3. |
| 15-14 | RESERVED | R/W | X | |
| 13-0 | PHY_DS_FSM_ERROR_INFO_MASK_3 | R/W | 0h | Data slice level FSM Error Info Mask for slice 3. |
DDRSS_PHY_851 is shown in Figure 8-1341 and described in Table 8-2694.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D4Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DS_TRAIN_CALIB_ERROR_INFO_3 | ||||||
| R/W-X | R-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3 | W | 0h | Data slice level training/calibration Error Info for slice 3. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK_3 | R/W | 0h | Data slice level training/calibration Error Info Mask for slice 3. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_DS_TRAIN_CALIB_ERROR_INFO_3 | R | 0h | Data slice level training/calibration Error Info for slice 3. |
DDRSS_PHY_852 is shown in Figure 8-1342 and described in Table 8-2696.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D50h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DQS_TSEL_ENABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQ_TSEL_SELECT_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_TSEL_SELECT_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DQ_TSEL_ENABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_DQS_TSEL_ENABLE_3 | R/W | 0h | Operation type tsel enables for DQS signals for slice 3. |
| 23-8 | PHY_DQ_TSEL_SELECT_3 | R/W | 0h | Operation type tsel select values for DQ/DM signals for slice 3. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_DQ_TSEL_ENABLE_3 | R/W | 0h | Operation type tsel enables for DQ/DM signals for slice 3. |
DDRSS_PHY_853 is shown in Figure 8-1343 and described in Table 8-2698.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D54h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_VREF_INITIAL_START_POINT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TWO_CYC_PREAMBLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQS_TSEL_SELECT_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQS_TSEL_SELECT_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-24 | PHY_VREF_INITIAL_START_POINT_3 | R/W | 0h | Data slice initial VREF training start value for slice 3. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_TWO_CYC_PREAMBLE_3 | R/W | 0h | 2 cycle preamble support for slice 3. |
| 15-0 | PHY_DQS_TSEL_SELECT_3 | R/W | 0h | Operation type tsel select values for DQS signals for slice 3. |
DDRSS_PHY_854 is shown in Figure 8-1344 and described in Table 8-2700.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D58h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_NTP_WDQ_STEP_SIZE_3 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_TRAIN_EN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_VREF_TRAINING_CTRL_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_VREF_INITIAL_STOP_POINT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_NTP_WDQ_STEP_SIZE_3 | R/W | 0h | Step size of WR DQ slave delay during No-Topology training for slice 3. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_NTP_TRAIN_EN_3 | R/W | 0h | Enable for No-Topology training for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_VREF_TRAINING_CTRL_3 | R/W | 0h | Data slice vref training enable control for slice 3. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_VREF_INITIAL_STOP_POINT_3 | R/W | 0h | Data slice initial VREF training stop value for slice 3. |
DDRSS_PHY_855 is shown in Figure 8-1345 and described in Table 8-2702.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D5Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_WDQ_STOP_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_NTP_WDQ_START_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_NTP_WDQ_STOP_3 | R/W | 0h | End of WR DQ slave delay in No-Topology training for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_NTP_WDQ_START_3 | R/W | 0h | Starting WR DQ slave delay in No-Topology training for slice 3. |
DDRSS_PHY_856 is shown in Figure 8-1346 and described in Table 8-2704.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D60h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_WDQLVL_DVW_MIN_EN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_DVW_MIN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_WDQLVL_DVW_MIN_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_NTP_WDQ_BIT_EN_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_SW_WDQLVL_DVW_MIN_EN_3 | R/W | 0h | SW override to enable use of PHY_WDQLVL_DVW_MIN for slice 3. |
| 23-18 | RESERVED | R/W | X | |
| 17-8 | PHY_WDQLVL_DVW_MIN_3 | R/W | 0h | Minimum data valid window across DQs and ranks for slice 3. |
| 7-0 | PHY_NTP_WDQ_BIT_EN_3 | R/W | 0h | Enable Bit for WR DQ during No-Topology training for slice 3. |
DDRSS_PHY_857 is shown in Figure 8-1347 and described in Table 8-2706.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D64h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_RX_DCD_0_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_TX_DCD_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_FAST_LVL_EN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_PER_START_OFFSET_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_RX_DCD_0_3 | R/W | 0h | Controls RX_DCD pin for each pad for slice 3. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_TX_DCD_3 | R/W | 0h | Controls TX_DCD pin for each pad for slice 3. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_FAST_LVL_EN_3 | R/W | 0h | Enable for fast multi-pattern window search for slice 3. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_WDQLVL_PER_START_OFFSET_3 | R/W | 0h | Peridic training start point offset for slice 3. |
DDRSS_PHY_858 is shown in Figure 8-1348 and described in Table 8-2708.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D68h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_RX_DCD_4_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_DCD_3_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_RX_DCD_2_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RX_DCD_1_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_RX_DCD_4_3 | R/W | 0h | Controls RX_DCD pin for each pad for slice 3. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_RX_DCD_3_3 | R/W | 0h | Controls RX_DCD pin for each pad for slice 3. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_RX_DCD_2_3 | R/W | 0h | Controls RX_DCD pin for each pad for slice 3. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_RX_DCD_1_3 | R/W | 0h | Controls RX_DCD pin for each pad for slice 3. |
DDRSS_PHY_859 is shown in Figure 8-1349 and described in Table 8-2710.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D6Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_DM_RX_DCD_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_RX_DCD_7_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_RX_DCD_6_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RX_DCD_5_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PAD_DM_RX_DCD_3 | R/W | 0h | Controls RX_DCD pin for dm pad for slice 3. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_PAD_RX_DCD_7_3 | R/W | 0h | Controls RX_DCD pin for each pad for slice 3. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_RX_DCD_6_3 | R/W | 0h | Controls RX_DCD pin for each pad for slice 3. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_RX_DCD_5_3 | R/W | 0h | Controls RX_DCD pin for each pad for slice 3. |
DDRSS_PHY_860 is shown in Figure 8-1350 and described in Table 8-2712.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D70h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_DSLICE_IO_CFG_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_FDBK_RX_DCD_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_DQS_RX_DCD_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-22 | RESERVED | R/W | X | |
| 21-16 | PHY_PAD_DSLICE_IO_CFG_3 | R/W | 0h | Controls PCLK/PARK pin for pad for slice 3. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_PAD_FDBK_RX_DCD_3 | R/W | 0h | Controls RX_DCD pin for fdbk pad for slice 3. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_PAD_DQS_RX_DCD_3 | R/W | 0h | Controls RX_DCD pin for dqs pad for slice 3. |
DDRSS_PHY_861 is shown in Figure 8-1351 and described in Table 8-2714.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D74h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ1_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ0_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ1_SLAVE_DELAY_3 | R/W | 0h | Read DQ1 slave delay setting for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ0_SLAVE_DELAY_3 | R/W | 0h | Read DQ0 slave delay setting for slice 3. |
DDRSS_PHY_862 is shown in Figure 8-1352 and described in Table 8-2716.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D78h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ3_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ2_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ3_SLAVE_DELAY_3 | R/W | 0h | Read DQ3 slave delay setting for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ2_SLAVE_DELAY_3 | R/W | 0h | Read DQ2 slave delay setting for slice 3. |
DDRSS_PHY_863 is shown in Figure 8-1353 and described in Table 8-2718.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D7Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ5_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ4_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ5_SLAVE_DELAY_3 | R/W | 0h | Read DQ5 slave delay setting for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ4_SLAVE_DELAY_3 | R/W | 0h | Read DQ4 slave delay setting for slice 3. |
DDRSS_PHY_864 is shown in Figure 8-1354 and described in Table 8-2720.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D80h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQ7_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQ6_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQ7_SLAVE_DELAY_3 | R/W | 0h | Read DQ7 slave delay setting for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQ6_SLAVE_DELAY_3 | R/W | 0h | Read DQ6 slave delay setting for slice 3. |
DDRSS_PHY_865 is shown in Figure 8-1355 and described in Table 8-2722.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D84h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_CAL_CLK_SEL_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDM_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDM_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R/W | X | |
| 18-16 | PHY_DATA_DC_CAL_CLK_SEL_3 | R/W | 0h | Determines DCC CAL clock for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDM_SLAVE_DELAY_3 | R/W | 0h | Read DM/DBI slave delay setting for slice 3. |
DDRSS_PHY_866 is shown in Figure 8-1356 and described in Table 8-2724.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D88h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_OE_TIMING_3 | PHY_DQ_TSEL_WR_TIMING_3 | ||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQ_TSEL_RD_TIMING_3 | PHY_DQ_OE_TIMING_3 | ||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DQS_OE_TIMING_3 | R/W | 0h | Start/end timing values for DQS output enable signals for slice 3. |
| 23-16 | PHY_DQ_TSEL_WR_TIMING_3 | R/W | 0h | Start/end timing values for DQ/DM write based termination enable and select signals for slice 3. |
| 15-8 | PHY_DQ_TSEL_RD_TIMING_3 | R/W | 0h | Start/end timing values for DQ/DM read based termination enable and select signals for slice 3. |
| 7-0 | PHY_DQ_OE_TIMING_3 | R/W | 0h | Start/end timing values for DQ/DM output enable signals for slice 3. |
DDRSS_PHY_867 is shown in Figure 8-1357 and described in Table 8-2726.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D8Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DQS_TSEL_WR_TIMING_3 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_OE_RD_TIMING_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQS_TSEL_RD_TIMING_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_IO_PAD_DELAY_TIMING_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DQS_TSEL_WR_TIMING_3 | R/W | 0h | Start/end timing values for DQS write based termination enable and select signals for slice 3. |
| 23-16 | PHY_DQS_OE_RD_TIMING_3 | R/W | 0h | Start/end timing values for DQS read based OE extension for slice 3. |
| 15-8 | PHY_DQS_TSEL_RD_TIMING_3 | R/W | 0h | Start/end timing values for DQS read based termination enable and select signals for slice 3. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_IO_PAD_DELAY_TIMING_3 | R/W | 0h | Feedback pad's OPAD and IPAD delay timing for slice 3. |
DDRSS_PHY_868 is shown in Figure 8-1358 and described in Table 8-2728.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D90h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_VREF_CTRL_DQ_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_VREF_SETTING_TIME_3 | |||||||||||||||
| R/W-0h | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-16 | PHY_PAD_VREF_CTRL_DQ_3 | R/W | 0h | Pad VREF control settings for DQ slice 3.
|
| 15-0 | PHY_VREF_SETTING_TIME_3 | R/W | 0h | Number of cycles for vref settle after setting is changed for slice 3. |
DDRSS_PHY_869 is shown in Figure 8-1359 and described in Table 8-2730.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D94h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDATA_EN_IE_DLY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_IE_TIMING_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_IE_TIMING_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PER_CS_TRAINING_EN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_RDDATA_EN_IE_DLY_3 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 3. |
| 23-16 | PHY_DQS_IE_TIMING_3 | R/W | 0h | Start/end timing values for DQS input enable signals for slice 3. |
| 15-8 | PHY_DQ_IE_TIMING_3 | R/W | 0h | Start/end timing values for DQ/DM input enable signals for slice 3. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_PER_CS_TRAINING_EN_3 | R/W | 0h | Enables the per-rank training and read/write timing capabilities for slice 3. |
DDRSS_PHY_870 is shown in Figure 8-1360 and described in Table 8-2732.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D98h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDATA_EN_OE_DLY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDATA_EN_TSEL_DLY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DBI_MODE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_IE_MODE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_RDDATA_EN_OE_DLY_3 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 3. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_RDDATA_EN_TSEL_DLY_3 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DBI_MODE_3 | R/W | 0h | DBI mode for slice 3. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_IE_MODE_3 | R/W | 0h | Input enable mode bits for slice 3. |
DDRSS_PHY_871 is shown in Figure 8-1361 and described in Table 8-2734.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4D9Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_MASTER_DELAY_STEP_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DELAY_START_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_MASTER_DELAY_START_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_MASTER_MODE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_MASTER_DELAY_STEP_3 | R/W | 0h | Incremental step size for master delay line locking algorithm for slice 3. |
| 23-19 | RESERVED | R/W | X | |
| 18-8 | PHY_MASTER_DELAY_START_3 | R/W | 0h | Start value for master delay line locking algorithm for slice 3. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_SW_MASTER_MODE_3 | R/W | 0h | Master delay line override settings for slice 3. |
DDRSS_PHY_872 is shown in Figure 8-1362 and described in Table 8-2736.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DA0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_WRLVL_DLY_STEP_3 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RPTR_UPDATE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_MASTER_DELAY_HALF_MEASURE_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_MASTER_DELAY_WAIT_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_WRLVL_DLY_STEP_3 | R/W | 0h | DQS slave delay step size during write leveling for slice 3. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_RPTR_UPDATE_3 | R/W | 0h | Offset in cycles from the dfi_rddata_en signal to release data from the entry FIFO for slice 3. |
| 15-8 | PHY_MASTER_DELAY_HALF_MEASURE_3 | R/W | 0h | Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle in the data slice master for slice 3. |
| 7-0 | PHY_MASTER_DELAY_WAIT_3 | R/W | 0h | Wait cycles for master delay line locking algorithm for slice 3. |
DDRSS_PHY_873 is shown in Figure 8-1363 and described in Table 8-2738.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DA4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GTLVL_RESP_WAIT_CNT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_DLY_STEP_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_RESP_WAIT_CNT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_DLY_FINE_STEP_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_GTLVL_RESP_WAIT_CNT_3 | R/W | 0h | Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 3. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GTLVL_DLY_STEP_3 | R/W | 0h | DQS slave delay step size during gate training for slice 3. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_WRLVL_RESP_WAIT_CNT_3 | R/W | 0h | Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 3. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_WRLVL_DLY_FINE_STEP_3 | R/W | 0h | DQS slave delay fine step size during write leveling for slice 3. |
DDRSS_PHY_874 is shown in Figure 8-1364 and described in Table 8-2740.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DA8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_FINAL_STEP_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GTLVL_BACK_STEP_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_GTLVL_FINAL_STEP_3 | R/W | 0h | Final backup step delay used in gate training algorithm for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_BACK_STEP_3 | R/W | 0h | Interim backup step delay used in gate training algorithm for slice 3. |
DDRSS_PHY_875 is shown in Figure 8-1365 and described in Table 8-2742.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_DLY_STEP_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TOGGLE_PRE_SUPPORT_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_QTR_DLY_STEP_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_DLY_STEP_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_RDLVL_DLY_STEP_3 | R/W | 0h | DQS slave delay step size during read leveling for slice 3. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_TOGGLE_PRE_SUPPORT_3 | R/W | 0h | Support the toggle read preamble for LPDDR4 for slice 3. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_WDQLVL_QTR_DLY_STEP_3 | R/W | 0h | Defines the step granularity for the logic to use once an edge is found for slice 3. |
| 7-0 | PHY_WDQLVL_DLY_STEP_3 | R/W | 0h | DQ slave delay step size during write data leveling for slice 3. |
DDRSS_PHY_876 is shown in Figure 8-1366 and described in Table 8-2744.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DB0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDLVL_MAX_EDGE_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_MAX_EDGE_3 | R/W | 0h | The maximun rdlvl slave delay search window for read eye training for slice 3. |
DDRSS_PHY_877 is shown in Figure 8-1367 and described in Table 8-2746.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DB4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDLVL_PER_START_OFFSET_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_RDLVL_DVW_MIN_EN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_DVW_MIN_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_DVW_MIN_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_RDLVL_PER_START_OFFSET_3 | R/W | 0h | Peridic training start point offset for slice 3. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_SW_RDLVL_DVW_MIN_EN_3 | R/W | 0h | SW override to enable use of PHY_RDLVL_DVW_MIN for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_DVW_MIN_3 | R/W | 0h | Minimum data valid window across DQs and ranks for slice 3. |
DDRSS_PHY_878 is shown in Figure 8-1368 and described in Table 8-2748.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DB8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DATA_DC_INIT_DISABLE_3 | ||||||
| R/W-X | R/W-3h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRPATH_GATE_TIMING_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRPATH_GATE_DISABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DATA_DC_INIT_DISABLE_3 | R/W | 3h | Disable duty cycle adjust at initialization for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_WRPATH_GATE_TIMING_3 | R/W | 0h | Write path clock gating timing for slice 3. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_WRPATH_GATE_DISABLE_3 | R/W | 0h | Write path clock gating disable for slice 3. |
DDRSS_PHY_879 is shown in Figure 8-1369 and described in Table 8-2750.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DBCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DATA_DC_DQ_INIT_SLV_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ_INIT_SLV_DELAY_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_DQS_INIT_SLV_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQS_INIT_SLV_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_DATA_DC_DQ_INIT_SLV_DELAY_3 | R/W | 0h | Initial value of write DQ slave delay for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_DATA_DC_DQS_INIT_SLV_DELAY_3 | R/W | 0h | Initial value of write DQS slave delay for slice 3. |
DDRSS_PHY_880 is shown in Figure 8-1370 and described in Table 8-2752.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DC0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DM_CLK_SE_THRSHLD_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_WDQLVL_ENABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_WRLVL_ENABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3 | R/W | 0h | Clock measurement cell threshold offset for differential signals for slice 3. |
| 23-16 | PHY_DATA_DC_DM_CLK_SE_THRSHLD_3 | R/W | 0h | Clock measurement cell threshold offset for single ended signals for slice 3. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_DATA_DC_WDQLVL_ENABLE_3 | R/W | 0h | Enable duty cycle adjust during write DQ training for slice 3. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_DATA_DC_WRLVL_ENABLE_3 | R/W | 0h | Enable duty cycle adjust during write leveling for slice 3. |
DDRSS_PHY_881 is shown in Figure 8-1371 and described in Table 8-2754.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DC4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDATA_EN_DLY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_MEAS_DLY_STEP_ENABLE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQ_OSC_DELTA_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | PHY_RDDATA_EN_DLY_3 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is early for slice 3. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_MEAS_DLY_STEP_ENABLE_3 | R/W | 0h | Data slice training step definition using phy_meas_dly_step_value for slice 3. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_WDQ_OSC_DELTA_3 | R/W | 0h | Slave delay offset that applies to a 1 bit change of dfi_wdq_osc_code for slice 3. |
DDRSS_PHY_882 is shown in Figure 8-1372 and described in Table 8-2756.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DC8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQ_DM_SWIZZLE0_3 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DQ_DM_SWIZZLE0_3 | R/W | 0h | DQ/DM bit swizzling 0 for slice 3. |
DDRSS_PHY_883 is shown in Figure 8-1373 and described in Table 8-2758.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DCCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DQ_DM_SWIZZLE1_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R/W | X | |
| 3-0 | PHY_DQ_DM_SWIZZLE1_3 | R/W | 0h | DQ/DM bit swizzling 1 for slice 3. |
DDRSS_PHY_884 is shown in Figure 8-1374 and described in Table 8-2760.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DD0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ1_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ0_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ1_SLAVE_DELAY_3 | R/W | 0h | Write clock slave delay setting for DQ1 for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ0_SLAVE_DELAY_3 | R/W | 0h | Write clock slave delay setting for DQ0 for slice 3. |
DDRSS_PHY_885 is shown in Figure 8-1375 and described in Table 8-2762.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DD4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ3_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ2_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ3_SLAVE_DELAY_3 | R/W | 0h | Write clock slave delay setting for DQ3 for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ2_SLAVE_DELAY_3 | R/W | 0h | Write clock slave delay setting for DQ2 for slice 3. |
DDRSS_PHY_886 is shown in Figure 8-1376 and described in Table 8-2764.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DD8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ5_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ4_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ5_SLAVE_DELAY_3 | R/W | 0h | Write clock slave delay setting for DQ5 for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ4_SLAVE_DELAY_3 | R/W | 0h | Write clock slave delay setting for DQ4 for slice 3. |
DDRSS_PHY_887 is shown in Figure 8-1377 and described in Table 8-2766.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DDCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQ7_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDQ6_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CLK_WRDQ7_SLAVE_DELAY_3 | R/W | 0h | Write clock slave delay setting for DQ7 for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDQ6_SLAVE_DELAY_3 | R/W | 0h | Write clock slave delay setting for DQ6 for slice 3. |
DDRSS_PHY_888 is shown in Figure 8-1378 and described in Table 8-2768.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DE0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_WRDQS_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_WRDM_SLAVE_DELAY_3 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_CLK_WRDQS_SLAVE_DELAY_3 | R/W | 0h | Write clock slave delay setting for DQS for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CLK_WRDM_SLAVE_DELAY_3 | R/W | 0h | Write clock slave delay setting for DM for slice 3. |
DDRSS_PHY_889 is shown in Figure 8-1379 and described in Table 8-2770.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DE4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_THRESHOLD_ADJUST_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-8 | PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3 | R/W | 0h | Rising edge read DQS slave delay setting for DQ0 for slice 3. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_WRLVL_THRESHOLD_ADJUST_3 | R/W | 0h | Write level threshold adjust value based on those thresholds for DQS for slice 3. |
DDRSS_PHY_890 is shown in Figure 8-1380 and described in Table 8-2772.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DE8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3 | R/W | 0h | Rising edge read DQS slave delay setting for DQ1 for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3 | R/W | 0h | Falling edge read DQS slave delay setting for DQ0 for slice 3. |
DDRSS_PHY_891 is shown in Figure 8-1381 and described in Table 8-2774.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3 | R/W | 0h | Rising edge read DQS slave delay setting for DQ2 for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3 | R/W | 0h | Falling edge read DQS slave delay setting for DQ1 for slice 3. |
DDRSS_PHY_892 is shown in Figure 8-1382 and described in Table 8-2776.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DF0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3 | R/W | 0h | Rising edge read DQS slave delay setting for DQ3 for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3 | R/W | 0h | Falling edge read DQS slave delay setting for DQ2 for slice 3. |
DDRSS_PHY_893 is shown in Figure 8-1383 and described in Table 8-2778.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DF4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3 | R/W | 0h | Rising edge read DQS slave delay setting for DQ4 for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3 | R/W | 0h | Falling edge read DQS slave delay setting for DQ3 for slice 3. |
DDRSS_PHY_894 is shown in Figure 8-1384 and described in Table 8-2780.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DF8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3 | R/W | 0h | Rising edge read DQS slave delay setting for DQ5 for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3 | R/W | 0h | Falling edge read DQS slave delay setting for DQ4 for slice 3. |
DDRSS_PHY_895 is shown in Figure 8-1385 and described in Table 8-2782.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4DFCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3 | R/W | 0h | Rising edge read DQS slave delay setting for DQ6 for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3 | R/W | 0h | Falling edge read DQS slave delay setting for DQ5 for slice 3. |
DDRSS_PHY_896 is shown in Figure 8-1386 and described in Table 8-2784.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E00h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3 | R/W | 0h | Rising edge read DQS slave delay setting for DQ7 for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3 | R/W | 0h | Falling edge read DQS slave delay setting for DQ6 for slice 3. |
DDRSS_PHY_897 is shown in Figure 8-1387 and described in Table 8-2786.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E04h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_DM_RISE_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_DM_RISE_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_DM_RISE_SLAVE_DELAY_3 | R/W | 0h | Rising edge read DQS slave delay setting for DM for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3 | R/W | 0h | Falling edge read DQS slave delay setting for DQ7 for slice 3. |
DDRSS_PHY_898 is shown in Figure 8-1388 and described in Table 8-2788.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E08h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQS_GATE_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDQS_GATE_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDQS_DM_FALL_SLAVE_DELAY_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDDQS_DM_FALL_SLAVE_DELAY_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_RDDQS_GATE_SLAVE_DELAY_3 | R/W | 0h | Read DQS slave delay setting for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDDQS_DM_FALL_SLAVE_DELAY_3 | R/W | 0h | Falling edge read DQS slave delay setting for DM for slice 3. |
DDRSS_PHY_899 is shown in Figure 8-1389 and described in Table 8-2790.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E0Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WRLVL_DELAY_EARLY_THRESHOLD_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_WRLVL_DELAY_EARLY_THRESHOLD_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRITE_PATH_LAT_ADD_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_RDDQS_LATENCY_ADJUST_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_WRLVL_DELAY_EARLY_THRESHOLD_3 | R/W | 0h | Write level delay threshold above which will be considered in previous cycle for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_WRITE_PATH_LAT_ADD_3 | R/W | 0h | Number of cycles to delay the incoming dfi_wrdata_en/dfi_wrdata signals for slice 3. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_RDDQS_LATENCY_ADJUST_3 | R/W | 0h | Number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 3. |
DDRSS_PHY_900 is shown in Figure 8-1390 and described in Table 8-2792.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E10h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_EARLY_FORCE_ZERO_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_WRLVL_EARLY_FORCE_ZERO_3 | R/W | 0h | Force the final write level delay value (that meets the early threshold) to 0 for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3 | R/W | 0h | Write level delay threshold below which will add a cycle of write path latency for slice 3. |
DDRSS_PHY_901 is shown in Figure 8-1391 and described in Table 8-2794.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E14h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_LAT_ADJ_START_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GTLVL_RDDQS_SLV_DLY_START_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GTLVL_RDDQS_SLV_DLY_START_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GTLVL_LAT_ADJ_START_3 | R/W | 0h | Initial read DQS gate cycle delay from dfi_rddata_en during gate training for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_GTLVL_RDDQS_SLV_DLY_START_3 | R/W | 0h | Initial read DQS gate slave delay setting during gate training for slice 3. |
DDRSS_PHY_902 is shown in Figure 8-1392 and described in Table 8-2796.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E18h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_NTP_PASS_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_NTP_WRLAT_START_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_DQDM_SLV_DLY_START_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_DQDM_SLV_DLY_START_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_NTP_PASS_3 | R/W | 0h | Indicates if No-topology training found a passing result for slice 3. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_NTP_WRLAT_START_3 | R/W | 0h | Initial value for phy_write_path_lat_add for No-topology training and early threshold for slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_WDQLVL_DQDM_SLV_DLY_START_3 | R/W | 0h | Initial DQ/DM slave delay setting during write data leveling for slice 3. |
DDRSS_PHY_903 is shown in Figure 8-1393 and described in Table 8-2798.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E1Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-10 | RESERVED | R/W | X | |
| 9-0 | PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3 | R/W | 0h | Read leveling starting value for the DQS/DQ slave delay settings for slice 3. |
DDRSS_PHY_904 is shown in Figure 8-1394 and described in Table 8-2800.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E20h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DQ2_CLK_ADJUST_3 | |||||||
| R/W-20h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ1_CLK_ADJUST_3 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DQ0_CLK_ADJUST_3 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQS_CLK_ADJUST_3 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DQ2_CLK_ADJUST_3 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 3. |
| 23-16 | PHY_DATA_DC_DQ1_CLK_ADJUST_3 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 3. |
| 15-8 | PHY_DATA_DC_DQ0_CLK_ADJUST_3 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 3. |
| 7-0 | PHY_DATA_DC_DQS_CLK_ADJUST_3 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 3. |
DDRSS_PHY_905 is shown in Figure 8-1395 and described in Table 8-2802.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E24h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DQ6_CLK_ADJUST_3 | |||||||
| R/W-20h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DQ5_CLK_ADJUST_3 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DQ4_CLK_ADJUST_3 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQ3_CLK_ADJUST_3 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_DATA_DC_DQ6_CLK_ADJUST_3 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 3. |
| 23-16 | PHY_DATA_DC_DQ5_CLK_ADJUST_3 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 3. |
| 15-8 | PHY_DATA_DC_DQ4_CLK_ADJUST_3 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 3. |
| 7-0 | PHY_DATA_DC_DQ3_CLK_ADJUST_3 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 3. |
DDRSS_PHY_906 is shown in Figure 8-1396 and described in Table 8-2804.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E28h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DSLICE_PAD_BOOSTPN_SETTING_3 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DSLICE_PAD_BOOSTPN_SETTING_3 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DATA_DC_DM_CLK_ADJUST_3 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_DC_DQ7_CLK_ADJUST_3 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | PHY_DSLICE_PAD_BOOSTPN_SETTING_3 | R/W | 0h | Setting for boost P/N of pad for slice 3. |
| 15-8 | PHY_DATA_DC_DM_CLK_ADJUST_3 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 3. |
| 7-0 | PHY_DATA_DC_DQ7_CLK_ADJUST_3 | R/W | 20h | Adjust value of Duty Cycle Adjuster for slice 3. |
DDRSS_PHY_907 is shown in Figure 8-1397 and described in Table 8-2806.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 4E2Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DQS_FFE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DQ_FFE_3 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DSLICE_PAD_RX_CTLE_SETTING_3 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DQS_FFE_3 | R/W | 0h | TX_FFE setting for DQS pad for slice 3. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_DQ_FFE_3 | R/W | 0h | TX_FFE setting for DQ/DM pad for slice 3. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DSLICE_PAD_RX_CTLE_SETTING_3 | R/W | 0h | Setting for RX ctle P/N of pad for slice 3. |
DDRSS_PHY_1024 is shown in Figure 8-1398 and described in Table 8-2808.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5000h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_ADR_MANUAL_CLEAR_0 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_CLK_BYPASS_OVERRIDE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | SC_PHY_ADR_MANUAL_CLEAR_0 | W | 0h | Manual reset/clear of internal logic for address slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_ADR_CLK_BYPASS_OVERRIDE_0 | R/W | 0h | Bypass mode override setting for address slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0 | R/W | 0h | Command/Address clock bypass mode slave delay setting for address slice 0. |
DDRSS_PHY_1025 is shown in Figure 8-1399 and described in Table 8-2810.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_LPBK_RESULT_OBS_0 | |||||||||||||||||||||||||||||||
| R-1000h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_ADR_LPBK_RESULT_OBS_0 | R | 1000h | Observation register containing loopback status/results for address slice 0. |
DDRSS_PHY_1026 is shown in Figure 8-1400 and described in Table 8-2812.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_ADR_MEAS_DLY_STEP_VALUE_0 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_ADR_LPBK_ERROR_COUNT_OBS_0 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_LPBK_ERROR_COUNT_OBS_0 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0 | R/W | 0h | Select value to map the internal master delay observation registers to the accessible master delay observation register for address slice 0. |
| 23-16 | PHY_ADR_MEAS_DLY_STEP_VALUE_0 | R | 0h | Contains the fraction of a cycle in 1 delay element numerator with demominator of 512, for address slice 0. |
| 15-0 | PHY_ADR_LPBK_ERROR_COUNT_OBS_0 | R | 0h | Observation register containing total number of loopback error data for address slice 0. |
DDRSS_PHY_1027 is shown in Figure 8-1401 and described in Table 8-2814.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 500Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0 | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_BASE_SLV_DLY_ENC_OBS_0 | ||||||
| R-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_MASTER_DLY_LOCK_OBS_0 | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_MASTER_DLY_LOCK_OBS_0 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing addr slave delay for address slice 0. |
| 23 | RESERVED | R | X | |
| 22-16 | PHY_ADR_BASE_SLV_DLY_ENC_OBS_0 | R | 0h | Observation register containing base slave delay for address slice 0. |
| 15-11 | RESERVED | R | X | |
| 10-0 | PHY_ADR_MASTER_DLY_LOCK_OBS_0 | R | 0h | Observation register containing master delay results for address slice 0. |
DDRSS_PHY_1028 is shown in Figure 8-1402 and described in Table 8-2816.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_TSEL_ENABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_ADR_SNAP_OBS_REGS_0 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_ADR_TSEL_ENABLE_0 | R/W | 0h | Enables tsel_en for address slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | SC_PHY_ADR_SNAP_OBS_REGS_0 | W | 0h | Initiates a snapshot of the internal observation registers for address slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0 | R/W | 0h | Select value to map the addr bits delay observation registers to the accessible delay observation register for address slice 0. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0 | R/W | 0h | Reserved for address slice 0. |
DDRSS_PHY_1029 is shown in Figure 8-1403 and described in Table 8-2818.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_PWR_RDC_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_PRBS_PATTERN_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_PRBS_PATTERN_START_0 | ||||||
| R/W-X | R/W-1h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_LPBK_CONTROL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_ADR_PWR_RDC_DISABLE_0 | R/W | 0h | Power reduction disable for address slice 0. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_ADR_PRBS_PATTERN_MASK_0 | R/W | 0h | PRBS7 mask signal for address slice 0. |
| 15 | RESERVED | R/W | X | |
| 14-8 | PHY_ADR_PRBS_PATTERN_START_0 | R/W | 1h | PRBS7 start pattern for address slice 0. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_ADR_LPBK_CONTROL_0 | R/W | 0h | Loopback control bits for address slice 0. |
DDRSS_PHY_1030 is shown in Figure 8-1404 and described in Table 8-2820.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5018h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_IE_MODE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_WRADDR_SHIFT_OBS_0 | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_TYPE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_ADR_IE_MODE_0 | R/W | 0h | Input enable control for address slice 0. |
| 23-19 | RESERVED | R/W | X | |
| 18-16 | PHY_ADR_WRADDR_SHIFT_OBS_0 | R | 0h | Observation register containing automatic half cycle and cycle shift values for address slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-8 | PHY_ADR_TYPE_0 | R/W | 0h | DRAM type for address slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0 | R/W | 0h | Power reduction slv_dly_control block gate disable for address slice 0. |
DDRSS_PHY_1031 is shown in Figure 8-1405 and described in Table 8-2822.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 501Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_DDL_MODE_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-0 | PHY_ADR_DDL_MODE_0 | R/W | 0h | DDL mode for address slice 0. |
DDRSS_PHY_1032 is shown in Figure 8-1406 and described in Table 8-2824.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5020h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_DDL_MASK_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-6 | RESERVED | R/W | X | |
| 5-0 | PHY_ADR_DDL_MASK_0 | R/W | 0h | DDL mask for address slice 0. |
DDRSS_PHY_1033 is shown in Figure 8-1407 and described in Table 8-2826.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5024h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_DDL_TEST_OBS_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_ADR_DDL_TEST_OBS_0 | R | 0h | Observation register containing DDL test bits for address slice 0. |
DDRSS_PHY_1034 is shown in Figure 8-1408 and described in Table 8-2828.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5028h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0 | R | 0h | Observation register containing master DDL bits for address slice 0. |
DDRSS_PHY_1035 is shown in Figure 8-1409 and described in Table 8-2830.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 502Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_CALVL_COARSE_DLY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_START_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_ADR_CALVL_COARSE_DLY_0 | R/W | 0h | Coarse CA training DDL increment value for address slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_ADR_CALVL_START_0 | R/W | 0h | CA training DDL start value for address slice 0. |
DDRSS_PHY_1036 is shown in Figure 8-1410 and described in Table 8-2832.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_QTR_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-11 | RESERVED | R/W | X | |
| 10-0 | PHY_ADR_CALVL_QTR_0 | R/W | 0h | CA training DDL quarter cycle delay value for address slice 0. |
DDRSS_PHY_1037 is shown in Figure 8-1411 and described in Table 8-2834.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5034h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_SWIZZLE0_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | X | |
| 23-0 | PHY_ADR_CALVL_SWIZZLE0_0 | R/W | 0h | CA training RD DQ bit swizzle map 0 for address slice 0. |
DDRSS_PHY_1038 is shown in Figure 8-1412 and described in Table 8-2836.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5038h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_CALVL_RANK_CTRL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_ADR_CALVL_SWIZZLE1_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_ADR_CALVL_SWIZZLE1_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_CALVL_SWIZZLE1_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_ADR_CALVL_RANK_CTRL_0 | R/W | 0h | CA training rank aggregation control bits for address slice 0. |
| 23-0 | PHY_ADR_CALVL_SWIZZLE1_0 | R/W | 0h | CA training RD DQ bit swizzle map 1 for address slice 0. |
DDRSS_PHY_1039 is shown in Figure 8-1413 and described in Table 8-2838.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 503Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_CALVL_PERIODIC_START_OFFSET_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_ADR_CALVL_PERIODIC_START_OFFSET_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_CALVL_RESP_WAIT_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_NUM_PATTERNS_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_ADR_CALVL_PERIODIC_START_OFFSET_0 | R/W | 0h | Relative offset to start periodic CALVL from previous result |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_ADR_CALVL_RESP_WAIT_CNT_0 | R/W | 0h | Number of samples to wait before sampling response during CA training for address slice 0. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_ADR_CALVL_NUM_PATTERNS_0 | R/W | 0h | Number of patterns to use during CA training for address slice 0. |
DDRSS_PHY_1040 is shown in Figure 8-1414 and described in Table 8-2840.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_CALVL_OBS_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_ADR_CALVL_ERROR_CLR_0 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_ADR_CALVL_DEBUG_CONT_0 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_DEBUG_MODE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_ADR_CALVL_OBS_SELECT_0 | R/W | 0h | CA bit lane to observe result from OBS0 during CA training for address slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | SC_PHY_ADR_CALVL_ERROR_CLR_0 | W | 0h | Clears the CA training state machine error status for address slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8 | SC_PHY_ADR_CALVL_DEBUG_CONT_0 | W | 0h | Allows the CA training state machine to advance (when in debug mode) for address slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_ADR_CALVL_DEBUG_MODE_0 | R/W | 0h | Enables CA training debug mode for address slice 0. |
DDRSS_PHY_1041 is shown in Figure 8-1415 and described in Table 8-2842.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5044h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_CALVL_CH0_OBS0_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_ADR_CALVL_CH0_OBS0_0 | R | 0h | Observation register for CA training for channel 0 slice 0. |
DDRSS_PHY_1042 is shown in Figure 8-1416 and described in Table 8-2844.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5048h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_CALVL_CH1_OBS0_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_ADR_CALVL_CH1_OBS0_0 | R | 0h | Observation register for CA training for channel 1 slice 0. |
DDRSS_PHY_1043 is shown in Figure 8-1417 and described in Table 8-2846.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 504Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_CALVL_OBS1_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_ADR_CALVL_OBS1_0 | R | 0h | Observation register contains general CA training bits for slice 0. |
DDRSS_PHY_1044 is shown in Figure 8-1418 and described in Table 8-2848.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5050h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_CALVL_OBS2_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_ADR_CALVL_OBS2_0 | R | 0h | Observation register contains periodic CA training bits for slice 0. |
DDRSS_PHY_1045 is shown in Figure 8-1419 and described in Table 8-2850.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5054h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_FG_0_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_ADR_CALVL_FG_0_0 | R/W | 0h | CA training foreground pattern 0 for address slice 0. |
DDRSS_PHY_1046 is shown in Figure 8-1420 and described in Table 8-2852.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5058h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_BG_0_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_ADR_CALVL_BG_0_0 | R/W | 0h | CA training background pattern 0 for address slice 0. |
DDRSS_PHY_1047 is shown in Figure 8-1421 and described in Table 8-2854.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 505Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_FG_1_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_ADR_CALVL_FG_1_0 | R/W | 0h | CA training foreground pattern 1 for address slice 0. |
DDRSS_PHY_1048 is shown in Figure 8-1422 and described in Table 8-2856.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5060h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_BG_1_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_ADR_CALVL_BG_1_0 | R/W | 0h | CA training background pattern 1 for address slice 0. |
DDRSS_PHY_1049 is shown in Figure 8-1423 and described in Table 8-2858.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5064h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_FG_2_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_ADR_CALVL_FG_2_0 | R/W | 0h | CA training foreground pattern 2 for address slice 0. |
DDRSS_PHY_1050 is shown in Figure 8-1424 and described in Table 8-2860.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5068h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_BG_2_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_ADR_CALVL_BG_2_0 | R/W | 0h | CA training background pattern 2 for address slice 0. |
DDRSS_PHY_1051 is shown in Figure 8-1425 and described in Table 8-2862.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 506Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_FG_3_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_ADR_CALVL_FG_3_0 | R/W | 0h | CA training foreground pattern 3 for address slice 0. |
DDRSS_PHY_1052 is shown in Figure 8-1426 and described in Table 8-2864.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5070h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_BG_3_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_ADR_CALVL_BG_3_0 | R/W | 0h | CA training background pattern 3 for address slice 0. |
DDRSS_PHY_1053 is shown in Figure 8-1427 and described in Table 8-2866.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5074h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_ADDR_SEL_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R/W | X | |
| 23-0 | PHY_ADR_ADDR_SEL_0 | R/W | 0h | Selects which DFI address pins connect to which CA pins for LPDDR3/4 for address slice 0. |
DDRSS_PHY_1054 is shown in Figure 8-1428 and described in Table 8-2868.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5078h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_SEG_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_BIT_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_LP4_BOOT_SLV_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_LP4_BOOT_SLV_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_ADR_SEG_MASK_0 | R/W | 0h | Segment mask bit for address slice 0. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_ADR_BIT_MASK_0 | R/W | 0h | Mask bit for address slice 0. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_ADR_LP4_BOOT_SLV_DELAY_0 | R/W | 0h | Address slave delay setting during the LPDDR4 boot frequency operation for address slice 0. |
DDRSS_PHY_1055 is shown in Figure 8-1429 and described in Table 8-2870.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 507Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_SW_TXIO_CTRL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_STATIC_TOG_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_CSLVL_TRAIN_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_TRAIN_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_ADR_SW_TXIO_CTRL_0 | R/W | 0h | Controls address pad output enable for address slice 0. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_ADR_STATIC_TOG_DISABLE_0 | R/W | 0h | Toggle control during static activity for address slice 0. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_ADR_CSLVL_TRAIN_MASK_0 | R/W | 0h | Mask bit for CS training participation for address slice 0. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_ADR_CALVL_TRAIN_MASK_0 | R/W | 0h | Mask bit for CA training participation for address slice 0. |
DDRSS_PHY_1056 is shown in Figure 8-1430 and described in Table 8-2872.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5080h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_ADR_DC_ADR2_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_ADR_DC_ADR1_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_ADR_DC_ADR0_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_DC_INIT_DISABLE_0 | ||||||
| R/W-X | R/W-3h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_ADR_DC_ADR2_CLK_ADJUST_0 | R/W | 20h | Adjust value of Clock Duty Cycle Adjuster lane 2 for address slice 0. |
| 23-16 | PHY_ADR_DC_ADR1_CLK_ADJUST_0 | R/W | 20h | Adjust value of Clock Duty Cycle Adjuster lane 1 for address slice 0. |
| 15-8 | PHY_ADR_DC_ADR0_CLK_ADJUST_0 | R/W | 20h | Adjust value of Clock Duty Cycle Adjuster lane 0 for address slice 0. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_ADR_DC_INIT_DISABLE_0 | R/W | 3h | Duty Cycle Corrector disable at initialization for address slice 0. |
DDRSS_PHY_1057 is shown in Figure 8-1431 and described in Table 8-2874.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5084h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_ADR_DC_ADR5_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_ADR_DC_ADR4_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_DC_ADR3_CLK_ADJUST_0 | |||||||
| R/W-20h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0 | R/W | 0h | DCC and RX_CAL clk gate disable for address slice 0. |
| 23-16 | PHY_ADR_DC_ADR5_CLK_ADJUST_0 | R/W | 20h | Adjust value of Clock Duty Cycle Adjuster lane 5 for address slice 0. |
| 15-8 | PHY_ADR_DC_ADR4_CLK_ADJUST_0 | R/W | 20h | Adjust value of Clock Duty Cycle Adjuster lane 4 for address slice 0. |
| 7-0 | PHY_ADR_DC_ADR3_CLK_ADJUST_0 | R/W | 20h | Adjust value of Clock Duty Cycle Adjuster lane 3 for address slice 0. |
DDRSS_PHY_1058 is shown in Figure 8-1432 and described in Table 8-2876.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5088h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_DC_ADJUST_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_DC_WEIGHT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_ADR_DC_CAL_TIMEOUT_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_DC_CAL_SAMPLE_WAIT_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_ADR_DC_ADJUST_START_0 | R/W | 0h | DCC calibration starting value for address slice 0. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_ADR_DC_WEIGHT_0 | R/W | 0h | DCC weighting factor base value for address slice 0. |
| 15-8 | PHY_ADR_DC_CAL_TIMEOUT_0 | R/W | 0h | DCC number of iterations to wait before timeout for address slice 0. |
| 7-0 | PHY_ADR_DC_CAL_SAMPLE_WAIT_0 | R/W | 0h | DCC cycles to wait after calibration change before sampling results for address slice 0. |
DDRSS_PHY_1059 is shown in Figure 8-1433 and described in Table 8-2878.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 508Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_DC_CAL_POLARITY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_DC_ADJUST_DIRECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_ADR_DC_ADJUST_THRSHLD_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_DC_ADJUST_SAMPLE_CNT_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_ADR_DC_CAL_POLARITY_0 | R/W | 0h | DCC calibration polarity for address slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_ADR_DC_ADJUST_DIRECT_0 | R/W | 0h | DCC adjust direction for address slice 0. |
| 15-8 | PHY_ADR_DC_ADJUST_THRSHLD_0 | R/W | 0h | DCC adjust threshold around the mid-point for address slice 0. |
| 7-0 | PHY_ADR_DC_ADJUST_SAMPLE_CNT_0 | R/W | 0h | DCC number of samples to take for address slice 0. |
DDRSS_PHY_1060 is shown in Figure 8-1434 and described in Table 8-2880.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5090h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PARITY_ERROR_REGIF_ADR_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_PARITY_ERROR_REGIF_ADR_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_SW_TXPWR_CTRL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_DC_CAL_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_PARITY_ERROR_REGIF_ADR_0 | R/W | 0h | Inject parity error to register interface signals for address slice 0. |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_ADR_SW_TXPWR_CTRL_0 | R/W | 0h | Disable address output enables in deep sleep mode for address slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_ADR_DC_CAL_START_0 | R/W | 0h | DCC Manual trigger for address slice 0. |
DDRSS_PHY_1061 is shown in Figure 8-1435 and described in Table 8-2882.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5094h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_AS_FSM_ERROR_INFO_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_AS_FSM_ERROR_INFO_MASK_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_AS_FSM_ERROR_INFO_0 | ||||||
| R/W-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_AS_FSM_ERROR_INFO_0 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | PHY_AS_FSM_ERROR_INFO_MASK_0 | R/W | 0h | FSM Error Info Mask for address slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_AS_FSM_ERROR_INFO_0 | R | 0h | FSM Error Info for address slice 0. |
DDRSS_PHY_1062 is shown in Figure 8-1436 and described in Table 8-2884.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5098h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_AS_TRAIN_CALIB_ERROR_INFO_0 | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0 | |||||||
| W-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0 | R/W | 0h | Training/Calibration Error Info Mask for address slice 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_AS_TRAIN_CALIB_ERROR_INFO_0 | R | 0h | Training/Calibration Error Info for address slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0 | W | 0h | FSM Error Info clear for address slice 0. |
DDRSS_PHY_1063 is shown in Figure 8-1437 and described in Table 8-2886.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 509Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0 | ||||||
| W-X | W-0h | ||||||
| LEGEND: W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | W | X | |
| 0 | SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0 | W | 0h | Training/Calibration Error Info clear for address slice 0. |
DDRSS_PHY_1064 is shown in Figure 8-1438 and described in Table 8-2888.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PAD_ADR_IO_CFG_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_PAD_ADR_IO_CFG_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_DC_CAL_CLK_SEL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_TSEL_SELECT_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_PAD_ADR_IO_CFG_0 | R/W | 0h | Controls I/O pads for address pad for address slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_ADR_DC_CAL_CLK_SEL_0 | R/W | 0h | DCC CAL clock for address slice 0. |
| 7-0 | PHY_ADR_TSEL_SELECT_0 | R/W | 0h | Tsel select values for address slice 0. |
DDRSS_PHY_1065 is shown in Figure 8-1439 and described in Table 8-2890.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR1_SW_WRADDR_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR0_CLK_WR_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_ADR0_CLK_WR_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR0_SW_WRADDR_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_ADR1_SW_WRADDR_SHIFT_0 | R/W | 0h | Manual override of CA bit 1 of automatic half_cycle_shift/cycle_shift for address slice 0. |
| 23-19 | RESERVED | R/W | X | |
| 18-8 | PHY_ADR0_CLK_WR_SLAVE_DELAY_0 | R/W | 0h | CA bit 0 slave delay setting for address slice 0. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_ADR0_SW_WRADDR_SHIFT_0 | R/W | 0h | Manual override of CA bit 0 of automatic half_cycle_shift/cycle_shift for address slice 0. |
DDRSS_PHY_1066 is shown in Figure 8-1440 and described in Table 8-2892.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50A8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR2_SW_WRADDR_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR1_CLK_WR_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR1_CLK_WR_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | PHY_ADR2_SW_WRADDR_SHIFT_0 | R/W | 0h | Manual override of CA bit 2 of automatic half_cycle_shift/cycle_shift for address slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_ADR1_CLK_WR_SLAVE_DELAY_0 | R/W | 0h | CA bit 1 slave delay setting for address slice 0. |
DDRSS_PHY_1067 is shown in Figure 8-1441 and described in Table 8-2894.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50ACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR3_SW_WRADDR_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR2_CLK_WR_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR2_CLK_WR_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | PHY_ADR3_SW_WRADDR_SHIFT_0 | R/W | 0h | Manual override of CA bit 3 of automatic half_cycle_shift/cycle_shift for address slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_ADR2_CLK_WR_SLAVE_DELAY_0 | R/W | 0h | CA bit 2 slave delay setting for address slice 0. |
DDRSS_PHY_1068 is shown in Figure 8-1442 and described in Table 8-2896.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50B0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR4_SW_WRADDR_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR3_CLK_WR_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR3_CLK_WR_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | PHY_ADR4_SW_WRADDR_SHIFT_0 | R/W | 0h | Manual override of CA bit 4 of automatic half_cycle_shift/cycle_shift for address slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_ADR3_CLK_WR_SLAVE_DELAY_0 | R/W | 0h | CA bit 3 slave delay setting for address slice 0. |
DDRSS_PHY_1069 is shown in Figure 8-1443 and described in Table 8-2898.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR5_SW_WRADDR_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR4_CLK_WR_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR4_CLK_WR_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | PHY_ADR5_SW_WRADDR_SHIFT_0 | R/W | 0h | Manual override of CA bit 5 of automatic half_cycle_shift/cycle_shift for address slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_ADR4_CLK_WR_SLAVE_DELAY_0 | R/W | 0h | CA bit 4 slave delay setting for address slice 0. |
DDRSS_PHY_1070 is shown in Figure 8-1444 and described in Table 8-2900.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_SW_MASTER_MODE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR5_CLK_WR_SLAVE_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR5_CLK_WR_SLAVE_DELAY_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-16 | PHY_ADR_SW_MASTER_MODE_0 | R/W | 0h | Master delay line override settings for address slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_ADR5_CLK_WR_SLAVE_DELAY_0 | R/W | 0h | CA bit 5 slave delay setting for address slice 0. |
DDRSS_PHY_1071 is shown in Figure 8-1445 and described in Table 8-2902.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_ADR_MASTER_DELAY_WAIT_0 | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_MASTER_DELAY_STEP_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_MASTER_DELAY_START_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_MASTER_DELAY_START_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_ADR_MASTER_DELAY_WAIT_0 | R/W | 0h | Wait cycles for master delay line locking algorithm for address slice 0. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_ADR_MASTER_DELAY_STEP_0 | R/W | 0h | Incremental step size for master delay line locking algorithm for address slice 0. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_ADR_MASTER_DELAY_START_0 | R/W | 0h | Start value for master delay line locking algorithm for address slice 0. |
DDRSS_PHY_1072 is shown in Figure 8-1446 and described in Table 8-2904.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_SW_CALVL_DVW_MIN_EN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADR_SW_CALVL_DVW_MIN_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_ADR_SW_CALVL_DVW_MIN_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_ADR_SW_CALVL_DVW_MIN_EN_0 | R/W | 0h | Enables the software override data valid window size during CA training for address slice 0. |
| 23-18 | RESERVED | R/W | X | |
| 17-8 | PHY_ADR_SW_CALVL_DVW_MIN_0 | R/W | 0h | Sets the software override data valid window size during CA training for address slice 0. |
| 7-0 | PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 | R/W | 0h | Defines the number of delay line elements to be considered in determing whether to lock to a half clock cycle for the master in address slice 0 |
DDRSS_PHY_1073 is shown in Figure 8-1447 and described in Table 8-2906.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50C4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_DLY_STEP_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-4 | RESERVED | R/W | X | |
| 3-0 | PHY_ADR_CALVL_DLY_STEP_0 | R/W | 0h | Sets the delay step size plus 1 during CA training for address slice 0. |
DDRSS_PHY_1074 is shown in Figure 8-1448 and described in Table 8-2908.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50C8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADR_DC_INIT_SLV_DELAY_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_ADR_DC_INIT_SLV_DELAY_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADR_MEAS_DLY_STEP_ENABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_CALVL_CAPTURE_CNT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_ADR_DC_INIT_SLV_DELAY_0 | R/W | 0h | DCC initialization value of write ADDR slave delay for address slice 0. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_ADR_MEAS_DLY_STEP_ENABLE_0 | R/W | 0h | Enables delay parameter setting using phy_adr_meas_dly_step_value for address slice 0. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_ADR_CALVL_CAPTURE_CNT_0 | R/W | 0h | Number of samples to take at each ADDR slave delay setting during CA training for address slice 0. |
DDRSS_PHY_1075 is shown in Figure 8-1449 and described in Table 8-2910.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 50CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_ADR_DC_DM_CLK_THRSHLD_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADR_DC_CALVL_ENABLE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R/W | X | |
| 15-8 | PHY_ADR_DC_DM_CLK_THRSHLD_0 | R/W | 0h | DCC clock measurement cell threshold offset for address slice 0. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_ADR_DC_CALVL_ENABLE_0 | R/W | 0h | DCC enable duty cycle adjust during CA leveling for address slice 0. |
DDRSS_PHY_1280 is shown in Figure 8-1450 and described in Table 8-2912.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5400h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_FREQ_SEL | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R/W | X | |
| 1-0 | PHY_FREQ_SEL | R/W | 0h | Specifies which copy of the frequency-dependent timing parameters will be used by the PHY. |
DDRSS_PHY_1281 is shown in Figure 8-1451 and described in Table 8-2914.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5404h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_GRP0_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_FREQ_SEL_INDEX | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_FREQ_SEL_MULTICAST_EN | ||||||
| R/W-X | R/W-1h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_FREQ_SEL_FROM_REGIF | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_SW_GRP0_SHIFT_0 | R/W | 0h | Address slice slave delay setting for address slice 4. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_FREQ_SEL_INDEX | R/W | 0h | Selects which frequency set to update when PHY_FREQ_SEL_MULTICAST_EN is not set. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_FREQ_SEL_MULTICAST_EN | R/W | 1h | When set, a register write will update parameters for all frequency sets simultaneously. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_FREQ_SEL_FROM_REGIF | R/W | 0h | Indicates which source is used to select the frequency copy. |
DDRSS_PHY_1282 is shown in Figure 8-1452 and described in Table 8-2916.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5408h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_GRP0_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_GRP3_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_GRP2_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_GRP1_SHIFT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_SW_GRP0_SHIFT_1 | R/W | 0h | Address slice slave delay setting for address slice 4. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_SW_GRP3_SHIFT_0 | R/W | 0h | Address slice slave delay setting for address slice 4. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_SW_GRP2_SHIFT_0 | R/W | 0h | Address slice slave delay setting for address slice 4. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_SW_GRP1_SHIFT_0 | R/W | 0h | Address slice slave delay setting for address slice 4. |
DDRSS_PHY_1283 is shown in Figure 8-1453 and described in Table 8-2918.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 540Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_GRP3_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_GRP2_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_GRP1_SHIFT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | PHY_SW_GRP3_SHIFT_1 | R/W | 0h | Address slice slave delay setting for address slice 4. |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_SW_GRP2_SHIFT_1 | R/W | 0h | Address slice slave delay setting for address slice 4. |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_SW_GRP1_SHIFT_1 | R/W | 0h | Address slice slave delay setting for address slice 4. |
DDRSS_PHY_1284 is shown in Figure 8-1454 and described in Table 8-2920.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5410h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GRP_BYPASS_OVERRIDE | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_GRP_BYPASS_SHIFT | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GRP_BYPASS_SLAVE_DELAY | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GRP_BYPASS_SLAVE_DELAY | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_GRP_BYPASS_OVERRIDE | R/W | 0h | Address/control group slice bypass mode override setting. |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_SW_GRP_BYPASS_SHIFT | R/W | 0h | Address/control group slice bypass mode shift settings. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_GRP_BYPASS_SLAVE_DELAY | R/W | 0h | Address/control group slice bypass mode slave delay setting. |
DDRSS_PHY_1285 is shown in Figure 8-1455 and described in Table 8-2922.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5414h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CSLVL_START | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_CSLVL_START | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_MANUAL_UPDATE_PHYUPD_ENABLE | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SC_PHY_MANUAL_UPDATE | ||||||
| R/W-X | W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_CSLVL_START | R/W | 0h | Defines the CS training DDL start value. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_MANUAL_UPDATE_PHYUPD_ENABLE | R/W | 0h | Manual update selection of all slave delay line settings. |
| 7-1 | RESERVED | R/W | X | |
| 0 | SC_PHY_MANUAL_UPDATE | W | 0h | Manual update of all slave delay line settings. |
DDRSS_PHY_1286 is shown in Figure 8-1456 and described in Table 8-2924.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5418h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_CSLVL_DEBUG_CONT | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CSLVL_DEBUG_MODE | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CSLVL_COARSE_DLY | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CSLVL_COARSE_DLY | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | SC_PHY_CSLVL_DEBUG_CONT | W | 0h | Allows the CS training state machine to advance (when in debug mode). |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_CSLVL_DEBUG_MODE | R/W | 0h | Enables CS training debug mode. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CSLVL_COARSE_DLY | R/W | 0h | Defines the CS training DDL coarse cycle delay value. |
DDRSS_PHY_1287 is shown in Figure 8-1457 and described in Table 8-2926.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 541Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SC_PHY_CSLVL_ERROR_CLR | ||||||
| W-X | W-0h | ||||||
| LEGEND: W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | W | X | |
| 0 | SC_PHY_CSLVL_ERROR_CLR | W | 0h | Clears the CS training state machine error status. |
DDRSS_PHY_1288 is shown in Figure 8-1458 and described in Table 8-2928.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5420h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CSLVL_OBS0 | |||||||||||||||||||||||||||||||
| R-06800000h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_CSLVL_OBS0 | R | 06800000h | Observation register for CS training delay values. |
DDRSS_PHY_1289 is shown in Figure 8-1459 and described in Table 8-2930.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5424h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CSLVL_OBS1 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_CSLVL_OBS1 | R | 0h | Observation register for CS training algorithm status. |
DDRSS_PHY_1290 is shown in Figure 8-1460 and described in Table 8-2932.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5428h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CSLVL_OBS2 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_CSLVL_OBS2 | R | 0h | Observation register for periodic CS training delay values. |
DDRSS_PHY_1291 is shown in Figure 8-1461 and described in Table 8-2934.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 542Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_DISABLE | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CSLVL_PERIODIC_START_OFFSET | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_CSLVL_PERIODIC_START_OFFSET | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CSLVL_ENABLE | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_LP4_BOOT_DISABLE | R/W | 0h | Controls the handling of the DFI frequency. |
| 23-17 | RESERVED | R/W | X | |
| 16-8 | PHY_CSLVL_PERIODIC_START_OFFSET | R/W | 0h | Defines the relative offset from previous LE and TE to start periodic CSLVL with. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_CSLVL_ENABLE | R/W | 0h | CS training enable. |
DDRSS_PHY_1292 is shown in Figure 8-1462 and described in Table 8-2936.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5430h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CSLVL_QTR | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_CSLVL_QTR | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CSLVL_CS_MAP | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R/W | X | |
| 18-8 | PHY_CSLVL_QTR | R/W | 0h | Defines the CS training DDL 1/4 cycle delay value. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_CSLVL_CS_MAP | R/W | 0h | CS training map. |
DDRSS_PHY_1293 is shown in Figure 8-1463 and described in Table 8-2938.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5434h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_CALVL_CS_MAP | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CSLVL_COARSE_CAPTURE_CNT | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CSLVL_COARSE_CHK | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CSLVL_COARSE_CHK | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_CALVL_CS_MAP | R/W | 0h | Defines the slice numbers associated with each CS during CA training. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_CSLVL_COARSE_CAPTURE_CNT | R/W | 0h | Defines the number of samples to take at each GRP slave delay setting during CS training coarse CA training. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_CSLVL_COARSE_CHK | R/W | 0h | Defines the CS training coarse CA training DDL 1/16th cycle delay value. |
DDRSS_PHY_1294 is shown in Figure 8-1464 and described in Table 8-2940.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5438h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADRCTL_LPDDR | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_DFI_PHYUPD_TYPE | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADRCTL_SNAP_OBS_REGS | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_ADRCTL_LPDDR | R/W | 0h | Adds a cycle of delay for the address/control slices to match the address slice. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_DFI_PHYUPD_TYPE | R/W | 0h | Defines the value of the dfi_phyupd_type output signal to MC. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_ADRCTL_SNAP_OBS_REGS | W | 0h | Initiates a snapshot of the internal observation registers for the address/control block. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE | R/W | 0h | Reserved for the address/control master. |
DDRSS_PHY_1295 is shown in Figure 8-1465 and described in Table 8-2942.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 543Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_CLK_DC_CAL_TIMEOUT | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_CLK_DC_CAL_SAMPLE_WAIT | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LPDDR3_CS | ||||||
| R/W-X | R/W-1h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LP4_ACTIVE | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_CLK_DC_CAL_TIMEOUT | R/W | 0h | Duty cycle correction maximum iteration count. |
| 23-16 | PHY_CLK_DC_CAL_SAMPLE_WAIT | R/W | 0h | Number of cal clock cycles to wait for a sample to be taken. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_LPDDR3_CS | R/W | 1h | Alters reset state polarity for LPDDR chip selects. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_LP4_ACTIVE | R/W | 0h | Indicates an LPDDR4 device is connected to the PHY. |
DDRSS_PHY_1296 is shown in Figure 8-1466 and described in Table 8-2944.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5440h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_CLK_DC_ADJUST_SAMPLE_CNT | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_DC_ADJUST_START | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CLK_DC_FREQ_CHG_ADJ | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_DC_WEIGHT | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | PHY_CLK_DC_ADJUST_SAMPLE_CNT | R/W | 0h | Duty cycle correction algorithm sample count per adjustment setting. |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_CLK_DC_ADJUST_START | R/W | 0h | Duty cycle correction algorithm adjustment starting value. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_CLK_DC_FREQ_CHG_ADJ | R/W | 0h | Duty cycle correction during frequency change control. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_CLK_DC_WEIGHT | R/W | 0h | Duty cycle correction weighting factor base value. |
DDRSS_PHY_1297 is shown in Figure 8-1467 and described in Table 8-2946.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5444h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CLK_DC_CAL_START | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CLK_DC_CAL_POLARITY | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CLK_DC_ADJUST_DIRECT | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CLK_DC_ADJUST_THRSHLD | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_CLK_DC_CAL_START | R/W | 0h | Duty cycle correction calibration manual start. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_CLK_DC_CAL_POLARITY | R/W | 0h | Duty cycle correction algorithm measurement polarity. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_CLK_DC_ADJUST_DIRECT | R/W | 0h | Duty cycle correction algorithm adjustment direction. |
| 7-0 | PHY_CLK_DC_ADJUST_THRSHLD | R/W | 0h | Duty cycle correction algorithm threshold delta comparison. |
DDRSS_PHY_1298 is shown in Figure 8-1468 and described in Table 8-2948.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5448h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_TXIO_CTRL_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_TXIO_CTRL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CONTINUOUS_CLK_CAL_UPDATE | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SC_PHY_UPDATE_CLK_CAL_VALUES | ||||||
| R/W-X | W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_SW_TXIO_CTRL_1 | R/W | 0h | This register is used to control if command pad (CS/RAS...) should be shutoff for TX mode. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_SW_TXIO_CTRL_0 | R/W | 0h | This register is used to control if command pad (CS/RAS...) should be shutoff for TX mode. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_CONTINUOUS_CLK_CAL_UPDATE | R/W | 0h | Continuous update of all latest PVTP,PVTN and PVTR values to the CLK IO pads. |
| 7-1 | RESERVED | R/W | X | |
| 0 | SC_PHY_UPDATE_CLK_CAL_VALUES | W | 0h | Manual update of all latest PVTP,PVTN and PVTR values to the CLK IO pads. |
DDRSS_PHY_1299 is shown in Figure 8-1469 and described in Table 8-2950.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 544Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_MEMCLK_SW_TXPWR_CTRL | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADRCTL_SW_TXPWR_CTRL_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADRCTL_SW_TXPWR_CTRL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_MEMCLK_SW_TXIO_CTRL | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_MEMCLK_SW_TXPWR_CTRL | R/W | 0h | This register is used to control if clk pads should be shutoff for TX mode in deep sleep mode. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_ADRCTL_SW_TXPWR_CTRL_1 | R/W | 0h | This register is used to control if address/command pad (address/CS/RAS...) should be shutoff for TX mode in deep sleep mode. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_ADRCTL_SW_TXPWR_CTRL_0 | R/W | 0h | This register is used to control if address/command pad (address/CS/RAS...) should be shutoff for TX mode in deep sleep mode. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_MEMCLK_SW_TXIO_CTRL | R/W | 0h | This register is used to control if clk pads should be shutoff for TX mode. |
DDRSS_PHY_1300 is shown in Figure 8-1470 and described in Table 8-2952.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5450h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_STATIC_TOG_CONTROL | |||||||
| R/W-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_STATIC_TOG_CONTROL | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_BYTE_DISABLE_STATIC_TOG_DISABLE | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_TOP_STATIC_TOG_DISABLE | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | PHY_STATIC_TOG_CONTROL | R/W | 0h | Clock divider to create toggle signal. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_BYTE_DISABLE_STATIC_TOG_DISABLE | R/W | 0h | Control to disable the toggle signal for data slice during static activity when dfi_data_byte_disable is asserted. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_TOP_STATIC_TOG_DISABLE | R/W | 0h | Disables the generation of the toggle for static clock based paths in the PHY to prevent assymetric aging. |
DDRSS_PHY_1301 is shown in Figure 8-1471 and described in Table 8-2954.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5454h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_PLL_BYPASS | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_MEMCLK_STATIC_TOG_DISABLE | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADRCTL_STATIC_TOG_DISABLE | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_LP4_BOOT_PLL_BYPASS | R/W | 0h | PHY clock PLL bypass select. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_MEMCLK_STATIC_TOG_DISABLE | R/W | 0h | Control to disable toggle during static activity. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_ADRCTL_STATIC_TOG_DISABLE | R/W | 0h | Control to disable toggle during static activity. |
DDRSS_PHY_1302 is shown in Figure 8-1472 and described in Table 8-2956.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5458h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CLK_SWITCH_OBS | |||||||||||||||||||||||||||||||
| R-10082650h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_CLK_SWITCH_OBS | R | 10082650h | Observation register for Clock switch state machine READ-ONLY |
DDRSS_PHY_1303 is shown in Figure 8-1473 and described in Table 8-2958.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 545Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PLL_WAIT | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R/W | X | |
| 15-0 | PHY_PLL_WAIT | R/W | 0h | PHY clock PLL wait time after locking. |
DDRSS_PHY_1304 is shown in Figure 8-1474 and described in Table 8-2960.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5460h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SW_PLL_BYPASS | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R/W | X | |
| 0 | PHY_SW_PLL_BYPASS | R/W | 0h | PHY clock PLL bypass select. |
DDRSS_PHY_1305 is shown in Figure 8-1475 and described in Table 8-2962.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5464h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CS_ACS_ALLOCATION_BIT1_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CS_ACS_ALLOCATION_BIT0_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SET_DFI_INPUT_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SET_DFI_INPUT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_CS_ACS_ALLOCATION_BIT1_0 | R/W | 0h | The map for which chip select is associated with each bit in the adrctl slice 0. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_CS_ACS_ALLOCATION_BIT0_0 | R/W | 0h | The map for which chip select is associated with each bit in the adrctl slice 0. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_SET_DFI_INPUT_1 | R/W | 0h | Used to indicate the default value of the adrctl slice bits. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_SET_DFI_INPUT_0 | R/W | 0h | Used to indicate the default value of the adrctl slice bits. |
DDRSS_PHY_1306 is shown in Figure 8-1476 and described in Table 8-2964.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5468h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CS_ACS_ALLOCATION_BIT1_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CS_ACS_ALLOCATION_BIT0_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CS_ACS_ALLOCATION_BIT3_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CS_ACS_ALLOCATION_BIT2_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_CS_ACS_ALLOCATION_BIT1_1 | R/W | 0h | The map for which chip select is associated with each bit in the adrctl slice 1. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_CS_ACS_ALLOCATION_BIT0_1 | R/W | 0h | The map for which chip select is associated with each bit in the adrctl slice 1. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_CS_ACS_ALLOCATION_BIT3_0 | R/W | 0h | The map for which chip select is associated with each bit in the adrctl slice 0. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_CS_ACS_ALLOCATION_BIT2_0 | R/W | 0h | The map for which chip select is associated with each bit in the adrctl slice 0. |
DDRSS_PHY_1307 is shown in Figure 8-1477 and described in Table 8-2966.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 546Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CLK_DC_INIT_DISABLE | ||||||
| R/W-X | R/W-1h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_CLK_DC_ADJUST_0 | |||||||
| R/W-20h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CS_ACS_ALLOCATION_BIT3_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CS_ACS_ALLOCATION_BIT2_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_CLK_DC_INIT_DISABLE | R/W | 1h | Disable duty cycle adjust at initialization. |
| 23-16 | PHY_CLK_DC_ADJUST_0 | R/W | 20h | Adjust value of Duty Cycle Adjuster for clock slice 0. |
| 15-12 | RESERVED | R/W | X | |
| 11-8 | PHY_CS_ACS_ALLOCATION_BIT3_1 | R/W | 0h | The map for which chip select is associated with each bit in the adrctl slice 1. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_CS_ACS_ALLOCATION_BIT2_1 | R/W | 0h | The map for which chip select is associated with each bit in the adrctl slice 1. |
DDRSS_PHY_1308 is shown in Figure 8-1478 and described in Table 8-2968.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5470h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_PLL_CTRL | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LP4_BOOT_PLL_CTRL | PHY_CLK_DC_DM_THRSHLD | ||||||||||||||
| R/W-0h | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-8 | PHY_LP4_BOOT_PLL_CTRL | R/W | 0h | PHY deskew PLL controls for LPDDR4 boot frequency. |
| 7-0 | PHY_CLK_DC_DM_THRSHLD | R/W | 0h | Data measurement cell threshold offset. |
DDRSS_PHY_1309 is shown in Figure 8-1479 and described in Table 8-2970.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5474h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_USE_PLL_DSKEWCALLOCK | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PLL_CTRL_OVERRIDE | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_CTRL_OVERRIDE | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_USE_PLL_DSKEWCALLOCK | R/W | 0h | Use DSKEWCALLOCK or not. |
| 15-0 | PHY_PLL_CTRL_OVERRIDE | R/W | 0h | Individual PHY clock PLL control overrides. |
DDRSS_PHY_1310 is shown in Figure 8-1480 and described in Table 8-2972.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5478h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_PLL_SPO_CAL_SNAP_OBS | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PLL_SPO_CAL_CTRL | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PLL_SPO_CAL_CTRL | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_SPO_CAL_CTRL | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | SC_PHY_PLL_SPO_CAL_SNAP_OBS | W | 0h | Register command to take a snapshot of PLL output. |
| 23-19 | RESERVED | R/W | X | |
| 18-0 | PHY_PLL_SPO_CAL_CTRL | R/W | 0h | PLL SPO Cal controls. |
DDRSS_PHY_1311 is shown in Figure 8-1481 and described in Table 8-2974.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 547Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_PLL_CAL_CLK_MEAS | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PLL_CAL_CLK_MEAS_CYCLES | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_CAL_CLK_MEAS_CYCLES | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-16 | SC_PHY_PLL_CAL_CLK_MEAS | W | 0h | Register command to initiate cal_clklout clock frequency measurement. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_PLL_CAL_CLK_MEAS_CYCLES | R/W | 0h | Measurement cycles of cal_clkout clock. |
DDRSS_PHY_1312 is shown in Figure 8-1482 and described in Table 8-2976.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5480h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PLL_OBS_0 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | X | |
| 15-0 | PHY_PLL_OBS_0 | R | 0h | PHY TOP level clock PLL_0 observe values. |
DDRSS_PHY_1313 is shown in Figure 8-1483 and described in Table 8-2978.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5484h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PLL_SPO_CAL_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_SPO_CAL_OBS_0 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R | X | |
| 16-0 | PHY_PLL_SPO_CAL_OBS_0 | R | 0h | PHY TOP level PLL_0 SPO Cal observe values. |
DDRSS_PHY_1314 is shown in Figure 8-1484 and described in Table 8-2980.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5488h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PLL_CAL_CLK_MEAS_OBS_0 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_CAL_CLK_MEAS_OBS_0 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R | X | |
| 17-0 | PHY_PLL_CAL_CLK_MEAS_OBS_0 | R | 0h | PHY TOP level PLL_0 cal_clkout measurement observe values. |
DDRSS_PHY_1315 is shown in Figure 8-1485 and described in Table 8-2982.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 548Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PLL_OBS_1 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R | X | |
| 15-0 | PHY_PLL_OBS_1 | R | 0h | PHY TOP level clock PLL_1 observe values. |
DDRSS_PHY_1316 is shown in Figure 8-1486 and described in Table 8-2984.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5490h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PLL_SPO_CAL_OBS_1 | ||||||||||||||
| R-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_SPO_CAL_OBS_1 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R | X | |
| 16-0 | PHY_PLL_SPO_CAL_OBS_1 | R | 0h | PHY TOP level PLL_1 SPO Cal observe values. |
DDRSS_PHY_1317 is shown in Figure 8-1487 and described in Table 8-2986.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5494h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_LOW_FREQ_SEL | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PLL_CAL_CLK_MEAS_OBS_1 | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PLL_CAL_CLK_MEAS_OBS_1 | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_CAL_CLK_MEAS_OBS_1 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_LP4_BOOT_LOW_FREQ_SEL | R/W | 0h | Control the PLL domain enter/exit from the negative clock edge for LPDDR4 boot frequency. |
| 23-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PLL_CAL_CLK_MEAS_OBS_1 | R | 0h | PHY TOP level PLL_1 cal_clkout measurement observe values. |
DDRSS_PHY_1318 is shown in Figure 8-1488 and described in Table 8-2988.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5498h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LS_IDLE_EN | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_LP_WAKEUP | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_TCKSRE_WAIT | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_LS_IDLE_EN | R/W | 0h | Indicates the Reduced Idle Power State is enabled in low power mode. |
| 15-8 | PHY_LP_WAKEUP | R/W | 0h | Specifies the number of cycles the PHY takes to wakeup in low power mode. |
| 7-4 | RESERVED | R/W | X | |
| 3-0 | PHY_TCKSRE_WAIT | R/W | 0h | Specifies the number of cycles the PHY should wait before turning off the PLL for a deep sleep or DFS event. |
DDRSS_PHY_1319 is shown in Figure 8-1489 and described in Table 8-2990.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 549Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TDFI_PHY_WRDELAY | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP_CTRLUPD_CNTR_CFG | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LP_CTRLUPD_CNTR_CFG | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_TDFI_PHY_WRDELAY | R/W | 0h | DFI timing parameter TDFI_PHY_WRDELAY. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_LP_CTRLUPD_CNTR_CFG | R/W | 0h | Specifies the number of cycles the PHY takes from light sleep req deassert to ack deassert in low power mode. |
DDRSS_PHY_1320 is shown in Figure 8-1490 and described in Table 8-2992.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_FDBK_TERM | ||||||||||||||||||||||||||||||
| R/W-X | R/W-4410h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PAD_FDBK_TERM | R/W | 4410h | Controls term settings for gate feedback pads. |
DDRSS_PHY_1321 is shown in Figure 8-1491 and described in Table 8-2994.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_DATA_TERM | ||||||||||||||||||||||||||||||
| R/W-X | R/W-4410h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16-0 | PHY_PAD_DATA_TERM | R/W | 4410h | Controls term settings for data pads. |
DDRSS_PHY_1322 is shown in Figure 8-1492 and described in Table 8-2996.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54A8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_DQS_TERM | ||||||||||||||||||||||||||||||
| R/W-X | R/W-4410h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16-0 | PHY_PAD_DQS_TERM | R/W | 4410h | Controls term settings for dqs pads. |
DDRSS_PHY_1323 is shown in Figure 8-1493 and described in Table 8-2998.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54ACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_ADDR_TERM | ||||||||||||||||||||||||||||||
| R/W-X | R/W-4410h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PAD_ADDR_TERM | R/W | 4410h | Controls term settings for the address/control pads. |
DDRSS_PHY_1324 is shown in Figure 8-1494 and described in Table 8-3000.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54B0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_CLK_TERM | ||||||||||||||||||||||||||||||
| R/W-X | R/W-4410h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PAD_CLK_TERM | R/W | 4410h | Controls term settings for clock pads. |
DDRSS_PHY_1325 is shown in Figure 8-1495 and described in Table 8-3002.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_CKE_TERM | ||||||||||||||||||||||||||||||
| R/W-X | R/W-4410h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PAD_CKE_TERM | R/W | 4410h | Controls term settings for cke pads. |
DDRSS_PHY_1326 is shown in Figure 8-1496 and described in Table 8-3004.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RST_TERM | ||||||||||||||||||||||||||||||
| R/W-X | R/W-4410h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PAD_RST_TERM | R/W | 4410h | Controls term settings for reset_n pads. |
DDRSS_PHY_1327 is shown in Figure 8-1497 and described in Table 8-3006.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_CS_TERM | ||||||||||||||||||||||||||||||
| R/W-X | R/W-4410h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PAD_CS_TERM | R/W | 4410h | Controls term settings for cs pads. |
DDRSS_PHY_1328 is shown in Figure 8-1498 and described in Table 8-3008.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_ODT_TERM | ||||||||||||||||||||||||||||||
| R/W-X | R/W-4410h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PAD_ODT_TERM | R/W | 4410h | Controls term settings for odt pads. |
DDRSS_PHY_1329 is shown in Figure 8-1499 and described in Table 8-3010.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54C4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADRCTL_LP3_RX_CAL | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADRCTL_RX_CAL | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-16 | PHY_ADRCTL_LP3_RX_CAL | R/W | 0h | PHY CKE/RESET_N RX calibration controls. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_ADRCTL_RX_CAL | R/W | 0h | PHY address/control RX calibration controls. |
DDRSS_PHY_1330 is shown in Figure 8-1500 and described in Table 8-3012.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54C8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CAL_START_0 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CAL_CLEAR_0 | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CAL_MODE_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CAL_MODE_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_CAL_START_0 | W | 0h | Manual start for the pad calibration state machine for block 0. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_CAL_CLEAR_0 | W | 0h | Clear the pad calibration state machine and results for block 0. |
| 15-13 | RESERVED | R/W | X | |
| 12-0 | PHY_CAL_MODE_0 | R/W | 0h | Pad calibration mode bits for block 0. |
DDRSS_PHY_1331 is shown in Figure 8-1501 and described in Table 8-3014.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CAL_INTERVAL_COUNT_0 | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_CAL_INTERVAL_COUNT_0 | R/W | 0h | Pad calibration interval counter compare value for block 0. |
DDRSS_PHY_1332 is shown in Figure 8-1502 and described in Table 8-3016.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54D0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_BOOT_CAL_CLK_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CAL_SAMPLE_WAIT_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-11 | RESERVED | R/W | X | |
| 10-8 | PHY_LP4_BOOT_CAL_CLK_SELECT_0 | R/W | 0h | Pad calibration pad clock frequency select setting for LPDDR4 boot frequency for block 0. |
| 7-0 | PHY_CAL_SAMPLE_WAIT_0 | R/W | 0h | Pad calibration state machine wait count in pad clock cycles for block 0. |
DDRSS_PHY_1333 is shown in Figure 8-1503 and described in Table 8-3018.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54D4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CAL_RESULT_OBS_0 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | X | |
| 23-0 | PHY_CAL_RESULT_OBS_0 | R | 0h | Pad calibration results observation values for block 0. |
DDRSS_PHY_1334 is shown in Figure 8-1504 and described in Table 8-3020.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54D8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CAL_RESULT2_OBS_0 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | X | |
| 23-0 | PHY_CAL_RESULT2_OBS_0 | R | 0h | Pad calibration results (CKE/RESET_N) observation values for block 0. |
DDRSS_PHY_1335 is shown in Figure 8-1505 and described in Table 8-3022.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54DCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CAL_RESULT4_OBS_0 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | X | |
| 23-0 | PHY_CAL_RESULT4_OBS_0 | R | 0h | Pad calibration pass1 shadow results observation values for block 0. |
DDRSS_PHY_1336 is shown in Figure 8-1506 and described in Table 8-3024.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CAL_RESULT5_OBS_0 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | X | |
| 23-0 | PHY_CAL_RESULT5_OBS_0 | R | 0h | Pad calibration pass2 shadow results observation values for block 0. |
DDRSS_PHY_1337 is shown in Figure 8-1507 and described in Table 8-3026.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CAL_RESULT6_OBS_0 | ||||||||||||||||||||||||||||||
| R-X | R-0h | ||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-24 | RESERVED | R | X | |
| 23-0 | PHY_CAL_RESULT6_OBS_0 | R | 0h | Pad calibration internal results observation delta values for block 0. |
DDRSS_PHY_1338 is shown in Figure 8-1508 and described in Table 8-3028.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54E8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CAL_CPTR_CNT_0 | PHY_CAL_RESULT7_OBS_0 | |||||||||||||
| R/W-X | R/W-0h | R-0h | |||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CAL_RESULT7_OBS_0 | |||||||||||||||
| R-0h | |||||||||||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-24 | PHY_CAL_CPTR_CNT_0 | R/W | 0h | defines sample capture number in pad calibration process |
| 23-0 | PHY_CAL_RESULT7_OBS_0 | R | 0h | Pad calibration internal results observation delta values for block 0. |
DDRSS_PHY_1339 is shown in Figure 8-1509 and described in Table 8-3030.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54ECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CAL_DBG_CFG_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_CAL_RCV_FINE_ADJ_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_CAL_PD_FINE_ADJ_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CAL_PU_FINE_ADJ_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_CAL_DBG_CFG_0 | R/W | 0h | defines debug configuration in pad calibration process |
| 23-16 | PHY_CAL_RCV_FINE_ADJ_0 | R/W | 0h | defines adjustment for RCV code in pad calibration process |
| 15-8 | PHY_CAL_PD_FINE_ADJ_0 | R/W | 0h | defines adjustment for PD code in pad calibration process |
| 7-0 | PHY_CAL_PU_FINE_ADJ_0 | R/W | 0h | defines adjustment for PU code in pad calibration process |
DDRSS_PHY_1340 is shown in Figure 8-1510 and described in Table 8-3032.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SC_PHY_PAD_DBG_CONT_0 | ||||||
| W-X | W-0h | ||||||
| LEGEND: W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | W | X | |
| 0 | SC_PHY_PAD_DBG_CONT_0 | W | 0h | Allows the pad calibration state machine to advance (when in debug mode) for slice 0. |
DDRSS_PHY_1341 is shown in Figure 8-1511 and described in Table 8-3034.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54F4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CAL_RESULT3_OBS_0 | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_CAL_RESULT3_OBS_0 | R | 0h | Pad calibration results first/last0/1 observation values for block 0. |
DDRSS_PHY_1342 is shown in Figure 8-1512 and described in Table 8-3036.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54F8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CAL_SLOPE_ADJ_0 | ||||||
| R/W-X | R/W-00041020h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_CAL_SLOPE_ADJ_0 | |||||||
| R/W-00041020h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_CAL_SLOPE_ADJ_0 | |||||||
| R/W-00041020h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADRCTL_PVT_MAP_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-8 | PHY_CAL_SLOPE_ADJ_0 | R/W | 00041020h | defines slope configure in pad calibration process |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_ADRCTL_PVT_MAP_0 | R/W | 0h | defines slope configure in pad calibration process |
DDRSS_PHY_1343 is shown in Figure 8-1513 and described in Table 8-3038.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 54FCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CAL_SLOPE_ADJ_PASS2_0 | ||||||||||||||
| R/W-X | R/W-00041020h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CAL_SLOPE_ADJ_PASS2_0 | |||||||||||||||
| R/W-00041020h | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_CAL_SLOPE_ADJ_PASS2_0 | R/W | 00041020h | defines slope configure for pass2 in pad calibration process |
DDRSS_PHY_1344 is shown in Figure 8-1514 and described in Table 8-3040.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5500h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CAL_TWO_PASS_CFG_0 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-00C98C98h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-0 | PHY_CAL_TWO_PASS_CFG_0 | R/W | 00C98C98h | defines cal_en configure in pad calibration process |
DDRSS_PHY_1345 is shown in Figure 8-1515 and described in Table 8-3042.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5504h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0 | ||||||
| R/W-X | R/W-3Fh | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CAL_SW_CAL_CFG_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_CAL_SW_CAL_CFG_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_CAL_SW_CAL_CFG_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0 | R/W | 3Fh | Pad calibration pass1 pu results won't update if out of max delta range . |
| 23 | RESERVED | R/W | X | |
| 22-0 | PHY_CAL_SW_CAL_CFG_0 | R/W | 0h | defines firmware based pad calibration process |
DDRSS_PHY_1346 is shown in Figure 8-1516 and described in Table 8-3044.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5508h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0 | ||||||
| R/W-X | R/W-3Fh | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0 | ||||||
| R/W-X | R/W-3Fh | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0 | ||||||
| R/W-X | R/W-1Fh | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0 | ||||||
| R/W-X | R/W-3Fh | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0 | R/W | 3Fh | Pad calibration pass2 pd results won't update if out of max delta range . |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0 | R/W | 3Fh | Pad calibration pass2 pu results won't update if out of max delta range . |
| 15-13 | RESERVED | R/W | X | |
| 12-8 | PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0 | R/W | 1Fh | Pad calibration pass1 rx results won't update if out of max delta range . |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0 | R/W | 3Fh | Pad calibration pass1 pd results won't update if out of max delta range . |
DDRSS_PHY_1347 is shown in Figure 8-1517 and described in Table 8-3046.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 550Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0 | ||||||
| R/W-X | R/W-1Fh | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0 | R/W | 0h | Pad calibration pass1 rx results won't update if out of min delta range . |
| 23-22 | RESERVED | R/W | X | |
| 21-16 | PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0 | R/W | 0h | Pad calibration pass1 pd results won't update if out of min delta range . |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0 | R/W | 0h | Pad calibration pass1 pu results won't update if out of min delta range . |
| 7-5 | RESERVED | R/W | X | |
| 4-0 | PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0 | R/W | 1Fh | Pad calibration pass2 rx results won't update if out of max delta range . |
DDRSS_PHY_1348 is shown in Figure 8-1518 and described in Table 8-3048.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5510h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-21 | RESERVED | R/W | X | |
| 20-16 | PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0 | R/W | 0h | Pad calibration pass2 rx results won't update if out of min delta range . |
| 15-14 | RESERVED | R/W | X | |
| 13-8 | PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0 | R/W | 0h | Pad calibration pass2 pd results won't update if out of min delta range . |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0 | R/W | 0h | Pad calibration pass2 pu results won't update if out of min delta range . |
DDRSS_PHY_1349 is shown in Figure 8-1519 and described in Table 8-3050.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5514h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PARITY_ERROR_REGIF_AC | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PAD_ATB_CTRL | |||||||||||||||
| R/W-0h | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_PARITY_ERROR_REGIF_AC | R/W | 0h | Inject parity error to register interface signals for ac slice. |
| 15-0 | PHY_PAD_ATB_CTRL | R/W | 0h | Pad ATB control settings. |
DDRSS_PHY_1350 is shown in Figure 8-1520 and described in Table 8-3052.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5518h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_AC_LPBK_ENABLE | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_AC_LPBK_OBS_SELECT | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_AC_LPBK_ERR_CLEAR | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADRCTL_MANUAL_UPDATE | ||||||
| R/W-X | W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_AC_LPBK_ENABLE | R/W | 0h | Loopback enable for the address/control slices. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_AC_LPBK_OBS_SELECT | R/W | 0h | Select value to map an individual loopback address/control slice observation register to the global observation register. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_AC_LPBK_ERR_CLEAR | W | 0h | Address/control loopback error clear. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_ADRCTL_MANUAL_UPDATE | W | 0h | Address/control manual update of slave delay lines. |
DDRSS_PHY_1351 is shown in Figure 8-1521 and described in Table 8-3054.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 551Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_AC_PRBS_PATTERN_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_AC_PRBS_PATTERN_START | ||||||
| R/W-X | R/W-1h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_AC_LPBK_CONTROL | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_AC_LPBK_CONTROL | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_AC_PRBS_PATTERN_MASK | R/W | 0h | PRBS7 mask signal for address/control slice. |
| 23 | RESERVED | R/W | X | |
| 22-16 | PHY_AC_PRBS_PATTERN_START | R/W | 1h | PRBS7 start pattern for address/control slice. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_AC_LPBK_CONTROL | R/W | 0h | Address/control slice loopback control setting. |
DDRSS_PHY_1352 is shown in Figure 8-1522 and described in Table 8-3056.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5520h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_AC_LPBK_RESULT_OBS | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_AC_LPBK_RESULT_OBS | R | 0h | Observation register for the loopback address/control slices. |
DDRSS_PHY_1353 is shown in Figure 8-1523 and described in Table 8-3058.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5524h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_AC_CLK_LPBK_CONTROL | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_AC_CLK_LPBK_ENABLE | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_AC_CLK_LPBK_OBS_SELECT | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-22 | RESERVED | R/W | X | |
| 21-16 | PHY_AC_CLK_LPBK_CONTROL | R/W | 0h | Mem clk block loopback control setting. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_AC_CLK_LPBK_ENABLE | R/W | 0h | Loopback enable for mem clk blocks. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_AC_CLK_LPBK_OBS_SELECT | R/W | 0h | Select value to map an individual loopback mem clk block observation register to the global observation register. |
DDRSS_PHY_1354 is shown in Figure 8-1524 and described in Table 8-3060.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5528h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_TOP_PWR_RDC_DISABLE | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_AC_PWR_RDC_DISABLE | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_AC_CLK_LPBK_RESULT_OBS | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_AC_CLK_LPBK_RESULT_OBS | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_TOP_PWR_RDC_DISABLE | R/W | 0h | top param power reduction disable. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_AC_PWR_RDC_DISABLE | R/W | 0h | ac slice power reduction disable. |
| 15-0 | PHY_AC_CLK_LPBK_RESULT_OBS | R | 0h | Observation register for loopback mem clk blocks. |
DDRSS_PHY_1355 is shown in Figure 8-1525 and described in Table 8-3062.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 552Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_AC_SLV_DLY_CTRL_GATE_DISABLE | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R/W | X | |
| 0 | PHY_AC_SLV_DLY_CTRL_GATE_DISABLE | R/W | 0h | ac slice slv_dly_control block power reduction disable. |
DDRSS_PHY_1356 is shown in Figure 8-1526 and described in Table 8-3064.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5530h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_BYTE_ORDER_SEL | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DATA_BYTE_ORDER_SEL | R/W | 0h | Used to define the data slice's byte swap for CA bits 7:0. |
DDRSS_PHY_1357 is shown in Figure 8-1527 and described in Table 8-3066.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5534h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADRCTL_MSTR_DLY_ENC_SEL_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CALVL_DEVICE_MAP | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LPDDR4_CONNECT | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DATA_BYTE_ORDER_SEL_HIGH | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_ADRCTL_MSTR_DLY_ENC_SEL_0 | R/W | 0h | Select adrctl_mstr_dly_enc for the address/control slice 0 . |
| 23-21 | RESERVED | R/W | X | |
| 20-16 | PHY_CALVL_DEVICE_MAP | R/W | 0h | Define which device's DQ feedback data bits should be used during CA training |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_LPDDR4_CONNECT | R/W | 0h | PHY is connected to LPDDR4 devices |
| 7-0 | PHY_DATA_BYTE_ORDER_SEL_HIGH | R/W | 0h | Used to define the data slice's byte swap for CA bits |
DDRSS_PHY_1358 is shown in Figure 8-1528 and described in Table 8-3068.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5538h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ADRCTL_MSTR_DLY_ENC_SEL_1 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-2 | RESERVED | R/W | X | |
| 1-0 | PHY_ADRCTL_MSTR_DLY_ENC_SEL_1 | R/W | 0h | Select adrctl_mstr_dly_enc for the address/control slice 1 . |
DDRSS_PHY_1359 is shown in Figure 8-1529 and described in Table 8-3070.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 553Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DDL_AC_ENABLE | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DDL_AC_ENABLE | R/W | 0h | PHY Address/Control DDL BIST mode enable. |
DDRSS_PHY_1360 is shown in Figure 8-1530 and described in Table 8-3072.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5540h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DDL_AC_MODE | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-0 | PHY_DDL_AC_MODE | R/W | 0h | PHY Address/Control DDL BIST mode. |
DDRSS_PHY_1361 is shown in Figure 8-1531 and described in Table 8-3074.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5544h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ERR_MASK_EN | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DDL_TRACK_UPD_THRESHOLD_AC | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_INIT_UPDATE_CONFIG | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DDL_AC_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_ERR_MASK_EN | R/W | 0h | PHY ERROR information report mask enable. |
| 23-16 | PHY_DDL_TRACK_UPD_THRESHOLD_AC | R/W | 0h | Specify threshold value for PHY init update tracking for AC slice. |
| 15-11 | RESERVED | R/W | X | |
| 10-8 | PHY_INIT_UPDATE_CONFIG | R/W | 0h | PHY init update function configuration. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_DDL_AC_MASK | R/W | 0h | PHY Address/Control DDL BIST mask. |
DDRSS_PHY_1362 is shown in Figure 8-1532 and described in Table 8-3076.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5548h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_ERR_STATUS | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-3 | RESERVED | R/W | X | |
| 2-0 | PHY_ERR_STATUS | R/W | 0h | PHY ERROR information. |
DDRSS_PHY_1363 is shown in Figure 8-1533 and described in Table 8-3078.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 554Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DS0_DQS_ERR_COUNTER | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DS0_DQS_ERR_COUNTER | R | 0h | PHY DATA SLICE 0 DQS ERROR counter. |
DDRSS_PHY_1364 is shown in Figure 8-1534 and described in Table 8-3080.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5550h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DS1_DQS_ERR_COUNTER | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DS1_DQS_ERR_COUNTER | R | 0h | PHY DATA SLICE 1 DQS ERROR counter. |
DDRSS_PHY_1365 is shown in Figure 8-1535 and described in Table 8-3082.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5554h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DS2_DQS_ERR_COUNTER | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DS2_DQS_ERR_COUNTER | R | 0h | PHY DATA SLICE 2 DQS ERROR counter. |
DDRSS_PHY_1366 is shown in Figure 8-1536 and described in Table 8-3084.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5558h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DS3_DQS_ERR_COUNTER | |||||||||||||||||||||||||||||||
| R-0h | |||||||||||||||||||||||||||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_DS3_DQS_ERR_COUNTER | R | 0h | PHY DATA SLICE 3 DQS ERROR counter. |
DDRSS_PHY_1367 is shown in Figure 8-1537 and described in Table 8-3086.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 555Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_DS_INIT_COMPLETE_OBS | ||||||
| R/W-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_AC_INIT_COMPLETE_OBS | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_AC_INIT_COMPLETE_OBS | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DLL_RST_EN | ||||||
| R/W-X | R/W-2h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_DS_INIT_COMPLETE_OBS | R | 0h | Observation register for dfi_init_complete for data slice. |
| 23-18 | RESERVED | R/W | X | |
| 17-8 | PHY_AC_INIT_COMPLETE_OBS | R | 0h | Observation register for dfi_init_complete for adr and ac slice. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | PHY_DLL_RST_EN | R/W | 2h | PHY DDL reset software interface enable. |
DDRSS_PHY_1368 is shown in Figure 8-1538 and described in Table 8-3088.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5560h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GRP_SHIFT_OBS_SELECT | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GRP_SLV_DLY_ENC_OBS_SELECT | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_UPDATE_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_GRP_SHIFT_OBS_SELECT | R/W | 0h | Select value to map an individual address/control group slice automatic cycle/half_cycle shift settings to the observation register. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_GRP_SLV_DLY_ENC_OBS_SELECT | R/W | 0h | Select value to map an individual address/control group slice slave delay to the encoded value observation register. |
| 15-9 | RESERVED | R/W | X | |
| 8 | PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE | R/W | 0h | Memory clock bit slice DCC block power reduction disable. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_UPDATE_MASK | R/W | 0h | Control to disable the generation of dfi_phyupd_req and use of dfi_ctrlupd_req. |
DDRSS_PHY_1369 is shown in Figure 8-1539 and described in Table 8-3090.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5564h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GRP_SHIFT_OBS | ||||||
| R-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GRP_SLV_DLY_ENC_OBS | ||||||
| R-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_GRP_SLV_DLY_ENC_OBS | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-19 | RESERVED | R | X | |
| 18-16 | PHY_GRP_SHIFT_OBS | R | 0h | Observation register for the address/control group automatic half cycle and cycle shift values. |
| 15-11 | RESERVED | R | X | |
| 10-0 | PHY_GRP_SLV_DLY_ENC_OBS | R | 0h | Observation register for all address/control group slice slave delay encoded values. |
DDRSS_PHY_1370 is shown in Figure 8-1540 and described in Table 8-3092.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5568h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PLL_LOCK_DEASSERT_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PARITY_ERROR_REGIF_PS | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PARITY_ERROR_REGIF_PS | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PARITY_ERROR_INJECTION_ENABLE | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-24 | PHY_PLL_LOCK_DEASSERT_MASK | R/W | 0h | PLL Lock de-assert Mask. |
| 23-19 | RESERVED | R/W | X | |
| 18-8 | PHY_PARITY_ERROR_REGIF_PS | R/W | 0h | Injects parity error to register interface signals in param_split. |
| 7-1 | RESERVED | R/W | X | |
| 0 | PHY_PARITY_ERROR_INJECTION_ENABLE | R/W | 0h | Enable parity error injection. |
DDRSS_PHY_1371 is shown in Figure 8-1541 and described in Table 8-3094.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 556Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | SC_PHY_PARITY_ERROR_INFO_WOCLR | ||||||
| R/W-X | W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PARITY_ERROR_INFO_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PARITY_ERROR_INFO | ||||||
| R/W-X | R-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-23 | RESERVED | R/W | X | |
| 22-16 | SC_PHY_PARITY_ERROR_INFO_WOCLR | W | 0h | Parity Error Info. |
| 15 | RESERVED | R/W | X | |
| 14-8 | PHY_PARITY_ERROR_INFO_MASK | R/W | 0h | Parity Error Info Mask. |
| 7 | RESERVED | R/W | X | |
| 6-0 | PHY_PARITY_ERROR_INFO | R | 0h | Parity Error Info. |
DDRSS_PHY_1372 is shown in Figure 8-1542 and described in Table 8-3096.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5570h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_TIMEOUT_ERROR_INFO_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_TIMEOUT_ERROR_INFO_MASK | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_TIMEOUT_ERROR_INFO | ||||||
| R/W-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_TIMEOUT_ERROR_INFO | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | PHY_TIMEOUT_ERROR_INFO_MASK | R/W | 0h | Timeout Error Info Mask. |
| 15-14 | RESERVED | R/W | X | |
| 13-0 | PHY_TIMEOUT_ERROR_INFO | R | 0h | Timeout Error Info. |
DDRSS_PHY_1373 is shown in Figure 8-1543 and described in Table 8-3098.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5574h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PLL_FREQUENCY_ERROR_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PLL_FREQUENCY_ERROR | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_TIMEOUT_ERROR_INFO_WOCLR | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SC_PHY_TIMEOUT_ERROR_INFO_WOCLR | |||||||
| W-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-24 | PHY_PLL_FREQUENCY_ERROR_MASK | R/W | 0h | PLL Frequency Error Info Mask. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_PLL_FREQUENCY_ERROR | R | 0h | PLL Frequency Error Info. |
| 15-14 | RESERVED | R/W | X | |
| 13-0 | SC_PHY_TIMEOUT_ERROR_INFO_WOCLR | W | 0h | Timeout Error Info. |
DDRSS_PHY_1374 is shown in Figure 8-1544 and described in Table 8-3100.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5578h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PLL_DSKEWCALOUT_MIN | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PLL_DSKEWCALOUT_MIN | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SC_PHY_PLL_FREQUENCY_ERROR_WOCLR | ||||||
| R/W-X | W-0h | ||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-8 | PHY_PLL_DSKEWCALOUT_MIN | R/W | 0h | PLL DSKEWCALOUT threshold min value. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | SC_PHY_PLL_FREQUENCY_ERROR_WOCLR | W | 0h | PLL_Frequency Error Info. |
DDRSS_PHY_1375 is shown in Figure 8-1545 and described in Table 8-3102.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 557Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PLL_DSKEWCALOUT_ERROR_INFO | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PLL_DSKEWCALOUT_MAX | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_DSKEWCALOUT_MAX | |||||||
| R/W-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK | R/W | 0h | PLL DSKEWCALOUT threshold Error Info Mask. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_PLL_DSKEWCALOUT_ERROR_INFO | R | 0h | PLL DSKEWCALOUT threshold Error Info. |
| 15-12 | RESERVED | R/W | X | |
| 11-0 | PHY_PLL_DSKEWCALOUT_MAX | R/W | 0h | PLL DSKEWCALOUT threshold max value. |
DDRSS_PHY_1376 is shown in Figure 8-1546 and described in Table 8-3104.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5580h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TOP_FSM_ERROR_INFO | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_TOP_FSM_ERROR_INFO | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR | ||||||
| R/W-X | W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16-8 | PHY_TOP_FSM_ERROR_INFO | R | 0h | Top level FSM Error Info. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR | W | 0h | PLL DSKEWCALOUT threshold Error Info. |
DDRSS_PHY_1377 is shown in Figure 8-1547 and described in Table 8-3106.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5584h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_TOP_FSM_ERROR_INFO_WOCLR | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SC_PHY_TOP_FSM_ERROR_INFO_WOCLR | |||||||
| W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_TOP_FSM_ERROR_INFO_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_TOP_FSM_ERROR_INFO_MASK | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24-16 | SC_PHY_TOP_FSM_ERROR_INFO_WOCLR | W | 0h | Top level FSM Error Info. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_TOP_FSM_ERROR_INFO_MASK | R/W | 0h | Top level FSM Error Info Mask. |
DDRSS_PHY_1378 is shown in Figure 8-1548 and described in Table 8-3108.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5588h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_FSM_TRANSIENT_ERROR_INFO_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_FSM_TRANSIENT_ERROR_INFO_MASK | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_FSM_TRANSIENT_ERROR_INFO | ||||||
| R/W-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_FSM_TRANSIENT_ERROR_INFO | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-16 | PHY_FSM_TRANSIENT_ERROR_INFO_MASK | R/W | 0h | Accumulated Top level FSM Error Info Mask. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | PHY_FSM_TRANSIENT_ERROR_INFO | R | 0h | Accumulated Top level FSM Error Info. |
DDRSS_PHY_1379 is shown in Figure 8-1549 and described in Table 8-3110.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 558Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TOP_TRAIN_CALIB_ERROR_INFO | ||||||
| R/W-X | R-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR | |||||||
| W-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R/W | X | |
| 25-24 | PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK | R/W | 0h | Training/Calibration Error Info Mask for TOP. |
| 23-18 | RESERVED | R/W | X | |
| 17-16 | PHY_TOP_TRAIN_CALIB_ERROR_INFO | R | 0h | Training/Calibration Error Info for TOP. |
| 15-10 | RESERVED | R/W | X | |
| 9-0 | SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR | W | 0h | Accumulated Top level FSM Error Info. |
DDRSS_PHY_1380 is shown in Figure 8-1550 and described in Table 8-3112.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5590h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TRAIN_CALIB_ERROR_INFO_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_TRAIN_CALIB_ERROR_INFO | ||||||
| R/W-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR | ||||||
| R/W-X | W-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-24 | SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR | W | 0h | Training/Calibration Error Info. |
| 23 | RESERVED | R/W | X | |
| 22-16 | PHY_TRAIN_CALIB_ERROR_INFO_MASK | R/W | 0h | Training/Calibration Error Info Mask. |
| 15 | RESERVED | R/W | X | |
| 14-8 | PHY_TRAIN_CALIB_ERROR_INFO | R | 0h | Training/Calibration Error Info. |
| 7-2 | RESERVED | R/W | X | |
| 1-0 | SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR | W | 0h | Training/Calibration Error Info for TOP. |
DDRSS_PHY_1381 is shown in Figure 8-1551 and described in Table 8-3114.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5594h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GLOBAL_ERROR_INFO_MASK | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GLOBAL_ERROR_INFO | ||||||
| R/W-X | R-0h | ||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-14 | RESERVED | R/W | X | |
| 13-8 | PHY_GLOBAL_ERROR_INFO_MASK | R/W | 0h | Global Error Info Mask. |
| 7-6 | RESERVED | R/W | X | |
| 5-0 | PHY_GLOBAL_ERROR_INFO | R | 0h | Global Error Info. |
DDRSS_PHY_1382 is shown in Figure 8-1552 and described in Table 8-3116.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5598h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_TRAINING_TIMEOUT_VALUE | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_TRAINING_TIMEOUT_VALUE | |||||||||||||||
| R/W-0h | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_TRAINING_TIMEOUT_VALUE | R/W | 0h | Training timeout value. |
DDRSS_PHY_1383 is shown in Figure 8-1553 and described in Table 8-3118.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 559Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_INIT_TIMEOUT_VALUE | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_INIT_TIMEOUT_VALUE | |||||||||||||||
| R/W-0h | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | X | |
| 19-0 | PHY_INIT_TIMEOUT_VALUE | R/W | 0h | Init or DFS timeout value. |
DDRSS_PHY_1384 is shown in Figure 8-1554 and described in Table 8-3120.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_LP_TIMEOUT_VALUE | |||||||||||||||
| R/W-0h | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-16 | RESERVED | R/W | X | |
| 15-0 | PHY_LP_TIMEOUT_VALUE | R/W | 0h | DFI LP timeout value. |
DDRSS_PHY_1385 is shown in Figure 8-1555 and described in Table 8-3122.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PHYUPD_TIMEOUT_VALUE | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_PHYUPD_TIMEOUT_VALUE | R/W | 0h | DFI PHYUPD timeout value. |
DDRSS_PHY_1386 is shown in Figure 8-1556 and described in Table 8-3124.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55A8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PLL_LOCK_0_MIN_VALUE | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PHYMSTR_TIMEOUT_VALUE | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PHYMSTR_TIMEOUT_VALUE | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PHYMSTR_TIMEOUT_VALUE | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R/W | X | |
| 28-24 | PHY_PLL_LOCK_0_MIN_VALUE | R/W | 0h | PLL min timeout value. |
| 23-20 | RESERVED | R/W | X | |
| 19-0 | PHY_PHYMSTR_TIMEOUT_VALUE | R/W | 0h | DFI PHYMSTR timeout value. |
DDRSS_PHY_1387 is shown in Figure 8-1557 and described in Table 8-3126.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55ACh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PLL_FREQUENCY_DELTA | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_RDDATA_VALID_TIMEOUT_VALUE | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_PLL_LOCK_TIMEOUT_VALUE | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_LOCK_TIMEOUT_VALUE | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_PLL_FREQUENCY_DELTA | R/W | 0h | Acceptable PLL frequency delta. |
| 23-16 | PHY_RDDATA_VALID_TIMEOUT_VALUE | R/W | 0h | RDDATA VALID timeout value. |
| 15-0 | PHY_PLL_LOCK_TIMEOUT_VALUE | R/W | 0h | PLL max timeout value. |
DDRSS_PHY_1388 is shown in Figure 8-1558 and described in Table 8-3128.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55B0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_ADRCTL_FSM_ERROR_INFO_0 | ||||||||||||||
| R/W-X | R-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_FREQUENCY_COMPARE_INTERVAL | |||||||||||||||
| R/W-0h | |||||||||||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | PHY_ADRCTL_FSM_ERROR_INFO_0 | R | 0h | ADRCTL slice level FSM Error Info. |
| 15-0 | PHY_PLL_FREQUENCY_COMPARE_INTERVAL | R/W | 0h | PLL Frequency compare interval. |
DDRSS_PHY_1389 is shown in Figure 8-1559 and described in Table 8-3130.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0 | |||||||
| W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADRCTL_FSM_ERROR_INFO_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADRCTL_FSM_ERROR_INFO_MASK_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0 | W | 0h | ADRCTL Slice level FSM Error Info. |
| 15-14 | RESERVED | R/W | X | |
| 13-0 | PHY_ADRCTL_FSM_ERROR_INFO_MASK_0 | R/W | 0h | ADRCTL Slice level FSM Error Info Mask. |
DDRSS_PHY_1390 is shown in Figure 8-1560 and described in Table 8-3132.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_ADRCTL_FSM_ERROR_INFO_MASK_1 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_ADRCTL_FSM_ERROR_INFO_MASK_1 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_ADRCTL_FSM_ERROR_INFO_1 | ||||||
| R/W-X | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_ADRCTL_FSM_ERROR_INFO_1 | |||||||
| R-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | PHY_ADRCTL_FSM_ERROR_INFO_MASK_1 | R/W | 0h | ADRCTL Slice level FSM Error Info Mask. |
| 15-14 | RESERVED | R/W | X | |
| 13-0 | PHY_ADRCTL_FSM_ERROR_INFO_1 | R | 0h | ADRCTL slice level FSM Error Info. |
DDRSS_PHY_1391 is shown in Figure 8-1561 and described in Table 8-3134.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_MEMCLK_FSM_ERROR_INFO_0 | ||||||
| R/W-X | R-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_MEMCLK_FSM_ERROR_INFO_0 | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1 | ||||||
| R/W-X | W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1 | |||||||
| W-0h | |||||||
| LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | PHY_MEMCLK_FSM_ERROR_INFO_0 | R | 0h | MEMCLK slice level FSM Error Info. |
| 15-14 | RESERVED | R/W | X | |
| 13-0 | SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1 | W | 0h | ADRCTL Slice level FSM Error Info. |
DDRSS_PHY_1392 is shown in Figure 8-1562 and described in Table 8-3136.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0 | ||||||
| R/W-X | W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0 | |||||||
| W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_MEMCLK_FSM_ERROR_INFO_MASK_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_MEMCLK_FSM_ERROR_INFO_MASK_0 | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-16 | SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0 | W | 0h | MEMCLK Slice level FSM Error Info. |
| 15-14 | RESERVED | R/W | X | |
| 13-0 | PHY_MEMCLK_FSM_ERROR_INFO_MASK_0 | R/W | 0h | MEMCLK Slice level FSM Error Info Mask. |
DDRSS_PHY_1393 is shown in Figure 8-1563 and described in Table 8-3138.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55C4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_CAL_IO_CFG_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PAD_CAL_IO_CFG_0 | |||||||||||||||
| R/W-0h | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PAD_CAL_IO_CFG_0 | R/W | 0h | Pad calibration Controls PCLK/PARK pin and vref switch. |
DDRSS_PHY_1394 is shown in Figure 8-1564 and described in Table 8-3140.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55C8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_ACS_IO_CFG | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-14 | RESERVED | R/W | X | |
| 13-0 | PHY_PAD_ACS_IO_CFG | R/W | 0h | Controls PCLK/PARK pin for acs pad. |
DDRSS_PHY_1395 is shown in Figure 8-1565 and described in Table 8-3142.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55CCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PLL_BYPASS | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-1 | RESERVED | R/W | X | |
| 0 | PHY_PLL_BYPASS | R/W | 0h | PHY clock PLL bypass select. |
DDRSS_PHY_1396 is shown in Figure 8-1566 and described in Table 8-3144.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55D0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LOW_FREQ_SEL | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PLL_CTRL | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PLL_CTRL | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-17 | RESERVED | R/W | X | |
| 16 | PHY_LOW_FREQ_SEL | R/W | 0h | Enables the PHY to enter/exit the PLL domain from the negative clock edge. |
| 15-13 | RESERVED | R/W | X | |
| 12-0 | PHY_PLL_CTRL | R/W | 0h | PHY clock PLL controls. |
DDRSS_PHY_1397 is shown in Figure 8-1567 and described in Table 8-3146.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55D4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CSLVL_DLY_STEP | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_CSLVL_CAPTURE_CNT | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_PAD_VREF_CTRL_AC | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PAD_VREF_CTRL_AC | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-28 | RESERVED | R/W | X | |
| 27-24 | PHY_CSLVL_DLY_STEP | R/W | 0h | Sets the delay step size plus 1 during CS training. |
| 23-20 | RESERVED | R/W | X | |
| 19-16 | PHY_CSLVL_CAPTURE_CNT | R/W | 0h | Defines the number of samples to take at each GRP slave delay setting during CS training. |
| 15-12 | RESERVED | R/W | X | |
| 11-0 | PHY_PAD_VREF_CTRL_AC | R/W | 0h | Pad VREF control settings for the address/control. |
DDRSS_PHY_1398 is shown in Figure 8-1568 and described in Table 8-3148.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55D8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LVL_MEAS_DLY_STEP_ENABLE | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_SW_CSLVL_DVW_MIN_EN | ||||||
| R/W-X | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_CSLVL_DVW_MIN | ||||||
| R/W-X | R/W-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_SW_CSLVL_DVW_MIN | |||||||
| R/W-0h | |||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-25 | RESERVED | R/W | X | |
| 24 | PHY_LVL_MEAS_DLY_STEP_ENABLE | R/W | 0h | Enables the phy_adr_meas_dly_step_value to be used instead of the phy_cslvl_dly_step parameter. |
| 23-17 | RESERVED | R/W | X | |
| 16 | PHY_SW_CSLVL_DVW_MIN_EN | R/W | 0h | Enables the software override data valid window size during CS training. |
| 15-9 | RESERVED | R/W | X | |
| 8-0 | PHY_SW_CSLVL_DVW_MIN | R/W | 0h | Sets the software override data valid window size during CS training. |
DDRSS_PHY_1399 is shown in Figure 8-1569 and described in Table 8-3150.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55DCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GRP1_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GRP0_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_GRP1_SLAVE_DELAY_0 | R/W | 0h | Address slice slave delay setting for address slice 1. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_GRP0_SLAVE_DELAY_0 | R/W | 0h | Address slice slave delay setting for address slice 0. |
DDRSS_PHY_1400 is shown in Figure 8-1570 and described in Table 8-3152.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GRP3_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GRP2_SLAVE_DELAY_0 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-16 | PHY_GRP3_SLAVE_DELAY_0 | R/W | 0h | Address slice slave delay setting for address slice 3. |
| 15-11 | RESERVED | R/W | X | |
| 10-0 | PHY_GRP2_SLAVE_DELAY_0 | R/W | 0h | Address slice slave delay setting for address slice 2. |
DDRSS_PHY_1401 is shown in Figure 8-1571 and described in Table 8-3154.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55E4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GRP0_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-11 | RESERVED | R/W | X | |
| 10-0 | PHY_GRP0_SLAVE_DELAY_1 | R/W | 0h | Address slice slave delay setting for address slice 0. |
DDRSS_PHY_1402 is shown in Figure 8-1572 and described in Table 8-3156.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55E8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GRP1_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-11 | RESERVED | R/W | X | |
| 10-0 | PHY_GRP1_SLAVE_DELAY_1 | R/W | 0h | Address slice slave delay setting for address slice 1. |
DDRSS_PHY_1403 is shown in Figure 8-1573 and described in Table 8-3158.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55ECh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GRP2_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-11 | RESERVED | R/W | X | |
| 10-0 | PHY_GRP2_SLAVE_DELAY_1 | R/W | 0h | Address slice slave delay setting for address slice 2. |
DDRSS_PHY_1404 is shown in Figure 8-1574 and described in Table 8-3160.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R/W-X | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_GRP3_SLAVE_DELAY_1 | ||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-11 | RESERVED | R/W | X | |
| 10-0 | PHY_GRP3_SLAVE_DELAY_1 | R/W | 0h | Address slice slave delay setting for address slice 3. |
DDRSS_PHY_1405 is shown in Figure 8-1575 and described in Table 8-3162.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55F4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R/W-X | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R/W-X | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R/W-X | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CLK_DC_CAL_CLK_SEL | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-3 | RESERVED | R/W | X | |
| 2-0 | PHY_CLK_DC_CAL_CLK_SEL | R/W | 0h | Determines DCC CAL clock. |
DDRSS_PHY_1406 is shown in Figure 8-1576 and described in Table 8-3164.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55F8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_FDBK_DRIVE | ||||||||||||||||||||||||||||||
| R/W-X | R/W-FFh | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-0 | PHY_PAD_FDBK_DRIVE | R/W | FFh | Controls drive settings for gate feedback pads. |
DDRSS_PHY_1407 is shown in Figure 8-1577 and described in Table 8-3166.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 55FCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PAD_FDBK_DRIVE2 | ||||||||||||||
| R/W-X | R/W-FFh | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PAD_FDBK_DRIVE2 | |||||||||||||||
| R/W-FFh | |||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PAD_FDBK_DRIVE2 | R/W | FFh | Controls drive settings (enslice/boost) for gate feedback pads. |
DDRSS_PHY_1408 is shown in Figure 8-1578 and described in Table 8-3168.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5600h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_DATA_DRIVE | ||||||||||||||||||||||||||||||
| R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-0 | PHY_PAD_DATA_DRIVE | R/W | 0h | Controls drive settings for data pads. |
DDRSS_PHY_1409 is shown in Figure 8-1579 and described in Table 8-3170.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5604h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PAD_DQS_DRIVE | |||||||||||||||||||||||||||||||
| R/W-0h | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_PAD_DQS_DRIVE | R/W | 0h | Controls drive settings for dqs pads. |
DDRSS_PHY_1410 is shown in Figure 8-1580 and described in Table 8-3172.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5608h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_ADDR_DRIVE | ||||||||||||||||||||||||||||||
| R/W-X | R/W-FFh | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-0 | PHY_PAD_ADDR_DRIVE | R/W | FFh | Controls drive settings for the address/control pads. |
DDRSS_PHY_1411 is shown in Figure 8-1581 and described in Table 8-3174.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 560Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_ADDR_DRIVE2 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-00FFFF00h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-0 | PHY_PAD_ADDR_DRIVE2 | R/W | 00FFFF00h | Controls drive settings for the address/control pads. |
DDRSS_PHY_1412 is shown in Figure 8-1582 and described in Table 8-3176.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5610h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_PAD_CLK_DRIVE | |||||||||||||||||||||||||||||||
| R/W-FFh | |||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-0 | PHY_PAD_CLK_DRIVE | R/W | FFh | Controls drive settings for clock pads. |
DDRSS_PHY_1413 is shown in Figure 8-1583 and described in Table 8-3178.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5614h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_CLK_DRIVE2 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-FFh | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-18 | RESERVED | R/W | X | |
| 17-0 | PHY_PAD_CLK_DRIVE2 | R/W | FFh | Controls drive settings for clock pads. |
DDRSS_PHY_1414 is shown in Figure 8-1584 and described in Table 8-3180.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5618h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_CKE_DRIVE | ||||||||||||||||||||||||||||||
| R/W-X | R/W-FFh | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-0 | PHY_PAD_CKE_DRIVE | R/W | FFh | Controls drive settings for cke pads. |
DDRSS_PHY_1415 is shown in Figure 8-1585 and described in Table 8-3182.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 561Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_CKE_DRIVE2 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-01FFFF00h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-0 | PHY_PAD_CKE_DRIVE2 | R/W | 01FFFF00h | Controls drive settings for cke pads. |
DDRSS_PHY_1416 is shown in Figure 8-1586 and described in Table 8-3184.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5620h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RST_DRIVE | ||||||||||||||||||||||||||||||
| R/W-X | R/W-FFh | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-0 | PHY_PAD_RST_DRIVE | R/W | FFh | Controls drive settings for reset_n pads. |
DDRSS_PHY_1417 is shown in Figure 8-1587 and described in Table 8-3186.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5624h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_RST_DRIVE2 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-01FFFF00h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-0 | PHY_PAD_RST_DRIVE2 | R/W | 01FFFF00h | Controls drive settings for reset_n pads. |
DDRSS_PHY_1418 is shown in Figure 8-1588 and described in Table 8-3188.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5628h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_CS_DRIVE | ||||||||||||||||||||||||||||||
| R/W-X | R/W-FFh | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-0 | PHY_PAD_CS_DRIVE | R/W | FFh | Controls drive settings for cs pads. |
DDRSS_PHY_1419 is shown in Figure 8-1589 and described in Table 8-3190.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 562Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_CS_DRIVE2 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-01FFFF00h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-0 | PHY_PAD_CS_DRIVE2 | R/W | 01FFFF00h | Controls drive settings for cs pads. |
DDRSS_PHY_1420 is shown in Figure 8-1590 and described in Table 8-3192.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5630h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_ODT_DRIVE | ||||||||||||||||||||||||||||||
| R/W-X | R/W-FFh | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-30 | RESERVED | R/W | X | |
| 29-0 | PHY_PAD_ODT_DRIVE | R/W | FFh | Controls drive settings for odt pads. |
DDRSS_PHY_1421 is shown in Figure 8-1591 and described in Table 8-3194.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5634h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PAD_ODT_DRIVE2 | ||||||||||||||||||||||||||||||
| R/W-X | R/W-01FFFF00h | ||||||||||||||||||||||||||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-27 | RESERVED | R/W | X | |
| 26-0 | PHY_PAD_ODT_DRIVE2 | R/W | 01FFFF00h | Controls drive settings for odt pads. |
DDRSS_PHY_1422 is shown in Figure 8-1592 and described in Table 8-3196.
Return to Summary Table.
| Instance | Physical Address |
|---|---|
| COMPUTE_CLUSTER0_CTL_CFG_PHY | 0299 5638h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_CAL_SETTLING_PRD_0 | ||||||
| R/W-X | R/W-0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_CAL_VREF_SWITCH_TIMER_0 | |||||||
| R/W-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_CAL_VREF_SWITCH_TIMER_0 | |||||||
| R/W-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_CAL_CLK_SELECT_0 | ||||||
| R/W-X | R/W-0h | ||||||
| LEGEND: R/W = Read/Write; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | R/W | X | |
| 30-24 | PHY_CAL_SETTLING_PRD_0 | R/W | 0h | Number of clock cycles to extend dfi_phyupd_req after the ack is received for settling of final values |
| 23-8 | PHY_CAL_VREF_SWITCH_TIMER_0 | R/W | 0h | The settling time for a switch in VREF during IO pad calibration. |
| 7-3 | RESERVED | R/W | X | |
| 2-0 | PHY_CAL_CLK_SELECT_0 | R/W | 0h | Pad calibration pad clock frequency select setting for block 0. |