SPRUIU1 User guide

SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1

8.2.5.2 DDR Controller Registers

Table 8-192 lists the memory-mapped registers for the DDR controller. All register offset addresses not listed in Table 8-192 should be considered as reserved locations and the register contents should not be modified.

Table 8-191 DDR Controller Instances

Instance	Base Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0000h

Table 8-192 DDR Controller Registers

Offset	Acronym	Register Name	COMPUTE_CLUSTER0_CTL_CFG Physical Address
0h	DDRSS_CTL_0	DDR Controller Register 0	0299 0000h
4h	DDRSS_CTL_1	DDR Controller Register 1	0299 0004h
8h	DDRSS_CTL_2	DDR Controller Register 2	0299 0008h
Ch	DDRSS_CTL_3	DDR Controller Register 3	0299 000Ch
10h	DDRSS_CTL_4	DDR Controller Register 4	0299 0010h
14h	DDRSS_CTL_5	DDR Controller Register 5	0299 0014h
18h	DDRSS_CTL_6	DDR Controller Register 6	0299 0018h
1Ch	DDRSS_CTL_7	DDR Controller Register 7	0299 001Ch
20h	DDRSS_CTL_8	DDR Controller Register 8	0299 0020h
24h	DDRSS_CTL_9	DDR Controller Register 9	0299 0024h
28h	DDRSS_CTL_10	DDR Controller Register 10	0299 0028h
2Ch	DDRSS_CTL_11	DDR Controller Register 11	0299 002Ch
30h	DDRSS_CTL_12	DDR Controller Register 12	0299 0030h
34h	DDRSS_CTL_13	DDR Controller Register 13	0299 0034h
38h	DDRSS_CTL_14	DDR Controller Register 14	0299 0038h
3Ch	DDRSS_CTL_15	DDR Controller Register 15	0299 003Ch
40h	DDRSS_CTL_16	DDR Controller Register 16	0299 0040h
44h	DDRSS_CTL_17	DDR Controller Register 17	0299 0044h
48h	DDRSS_CTL_18	DDR Controller Register 18	0299 0048h
4Ch	DDRSS_CTL_19	DDR Controller Register 19	0299 004Ch
50h	DDRSS_CTL_20	DDR Controller Register 20	0299 0050h
54h	DDRSS_CTL_21	DDR Controller Register 21	0299 0054h
58h	DDRSS_CTL_22	DDR Controller Register 22	0299 0058h
5Ch	DDRSS_CTL_23	DDR Controller Register 23	0299 005Ch
60h	DDRSS_CTL_24	DDR Controller Register 24	0299 0060h
68h	DDRSS_CTL_26	DDR Controller Register 26	0299 0068h
6Ch	DDRSS_CTL_27	DDR Controller Register 27	0299 006Ch
70h	DDRSS_CTL_28	DDR Controller Register 28	0299 0070h
74h	DDRSS_CTL_29	DDR Controller Register 29	0299 0074h
78h	DDRSS_CTL_30	DDR Controller Register 30	0299 0078h
7Ch	DDRSS_CTL_31	DDR Controller Register 31	0299 007Ch
80h	DDRSS_CTL_32	DDR Controller Register 32	0299 0080h
84h	DDRSS_CTL_33	DDR Controller Register 33	0299 0084h
88h	DDRSS_CTL_34	DDR Controller Register 34	0299 0088h
8Ch	DDRSS_CTL_35	DDR Controller Register 35	0299 008Ch
90h	DDRSS_CTL_36	DDR Controller Register 36	0299 0090h
94h	DDRSS_CTL_37	DDR Controller Register 37	0299 0094h
98h	DDRSS_CTL_38	DDR Controller Register 38	0299 0098h
9Ch	DDRSS_CTL_39	DDR Controller Register 39	0299 009Ch
A0h	DDRSS_CTL_40	DDR Controller Register 40	0299 00A0h
A4h	DDRSS_CTL_41	DDR Controller Register 41	0299 00A4h
A8h	DDRSS_CTL_42	DDR Controller Register 42	0299 00A8h
ACh	DDRSS_CTL_43	DDR Controller Register 43	0299 00ACh
B0h	DDRSS_CTL_44	DDR Controller Register 44	0299 00B0h
B4h	DDRSS_CTL_45	DDR Controller Register 45	0299 00B4h
B8h	DDRSS_CTL_46	DDR Controller Register 46	0299 00B8h
BCh	DDRSS_CTL_47	DDR Controller Register 47	0299 00BCh
C0h	DDRSS_CTL_48	DDR Controller Register 48	0299 00C0h
C4h	DDRSS_CTL_49	DDR Controller Register 49	0299 00C4h
C8h	DDRSS_CTL_50	DDR Controller Register 50	0299 00C8h
CCh	DDRSS_CTL_51	DDR Controller Register 51	0299 00CCh
D0h	DDRSS_CTL_52	DDR Controller Register 52	0299 00D0h
D4h	DDRSS_CTL_53	DDR Controller Register 53	0299 00D4h
D8h	DDRSS_CTL_54	DDR Controller Register 54	0299 00D8h
DCh	DDRSS_CTL_55	DDR Controller Register 55	0299 00DCh
E0h	DDRSS_CTL_56	DDR Controller Register 56	0299 00E0h
E4h	DDRSS_CTL_57	DDR Controller Register 57	0299 00E4h
E8h	DDRSS_CTL_58	DDR Controller Register 58	0299 00E8h
ECh	DDRSS_CTL_59	DDR Controller Register 59	0299 00ECh
F0h	DDRSS_CTL_60	DDR Controller Register 60	0299 00F0h
F4h	DDRSS_CTL_61	DDR Controller Register 61	0299 00F4h
F8h	DDRSS_CTL_62	DDR Controller Register 62	0299 00F8h
FCh	DDRSS_CTL_63	DDR Controller Register 63	0299 00FCh
100h	DDRSS_CTL_64	DDR Controller Register 64	0299 0100h
104h	DDRSS_CTL_65	DDR Controller Register 65	0299 0104h
108h	DDRSS_CTL_66	DDR Controller Register 66	0299 0108h
10Ch	DDRSS_CTL_67	DDR Controller Register 67	0299 010Ch
110h	DDRSS_CTL_68	DDR Controller Register 68	0299 0110h
114h	DDRSS_CTL_69	DDR Controller Register 69	0299 0114h
118h	DDRSS_CTL_70	DDR Controller Register 70	0299 0118h
11Ch	DDRSS_CTL_71	DDR Controller Register 71	0299 011Ch
120h	DDRSS_CTL_72	DDR Controller Register 72	0299 0120h
124h	DDRSS_CTL_73	DDR Controller Register 73	0299 0124h
128h	DDRSS_CTL_74	DDR Controller Register 74	0299 0128h
12Ch	DDRSS_CTL_75	DDR Controller Register 75	0299 012Ch
130h	DDRSS_CTL_76	DDR Controller Register 76	0299 0130h
134h	DDRSS_CTL_77	DDR Controller Register 77	0299 0134h
138h	DDRSS_CTL_78	DDR Controller Register 78	0299 0138h
13Ch	DDRSS_CTL_79	DDR Controller Register 79	0299 013Ch
140h	DDRSS_CTL_80	DDR Controller Register 80	0299 0140h
144h	DDRSS_CTL_81	DDR Controller Register 81	0299 0144h
148h	DDRSS_CTL_82	DDR Controller Register 82	0299 0148h
14Ch	DDRSS_CTL_83	DDR Controller Register 83	0299 014Ch
150h	DDRSS_CTL_84	DDR Controller Register 84	0299 0150h
154h	DDRSS_CTL_85	DDR Controller Register 85	0299 0154h
158h	DDRSS_CTL_86	DDR Controller Register 86	0299 0158h
15Ch	DDRSS_CTL_87	DDR Controller Register 87	0299 015Ch
160h	DDRSS_CTL_88	DDR Controller Register 88	0299 0160h
164h	DDRSS_CTL_89	DDR Controller Register 89	0299 0164h
168h	DDRSS_CTL_90	DDR Controller Register 90	0299 0168h
16Ch	DDRSS_CTL_91	DDR Controller Register 91	0299 016Ch
170h	DDRSS_CTL_92	DDR Controller Register 92	0299 0170h
178h	DDRSS_CTL_94	DDR Controller Register 94	0299 0178h
17Ch	DDRSS_CTL_95	DDR Controller Register 95	0299 017Ch
180h	DDRSS_CTL_96	DDR Controller Register 96	0299 0180h
184h	DDRSS_CTL_97	DDR Controller Register 97	0299 0184h
188h	DDRSS_CTL_98	DDR Controller Register 98	0299 0188h
18Ch	DDRSS_CTL_99	DDR Controller Register 99	0299 018Ch
190h	DDRSS_CTL_100	DDR Controller Register 100	0299 0190h
194h	DDRSS_CTL_101	DDR Controller Register 101	0299 0194h
198h	DDRSS_CTL_102	DDR Controller Register 102	0299 0198h
19Ch	DDRSS_CTL_103	DDR Controller Register 103	0299 019Ch
1A0h	DDRSS_CTL_104	DDR Controller Register 104	0299 01A0h
1A4h	DDRSS_CTL_105	DDR Controller Register 105	0299 01A4h
1A8h	DDRSS_CTL_106	DDR Controller Register 106	0299 01A8h
1ACh	DDRSS_CTL_107	DDR Controller Register 107	0299 01ACh
1B0h	DDRSS_CTL_108	DDR Controller Register 108	0299 01B0h
1B4h	DDRSS_CTL_109	DDR Controller Register 109	0299 01B4h
1B8h	DDRSS_CTL_110	DDR Controller Register 110	0299 01B8h
1BCh	DDRSS_CTL_111	DDR Controller Register 111	0299 01BCh
1C0h	DDRSS_CTL_112	DDR Controller Register 112	0299 01C0h
1C4h	DDRSS_CTL_113	DDR Controller Register 113	0299 01C4h
1C8h	DDRSS_CTL_114	DDR Controller Register 114	0299 01C8h
1CCh	DDRSS_CTL_115	DDR Controller Register 115	0299 01CCh
1D0h	DDRSS_CTL_116	DDR Controller Register 116	0299 01D0h
1D4h	DDRSS_CTL_117	DDR Controller Register 117	0299 01D4h
1D8h	DDRSS_CTL_118	DDR Controller Register 118	0299 01D8h
1DCh	DDRSS_CTL_119	DDR Controller Register 119	0299 01DCh
1E0h	DDRSS_CTL_120	DDR Controller Register 120	0299 01E0h
1E4h	DDRSS_CTL_121	DDR Controller Register 121	0299 01E4h
1E8h	DDRSS_CTL_122	DDR Controller Register 122	0299 01E8h
1ECh	DDRSS_CTL_123	DDR Controller Register 123	0299 01ECh
1F0h	DDRSS_CTL_124	DDR Controller Register 124	0299 01F0h
1F4h	DDRSS_CTL_125	DDR Controller Register 125	0299 01F4h
1F8h	DDRSS_CTL_126	DDR Controller Register 126	0299 01F8h
1FCh	DDRSS_CTL_127	DDR Controller Register 127	0299 01FCh
200h	DDRSS_CTL_128	DDR Controller Register 128	0299 0200h
204h	DDRSS_CTL_129	DDR Controller Register 129	0299 0204h
208h	DDRSS_CTL_130	DDR Controller Register 130	0299 0208h
20Ch	DDRSS_CTL_131	DDR Controller Register 131	0299 020Ch
210h	DDRSS_CTL_132	DDR Controller Register 132	0299 0210h
214h	DDRSS_CTL_133	DDR Controller Register 133	0299 0214h
218h	DDRSS_CTL_134	DDR Controller Register 134	0299 0218h
21Ch	DDRSS_CTL_135	DDR Controller Register 135	0299 021Ch
220h	DDRSS_CTL_136	DDR Controller Register 136	0299 0220h
224h	DDRSS_CTL_137	DDR Controller Register 137	0299 0224h
228h	DDRSS_CTL_138	DDR Controller Register 138	0299 0228h
22Ch	DDRSS_CTL_139	DDR Controller Register 139	0299 022Ch
230h	DDRSS_CTL_140	DDR Controller Register 140	0299 0230h
234h	DDRSS_CTL_141	DDR Controller Register 141	0299 0234h
238h	DDRSS_CTL_142	DDR Controller Register 142	0299 0238h
23Ch	DDRSS_CTL_143	DDR Controller Register 143	0299 023Ch
240h	DDRSS_CTL_144	DDR Controller Register 144	0299 0240h
244h	DDRSS_CTL_145	DDR Controller Register 145	0299 0244h
248h	DDRSS_CTL_146	DDR Controller Register 146	0299 0248h
24Ch	DDRSS_CTL_147	DDR Controller Register 147	0299 024Ch
250h	DDRSS_CTL_148	DDR Controller Register 148	0299 0250h
254h	DDRSS_CTL_149	DDR Controller Register 149	0299 0254h
258h	DDRSS_CTL_150	DDR Controller Register 150	0299 0258h
25Ch	DDRSS_CTL_151	DDR Controller Register 151	0299 025Ch
260h	DDRSS_CTL_152	DDR Controller Register 152	0299 0260h
264h	DDRSS_CTL_153	DDR Controller Register 153	0299 0264h
268h	DDRSS_CTL_154	DDR Controller Register 154	0299 0268h
26Ch	DDRSS_CTL_155	DDR Controller Register 155	0299 026Ch
270h	DDRSS_CTL_156	DDR Controller Register 156	0299 0270h
274h	DDRSS_CTL_157	DDR Controller Register 157	0299 0274h
278h	DDRSS_CTL_158	DDR Controller Register 158	0299 0278h
27Ch	DDRSS_CTL_159	DDR Controller Register 159	0299 027Ch
280h	DDRSS_CTL_160	DDR Controller Register 160	0299 0280h
284h	DDRSS_CTL_161	DDR Controller Register 161	0299 0284h
288h	DDRSS_CTL_162	DDR Controller Register 162	0299 0288h
28Ch	DDRSS_CTL_163	DDR Controller Register 163	0299 028Ch
290h	DDRSS_CTL_164	DDR Controller Register 164	0299 0290h
294h	DDRSS_CTL_165	DDR Controller Register 165	0299 0294h
298h	DDRSS_CTL_166	DDR Controller Register 166	0299 0298h
29Ch	DDRSS_CTL_167	DDR Controller Register 167	0299 029Ch
2A0h	DDRSS_CTL_168	DDR Controller Register 168	0299 02A0h
2A4h	DDRSS_CTL_169	DDR Controller Register 169	0299 02A4h
2A8h	DDRSS_CTL_170	DDR Controller Register 170	0299 02A8h
2ACh	DDRSS_CTL_171	DDR Controller Register 171	0299 02ACh
2B0h	DDRSS_CTL_172	DDR Controller Register 172	0299 02B0h
2B4h	DDRSS_CTL_173	DDR Controller Register 173	0299 02B4h
2B8h	DDRSS_CTL_174	DDR Controller Register 174	0299 02B8h
2BCh	DDRSS_CTL_175	DDR Controller Register 175	0299 02BCh
2C0h	DDRSS_CTL_176	DDR Controller Register 176	0299 02C0h
2C4h	DDRSS_CTL_177	DDR Controller Register 177	0299 02C4h
2C8h	DDRSS_CTL_178	DDR Controller Register 178	0299 02C8h
2CCh	DDRSS_CTL_179	DDR Controller Register 179	0299 02CCh
2D0h	DDRSS_CTL_180	DDR Controller Register 180	0299 02D0h
2D4h	DDRSS_CTL_181	DDR Controller Register 181	0299 02D4h
2D8h	DDRSS_CTL_182	DDR Controller Register 182	0299 02D8h
2DCh	DDRSS_CTL_183	DDR Controller Register 183	0299 02DCh
2E0h	DDRSS_CTL_184	DDR Controller Register 184	0299 02E0h
2E4h	DDRSS_CTL_185	DDR Controller Register 185	0299 02E4h
2E8h	DDRSS_CTL_186	DDR Controller Register 186	0299 02E8h
2ECh	DDRSS_CTL_187	DDR Controller Register 187	0299 02ECh
2F0h	DDRSS_CTL_188	DDR Controller Register 188	0299 02F0h
2F4h	DDRSS_CTL_189	DDR Controller Register 189	0299 02F4h
2F8h	DDRSS_CTL_190	DDR Controller Register 190	0299 02F8h
2FCh	DDRSS_CTL_191	DDR Controller Register 191	0299 02FCh
300h	DDRSS_CTL_192	DDR Controller Register 192	0299 0300h
304h	DDRSS_CTL_193	DDR Controller Register 193	0299 0304h
308h	DDRSS_CTL_194	DDR Controller Register 194	0299 0308h
30Ch	DDRSS_CTL_195	DDR Controller Register 195	0299 030Ch
310h	DDRSS_CTL_196	DDR Controller Register 196	0299 0310h
314h	DDRSS_CTL_197	DDR Controller Register 197	0299 0314h
318h	DDRSS_CTL_198	DDR Controller Register 198	0299 0318h
31Ch	DDRSS_CTL_199	DDR Controller Register 199	0299 031Ch
320h	DDRSS_CTL_200	DDR Controller Register 200	0299 0320h
324h	DDRSS_CTL_201	DDR Controller Register 201	0299 0324h
328h	DDRSS_CTL_202	DDR Controller Register 202	0299 0328h
32Ch	DDRSS_CTL_203	DDR Controller Register 203	0299 032Ch
330h	DDRSS_CTL_204	DDR Controller Register 204	0299 0330h
334h	DDRSS_CTL_205	DDR Controller Register 205	0299 0334h
338h	DDRSS_CTL_206	DDR Controller Register 206	0299 0338h
33Ch	DDRSS_CTL_207	DDR Controller Register 207	0299 033Ch
340h	DDRSS_CTL_208	DDR Controller Register 208	0299 0340h
344h	DDRSS_CTL_209	DDR Controller Register 209	0299 0344h
348h	DDRSS_CTL_210	DDR Controller Register 210	0299 0348h
34Ch	DDRSS_CTL_211	DDR Controller Register 211	0299 034Ch
350h	DDRSS_CTL_212	DDR Controller Register 212	0299 0350h
354h	DDRSS_CTL_213	DDR Controller Register 213	0299 0354h
358h	DDRSS_CTL_214	DDR Controller Register 214	0299 0358h
35Ch	DDRSS_CTL_215	DDR Controller Register 215	0299 035Ch
360h	DDRSS_CTL_216	DDR Controller Register 216	0299 0360h
364h	DDRSS_CTL_217	DDR Controller Register 217	0299 0364h
368h	DDRSS_CTL_218	DDR Controller Register 218	0299 0368h
36Ch	DDRSS_CTL_219	DDR Controller Register 219	0299 036Ch
370h	DDRSS_CTL_220	DDR Controller Register 220	0299 0370h
374h	DDRSS_CTL_221	DDR Controller Register 221	0299 0374h
378h	DDRSS_CTL_222	DDR Controller Register 222	0299 0378h
37Ch	DDRSS_CTL_223	DDR Controller Register 223	0299 037Ch
380h	DDRSS_CTL_224	DDR Controller Register 224	0299 0380h
384h	DDRSS_CTL_225	DDR Controller Register 225	0299 0384h
388h	DDRSS_CTL_226	DDR Controller Register 226	0299 0388h
38Ch	DDRSS_CTL_227	DDR Controller Register 227	0299 038Ch
390h	DDRSS_CTL_228	DDR Controller Register 228	0299 0390h
394h	DDRSS_CTL_229	DDR Controller Register 229	0299 0394h
398h	DDRSS_CTL_230	DDR Controller Register 230	0299 0398h
39Ch	DDRSS_CTL_231	DDR Controller Register 231	0299 039Ch
3A0h	DDRSS_CTL_232	DDR Controller Register 232	0299 03A0h
3A4h	DDRSS_CTL_233	DDR Controller Register 233	0299 03A4h
3A8h	DDRSS_CTL_234	DDR Controller Register 234	0299 03A8h
3ACh	DDRSS_CTL_235	DDR Controller Register 235	0299 03ACh
3B0h	DDRSS_CTL_236	DDR Controller Register 236	0299 03B0h
3B4h	DDRSS_CTL_237	DDR Controller Register 237	0299 03B4h
3B8h	DDRSS_CTL_238	DDR Controller Register 238	0299 03B8h
3BCh	DDRSS_CTL_239	DDR Controller Register 239	0299 03BCh
3C0h	DDRSS_CTL_240	DDR Controller Register 240	0299 03C0h
3C4h	DDRSS_CTL_241	DDR Controller Register 241	0299 03C4h
3C8h	DDRSS_CTL_242	DDR Controller Register 242	0299 03C8h
3CCh	DDRSS_CTL_243	DDR Controller Register 243	0299 03CCh
3D0h	DDRSS_CTL_244	DDR Controller Register 244	0299 03D0h
3D4h	DDRSS_CTL_245	DDR Controller Register 245	0299 03D4h
3D8h	DDRSS_CTL_246	DDR Controller Register 246	0299 03D8h
3DCh	DDRSS_CTL_247	DDR Controller Register 247	0299 03DCh
3E0h	DDRSS_CTL_248	DDR Controller Register 248	0299 03E0h
3E4h	DDRSS_CTL_249	DDR Controller Register 249	0299 03E4h
3E8h	DDRSS_CTL_250	DDR Controller Register 250	0299 03E8h
3ECh	DDRSS_CTL_251	DDR Controller Register 251	0299 03ECh
3F0h	DDRSS_CTL_252	DDR Controller Register 252	0299 03F0h
3F4h	DDRSS_CTL_253	DDR Controller Register 253	0299 03F4h
3F8h	DDRSS_CTL_254	DDR Controller Register 254	0299 03F8h
3FCh	DDRSS_CTL_255	DDR Controller Register 255	0299 03FCh
400h	DDRSS_CTL_256	DDR Controller Register 256	0299 0400h
404h	DDRSS_CTL_257	DDR Controller Register 257	0299 0404h
408h	DDRSS_CTL_258	DDR Controller Register 258	0299 0408h
40Ch	DDRSS_CTL_259	DDR Controller Register 259	0299 040Ch
410h	DDRSS_CTL_260	DDR Controller Register 260	0299 0410h
414h	DDRSS_CTL_261	DDR Controller Register 261	0299 0414h
418h	DDRSS_CTL_262	DDR Controller Register 262	0299 0418h
41Ch	DDRSS_CTL_263	DDR Controller Register 263	0299 041Ch
420h	DDRSS_CTL_264	DDR Controller Register 264	0299 0420h
424h	DDRSS_CTL_265	DDR Controller Register 265	0299 0424h
428h	DDRSS_CTL_266	DDR Controller Register 266	0299 0428h
42Ch	DDRSS_CTL_267	DDR Controller Register 267	0299 042Ch
430h	DDRSS_CTL_268	DDR Controller Register 268	0299 0430h
434h	DDRSS_CTL_269	DDR Controller Register 269	0299 0434h
438h	DDRSS_CTL_270	DDR Controller Register 270	0299 0438h
43Ch	DDRSS_CTL_271	DDR Controller Register 271	0299 043Ch
440h	DDRSS_CTL_272	DDR Controller Register 272	0299 0440h
444h	DDRSS_CTL_273	DDR Controller Register 273	0299 0444h
448h	DDRSS_CTL_274	DDR Controller Register 274	0299 0448h
44Ch	DDRSS_CTL_275	DDR Controller Register 275	0299 044Ch
450h	DDRSS_CTL_276	DDR Controller Register 276	0299 0450h
454h	DDRSS_CTL_277	DDR Controller Register 277	0299 0454h
458h	DDRSS_CTL_278	DDR Controller Register 278	0299 0458h
45Ch	DDRSS_CTL_279	DDR Controller Register 279	0299 045Ch
460h	DDRSS_CTL_280	DDR Controller Register 280	0299 0460h
464h	DDRSS_CTL_281	DDR Controller Register 281	0299 0464h
468h	DDRSS_CTL_282	DDR Controller Register 282	0299 0468h
46Ch	DDRSS_CTL_283	DDR Controller Register 283	0299 046Ch
470h	DDRSS_CTL_284	DDR Controller Register 284	0299 0470h
474h	DDRSS_CTL_285	DDR Controller Register 285	0299 0474h
478h	DDRSS_CTL_286	DDR Controller Register 286	0299 0478h
47Ch	DDRSS_CTL_287	DDR Controller Register 287	0299 047Ch
480h	DDRSS_CTL_288	DDR Controller Register 288	0299 0480h
484h	DDRSS_CTL_289	DDR Controller Register 289	0299 0484h
488h	DDRSS_CTL_290	DDR Controller Register 290	0299 0488h
48Ch	DDRSS_CTL_291	DDR Controller Register 291	0299 048Ch
490h	DDRSS_CTL_292	DDR Controller Register 292	0299 0490h
494h	DDRSS_CTL_293	DDR Controller Register 293	0299 0494h
498h	DDRSS_CTL_294	DDR Controller Register 294	0299 0498h
49Ch	DDRSS_CTL_295	DDR Controller Register 295	0299 049Ch
4A0h	DDRSS_CTL_296	DDR Controller Register 296	0299 04A0h
4A4h	DDRSS_CTL_297	DDR Controller Register 297	0299 04A4h
4A8h	DDRSS_CTL_298	DDR Controller Register 298	0299 04A8h
4ACh	DDRSS_CTL_299	DDR Controller Register 299	0299 04ACh
4B0h	DDRSS_CTL_300	DDR Controller Register 300	0299 04B0h
4B4h	DDRSS_CTL_301	DDR Controller Register 301	0299 04B4h
4B8h	DDRSS_CTL_302	DDR Controller Register 302	0299 04B8h
4BCh	DDRSS_CTL_303	DDR Controller Register 303	0299 04BCh
4C0h	DDRSS_CTL_304	DDR Controller Register 304	0299 04C0h
4C4h	DDRSS_CTL_305	DDR Controller Register 305	0299 04C4h
4C8h	DDRSS_CTL_306	DDR Controller Register 306	0299 04C8h
4CCh	DDRSS_CTL_307	DDR Controller Register 307	0299 04CCh
4D0h	DDRSS_CTL_308	DDR Controller Register 308	0299 04D0h
4D4h	DDRSS_CTL_309	DDR Controller Register 309	0299 04D4h
4D8h	DDRSS_CTL_310	DDR Controller Register 310	0299 04D8h
4DCh	DDRSS_CTL_311	DDR Controller Register 311	0299 04DCh
4E0h	DDRSS_CTL_312	DDR Controller Register 312	0299 04E0h
4E4h	DDRSS_CTL_313	DDR Controller Register 313	0299 04E4h
4E8h	DDRSS_CTL_314	DDR Controller Register 314	0299 04E8h
4ECh	DDRSS_CTL_315	DDR Controller Register 315	0299 04ECh
4F0h	DDRSS_CTL_316	DDR Controller Register 316	0299 04F0h
4F4h	DDRSS_CTL_317	DDR Controller Register 317	0299 04F4h
4F8h	DDRSS_CTL_318	DDR Controller Register 318	0299 04F8h
4FCh	DDRSS_CTL_319	DDR Controller Register 319	0299 04FCh
500h	DDRSS_CTL_320	DDR Controller Register 320	0299 0500h
504h	DDRSS_CTL_321	DDR Controller Register 321	0299 0504h
508h	DDRSS_CTL_322	DDR Controller Register 322	0299 0508h
50Ch	DDRSS_CTL_323	DDR Controller Register 323	0299 050Ch
510h	DDRSS_CTL_324	DDR Controller Register 324	0299 0510h
514h	DDRSS_CTL_325	DDR Controller Register 325	0299 0514h
518h	DDRSS_CTL_326	DDR Controller Register 326	0299 0518h
51Ch	DDRSS_CTL_327	DDR Controller Register 327	0299 051Ch
520h	DDRSS_CTL_328	DDR Controller Register 328	0299 0520h
524h	DDRSS_CTL_329	DDR Controller Register 329	0299 0524h
528h	DDRSS_CTL_330	DDR Controller Register 330	0299 0528h
52Ch	DDRSS_CTL_331	DDR Controller Register 331	0299 052Ch
530h	DDRSS_CTL_332	DDR Controller Register 332	0299 0530h
534h	DDRSS_CTL_333	DDR Controller Register 333	0299 0534h
538h	DDRSS_CTL_334	DDR Controller Register 334	0299 0538h
53Ch	DDRSS_CTL_335	DDR Controller Register 335	0299 053Ch
540h	DDRSS_CTL_336	DDR Controller Register 336	0299 0540h
544h	DDRSS_CTL_337	DDR Controller Register 337	0299 0544h
548h	DDRSS_CTL_338	DDR Controller Register 338	0299 0548h
54Ch	DDRSS_CTL_339	DDR Controller Register 339	0299 054Ch
550h	DDRSS_CTL_340	DDR Controller Register 340	0299 0550h
554h	DDRSS_CTL_341	DDR Controller Register 341	0299 0554h
558h	DDRSS_CTL_342	DDR Controller Register 342	0299 0558h
55Ch	DDRSS_CTL_343	DDR Controller Register 343	0299 055Ch
560h	DDRSS_CTL_344	DDR Controller Register 344	0299 0560h
564h	DDRSS_CTL_345	DDR Controller Register 345	0299 0564h
568h	DDRSS_CTL_346	DDR Controller Register 346	0299 0568h
56Ch	DDRSS_CTL_347	DDR Controller Register 347	0299 056Ch
570h	DDRSS_CTL_348	DDR Controller Register 348	0299 0570h
574h	DDRSS_CTL_349	DDR Controller Register 349	0299 0574h
578h	DDRSS_CTL_350	DDR Controller Register 350	0299 0578h
57Ch	DDRSS_CTL_351	DDR Controller Register 351	0299 057Ch
580h	DDRSS_CTL_352	DDR Controller Register 352	0299 0580h
584h	DDRSS_CTL_353	DDR Controller Register 353	0299 0584h
588h	DDRSS_CTL_354	DDR Controller Register 354	0299 0588h
58Ch	DDRSS_CTL_355	DDR Controller Register 355	0299 058Ch
590h	DDRSS_CTL_356	DDR Controller Register 356	0299 0590h
594h	DDRSS_CTL_357	DDR Controller Register 357	0299 0594h
598h	DDRSS_CTL_358	DDR Controller Register 358	0299 0598h
59Ch	DDRSS_CTL_359	DDR Controller Register 359	0299 059Ch
5A0h	DDRSS_CTL_360	DDR Controller Register 360	0299 05A0h
5A4h	DDRSS_CTL_361	DDR Controller Register 361	0299 05A4h
5A8h	DDRSS_CTL_362	DDR Controller Register 362	0299 05A8h
5ACh	DDRSS_CTL_363	DDR Controller Register 363	0299 05ACh
5B0h	DDRSS_CTL_364	DDR Controller Register 364	0299 05B0h
5B4h	DDRSS_CTL_365	DDR Controller Register 365	0299 05B4h
5B8h	DDRSS_CTL_366	DDR Controller Register 366	0299 05B8h
5BCh	DDRSS_CTL_367	DDR Controller Register 367	0299 05BCh
5C0h	DDRSS_CTL_368	DDR Controller Register 368	0299 05C0h
5C4h	DDRSS_CTL_369	DDR Controller Register 369	0299 05C4h
5C8h	DDRSS_CTL_370	DDR Controller Register 370	0299 05C8h
5CCh	DDRSS_CTL_371	DDR Controller Register 371	0299 05CCh
5D0h	DDRSS_CTL_372	DDR Controller Register 372	0299 05D0h
5D4h	DDRSS_CTL_373	DDR Controller Register 373	0299 05D4h
5D8h	DDRSS_CTL_374	DDR Controller Register 374	0299 05D8h
5DCh	DDRSS_CTL_375	DDR Controller Register 375	0299 05DCh
5E0h	DDRSS_CTL_376	DDR Controller Register 376	0299 05E0h
5E4h	DDRSS_CTL_377	DDR Controller Register 377	0299 05E4h
5E8h	DDRSS_CTL_378	DDR Controller Register 378	0299 05E8h
5ECh	DDRSS_CTL_379	DDR Controller Register 379	0299 05ECh
5F0h	DDRSS_CTL_380	DDR Controller Register 380	0299 05F0h
5F4h	DDRSS_CTL_381	DDR Controller Register 381	0299 05F4h
5F8h	DDRSS_CTL_382	DDR Controller Register 382	0299 05F8h
5FCh	DDRSS_CTL_383	DDR Controller Register 383	0299 05FCh
600h	DDRSS_CTL_384	DDR Controller Register 384	0299 0600h
604h	DDRSS_CTL_385	DDR Controller Register 385	0299 0604h
608h	DDRSS_CTL_386	DDR Controller Register 386	0299 0608h
60Ch	DDRSS_CTL_387	DDR Controller Register 387	0299 060Ch
610h	DDRSS_CTL_388	DDR Controller Register 388	0299 0610h
614h	DDRSS_CTL_389	DDR Controller Register 389	0299 0614h
618h	DDRSS_CTL_390	DDR Controller Register 390	0299 0618h
61Ch	DDRSS_CTL_391	DDR Controller Register 391	0299 061Ch
620h	DDRSS_CTL_392	DDR Controller Register 392	0299 0620h
624h	DDRSS_CTL_393	DDR Controller Register 393	0299 0624h
628h	DDRSS_CTL_394	DDR Controller Register 394	0299 0628h
62Ch	DDRSS_CTL_395	DDR Controller Register 395	0299 062Ch
630h	DDRSS_CTL_396	DDR Controller Register 396	0299 0630h
634h	DDRSS_CTL_397	DDR Controller Register 397	0299 0634h
638h	DDRSS_CTL_398	DDR Controller Register 398	0299 0638h
63Ch	DDRSS_CTL_399	DDR Controller Register 399	0299 063Ch
640h	DDRSS_CTL_400	DDR Controller Register 400	0299 0640h
644h	DDRSS_CTL_401	DDR Controller Register 401	0299 0644h
648h	DDRSS_CTL_402	DDR Controller Register 402	0299 0648h
64Ch	DDRSS_CTL_403	DDR Controller Register 403	0299 064Ch
650h	DDRSS_CTL_404	DDR Controller Register 404	0299 0650h
654h	DDRSS_CTL_405	DDR Controller Register 405	0299 0654h
658h	DDRSS_CTL_406	DDR Controller Register 406	0299 0658h
65Ch	DDRSS_CTL_407	DDR Controller Register 407	0299 065Ch
660h	DDRSS_CTL_408	DDR Controller Register 408	0299 0660h
664h	DDRSS_CTL_409	DDR Controller Register 409	0299 0664h
668h	DDRSS_CTL_410	DDR Controller Register 410	0299 0668h
66Ch	DDRSS_CTL_411	DDR Controller Register 411	0299 066Ch
670h	DDRSS_CTL_412	DDR Controller Register 412	0299 0670h
674h	DDRSS_CTL_413	DDR Controller Register 413	0299 0674h
678h	DDRSS_CTL_414	DDR Controller Register 414	0299 0678h
67Ch	DDRSS_CTL_415	DDR Controller Register 415	0299 067Ch
680h	DDRSS_CTL_416	DDR Controller Register 416	0299 0680h
684h	DDRSS_CTL_417	DDR Controller Register 417	0299 0684h
688h	DDRSS_CTL_418	DDR Controller Register 418	0299 0688h
68Ch	DDRSS_CTL_419	DDR Controller Register 419	0299 068Ch
690h	DDRSS_CTL_420	DDR Controller Register 420	0299 0690h
694h	DDRSS_CTL_421	DDR Controller Register 421	0299 0694h
698h	DDRSS_CTL_422	DDR Controller Register 422	0299 0698h
69Ch	DDRSS_CTL_423	DDR Controller Register 423	0299 069Ch
6A0h	DDRSS_CTL_424	DDR Controller Register 424	0299 06A0h
6A4h	DDRSS_CTL_425	DDR Controller Register 425	0299 06A4h
6A8h	DDRSS_CTL_426	DDR Controller Register 426	0299 06A8h
6ACh	DDRSS_CTL_427	DDR Controller Register 427	0299 06ACh
6B0h	DDRSS_CTL_428	DDR Controller Register 428	0299 06B0h
6B4h	DDRSS_CTL_429	DDR Controller Register 429	0299 06B4h
6B8h	DDRSS_CTL_430	DDR Controller Register 430	0299 06B8h
6D4h	DDRSS_CTL_437	DDR Controller Register 437	0299 06D4h
6D8h	DDRSS_CTL_438	DDR Controller Register 438	0299 06D8h
6DCh	DDRSS_CTL_439	DDR Controller Register 439	0299 06DCh
6E0h	DDRSS_CTL_440	DDR Controller Register 440	0299 06E0h
6E4h	DDRSS_CTL_441	DDR Controller Register 441	0299 06E4h
6E8h	DDRSS_CTL_442	DDR Controller Register 442	0299 06E8h
6ECh	DDRSS_CTL_443	DDR Controller Register 443	0299 06ECh
6F0h	DDRSS_CTL_444	DDR Controller Register 444	0299 06F0h
6FCh	DDRSS_CTL_447	DDR Controller Register 447	0299 06FCh
700h	DDRSS_CTL_448	DDR Controller Register 448	0299 0700h
704h	DDRSS_CTL_449	DDR Controller Register 449	0299 0704h
708h	DDRSS_CTL_450	DDR Controller Register 450	0299 0708h
71Ch	DDRSS_CTL_455	DDR Controller Register 455	0299 071Ch
720h	DDRSS_CTL_456	DDR Controller Register 456	0299 0720h
724h	DDRSS_CTL_457	DDR Controller Register 457	0299 0724h
728h	DDRSS_CTL_458	DDR Controller Register 458	0299 0728h

2.5.2.1 DDRSS_CTL_0 Register (Offset = 0h) [reset = X]

DDRSS_CTL_0 is shown in Figure 8-93 and described in Table 8-194.

Return to Summary Table.

Table 8-193 DDRSS_CTL_0 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0000h

Figure 8-93 DDRSS_CTL_0 Register

31	30	29	28	27	26	25	24
CONTROLLER_ID
R-1046h

23	22	21	20	19	18	17	16
CONTROLLER_ID
R-1046h

15	14	13	12	11	10	9	8
RESERVED				DRAM_CLASS
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED							START
R/W-X							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-194 DDRSS_CTL_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CONTROLLER_ID	R	1046h	Holds the controller product id number. READ-ONLY
15-12	RESERVED	R/W	X
11-8	DRAM_CLASS	R/W	0h	Defines the class of DRAM memory which is connected to the controller. 7h - LPDDR3 Bh - LPDDR4 All other values reserved
7-1	RESERVED	R/W	X
0	START	R/W	0h	Initiate command processing in the controller. Set to 1 to initiate.

2.5.2.2 DDRSS_CTL_1 Register (Offset = 4h) [reset = 67433A40h]

DDRSS_CTL_1 is shown in Figure 8-94 and described in Table 8-196.

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Table 8-195 DDRSS_CTL_1 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0004h

Figure 8-94 DDRSS_CTL_1 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CONTROLLER_VERSION_0
R-67433A40h

LEGEND: R = Read Only; -n = value after reset

Table 8-196 DDRSS_CTL_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CONTROLLER_VERSION_0	R	67433A40h	Holds the controller version id. READ-ONLY

2.5.2.3 DDRSS_CTL_2 Register (Offset = 8h) [reset = 22117A20h]

DDRSS_CTL_2 is shown in Figure 8-95 and described in Table 8-198.

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Table 8-197 DDRSS_CTL_2 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0008h

Figure 8-95 DDRSS_CTL_2 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CONTROLLER_VERSION_1
R-22117A20h

LEGEND: R = Read Only; -n = value after reset

Table 8-198 DDRSS_CTL_2 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CONTROLLER_VERSION_1	R	22117A20h	Holds the controller version id. READ-ONLY

2.5.2.4 DDRSS_CTL_3 Register (Offset = Ch) [reset = X]

DDRSS_CTL_3 is shown in Figure 8-96 and described in Table 8-200.

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Table 8-199 DDRSS_CTL_3 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 000Ch

Figure 8-96 DDRSS_CTL_3 Register

31	30	29	28	27	26	25	24
READ_DATA_FIFO_DEPTH
R-40h

23	22	21	20	19	18	17	16
RESERVED						MAX_CS_REG
R-X						R-2h

15	14	13	12	11	10	9	8
RESERVED				MAX_COL_REG
R-X				R-Ch

7	6	5	4	3	2	1	0
RESERVED			MAX_ROW_REG
R-X			R-11h

LEGEND: R = Read Only; -n = value after reset

Table 8-200 DDRSS_CTL_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	READ_DATA_FIFO_DEPTH	R	40h	Reports the depth of the controller core read data queue. READ-ONLY
23-18	RESERVED	R	X
17-16	MAX_CS_REG	R	2h	Holds the maximum number of chip selects available. READ-ONLY
15-12	RESERVED	R	X
11-8	MAX_COL_REG	R	Ch	Holds the maximum width of column address in DRAMs. READ-ONLY
7-5	RESERVED	R	X
4-0	MAX_ROW_REG	R	11h	Holds the maximum width of memory address bus. READ-ONLY

2.5.2.5 DDRSS_CTL_4 Register (Offset = 10h) [reset = X]

DDRSS_CTL_4 is shown in Figure 8-97 and described in Table 8-202.

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Table 8-201 DDRSS_CTL_4 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0010h

Figure 8-97 DDRSS_CTL_4 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
WRITE_DATA_FIFO_PTR_WIDTH
R-5h

15	14	13	12	11	10	9	8
WRITE_DATA_FIFO_DEPTH
R-20h

7	6	5	4	3	2	1	0
READ_DATA_FIFO_PTR_WIDTH
R-6h

LEGEND: R = Read Only; -n = value after reset

Table 8-202 DDRSS_CTL_4 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X
23-16	WRITE_DATA_FIFO_PTR_WIDTH	R	5h	Reports the width of the controller core write data latency queue pointer. READ-ONLY
15-8	WRITE_DATA_FIFO_DEPTH	R	20h	Reports the depth of the controller core write data latency queue. READ-ONLY
7-0	READ_DATA_FIFO_PTR_WIDTH	R	6h	Reports the width of the controller core read data queue pointer. READ-ONLY

2.5.2.6 DDRSS_CTL_5 Register (Offset = 14h) [reset = 02050020h]

DDRSS_CTL_5 is shown in Figure 8-98 and described in Table 8-204.

Return to Summary Table.

Table 8-203 DDRSS_CTL_5 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0014h

Figure 8-98 DDRSS_CTL_5 Register

31	30	29	28	27	26	25	24
ASYNC_CDC_STAGES
R-2h

23	22	21	20	19	18	17	16
MEMCD_RMODW_FIFO_PTR_WIDTH
R-5h

15	14	13	12	11	10	9	8
MEMCD_RMODW_FIFO_DEPTH
R-20h

7	6	5	4	3	2	1	0
MEMCD_RMODW_FIFO_DEPTH
R-20h

LEGEND: R = Read Only; -n = value after reset

Table 8-204 DDRSS_CTL_5 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	ASYNC_CDC_STAGES	R	2h	Reports the number of synchronizer delays specified for the asynchronous boundary crossings. READ-ONLY
23-16	MEMCD_RMODW_FIFO_PTR_WIDTH	R	5h	Reports the width of the controller core read/modify/write FIFO pointer. READ-ONLY
15-0	MEMCD_RMODW_FIFO_DEPTH	R	20h	Reports the depth of the controller core read/modify/write FIFO. READ-ONLY

2.5.2.7 DDRSS_CTL_6 Register (Offset = 18h) [reset = 03070101h]

DDRSS_CTL_6 is shown in Figure 8-99 and described in Table 8-206.

Return to Summary Table.

Table 8-205 DDRSS_CTL_6 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0018h

Figure 8-99 DDRSS_CTL_6 Register

31	30	29	28	27	26	25	24
AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
R-3h

23	22	21	20	19	18	17	16
AXI0_WR_ARRAY_LOG2_DEPTH
R-7h

15	14	13	12	11	10	9	8
AXI0_RDFIFO_LOG2_DEPTH
R-1h

7	6	5	4	3	2	1	0
AXI0_CMDFIFO_LOG2_DEPTH
R-1h

LEGEND: R = Read Only; -n = value after reset

Table 8-206 DDRSS_CTL_6 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH	R	3h	Reports the depth of the AXI port 0 write command processing FIFO. Value is the log2 value of the depth. READ-ONLY
23-16	AXI0_WR_ARRAY_LOG2_DEPTH	R	7h	Reports the depth of the AXI port 0 write data array. Value is the log2 value of the depth. READ-ONLY
15-8	AXI0_RDFIFO_LOG2_DEPTH	R	1h	Reports the depth of the AXI port 0 read data FIFO. Value is the log2 value of the depth. READ-ONLY
7-0	AXI0_CMDFIFO_LOG2_DEPTH	R	1h	Reports the depth of the AXI port 0 command FIFO. Value is the log2 value of the depth. READ-ONLY

2.5.2.8 DDRSS_CTL_7 Register (Offset = 1Ch) [reset = X]

DDRSS_CTL_7 is shown in Figure 8-100 and described in Table 8-208.

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Table 8-207 DDRSS_CTL_7 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 001Ch

Figure 8-100 DDRSS_CTL_7 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT_F0
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-208 DDRSS_CTL_7 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT_F0	R/W	0h	DRAM TINIT value for frequency copy 0 in cycles.

2.5.2.9 DDRSS_CTL_8 Register (Offset = 20h) [reset = X]

DDRSS_CTL_8 is shown in Figure 8-101 and described in Table 8-210.

Return to Summary Table.

Table 8-209 DDRSS_CTL_8 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0020h

Figure 8-101 DDRSS_CTL_8 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT3_F0
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-210 DDRSS_CTL_8 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT3_F0	R/W	0h	DRAM TINIT3 value for frequency copy 0 in cycles.

2.5.2.10 DDRSS_CTL_9 Register (Offset = 24h) [reset = X]

DDRSS_CTL_9 is shown in Figure 8-102 and described in Table 8-212.

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Table 8-211 DDRSS_CTL_9 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0024h

Figure 8-102 DDRSS_CTL_9 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT4_F0
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-212 DDRSS_CTL_9 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT4_F0	R/W	0h	DRAM TINIT4 value for frequency copy 0 in cycles.

2.5.2.11 DDRSS_CTL_10 Register (Offset = 28h) [reset = X]

DDRSS_CTL_10 is shown in Figure 8-103 and described in Table 8-214.

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Table 8-213 DDRSS_CTL_10 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0028h

Figure 8-103 DDRSS_CTL_10 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT5_F0
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-214 DDRSS_CTL_10 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT5_F0	R/W	0h	DRAM TINIT5 value for frequency copy 0 in cycles.

2.5.2.12 DDRSS_CTL_11 Register (Offset = 2Ch) [reset = X]

DDRSS_CTL_11 is shown in Figure 8-104 and described in Table 8-216.

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Table 8-215 DDRSS_CTL_11 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 002Ch

Figure 8-104 DDRSS_CTL_11 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT_F1
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-216 DDRSS_CTL_11 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT_F1	R/W	0h	DRAM TINIT value for frequency copy 1 in cycles.

2.5.2.13 DDRSS_CTL_12 Register (Offset = 30h) [reset = X]

DDRSS_CTL_12 is shown in Figure 8-105 and described in Table 8-218.

Return to Summary Table.

Table 8-217 DDRSS_CTL_12 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0030h

Figure 8-105 DDRSS_CTL_12 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT3_F1
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-218 DDRSS_CTL_12 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT3_F1	R/W	0h	DRAM TINIT3 value for frequency copy 1 in cycles.

2.5.2.14 DDRSS_CTL_13 Register (Offset = 34h) [reset = X]

DDRSS_CTL_13 is shown in Figure 8-106 and described in Table 8-220.

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Table 8-219 DDRSS_CTL_13 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0034h

Figure 8-106 DDRSS_CTL_13 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT4_F1
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-220 DDRSS_CTL_13 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT4_F1	R/W	0h	DRAM TINIT4 value for frequency copy 1 in cycles.

2.5.2.15 DDRSS_CTL_14 Register (Offset = 38h) [reset = X]

DDRSS_CTL_14 is shown in Figure 8-107 and described in Table 8-222.

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Table 8-221 DDRSS_CTL_14 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0038h

Figure 8-107 DDRSS_CTL_14 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT5_F1
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-222 DDRSS_CTL_14 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT5_F1	R/W	0h	DRAM TINIT5 value for frequency copy 1 in cycles.

2.5.2.16 DDRSS_CTL_15 Register (Offset = 3Ch) [reset = X]

DDRSS_CTL_15 is shown in Figure 8-108 and described in Table 8-224.

Return to Summary Table.

Table 8-223 DDRSS_CTL_15 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 003Ch

Figure 8-108 DDRSS_CTL_15 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT_F2
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-224 DDRSS_CTL_15 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT_F2	R/W	0h	DRAM TINIT value for frequency copy 2 in cycles.

2.5.2.17 DDRSS_CTL_16 Register (Offset = 40h) [reset = X]

DDRSS_CTL_16 is shown in Figure 8-109 and described in Table 8-226.

Return to Summary Table.

Table 8-225 DDRSS_CTL_16 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0040h

Figure 8-109 DDRSS_CTL_16 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT3_F2
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-226 DDRSS_CTL_16 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT3_F2	R/W	0h	DRAM TINIT3 value for frequency copy 2 in cycles.

2.5.2.18 DDRSS_CTL_17 Register (Offset = 44h) [reset = X]

DDRSS_CTL_17 is shown in Figure 8-110 and described in Table 8-228.

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Table 8-227 DDRSS_CTL_17 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0044h

Figure 8-110 DDRSS_CTL_17 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TINIT4_F2
R/W-X								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-228 DDRSS_CTL_17 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-0	TINIT4_F2	R/W	0h	DRAM TINIT4 value for frequency copy 2 in cycles.

2.5.2.19 DDRSS_CTL_18 Register (Offset = 48h) [reset = X]

DDRSS_CTL_18 is shown in Figure 8-111 and described in Table 8-230.

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Table 8-229 DDRSS_CTL_18 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0048h

Figure 8-111 DDRSS_CTL_18 Register

31	30	29	28	27	26	25	24
RESERVED							NO_AUTO_MRR_INIT
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
TINIT5_F2
R/W-0h

15	14	13	12	11	10	9	8
TINIT5_F2
R/W-0h

7	6	5	4	3	2	1	0
TINIT5_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-230 DDRSS_CTL_18 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	NO_AUTO_MRR_INIT	R/W	0h	Disable MRR commands during initialization. Set to 1 to disable.
23-0	TINIT5_F2	R/W	0h	DRAM TINIT5 value for frequency copy 2 in cycles.

2.5.2.20 DDRSS_CTL_19 Register (Offset = 4Ch) [reset = X]

DDRSS_CTL_19 is shown in Figure 8-112 and described in Table 8-232.

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Table 8-231 DDRSS_CTL_19 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 004Ch

Figure 8-112 DDRSS_CTL_19 Register

31	30	29	28	27	26	25	24
RESERVED							ODT_VALUE
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							NO_MRW_INIT
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							DFI_INV_DATA_CS
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							MRR_ERROR_STATUS
R/W-X							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-232 DDRSS_CTL_19 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	ODT_VALUE	R/W	0h	When using LPDDR4, this value will be driven out on the dfi_odt signal.
23-17	RESERVED	R/W	X
16	NO_MRW_INIT	R/W	0h	Disable MRW commands during initialization. Set to 1 to disable.
15-9	RESERVED	R/W	X
8	DFI_INV_DATA_CS	R/W	0h	Forces the inversion of the dfi_rddata_cs_n_X and dfi_wrdata_cs_n_X signals. Set to 1 to force inversion.
7-1	RESERVED	R/W	X
0	MRR_ERROR_STATUS	R	0h	Indicates that an MRR was issued while in self-refresh. Value of 1 indicates a violation. READ-ONLY

2.5.2.21 DDRSS_CTL_20 Register (Offset = 50h) [reset = X]

DDRSS_CTL_20 is shown in Figure 8-113 and described in Table 8-234.

Return to Summary Table.

Table 8-233 DDRSS_CTL_20 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0050h

Figure 8-113 DDRSS_CTL_20 Register

31	30	29	28	27	26	25	24
RESERVED						DFIBUS_FREQ_INIT
R/W-X						R/W-0h

23	22	21	20	19	18	17	16
RESERVED							PHY_INDEP_INIT_MODE
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED		TSREF2PHYMSTR
R/W-X		R/W-0h

7	6	5	4	3	2	1	0
RESERVED							PHY_INDEP_TRAIN_MODE
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-234 DDRSS_CTL_20 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-24	DFIBUS_FREQ_INIT	R/W	0h	Defines the initial DFI bus frequency.
23-17	RESERVED	R/W	X
16	PHY_INDEP_INIT_MODE	R/W	0h	Enable PHY independent initailization mode commands during initialization. Set to 1 to enable.
15-14	RESERVED	R/W	X
13-8	TSREF2PHYMSTR	R/W	0h	Specifies the minimum time after a self-refresh exit command on the DFI bus that the Controller will wait for the PHY to assert the dfi_phymstr_req signal, before completing other commands. Used when the low power control logic is expected to pass control to the PHY for training when exiting SREF.
7-1	RESERVED	R/W	X
0	PHY_INDEP_TRAIN_MODE	R/W	0h	Enable PHY independent training mode commands during initialization. Set to 1 to enable.

2.5.2.22 DDRSS_CTL_21 Register (Offset = 54h) [reset = X]

DDRSS_CTL_21 is shown in Figure 8-114 and described in Table 8-236.

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Table 8-235 DDRSS_CTL_21 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0054h

Figure 8-114 DDRSS_CTL_21 Register

31	30	29	28	27	26	25	24
RESERVED			DFIBUS_FREQ_F2
R/W-X			R/W-0h

23	22	21	20	19	18	17	16
RESERVED			DFIBUS_FREQ_F1
R/W-X			R/W-0h

15	14	13	12	11	10	9	8
RESERVED			DFIBUS_FREQ_F0
R/W-X			R/W-0h

7	6	5	4	3	2	1	0
RESERVED						DFIBUS_BOOT_FREQ
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-236 DDRSS_CTL_21 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	DFIBUS_FREQ_F2	R/W	0h	Defines the DFI bus frequency for frequency copy 2.
23-21	RESERVED	R/W	X
20-16	DFIBUS_FREQ_F1	R/W	0h	Defines the DFI bus frequency for frequency copy 1.
15-13	RESERVED	R/W	X
12-8	DFIBUS_FREQ_F0	R/W	0h	Defines the DFI bus frequency for frequency copy 0.
7-2	RESERVED	R/W	X
1-0	DFIBUS_BOOT_FREQ	R/W	0h	Defines the DFI bus boot frequency.

2.5.2.23 DDRSS_CTL_22 Register (Offset = 58h) [reset = X]

DDRSS_CTL_22 is shown in Figure 8-115 and described in Table 8-238.

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Table 8-237 DDRSS_CTL_22 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0058h

Figure 8-115 DDRSS_CTL_22 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED						FREQ_CHANGE_TYPE_F2
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
RESERVED						FREQ_CHANGE_TYPE_F1
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED						FREQ_CHANGE_TYPE_F0
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-238 DDRSS_CTL_22 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R/W	X
17-16	FREQ_CHANGE_TYPE_F2	R/W	0h	Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation.
15-10	RESERVED	R/W	X
9-8	FREQ_CHANGE_TYPE_F1	R/W	0h	Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation.
7-2	RESERVED	R/W	X
1-0	FREQ_CHANGE_TYPE_F0	R/W	0h	Defines the encoded frequency driven out on the cntrl_freq_change_req_type signal during a frequency change operation.

2.5.2.24 DDRSS_CTL_23 Register (Offset = 5Ch) [reset = 0h]

DDRSS_CTL_23 is shown in Figure 8-116 and described in Table 8-240.

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Table 8-239 DDRSS_CTL_23 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 005Ch

Figure 8-116 DDRSS_CTL_23 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRST_PWRON
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-240 DDRSS_CTL_23 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TRST_PWRON	R/W	0h	Duration of memory reset during power-on initialization.

2.5.2.25 DDRSS_CTL_24 Register (Offset = 60h) [reset = 0h]

DDRSS_CTL_24 is shown in Figure 8-117 and described in Table 8-242.

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Table 8-241 DDRSS_CTL_24 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0060h

Figure 8-117 DDRSS_CTL_24 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CKE_INACTIVE
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-242 DDRSS_CTL_24 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CKE_INACTIVE	R/W	0h	Number of cycles after reset before CKE will be active.

2.5.2.26 DDRSS_CTL_26 Register (Offset = 68h) [reset = X]

DDRSS_CTL_26 is shown in Figure 8-118 and described in Table 8-244.

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Table 8-243 DDRSS_CTL_26 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0068h

Figure 8-118 DDRSS_CTL_26 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED							DQS_OSC_ENABLE
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-0h

7	6	5	4	3	2	1	0
RESERVED
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-244 DDRSS_CTL_26 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R/W	X
16	DQS_OSC_ENABLE	R/W	0h	Enable DQS oscillator measurement function in DRAM. Set to 1 to enable.
15-8	RESERVED	R/W	0h	Reserved
7-0	RESERVED	R/W	0h	Reserved

2.5.2.27 DDRSS_CTL_27 Register (Offset = 6Ch) [reset = X]

DDRSS_CTL_27 is shown in Figure 8-119 and described in Table 8-246.

Return to Summary Table.

Table 8-245 DDRSS_CTL_27 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 006Ch

Figure 8-119 DDRSS_CTL_27 Register

31	30	29	28	27	26	25	24
TOSCO_F0
R/W-0h

23	22	21	20	19	18	17	16
RESERVED				FUNC_VALID_CYCLES
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED	DQS_OSC_PERIOD
R/W-X	R/W-0h

7	6	5	4	3	2	1	0
DQS_OSC_PERIOD
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-246 DDRSS_CTL_27 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TOSCO_F0	R/W	0h	Number of cycles for tOSCO timing parameter for frequency copy 0. tOSCO is the time for the DQS Oscillator measurement to be available in the mode registers.
23-20	RESERVED	R/W	X
19-16	FUNC_VALID_CYCLES	R/W	0h	Number of cycles to hold dfi_function_valid asserted.
15	RESERVED	R/W	X
14-0	DQS_OSC_PERIOD	R/W	0h	Number of cycles to run the oscillator measurement. Must reflect cycles programmed into mode register.

2.5.2.28 DDRSS_CTL_28 Register (Offset = 70h) [reset = 0h]

DDRSS_CTL_28 is shown in Figure 8-120 and described in Table 8-248.

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Table 8-247 DDRSS_CTL_28 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0070h

Figure 8-120 DDRSS_CTL_28 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DQS_OSC_HIGH_THRESHOLD								DQS_OSC_NORM_THRESHOLD
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TOSCO_F2								TOSCO_F1
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-248 DDRSS_CTL_28 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	DQS_OSC_HIGH_THRESHOLD	R/W	0h	Number of long counts until the high priority request is asserted for DQS Oscillator.
23-16	DQS_OSC_NORM_THRESHOLD	R/W	0h	Number of long counts until the normal priority request is asserted for DQS Oscillator.
15-8	TOSCO_F2	R/W	0h	Number of cycles for tOSCO timing parameter for frequency copy 2. tOSCO is the time for the DQS Oscillator measurement to be available in the mode registers.
7-0	TOSCO_F1	R/W	0h	Number of cycles for tOSCO timing parameter for frequency copy 1. tOSCO is the time for the DQS Oscillator measurement to be available in the mode registers.

2.5.2.29 DDRSS_CTL_29 Register (Offset = 74h) [reset = 0h]

DDRSS_CTL_29 is shown in Figure 8-121 and described in Table 8-250.

Return to Summary Table.

Table 8-249 DDRSS_CTL_29 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0074h

Figure 8-121 DDRSS_CTL_29 Register

31	30	29	28	27	26	25	24
OSC_VARIANCE_LIMIT
R/W-0h

23	22	21	20	19	18	17	16
OSC_VARIANCE_LIMIT
R/W-0h

15	14	13	12	11	10	9	8
DQS_OSC_PROMOTE_THRESHOLD
R/W-0h

7	6	5	4	3	2	1	0
DQS_OSC_TIMEOUT
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-250 DDRSS_CTL_29 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	OSC_VARIANCE_LIMIT	R/W	0h	Allowed difference between base value and DQS Oscillator measurement.
15-8	DQS_OSC_PROMOTE_THRESHOLD	R/W	0h	Number of long counts until a software request for the DQS Oscillator is promoted to high priority.
7-0	DQS_OSC_TIMEOUT	R/W	0h	Number of long counts until the timeout is asserted for DQS Oscillator.

2.5.2.30 DDRSS_CTL_30 Register (Offset = 78h) [reset = X]

DDRSS_CTL_30 is shown in Figure 8-122 and described in Table 8-252.

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Table 8-251 DDRSS_CTL_30 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0078h

Figure 8-122 DDRSS_CTL_30 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
OSC_BASE_VALUE_0_CS0
R-0h

15	14	13	12	11	10	9	8
OSC_BASE_VALUE_0_CS0
R-0h

7	6	5	4	3	2	1	0
RESERVED							DQS_OSC_REQUEST
R/W-X							W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-252 DDRSS_CTL_30 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-8	OSC_BASE_VALUE_0_CS0	R	0h	Base value for device 0 on chip 0. READ-ONLY
7-1	RESERVED	R/W	X
0	DQS_OSC_REQUEST	W	0h	Software request for DQS Oscillator measurement function in DRAM. WRITE-ONLY

2.5.2.31 DDRSS_CTL_31 Register (Offset = 7Ch) [reset = 0h]

DDRSS_CTL_31 is shown in Figure 8-123 and described in Table 8-254.

Return to Summary Table.

Table 8-253 DDRSS_CTL_31 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 007Ch

Figure 8-123 DDRSS_CTL_31 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSC_BASE_VALUE_2_CS0
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSC_BASE_VALUE_1_CS0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-254 DDRSS_CTL_31 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	OSC_BASE_VALUE_2_CS0	R	0h	Base value for device 2 on chip 0. READ-ONLY
15-0	OSC_BASE_VALUE_1_CS0	R	0h	Base value for device 1 on chip 0. READ-ONLY

2.5.2.32 DDRSS_CTL_32 Register (Offset = 80h) [reset = 0h]

DDRSS_CTL_32 is shown in Figure 8-124 and described in Table 8-256.

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Table 8-255 DDRSS_CTL_32 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0080h

Figure 8-124 DDRSS_CTL_32 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSC_BASE_VALUE_0_CS1
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSC_BASE_VALUE_3_CS0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-256 DDRSS_CTL_32 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	OSC_BASE_VALUE_0_CS1	R	0h	Base value for device 0 on chip 1. READ-ONLY
15-0	OSC_BASE_VALUE_3_CS0	R	0h	Base value for device 3 on chip 0. READ-ONLY

2.5.2.33 DDRSS_CTL_33 Register (Offset = 84h) [reset = 0h]

DDRSS_CTL_33 is shown in Figure 8-125 and described in Table 8-258.

Return to Summary Table.

Table 8-257 DDRSS_CTL_33 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0084h

Figure 8-125 DDRSS_CTL_33 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSC_BASE_VALUE_2_CS1
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSC_BASE_VALUE_1_CS1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-258 DDRSS_CTL_33 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	OSC_BASE_VALUE_2_CS1	R	0h	Base value for device 2 on chip 1. READ-ONLY
15-0	OSC_BASE_VALUE_1_CS1	R	0h	Base value for device 1 on chip 1. READ-ONLY

2.5.2.34 DDRSS_CTL_34 Register (Offset = 88h) [reset = X]

DDRSS_CTL_34 is shown in Figure 8-126 and described in Table 8-260.

Return to Summary Table.

Table 8-259 DDRSS_CTL_34 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0088h

Figure 8-126 DDRSS_CTL_34 Register

31	30	29	28	27	26	25	24
RESERVED	WRLAT_F0
R/W-X	R/W-0h

23	22	21	20	19	18	17	16
RESERVED	CASLAT_LIN_F0
R/W-X	R/W-0h

15	14	13	12	11	10	9	8
OSC_BASE_VALUE_3_CS1
R-0h

7	6	5	4	3	2	1	0
OSC_BASE_VALUE_3_CS1
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-260 DDRSS_CTL_34 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30-24	WRLAT_F0	R/W	0h	DRAM WRLAT value for frequency copy 0 in cycles.
23	RESERVED	R/W	X
22-16	CASLAT_LIN_F0	R/W	0h	Sets latency from read command send to data receive from/to controller for frequency copy 0. Bit (0) is half-cycle increment and the upper bits define memory CAS latency for the controller.
15-0	OSC_BASE_VALUE_3_CS1	R	0h	Base value for device 3 on chip 1. READ-ONLY

2.5.2.35 DDRSS_CTL_35 Register (Offset = 8Ch) [reset = X]

DDRSS_CTL_35 is shown in Figure 8-127 and described in Table 8-262.

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Table 8-261 DDRSS_CTL_35 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 008Ch

Figure 8-127 DDRSS_CTL_35 Register

31	30	29	28	27	26	25	24
RESERVED	WRLAT_F2
R/W-X	R/W-0h

23	22	21	20	19	18	17	16
RESERVED	CASLAT_LIN_F2
R/W-X	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	WRLAT_F1
R/W-X	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	CASLAT_LIN_F1
R/W-X	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-262 DDRSS_CTL_35 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30-24	WRLAT_F2	R/W	0h	DRAM WRLAT value for frequency copy 2 in cycles.
23	RESERVED	R/W	X
22-16	CASLAT_LIN_F2	R/W	0h	Sets latency from read command send to data receive from/to controller for frequency copy 2. Bit (0) is half-cycle increment and the upper bits define memory CAS latency for the controller.
15	RESERVED	R/W	X
14-8	WRLAT_F1	R/W	0h	DRAM WRLAT value for frequency copy 1 in cycles.
7	RESERVED	R/W	X
6-0	CASLAT_LIN_F1	R/W	0h	Sets latency from read command send to data receive from/to controller for frequency copy 1. Bit (0) is half-cycle increment and the upper bits define memory CAS latency for the controller.

2.5.2.36 DDRSS_CTL_36 Register (Offset = 90h) [reset = X]

DDRSS_CTL_36 is shown in Figure 8-128 and described in Table 8-264.

Return to Summary Table.

Table 8-263 DDRSS_CTL_36 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0090h

Figure 8-128 DDRSS_CTL_36 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
TRRD_F0
R/W-0h

15	14	13	12	11	10	9	8
RESERVED			TCCD
R/W-X			R/W-0h

7	6	5	4	3	2	1	0
RESERVED					TBST_INT_INTERVAL
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-264 DDRSS_CTL_36 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-16	TRRD_F0	R/W	0h	DRAM TRRD value for frequency copy 0 in cycles.
15-13	RESERVED	R/W	X
12-8	TCCD	R/W	0h	DRAM CAS-to-CAS value in cycles.
7-3	RESERVED	R/W	X
2-0	TBST_INT_INTERVAL	R/W	0h	DRAM burst interrupt interval value in cycles.

2.5.2.37 DDRSS_CTL_37 Register (Offset = 94h) [reset = X]

DDRSS_CTL_37 is shown in Figure 8-129 and described in Table 8-266.

Return to Summary Table.

Table 8-265 DDRSS_CTL_37 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0094h

Figure 8-129 DDRSS_CTL_37 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED		TWTR_F0						TRAS_MIN_F0
R/W-X		R/W-0h						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED							TRC_F0
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-266 DDRSS_CTL_37 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R/W	X
29-24	TWTR_F0	R/W	0h	DRAM TWTR value for frequency copy 0 in cycles.
23-16	TRAS_MIN_F0	R/W	0h	DRAM TRAS_MIN value for frequency copy 0 in cycles.
15-9	RESERVED	R/W	X
8-0	TRC_F0	R/W	0h	DRAM TRC value for frequency copy 0 in cycles.

2.5.2.38 DDRSS_CTL_38 Register (Offset = 98h) [reset = X]

DDRSS_CTL_38 is shown in Figure 8-130 and described in Table 8-268.

Return to Summary Table.

Table 8-267 DDRSS_CTL_38 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0098h

Figure 8-130 DDRSS_CTL_38 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TRRD_F1								RESERVED							TFAW_F0
R/W-0h								R/W-X							R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TFAW_F0								TRP_F0
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-268 DDRSS_CTL_38 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TRRD_F1	R/W	0h	DRAM TRRD value for frequency copy 1 in cycles.
23-17	RESERVED	R/W	X
16-8	TFAW_F0	R/W	0h	DRAM TFAW value for frequency copy 0 in cycles.
7-0	TRP_F0	R/W	0h	DRAM TRP value for frequency copy 0 in cycles.

2.5.2.39 DDRSS_CTL_39 Register (Offset = 9Ch) [reset = X]

DDRSS_CTL_39 is shown in Figure 8-131 and described in Table 8-270.

Return to Summary Table.

Table 8-269 DDRSS_CTL_39 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 009Ch

Figure 8-131 DDRSS_CTL_39 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED		TWTR_F1						TRAS_MIN_F1
R/W-X		R/W-0h						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED							TRC_F1
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-270 DDRSS_CTL_39 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R/W	X
29-24	TWTR_F1	R/W	0h	DRAM TWTR value for frequency copy 1 in cycles.
23-16	TRAS_MIN_F1	R/W	0h	DRAM TRAS_MIN value for frequency copy 1 in cycles.
15-9	RESERVED	R/W	X
8-0	TRC_F1	R/W	0h	DRAM TRC value for frequency copy 1 in cycles.

2.5.2.40 DDRSS_CTL_40 Register (Offset = A0h) [reset = X]

DDRSS_CTL_40 is shown in Figure 8-132 and described in Table 8-272.

Return to Summary Table.

Table 8-271 DDRSS_CTL_40 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00A0h

Figure 8-132 DDRSS_CTL_40 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TRRD_F2								RESERVED							TFAW_F1
R/W-0h								R/W-X							R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TFAW_F1								TRP_F1
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-272 DDRSS_CTL_40 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TRRD_F2	R/W	0h	DRAM TRRD value for frequency copy 2 in cycles.
23-17	RESERVED	R/W	X
16-8	TFAW_F1	R/W	0h	DRAM TFAW value for frequency copy 1 in cycles.
7-0	TRP_F1	R/W	0h	DRAM TRP value for frequency copy 1 in cycles.

2.5.2.41 DDRSS_CTL_41 Register (Offset = A4h) [reset = X]

DDRSS_CTL_41 is shown in Figure 8-133 and described in Table 8-274.

Return to Summary Table.

Table 8-273 DDRSS_CTL_41 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00A4h

Figure 8-133 DDRSS_CTL_41 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED		TWTR_F2						TRAS_MIN_F2
R/W-X		R/W-0h						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED							TRC_F2
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-274 DDRSS_CTL_41 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R/W	X
29-24	TWTR_F2	R/W	0h	DRAM TWTR value for frequency copy 2 in cycles.
23-16	TRAS_MIN_F2	R/W	0h	DRAM TRAS_MIN value for frequency copy 2 in cycles.
15-9	RESERVED	R/W	X
8-0	TRC_F2	R/W	0h	DRAM TRC value for frequency copy 2 in cycles.

2.5.2.42 DDRSS_CTL_42 Register (Offset = A8h) [reset = X]

DDRSS_CTL_42 is shown in Figure 8-134 and described in Table 8-276.

Return to Summary Table.

Table 8-275 DDRSS_CTL_42 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00A8h

Figure 8-134 DDRSS_CTL_42 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED		TCCDMW						RESERVED							TFAW_F2
R/W-X		R/W-20h						R/W-X							R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TFAW_F2								TRP_F2
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-276 DDRSS_CTL_42 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R/W	X
29-24	TCCDMW	R/W	20h	DRAM CAS-to-CAS masked write value in cycles.
23-17	RESERVED	R/W	X
16-8	TFAW_F2	R/W	0h	DRAM TFAW value for frequency copy 2 in cycles.
7-0	TRP_F2	R/W	0h	DRAM TRP value for frequency copy 2 in cycles.

2.5.2.43 DDRSS_CTL_43 Register (Offset = ACh) [reset = X]

DDRSS_CTL_43 is shown in Figure 8-135 and described in Table 8-278.

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Table 8-277 DDRSS_CTL_43 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00ACh

Figure 8-135 DDRSS_CTL_43 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								TMOD_F0								TMRD_F0								TRTP_F0
R/W-X								R/W-0h								R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-278 DDRSS_CTL_43 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-16	TMOD_F0	R/W	0h	DRAM TMOD value for frequency copy 0 in cycles.
15-8	TMRD_F0	R/W	0h	DRAM TMRD value for frequency copy 0 in cycles.
7-0	TRTP_F0	R/W	0h	DRAM TRTP value for frequency copy 0 in cycles.

2.5.2.44 DDRSS_CTL_44 Register (Offset = B0h) [reset = X]

DDRSS_CTL_44 is shown in Figure 8-136 and described in Table 8-280.

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Table 8-279 DDRSS_CTL_44 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00B0h

Figure 8-136 DDRSS_CTL_44 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			TCKE_F0					RESERVED							TRAS_MAX_F0
R/W-X			R/W-0h					R/W-X							R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRAS_MAX_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-280 DDRSS_CTL_44 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TCKE_F0	R/W	0h	Minimum CKE pulse width for frequency copy 0.
23-17	RESERVED	R/W	X
16-0	TRAS_MAX_F0	R/W	0h	DRAM TRAS_MAX value for frequency copy 0 in cycles.

2.5.2.45 DDRSS_CTL_45 Register (Offset = B4h) [reset = 0h]

DDRSS_CTL_45 is shown in Figure 8-137 and described in Table 8-282.

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Table 8-281 DDRSS_CTL_45 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00B4h

Figure 8-137 DDRSS_CTL_45 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TMOD_F1								TMRD_F1
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRTP_F1								TCKESR_F0
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-282 DDRSS_CTL_45 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TMOD_F1	R/W	0h	DRAM TMOD value for frequency copy 1 in cycles.
23-16	TMRD_F1	R/W	0h	DRAM TMRD value for frequency copy 1 in cycles.
15-8	TRTP_F1	R/W	0h	DRAM TRTP value for frequency copy 1 in cycles.
7-0	TCKESR_F0	R/W	0h	Minimum CKE low pulse width during a self-refresh for frequency copy 0.

2.5.2.46 DDRSS_CTL_46 Register (Offset = B8h) [reset = X]

DDRSS_CTL_46 is shown in Figure 8-138 and described in Table 8-284.

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Table 8-283 DDRSS_CTL_46 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00B8h

Figure 8-138 DDRSS_CTL_46 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			TCKE_F1					RESERVED							TRAS_MAX_F1
R/W-X			R/W-0h					R/W-X							R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRAS_MAX_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-284 DDRSS_CTL_46 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TCKE_F1	R/W	0h	Minimum CKE pulse width for frequency copy 1.
23-17	RESERVED	R/W	X
16-0	TRAS_MAX_F1	R/W	0h	DRAM TRAS_MAX value for frequency copy 1 in cycles.

2.5.2.47 DDRSS_CTL_47 Register (Offset = BCh) [reset = 0h]

DDRSS_CTL_47 is shown in Figure 8-139 and described in Table 8-286.

Return to Summary Table.

Table 8-285 DDRSS_CTL_47 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00BCh

Figure 8-139 DDRSS_CTL_47 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TMOD_F2								TMRD_F2
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRTP_F2								TCKESR_F1
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-286 DDRSS_CTL_47 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TMOD_F2	R/W	0h	DRAM TMOD value for frequency copy 2 in cycles.
23-16	TMRD_F2	R/W	0h	DRAM TMRD value for frequency copy 2 in cycles.
15-8	TRTP_F2	R/W	0h	DRAM TRTP value for frequency copy 2 in cycles.
7-0	TCKESR_F1	R/W	0h	Minimum CKE low pulse width during a self-refresh for frequency copy 1.

2.5.2.48 DDRSS_CTL_48 Register (Offset = C0h) [reset = X]

DDRSS_CTL_48 is shown in Figure 8-140 and described in Table 8-288.

Return to Summary Table.

Table 8-287 DDRSS_CTL_48 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00C0h

Figure 8-140 DDRSS_CTL_48 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			TCKE_F2					RESERVED							TRAS_MAX_F2
R/W-X			R/W-0h					R/W-X							R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRAS_MAX_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-288 DDRSS_CTL_48 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TCKE_F2	R/W	0h	Minimum CKE pulse width for frequency copy 2.
23-17	RESERVED	R/W	X
16-0	TRAS_MAX_F2	R/W	0h	DRAM TRAS_MAX value for frequency copy 2 in cycles.

2.5.2.49 DDRSS_CTL_49 Register (Offset = C4h) [reset = X]

DDRSS_CTL_49 is shown in Figure 8-141 and described in Table 8-290.

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Table 8-289 DDRSS_CTL_49 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00C4h

Figure 8-141 DDRSS_CTL_49 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED					RESERVED			RESERVED					RESERVED
R/W-X					R/W-0h			R/W-X					R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED					TPPD			TCKESR_F2
R/W-X					R/W-4h			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-290 DDRSS_CTL_49 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-24	RESERVED	R/W	0h	Reserved
23-19	RESERVED	R/W	X
18-16	RESERVED	R/W	0h	Reserved
15-11	RESERVED	R/W	X
10-8	TPPD	R/W	4h	DRAM TPPD value in cycles.
7-0	TCKESR_F2	R/W	0h	Minimum CKE low pulse width during a self-refresh for frequency copy 2.

2.5.2.50 DDRSS_CTL_50 Register (Offset = C8h) [reset = X]

DDRSS_CTL_50 is shown in Figure 8-142 and described in Table 8-292.

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Table 8-291 DDRSS_CTL_50 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00C8h

Figure 8-142 DDRSS_CTL_50 Register

31	30	29	28	27	26	25	24
TRCD_F1
R/W-0h

23	22	21	20	19	18	17	16
TWR_F0
R/W-0h

15	14	13	12	11	10	9	8
TRCD_F0
R/W-0h

7	6	5	4	3	2	1	0
RESERVED							WRITEINTERP
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-292 DDRSS_CTL_50 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TRCD_F1	R/W	0h	DRAM TRCD value for frequency copy 1 in cycles.
23-16	TWR_F0	R/W	0h	DRAM TWR value for frequency copy 0 in cycles.
15-8	TRCD_F0	R/W	0h	DRAM TRCD value for frequency copy 0 in cycles.
7-1	RESERVED	R/W	X
0	WRITEINTERP	R/W	0h	Allow controller to interrupt a write burst to the DRAMs with a read command. Set to 1 to allow interruption.

2.5.2.51 DDRSS_CTL_51 Register (Offset = CCh) [reset = X]

DDRSS_CTL_51 is shown in Figure 8-143 and described in Table 8-294.

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Table 8-293 DDRSS_CTL_51 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00CCh

Figure 8-143 DDRSS_CTL_51 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				TMRR				TWR_F2								TRCD_F2								TWR_F1
R/W-X				R/W-0h				R/W-0h								R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-294 DDRSS_CTL_51 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	TMRR	R/W	0h	DRAM TMRR value in cycles.
23-16	TWR_F2	R/W	0h	DRAM TWR value for frequency copy 2 in cycles.
15-8	TRCD_F2	R/W	0h	DRAM TRCD value for frequency copy 2 in cycles.
7-0	TWR_F1	R/W	0h	DRAM TWR value for frequency copy 1 in cycles.

2.5.2.52 DDRSS_CTL_52 Register (Offset = D0h) [reset = X]

DDRSS_CTL_52 is shown in Figure 8-144 and described in Table 8-296.

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Table 8-295 DDRSS_CTL_52 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00D0h

Figure 8-144 DDRSS_CTL_52 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED		TCAMRD						RESERVED						TCAENT
R/W-X		R/W-0h						R/W-X						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TCAENT								RESERVED			TCACKEL
R/W-0h								R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-296 DDRSS_CTL_52 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R/W	X
29-24	TCAMRD	R/W	0h	DRAM TCAMRD value in cycles.
23-18	RESERVED	R/W	X
17-8	TCAENT	R/W	0h	DRAM TCAENT value in cycles.
7-5	RESERVED	R/W	X
4-0	TCACKEL	R/W	0h	DRAM TCACKEL value in cycles.

2.5.2.53 DDRSS_CTL_53 Register (Offset = D4h) [reset = X]

DDRSS_CTL_53 is shown in Figure 8-145 and described in Table 8-298.

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Table 8-297 DDRSS_CTL_53 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00D4h

Figure 8-145 DDRSS_CTL_53 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			TMRZ_F1					RESERVED			TMRZ_F0
R/W-X			R/W-0h					R/W-X			R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCACKEH					RESERVED			TCAEXT
R/W-X			R/W-0h					R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-298 DDRSS_CTL_53 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TMRZ_F1	R/W	0h	DRAM TMRZ value for frequency copy 1 in cycles.
23-21	RESERVED	R/W	X
20-16	TMRZ_F0	R/W	0h	DRAM TMRZ value for frequency copy 0 in cycles.
15-13	RESERVED	R/W	X
12-8	TCACKEH	R/W	0h	DRAM TCACKEH value in cycles.
7-5	RESERVED	R/W	X
4-0	TCAEXT	R/W	0h	DRAM TCAEXT value in cycles.

2.5.2.54 DDRSS_CTL_54 Register (Offset = D8h) [reset = X]

DDRSS_CTL_54 is shown in Figure 8-146 and described in Table 8-300.

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Table 8-299 DDRSS_CTL_54 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00D8h

Figure 8-146 DDRSS_CTL_54 Register

31	30	29	28	27	26	25	24
RESERVED							TRAS_LOCKOUT
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							CONCURRENTAP
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							AP
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED			TMRZ_F2
R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-300 DDRSS_CTL_54 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	TRAS_LOCKOUT	R/W	0h	IF the DRAM supports it, this allows the controller to execute auto pre-charge commands before the TRAS_MIN parameter expires. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	CONCURRENTAP	R/W	0h	IF the DRAM supports it, this allows the controller to issue commands to other banks while a bank is in auto pre-charge. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	AP	R/W	0h	Enable auto pre-charge mode of controller. Set to 1 to enable.
7-5	RESERVED	R/W	X
4-0	TMRZ_F2	R/W	0h	DRAM TMRZ value for frequency copy 2 in cycles.

2.5.2.55 DDRSS_CTL_55 Register (Offset = DCh) [reset = X]

DDRSS_CTL_55 is shown in Figure 8-147 and described in Table 8-302.

Return to Summary Table.

Table 8-301 DDRSS_CTL_55 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00DCh

Figure 8-147 DDRSS_CTL_55 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			BSTLEN					TDAL_F2
R/W-X			R/W-2h					R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDAL_F1								TDAL_F0
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-302 DDRSS_CTL_55 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	BSTLEN	R/W	2h	Encoded burst length sent to DRAMs during initialization. Program to 1 for BL2, program to 2 for BL4, program to 3 for BL8, program to 4 for BL16, or program to 5 for BL32. All other settings are reserved.
23-16	TDAL_F2	R/W	0h	DRAM TDAL value for frequency copy 2 in cycles.
15-8	TDAL_F1	R/W	0h	DRAM TDAL value for frequency copy 1 in cycles.
7-0	TDAL_F0	R/W	0h	DRAM TDAL value for frequency copy 0 in cycles.

2.5.2.56 DDRSS_CTL_56 Register (Offset = E0h) [reset = 0h]

DDRSS_CTL_56 is shown in Figure 8-148 and described in Table 8-304.

Return to Summary Table.

Table 8-303 DDRSS_CTL_56 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00E0h

Figure 8-148 DDRSS_CTL_56 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TRP_AB_F0_1								TRP_AB_F2_0
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRP_AB_F1_0								TRP_AB_F0_0
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-304 DDRSS_CTL_56 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TRP_AB_F0_1	R/W	0h	DRAM TRP all bank value for frequency copy 0 in cycles for chip select 1.
23-16	TRP_AB_F2_0	R/W	0h	DRAM TRP all bank value for frequency copy 2 in cycles for chip select 0.
15-8	TRP_AB_F1_0	R/W	0h	DRAM TRP all bank value for frequency copy 1 in cycles for chip select 0.
7-0	TRP_AB_F0_0	R/W	0h	DRAM TRP all bank value for frequency copy 0 in cycles for chip select 0.

2.5.2.57 DDRSS_CTL_57 Register (Offset = E4h) [reset = X]

DDRSS_CTL_57 is shown in Figure 8-149 and described in Table 8-306.

Return to Summary Table.

Table 8-305 DDRSS_CTL_57 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00E4h

Figure 8-149 DDRSS_CTL_57 Register

31	30	29	28	27	26	25	24
RESERVED						RESERVED
R/W-X						R/W-0h

23	22	21	20	19	18	17	16
RESERVED							REG_DIMM_ENABLE
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
TRP_AB_F2_1
R/W-0h

7	6	5	4	3	2	1	0
TRP_AB_F1_1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-306 DDRSS_CTL_57 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-24	RESERVED	R/W	0h	Reserved
23-17	RESERVED	R/W	X
16	REG_DIMM_ENABLE	R/W	0h	Enable registered DIMM operation of the controller. Set to 1 to enable.
15-8	TRP_AB_F2_1	R/W	0h	DRAM TRP all bank value for frequency copy 2 in cycles for chip select 1.
7-0	TRP_AB_F1_1	R/W	0h	DRAM TRP all bank value for frequency copy 1 in cycles for chip select 1.

2.5.2.58 DDRSS_CTL_58 Register (Offset = E8h) [reset = X]

DDRSS_CTL_58 is shown in Figure 8-150 and described in Table 8-308.

Return to Summary Table.

Table 8-307 DDRSS_CTL_58 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00E8h

Figure 8-150 DDRSS_CTL_58 Register

31	30	29	28	27	26	25	24
RESERVED							NO_MEMORY_DM
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							RESERVED
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							OPTIMAL_RMODW_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED	RESERVED
R/W-X	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-308 DDRSS_CTL_58 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	NO_MEMORY_DM	R/W	0h	Indicates that the external DRAM does not support DM masking. Set to 1 for no DM masking at the DRAM.
23-17	RESERVED	R/W	X
16	RESERVED	R/W	0h	Reserved
15-9	RESERVED	R/W	X
8	OPTIMAL_RMODW_EN	R/W	0h	Enables optimized RMODW logic in the controller. A value of 1 enables optimized RMODW operation. All RMODW operations are still supported in a non-optimal manner when the value is 0.
7	RESERVED	R/W	X
6-0	RESERVED	R/W	0h	Reserved

2.5.2.59 DDRSS_CTL_59 Register (Offset = ECh) [reset = X]

DDRSS_CTL_59 is shown in Figure 8-151 and described in Table 8-310.

Return to Summary Table.

Table 8-309 DDRSS_CTL_59 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00ECh

Figure 8-151 DDRSS_CTL_59 Register

31	30	29	28	27	26	25	24
RESERVED					RESERVED
R/W-X					R/W-0h

23	22	21	20	19	18	17	16
RESERVED							TREF_ENABLE
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							AREF_STATUS
R/W-X							R-0h

7	6	5	4	3	2	1	0
RESERVED							AREFRESH
R/W-X							W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-310 DDRSS_CTL_59 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-24	RESERVED	R/W	0h	Reserved
23-17	RESERVED	R/W	X
16	TREF_ENABLE	R/W	0h	Issue auto-refresh commands to the DRAMs at the interval defined in the TREF parameter. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	AREF_STATUS	R	0h	Indicates a SR error associated with the AREF interrupt. Value of 1 indicates a violation. READ-ONLY
7-1	RESERVED	R/W	X
0	AREFRESH	W	0h	Initiate auto-refresh at the end of the current burst boundary. Set to 1 to trigger. WRITE-ONLY

2.5.2.60 DDRSS_CTL_60 Register (Offset = F0h) [reset = X]

DDRSS_CTL_60 is shown in Figure 8-152 and described in Table 8-312.

Return to Summary Table.

Table 8-311 DDRSS_CTL_60 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00F0h

Figure 8-152 DDRSS_CTL_60 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED						TRFC_F0
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
TRFC_F0
R/W-0h

7	6	5	4	3	2	1	0
RESERVED		CS_COMPARISON_FOR_REFRESH_DEPTH
R/W-X		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-312 DDRSS_CTL_60 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R/W	X
17-8	TRFC_F0	R/W	0h	DRAM TRFC value for frequency copy 0 in cycles.
7-6	RESERVED	R/W	X
5-0	CS_COMPARISON_FOR_REFRESH_DEPTH	R/W	0h	Defines the number of entries of the command queue that the refresh logic will consider for sending a refresh command. A non-zero value limits the decode to a subset of the full command pipeline.

2.5.2.61 DDRSS_CTL_61 Register (Offset = F4h) [reset = X]

DDRSS_CTL_61 is shown in Figure 8-153 and described in Table 8-314.

Return to Summary Table.

Table 8-313 DDRSS_CTL_61 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00F4h

Figure 8-153 DDRSS_CTL_61 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												TREF_F0
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-314 DDRSS_CTL_61 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	TREF_F0	R/W	0h	DRAM TREF value for frequency copy 0 in cycles.

2.5.2.62 DDRSS_CTL_62 Register (Offset = F8h) [reset = X]

DDRSS_CTL_62 is shown in Figure 8-154 and described in Table 8-316.

Return to Summary Table.

Table 8-315 DDRSS_CTL_62 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00F8h

Figure 8-154 DDRSS_CTL_62 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																						TRFC_F1
R/W-X																						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-316 DDRSS_CTL_62 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R/W	X
9-0	TRFC_F1	R/W	0h	DRAM TRFC value for frequency copy 1 in cycles.

2.5.2.63 DDRSS_CTL_63 Register (Offset = FCh) [reset = X]

DDRSS_CTL_63 is shown in Figure 8-155 and described in Table 8-318.

Return to Summary Table.

Table 8-317 DDRSS_CTL_63 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 00FCh

Figure 8-155 DDRSS_CTL_63 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												TREF_F1
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-318 DDRSS_CTL_63 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	TREF_F1	R/W	0h	DRAM TREF value for frequency copy 1 in cycles.

2.5.2.64 DDRSS_CTL_64 Register (Offset = 100h) [reset = X]

DDRSS_CTL_64 is shown in Figure 8-156 and described in Table 8-320.

Return to Summary Table.

Table 8-319 DDRSS_CTL_64 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0100h

Figure 8-156 DDRSS_CTL_64 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																						TRFC_F2
R/W-X																						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-320 DDRSS_CTL_64 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R/W	X
9-0	TRFC_F2	R/W	0h	DRAM TRFC value for frequency copy 2 in cycles.

2.5.2.65 DDRSS_CTL_65 Register (Offset = 104h) [reset = X]

DDRSS_CTL_65 is shown in Figure 8-157 and described in Table 8-322.

Return to Summary Table.

Table 8-321 DDRSS_CTL_65 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0104h

Figure 8-157 DDRSS_CTL_65 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												TREF_F2
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-322 DDRSS_CTL_65 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	TREF_F2	R/W	0h	DRAM TREF value for frequency copy 2 in cycles.

2.5.2.66 DDRSS_CTL_66 Register (Offset = 108h) [reset = X]

DDRSS_CTL_66 is shown in Figure 8-158 and described in Table 8-324.

Return to Summary Table.

Table 8-323 DDRSS_CTL_66 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0108h

Figure 8-158 DDRSS_CTL_66 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												TREF_INTERVAL
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-324 DDRSS_CTL_66 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	TREF_INTERVAL	R/W	0h	Defines the cycles between refreshes to different chip selects.

2.5.2.67 DDRSS_CTL_67 Register (Offset = 10Ch) [reset = X]

DDRSS_CTL_67 is shown in Figure 8-159 and described in Table 8-326.

Return to Summary Table.

Table 8-325 DDRSS_CTL_67 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 010Ch

Figure 8-159 DDRSS_CTL_67 Register

31	30	29	28	27	26	25	24
RESERVED						TRFC_PB_F0
R/W-X						R/W-0h

23	22	21	20	19	18	17	16
TRFC_PB_F0
R/W-0h

15	14	13	12	11	10	9	8
RESERVED							PBR_NUMERIC_ORDER
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							PBR_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-326 DDRSS_CTL_67 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TRFC_PB_F0	R/W	0h	DRAM TRFC_PB value for frequency copy 0 in cycles.
15-9	RESERVED	R/W	X
8	PBR_NUMERIC_ORDER	R/W	0h	Enables the PBR to run REFpb commands in numeric bank order (0,1,2,3, etc.) When disabled, the order may be modified if supported by the memory type. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	PBR_EN	R/W	0h	Enables the per-bank refresh feature. Set to 1 to enable.

2.5.2.68 DDRSS_CTL_68 Register (Offset = 110h) [reset = X]

DDRSS_CTL_68 is shown in Figure 8-160 and described in Table 8-328.

Return to Summary Table.

Table 8-327 DDRSS_CTL_68 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0110h

Figure 8-160 DDRSS_CTL_68 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TRFC_PB_F1										TREFI_PB_F0
R/W-X						R/W-0h										R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-328 DDRSS_CTL_68 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TRFC_PB_F1	R/W	0h	DRAM TRFC_PB value for frequency copy 1 in cycles.
15-0	TREFI_PB_F0	R/W	0h	DRAM TREFI_PB value for frequency copy 0 in cycles.

2.5.2.69 DDRSS_CTL_69 Register (Offset = 114h) [reset = X]

DDRSS_CTL_69 is shown in Figure 8-161 and described in Table 8-330.

Return to Summary Table.

Table 8-329 DDRSS_CTL_69 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0114h

Figure 8-161 DDRSS_CTL_69 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TRFC_PB_F2										TREFI_PB_F1
R/W-X						R/W-0h										R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-330 DDRSS_CTL_69 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TRFC_PB_F2	R/W	0h	DRAM TRFC_PB value for frequency copy 2 in cycles.
15-0	TREFI_PB_F1	R/W	0h	DRAM TREFI_PB value for frequency copy 1 in cycles.

2.5.2.70 DDRSS_CTL_70 Register (Offset = 118h) [reset = 0h]

DDRSS_CTL_70 is shown in Figure 8-162 and described in Table 8-332.

Return to Summary Table.

Table 8-331 DDRSS_CTL_70 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0118h

Figure 8-162 DDRSS_CTL_70 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PBR_MAX_BANK_WAIT
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TREFI_PB_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-332 DDRSS_CTL_70 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	PBR_MAX_BANK_WAIT	R/W	0h	Defines the maximum number of cycles that the PBR module will wait for Strategy to release the target bank until the PBR will assert the inhibit and close the target bank.
15-0	TREFI_PB_F2	R/W	0h	DRAM TREFI_PB value for frequency copy 2 in cycles.

2.5.2.71 DDRSS_CTL_71 Register (Offset = 11Ch) [reset = X]

DDRSS_CTL_71 is shown in Figure 8-163 and described in Table 8-334.

Return to Summary Table.

Table 8-333 DDRSS_CTL_71 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 011Ch

Figure 8-163 DDRSS_CTL_71 Register

31	30	29	28	27	26	25	24
RESERVED			AREF_PBR_CONT_DIS_THRESHOLD
R/W-X			R/W-0h

23	22	21	20	19	18	17	16
RESERVED			AREF_PBR_CONT_EN_THRESHOLD
R/W-X			R/W-0h

15	14	13	12	11	10	9	8
RESERVED							PBR_CONT_REQ_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED				PBR_BANK_SELECT_DELAY
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-334 DDRSS_CTL_71 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	AREF_PBR_CONT_DIS_THRESHOLD	R/W	0h	Sets the auto-refresh request count threshold when the PBR continuous refresh request enable will be deasserted.
23-21	RESERVED	R/W	X
20-16	AREF_PBR_CONT_EN_THRESHOLD	R/W	0h	Sets the auto-refresh request count threshold when the PBR continuous refresh request enable will be asserted.
15-9	RESERVED	R/W	X
8	PBR_CONT_REQ_EN	R/W	0h	Enables the per-bank refresh continuous request feature. Set to 1 to enable.
7-4	RESERVED	R/W	X
3-0	PBR_BANK_SELECT_DELAY	R/W	0h	Defines the PBR bank select to command delay, the time from bank selection to when the command queue bank selection logic is guaranteed to have blocked the bank.

2.5.2.72 DDRSS_CTL_72 Register (Offset = 120h) [reset = 0h]

DDRSS_CTL_72 is shown in Figure 8-164 and described in Table 8-336.

Return to Summary Table.

Table 8-335 DDRSS_CTL_72 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0120h

Figure 8-164 DDRSS_CTL_72 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TPDEX_F1																TPDEX_F0
R/W-0h																R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-336 DDRSS_CTL_72 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TPDEX_F1	R/W	0h	DRAM TPDEX value for frequency copy 1 in cycles.
15-0	TPDEX_F0	R/W	0h	DRAM TPDEX value for frequency copy 0 in cycles.

2.5.2.73 DDRSS_CTL_73 Register (Offset = 124h) [reset = 0h]

DDRSS_CTL_73 is shown in Figure 8-165 and described in Table 8-338.

Return to Summary Table.

Table 8-337 DDRSS_CTL_73 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0124h

Figure 8-165 DDRSS_CTL_73 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TMRRI_F1								TMRRI_F0								TPDEX_F2
R/W-0h								R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-338 DDRSS_CTL_73 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TMRRI_F1	R/W	0h	DRAM TMRRI value for frequency copy 1 in cycles.
23-16	TMRRI_F0	R/W	0h	DRAM TMRRI value for frequency copy 0 in cycles.
15-0	TPDEX_F2	R/W	0h	DRAM TPDEX value for frequency copy 2 in cycles.

2.5.2.74 DDRSS_CTL_74 Register (Offset = 128h) [reset = X]

DDRSS_CTL_74 is shown in Figure 8-166 and described in Table 8-340.

Return to Summary Table.

Table 8-339 DDRSS_CTL_74 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0128h

Figure 8-166 DDRSS_CTL_74 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			TCKEHCS_F0					RESERVED			TCKELCS_F0
R/W-X			R/W-0h					R/W-X			R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCSCKE_F0					TMRRI_F2
R/W-X			R/W-0h					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-340 DDRSS_CTL_74 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TCKEHCS_F0	R/W	0h	DRAM TCKEHCS value for frequency copy 0 in cycles.
23-21	RESERVED	R/W	X
20-16	TCKELCS_F0	R/W	0h	DRAM TCKELCS value for frequency copy 0 in cycles.
15-13	RESERVED	R/W	X
12-8	TCSCKE_F0	R/W	0h	DRAM TCSCKE value for frequency copy 0 in cycles.
7-0	TMRRI_F2	R/W	0h	DRAM TMRRI value for frequency copy 2 in cycles.

2.5.2.75 DDRSS_CTL_75 Register (Offset = 12Ch) [reset = X]

DDRSS_CTL_75 is shown in Figure 8-167 and described in Table 8-342.

Return to Summary Table.

Table 8-341 DDRSS_CTL_75 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 012Ch

Figure 8-167 DDRSS_CTL_75 Register

31	30	29	28	27	26	25	24
RESERVED			TCSCKE_F1
R/W-X			R/W-0h

23	22	21	20	19	18	17	16
RESERVED							CA_DEFAULT_VAL_F0
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED				TZQCKE_F0
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED			TMRWCKEL_F0
R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-342 DDRSS_CTL_75 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TCSCKE_F1	R/W	0h	DRAM TCSCKE value for frequency copy 1 in cycles.
23-17	RESERVED	R/W	X
16	CA_DEFAULT_VAL_F0	R/W	0h	Defines how unused address/command bits are driven for frequency copy 0. Set to 1 to use last value or clear to 0 to drive low.
15-12	RESERVED	R/W	X
11-8	TZQCKE_F0	R/W	0h	DRAM TZQCKE value for frequency copy 0 in cycles.
7-5	RESERVED	R/W	X
4-0	TMRWCKEL_F0	R/W	0h	DRAM TMRWCKEL value for frequency copy 0 in cycles.

2.5.2.76 DDRSS_CTL_76 Register (Offset = 130h) [reset = X]

DDRSS_CTL_76 is shown in Figure 8-168 and described in Table 8-344.

Return to Summary Table.

Table 8-343 DDRSS_CTL_76 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0130h

Figure 8-168 DDRSS_CTL_76 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				TZQCKE_F1				RESERVED			TMRWCKEL_F1
R/W-X				R/W-0h				R/W-X			R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCKEHCS_F1					RESERVED			TCKELCS_F1
R/W-X			R/W-0h					R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-344 DDRSS_CTL_76 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	TZQCKE_F1	R/W	0h	DRAM TZQCKE value for frequency copy 1 in cycles.
23-21	RESERVED	R/W	X
20-16	TMRWCKEL_F1	R/W	0h	DRAM TMRWCKEL value for frequency copy 1 in cycles.
15-13	RESERVED	R/W	X
12-8	TCKEHCS_F1	R/W	0h	DRAM TCKEHCS value for frequency copy 1 in cycles.
7-5	RESERVED	R/W	X
4-0	TCKELCS_F1	R/W	0h	DRAM TCKELCS value for frequency copy 1 in cycles.

2.5.2.77 DDRSS_CTL_77 Register (Offset = 134h) [reset = X]

DDRSS_CTL_77 is shown in Figure 8-169 and described in Table 8-346.

Return to Summary Table.

Table 8-345 DDRSS_CTL_77 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0134h

Figure 8-169 DDRSS_CTL_77 Register

31	30	29	28	27	26	25	24
RESERVED			TCKEHCS_F2
R/W-X			R/W-0h

23	22	21	20	19	18	17	16
RESERVED			TCKELCS_F2
R/W-X			R/W-0h

15	14	13	12	11	10	9	8
RESERVED			TCSCKE_F2
R/W-X			R/W-0h

7	6	5	4	3	2	1	0
RESERVED							CA_DEFAULT_VAL_F1
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-346 DDRSS_CTL_77 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TCKEHCS_F2	R/W	0h	DRAM TCKEHCS value for frequency copy 2 in cycles.
23-21	RESERVED	R/W	X
20-16	TCKELCS_F2	R/W	0h	DRAM TCKELCS value for frequency copy 2 in cycles.
15-13	RESERVED	R/W	X
12-8	TCSCKE_F2	R/W	0h	DRAM TCSCKE value for frequency copy 2 in cycles.
7-1	RESERVED	R/W	X
0	CA_DEFAULT_VAL_F1	R/W	0h	Defines how unused address/command bits are driven for frequency copy 1. Set to 1 to use last value or clear to 0 to drive low.

2.5.2.78 DDRSS_CTL_78 Register (Offset = 138h) [reset = X]

DDRSS_CTL_78 is shown in Figure 8-170 and described in Table 8-348.

Return to Summary Table.

Table 8-347 DDRSS_CTL_78 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0138h

Figure 8-170 DDRSS_CTL_78 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED							CA_DEFAULT_VAL_F2
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED				TZQCKE_F2
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED			TMRWCKEL_F2
R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-348 DDRSS_CTL_78 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R/W	X
16	CA_DEFAULT_VAL_F2	R/W	0h	Defines how unused address/command bits are driven for frequency copy 2. Set to 1 to use last value or clear to 0 to drive low.
15-12	RESERVED	R/W	X
11-8	TZQCKE_F2	R/W	0h	DRAM TZQCKE value for frequency copy 2 in cycles.
7-5	RESERVED	R/W	X
4-0	TMRWCKEL_F2	R/W	0h	DRAM TMRWCKEL value for frequency copy 2 in cycles.

2.5.2.79 DDRSS_CTL_79 Register (Offset = 13Ch) [reset = 0h]

DDRSS_CTL_79 is shown in Figure 8-171 and described in Table 8-350.

Return to Summary Table.

Table 8-349 DDRSS_CTL_79 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 013Ch

Figure 8-171 DDRSS_CTL_79 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXSNR_F0																TXSR_F0
R/W-0h																R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-350 DDRSS_CTL_79 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TXSNR_F0	R/W	0h	DRAM TXSNR value for frequency copy 0 in cycles.
15-0	TXSR_F0	R/W	0h	DRAM TXSR value for frequency copy 0 in cycles.

2.5.2.80 DDRSS_CTL_80 Register (Offset = 140h) [reset = 0h]

DDRSS_CTL_80 is shown in Figure 8-172 and described in Table 8-352.

Return to Summary Table.

Table 8-351 DDRSS_CTL_80 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0140h

Figure 8-172 DDRSS_CTL_80 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXSNR_F1																TXSR_F1
R/W-0h																R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-352 DDRSS_CTL_80 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TXSNR_F1	R/W	0h	DRAM TXSNR value for frequency copy 1 in cycles.
15-0	TXSR_F1	R/W	0h	DRAM TXSR value for frequency copy 1 in cycles.

2.5.2.81 DDRSS_CTL_81 Register (Offset = 144h) [reset = 0h]

DDRSS_CTL_81 is shown in Figure 8-173 and described in Table 8-354.

Return to Summary Table.

Table 8-353 DDRSS_CTL_81 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0144h

Figure 8-173 DDRSS_CTL_81 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TXSNR_F2																TXSR_F2
R/W-0h																R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-354 DDRSS_CTL_81 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TXSNR_F2	R/W	0h	DRAM TXSNR value for frequency copy 2 in cycles.
15-0	TXSR_F2	R/W	0h	DRAM TXSR value for frequency copy 2 in cycles.

2.5.2.82 DDRSS_CTL_82 Register (Offset = 148h) [reset = X]

DDRSS_CTL_82 is shown in Figure 8-174 and described in Table 8-356.

Return to Summary Table.

Table 8-355 DDRSS_CTL_82 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0148h

Figure 8-174 DDRSS_CTL_82 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TSR_F0								RESERVED			TCKCKEL_F0
R/W-0h								R/W-X			R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCKEHCMD_F0					RESERVED			TCKELCMD_F0
R/W-X			R/W-0h					R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-356 DDRSS_CTL_82 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TSR_F0	R/W	0h	DRAM TSR value for frequency copy 0 in cycles.
23-21	RESERVED	R/W	X
20-16	TCKCKEL_F0	R/W	0h	DRAM TCKCKEL value for frequency copy 0 in cycles.
15-13	RESERVED	R/W	X
12-8	TCKEHCMD_F0	R/W	0h	DRAM TCKEHCMD value for frequency copy 0 in cycles.
7-5	RESERVED	R/W	X
4-0	TCKELCMD_F0	R/W	0h	DRAM TCKELCMD value for frequency copy 0 in cycles.

2.5.2.83 DDRSS_CTL_83 Register (Offset = 14Ch) [reset = X]

DDRSS_CTL_83 is shown in Figure 8-175 and described in Table 8-358.

Return to Summary Table.

Table 8-357 DDRSS_CTL_83 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 014Ch

Figure 8-175 DDRSS_CTL_83 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			TCMDCKE_F0					RESERVED			TCSCKEH_F0
R/W-X			R/W-0h					R/W-X			R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCKELPD_F0					RESERVED					TESCKE_F0
R/W-X			R/W-0h					R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-358 DDRSS_CTL_83 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TCMDCKE_F0	R/W	0h	DRAM TCMDCKE value for frequency copy 0 in cycles.
23-21	RESERVED	R/W	X
20-16	TCSCKEH_F0	R/W	0h	DRAM TCSCKEH value for frequency copy 0 in cycles.
15-13	RESERVED	R/W	X
12-8	TCKELPD_F0	R/W	0h	DRAM TCKELPD value for frequency copy 0 in cycles.
7-3	RESERVED	R/W	X
2-0	TESCKE_F0	R/W	0h	DRAM TESCKE value for frequency copy 0 in cycles.

2.5.2.84 DDRSS_CTL_84 Register (Offset = 150h) [reset = X]

DDRSS_CTL_84 is shown in Figure 8-176 and described in Table 8-360.

Return to Summary Table.

Table 8-359 DDRSS_CTL_84 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0150h

Figure 8-176 DDRSS_CTL_84 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TSR_F1								RESERVED			TCKCKEL_F1
R/W-0h								R/W-X			R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCKEHCMD_F1					RESERVED			TCKELCMD_F1
R/W-X			R/W-0h					R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-360 DDRSS_CTL_84 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TSR_F1	R/W	0h	DRAM TSR value for frequency copy 1 in cycles.
23-21	RESERVED	R/W	X
20-16	TCKCKEL_F1	R/W	0h	DRAM TCKCKEL value for frequency copy 1 in cycles.
15-13	RESERVED	R/W	X
12-8	TCKEHCMD_F1	R/W	0h	DRAM TCKEHCMD value for frequency copy 1 in cycles.
7-5	RESERVED	R/W	X
4-0	TCKELCMD_F1	R/W	0h	DRAM TCKELCMD value for frequency copy 1 in cycles.

2.5.2.85 DDRSS_CTL_85 Register (Offset = 154h) [reset = X]

DDRSS_CTL_85 is shown in Figure 8-177 and described in Table 8-362.

Return to Summary Table.

Table 8-361 DDRSS_CTL_85 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0154h

Figure 8-177 DDRSS_CTL_85 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			TCMDCKE_F1					RESERVED			TCSCKEH_F1
R/W-X			R/W-0h					R/W-X			R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCKELPD_F1					RESERVED					TESCKE_F1
R/W-X			R/W-0h					R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-362 DDRSS_CTL_85 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TCMDCKE_F1	R/W	0h	DRAM TCMDCKE value for frequency copy 1 in cycles.
23-21	RESERVED	R/W	X
20-16	TCSCKEH_F1	R/W	0h	DRAM TCSCKEH value for frequency copy 1 in cycles.
15-13	RESERVED	R/W	X
12-8	TCKELPD_F1	R/W	0h	DRAM TCKELPD value for frequency copy 1 in cycles.
7-3	RESERVED	R/W	X
2-0	TESCKE_F1	R/W	0h	DRAM TESCKE value for frequency copy 1 in cycles.

2.5.2.86 DDRSS_CTL_86 Register (Offset = 158h) [reset = X]

DDRSS_CTL_86 is shown in Figure 8-178 and described in Table 8-364.

Return to Summary Table.

Table 8-363 DDRSS_CTL_86 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0158h

Figure 8-178 DDRSS_CTL_86 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TSR_F2								RESERVED			TCKCKEL_F2
R/W-0h								R/W-X			R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCKEHCMD_F2					RESERVED			TCKELCMD_F2
R/W-X			R/W-0h					R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-364 DDRSS_CTL_86 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TSR_F2	R/W	0h	DRAM TSR value for frequency copy 2 in cycles.
23-21	RESERVED	R/W	X
20-16	TCKCKEL_F2	R/W	0h	DRAM TCKCKEL value for frequency copy 2 in cycles.
15-13	RESERVED	R/W	X
12-8	TCKEHCMD_F2	R/W	0h	DRAM TCKEHCMD value for frequency copy 2 in cycles.
7-5	RESERVED	R/W	X
4-0	TCKELCMD_F2	R/W	0h	DRAM TCKELCMD value for frequency copy 2 in cycles.

2.5.2.87 DDRSS_CTL_87 Register (Offset = 15Ch) [reset = X]

DDRSS_CTL_87 is shown in Figure 8-179 and described in Table 8-366.

Return to Summary Table.

Table 8-365 DDRSS_CTL_87 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 015Ch

Figure 8-179 DDRSS_CTL_87 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			TCMDCKE_F2					RESERVED			TCSCKEH_F2
R/W-X			R/W-0h					R/W-X			R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCKELPD_F2					RESERVED					TESCKE_F2
R/W-X			R/W-0h					R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-366 DDRSS_CTL_87 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TCMDCKE_F2	R/W	0h	DRAM TCMDCKE value for frequency copy 2 in cycles.
23-21	RESERVED	R/W	X
20-16	TCSCKEH_F2	R/W	0h	DRAM TCSCKEH value for frequency copy 2 in cycles.
15-13	RESERVED	R/W	X
12-8	TCKELPD_F2	R/W	0h	DRAM TCKELPD value for frequency copy 2 in cycles.
7-3	RESERVED	R/W	X
2-0	TESCKE_F2	R/W	0h	DRAM TESCKE value for frequency copy 2 in cycles.

2.5.2.88 DDRSS_CTL_88 Register (Offset = 160h) [reset = X]

DDRSS_CTL_88 is shown in Figure 8-180 and described in Table 8-368.

Return to Summary Table.

Table 8-367 DDRSS_CTL_88 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0160h

Figure 8-180 DDRSS_CTL_88 Register

31	30	29	28	27	26	25	24
RESERVED					CKE_DELAY
R/W-X					R/W-0h

23	22	21	20	19	18	17	16
RESERVED							ENABLE_QUICK_SREFRESH
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							RESERVED
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							PWRUP_SREFRESH_EXIT
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-368 DDRSS_CTL_88 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-24	CKE_DELAY	R/W	0h	Additional cycles to delay CKE for status reporting.
23-17	RESERVED	R/W	X
16	ENABLE_QUICK_SREFRESH	R/W	0h	Allow user to interrupt memory initialization to enter self-refresh mode. Set to 1 to allow interruption.
15-9	RESERVED	R/W	X
8	RESERVED	R/W	0h	Reserved
7-1	RESERVED	R/W	X
0	PWRUP_SREFRESH_EXIT	R/W	0h	Allow powerup via self-refresh instead of full memory initialization. Set to 1 to enable.

2.5.2.89 DDRSS_CTL_89 Register (Offset = 164h) [reset = X]

DDRSS_CTL_89 is shown in Figure 8-181 and described in Table 8-370.

Return to Summary Table.

Table 8-369 DDRSS_CTL_89 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0164h

Figure 8-181 DDRSS_CTL_89 Register

31	30	29	28	27	26	25	24
RESERVED							DFS_CALVL_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							DFS_ZQ_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED						DFS_STATUS
R/W-X						R-0h

7	6	5	4	3	2	1	0
RESERVED			RESERVED
R/W-X			W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-370 DDRSS_CTL_89 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	DFS_CALVL_EN	R/W	0h	Enables CA training during a DFS exit. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	DFS_ZQ_EN	R/W	0h	Enables ZQ calibration during a DFS exit. Set to 1 to enable.
15-10	RESERVED	R/W	X
9-8	DFS_STATUS	R	0h	Holds the error associated with the DFS interrupt. Bit (0) set indicates an illegal command and bit (1) set indicates that a shutdown occurred during DFS. READ-ONLY
7-5	RESERVED	R/W	X
4-0	RESERVED	W	0h	Reserved

2.5.2.90 DDRSS_CTL_90 Register (Offset = 168h) [reset = X]

DDRSS_CTL_90 is shown in Figure 8-182 and described in Table 8-372.

Return to Summary Table.

Table 8-371 DDRSS_CTL_90 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0168h

Figure 8-182 DDRSS_CTL_90 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED							DFS_RDLVL_GATE_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							DFS_RDLVL_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							DFS_WRLVL_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-372 DDRSS_CTL_90 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R/W	X
16	DFS_RDLVL_GATE_EN	R/W	0h	Enables read gate training during a DFS exit. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	DFS_RDLVL_EN	R/W	0h	Enables read data eye training during a DFS exit. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	DFS_WRLVL_EN	R/W	0h	Enables write leveling during a DFS exit. Set to 1 to enable.

2.5.2.91 DDRSS_CTL_91 Register (Offset = 16Ch) [reset = 0h]

DDRSS_CTL_91 is shown in Figure 8-183 and described in Table 8-374.

Return to Summary Table.

Table 8-373 DDRSS_CTL_91 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 016Ch

Figure 8-183 DDRSS_CTL_91 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DFS_PROMOTE_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DFS_PROMOTE_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-374 DDRSS_CTL_91 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	DFS_PROMOTE_THRESHOLD_F1	R/W	0h	DFS promotion number of long counts until the high priority request is asserted for frequency copy 1. Applies to SW and HW DFS commands.
15-0	DFS_PROMOTE_THRESHOLD_F0	R/W	0h	DFS promotion number of long counts until the high priority request is asserted for frequency copy 0. Applies to SW and HW DFS commands.

2.5.2.92 DDRSS_CTL_92 Register (Offset = 170h) [reset = X]

DDRSS_CTL_92 is shown in Figure 8-184 and described in Table 8-376.

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Table 8-375 DDRSS_CTL_92 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0170h

Figure 8-184 DDRSS_CTL_92 Register

31	30	29	28	27	26	25	24
RESERVED					RESERVED
R/W-X					R/W-0h

23	22	21	20	19	18	17	16
RESERVED					ZQ_STATUS_LOG
R/W-X					R-0h

15	14	13	12	11	10	9	8
DFS_PROMOTE_THRESHOLD_F2
R/W-0h

7	6	5	4	3	2	1	0
DFS_PROMOTE_THRESHOLD_F2
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-376 DDRSS_CTL_92 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-24	RESERVED	R/W	0h	Reserved
23-19	RESERVED	R/W	X
18-16	ZQ_STATUS_LOG	R	0h	Indicates what kind of ZQ command was terminated without execution that caused the ZQ status interrupt to assert. Bit (0) correlates to a ZQ cal init, reset, short or long command. Bit (1) correlates to a ZQ cal start command. Bit (2) correlates to a ZQ cal latch command. Value of 1 indicates that that type of command was received, but terminated without execution. READ_ONLY
15-0	DFS_PROMOTE_THRESHOLD_F2	R/W	0h	DFS promotion number of long counts until the high priority request is asserted for frequency copy 2. Applies to SW and HW DFS commands.

2.5.2.93 DDRSS_CTL_94 Register (Offset = 178h) [reset = 0h]

DDRSS_CTL_94 is shown in Figure 8-185 and described in Table 8-378.

Return to Summary Table.

Table 8-377 DDRSS_CTL_94 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0178h

Figure 8-185 DDRSS_CTL_94 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UPD_CTRLUPD_HIGH_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UPD_CTRLUPD_NORM_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-378 DDRSS_CTL_94 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	UPD_CTRLUPD_HIGH_THRESHOLD_F0	R/W	0h	DFI control update number of long counts until the high priority request is asserted for frequency copy 0.
15-0	UPD_CTRLUPD_NORM_THRESHOLD_F0	R/W	0h	DFI control update number of long counts until the normal priority request is asserted for frequency copy 0.

2.5.2.94 DDRSS_CTL_95 Register (Offset = 17Ch) [reset = 0h]

DDRSS_CTL_95 is shown in Figure 8-186 and described in Table 8-380.

Return to Summary Table.

Table 8-379 DDRSS_CTL_95 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 017Ch

Figure 8-186 DDRSS_CTL_95 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UPD_CTRLUPD_TIMEOUT_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-380 DDRSS_CTL_95 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0	R/W	0h	DFI control update SW promotion number of long counts until the high priority request is asserted for frequency copy 0.
15-0	UPD_CTRLUPD_TIMEOUT_F0	R/W	0h	DFI control update number of long counts until the timeout is asserted for frequency copy 0.

2.5.2.95 DDRSS_CTL_96 Register (Offset = 180h) [reset = 0h]

DDRSS_CTL_96 is shown in Figure 8-187 and described in Table 8-382.

Return to Summary Table.

Table 8-381 DDRSS_CTL_96 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0180h

Figure 8-187 DDRSS_CTL_96 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UPD_CTRLUPD_NORM_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-382 DDRSS_CTL_96 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	UPD_CTRLUPD_NORM_THRESHOLD_F1	R/W	0h	DFI control update number of long counts until the normal priority request is asserted for frequency copy 1.
15-0	UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0	R/W	0h	DFI PHY update DFI promotion number of long counts until the high priority request is asserted for frequency copy 0.

2.5.2.96 DDRSS_CTL_97 Register (Offset = 184h) [reset = 0h]

DDRSS_CTL_97 is shown in Figure 8-188 and described in Table 8-384.

Return to Summary Table.

Table 8-383 DDRSS_CTL_97 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0184h

Figure 8-188 DDRSS_CTL_97 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UPD_CTRLUPD_TIMEOUT_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UPD_CTRLUPD_HIGH_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-384 DDRSS_CTL_97 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	UPD_CTRLUPD_TIMEOUT_F1	R/W	0h	DFI control update number of long counts until the timeout is asserted for frequency copy 1.
15-0	UPD_CTRLUPD_HIGH_THRESHOLD_F1	R/W	0h	DFI control update number of long counts until the high priority request is asserted for frequency copy 1.

2.5.2.97 DDRSS_CTL_98 Register (Offset = 188h) [reset = 0h]

DDRSS_CTL_98 is shown in Figure 8-189 and described in Table 8-386.

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Table 8-385 DDRSS_CTL_98 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0188h

Figure 8-189 DDRSS_CTL_98 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-386 DDRSS_CTL_98 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1	R/W	0h	DFI PHY update DFI promotion number of long counts until the high priority request is asserted for frequency copy 1.
15-0	UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1	R/W	0h	DFI control update SW promotion number of long counts until the high priority request is asserted for frequency copy 1.

2.5.2.98 DDRSS_CTL_99 Register (Offset = 18Ch) [reset = 0h]

DDRSS_CTL_99 is shown in Figure 8-190 and described in Table 8-388.

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Table 8-387 DDRSS_CTL_99 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 018Ch

Figure 8-190 DDRSS_CTL_99 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UPD_CTRLUPD_HIGH_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UPD_CTRLUPD_NORM_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-388 DDRSS_CTL_99 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	UPD_CTRLUPD_HIGH_THRESHOLD_F2	R/W	0h	DFI control update number of long counts until the high priority request is asserted for frequency copy 2.
15-0	UPD_CTRLUPD_NORM_THRESHOLD_F2	R/W	0h	DFI control update number of long counts until the normal priority request is asserted for frequency copy 2.

2.5.2.99 DDRSS_CTL_100 Register (Offset = 190h) [reset = 0h]

DDRSS_CTL_100 is shown in Figure 8-191 and described in Table 8-390.

Return to Summary Table.

Table 8-389 DDRSS_CTL_100 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0190h

Figure 8-191 DDRSS_CTL_100 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UPD_CTRLUPD_TIMEOUT_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-390 DDRSS_CTL_100 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2	R/W	0h	DFI control update SW promotion number of long counts until the high priority request is asserted for frequency copy 2.
15-0	UPD_CTRLUPD_TIMEOUT_F2	R/W	0h	DFI control update number of long counts until the timeout is asserted for frequency copy 2.

2.5.2.100 DDRSS_CTL_101 Register (Offset = 194h) [reset = X]

DDRSS_CTL_101 is shown in Figure 8-192 and described in Table 8-392.

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Table 8-391 DDRSS_CTL_101 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0194h

Figure 8-192 DDRSS_CTL_101 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-392 DDRSS_CTL_101 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	X
15-0	UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2	R/W	0h	DFI PHY update DFI promotion number of long counts until the high priority request is asserted for frequency copy 2.

2.5.2.101 DDRSS_CTL_102 Register (Offset = 198h) [reset = 0h]

DDRSS_CTL_102 is shown in Figure 8-193 and described in Table 8-394.

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Table 8-393 DDRSS_CTL_102 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0198h

Figure 8-193 DDRSS_CTL_102 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-394 DDRSS_CTL_102 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_F0	R/W	0h	Defines the DFI tPHYMSTR_MAX timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack, for frequency copy 0. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.102 DDRSS_CTL_103 Register (Offset = 19Ch) [reset = 0h]

DDRSS_CTL_103 is shown in Figure 8-194 and described in Table 8-396.

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Table 8-395 DDRSS_CTL_103 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 019Ch

Figure 8-194 DDRSS_CTL_103 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE0_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-396 DDRSS_CTL_103 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE0_F0	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE0 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=0, for frequency copy 0. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.103 DDRSS_CTL_104 Register (Offset = 1A0h) [reset = 0h]

DDRSS_CTL_104 is shown in Figure 8-195 and described in Table 8-398.

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Table 8-397 DDRSS_CTL_104 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01A0h

Figure 8-195 DDRSS_CTL_104 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE1_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-398 DDRSS_CTL_104 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE1_F0	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE1 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=1, for frequency copy 0. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.104 DDRSS_CTL_105 Register (Offset = 1A4h) [reset = 0h]

DDRSS_CTL_105 is shown in Figure 8-196 and described in Table 8-400.

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Table 8-399 DDRSS_CTL_105 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01A4h

Figure 8-196 DDRSS_CTL_105 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE2_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-400 DDRSS_CTL_105 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE2_F0	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE2 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=2, for frequency copy 0. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.105 DDRSS_CTL_106 Register (Offset = 1A8h) [reset = 0h]

DDRSS_CTL_106 is shown in Figure 8-197 and described in Table 8-402.

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Table 8-401 DDRSS_CTL_106 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01A8h

Figure 8-197 DDRSS_CTL_106 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE3_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-402 DDRSS_CTL_106 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE3_F0	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE3 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=3, for frequency copy 0. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.106 DDRSS_CTL_107 Register (Offset = 1ACh) [reset = X]

DDRSS_CTL_107 is shown in Figure 8-198 and described in Table 8-404.

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Table 8-403 DDRSS_CTL_107 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01ACh

Figure 8-198 DDRSS_CTL_107 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-404 DDRSS_CTL_107 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	X
15-0	PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0	R/W	0h	Defines the DFI(4.0 and 4.0v2) PHY master request promotion number of regular (not long) counts until the high priority request is asserted for frequency copy 0.

2.5.2.107 DDRSS_CTL_108 Register (Offset = 1B0h) [reset = X]

DDRSS_CTL_108 is shown in Figure 8-199 and described in Table 8-406.

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Table 8-405 DDRSS_CTL_108 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01B0h

Figure 8-199 DDRSS_CTL_108 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												TDFI_PHYMSTR_RESP_F0
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-406 DDRSS_CTL_108 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	TDFI_PHYMSTR_RESP_F0	R/W	0h	Defines the DFI tPHYMSTR_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_phymstr_req assertion and a dfi_phymstr_ack assertion, for frequency copy 0. If programmed to a non-zero, a timing violation will cause an interrupt and bit (1) to be set to 1 in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.108 DDRSS_CTL_109 Register (Offset = 1B4h) [reset = 0h]

DDRSS_CTL_109 is shown in Figure 8-200 and described in Table 8-408.

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Table 8-407 DDRSS_CTL_109 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01B4h

Figure 8-200 DDRSS_CTL_109 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-408 DDRSS_CTL_109 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_F1	R/W	0h	Defines the DFI tPHYMSTR_MAX timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack, for frequency copy 1. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.109 DDRSS_CTL_110 Register (Offset = 1B8h) [reset = 0h]

DDRSS_CTL_110 is shown in Figure 8-201 and described in Table 8-410.

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Table 8-409 DDRSS_CTL_110 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01B8h

Figure 8-201 DDRSS_CTL_110 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE0_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-410 DDRSS_CTL_110 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE0_F1	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE0 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=0, for frequency copy 1. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.110 DDRSS_CTL_111 Register (Offset = 1BCh) [reset = 0h]

DDRSS_CTL_111 is shown in Figure 8-202 and described in Table 8-412.

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Table 8-411 DDRSS_CTL_111 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01BCh

Figure 8-202 DDRSS_CTL_111 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE1_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-412 DDRSS_CTL_111 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE1_F1	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE1 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=1, for frequency copy 1. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.111 DDRSS_CTL_112 Register (Offset = 1C0h) [reset = 0h]

DDRSS_CTL_112 is shown in Figure 8-203 and described in Table 8-414.

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Table 8-413 DDRSS_CTL_112 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01C0h

Figure 8-203 DDRSS_CTL_112 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE2_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-414 DDRSS_CTL_112 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE2_F1	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE2 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=2, for frequency copy 1. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.112 DDRSS_CTL_113 Register (Offset = 1C4h) [reset = 0h]

DDRSS_CTL_113 is shown in Figure 8-204 and described in Table 8-416.

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Table 8-415 DDRSS_CTL_113 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01C4h

Figure 8-204 DDRSS_CTL_113 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE3_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-416 DDRSS_CTL_113 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE3_F1	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE3 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=3, for frequency copy 1. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.113 DDRSS_CTL_114 Register (Offset = 1C8h) [reset = X]

DDRSS_CTL_114 is shown in Figure 8-205 and described in Table 8-418.

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Table 8-417 DDRSS_CTL_114 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01C8h

Figure 8-205 DDRSS_CTL_114 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-418 DDRSS_CTL_114 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	X
15-0	PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1	R/W	0h	Defines the DFI(4.0 and 4.0v2) PHY master request promotion number of regular (not long) counts until the high priority request is asserted for frequency copy 1.

2.5.2.114 DDRSS_CTL_115 Register (Offset = 1CCh) [reset = X]

DDRSS_CTL_115 is shown in Figure 8-206 and described in Table 8-420.

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Table 8-419 DDRSS_CTL_115 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01CCh

Figure 8-206 DDRSS_CTL_115 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												TDFI_PHYMSTR_RESP_F1
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-420 DDRSS_CTL_115 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	TDFI_PHYMSTR_RESP_F1	R/W	0h	Defines the DFI tPHYMSTR_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_phymstr_req assertion and a dfi_phymstr_ack assertion, for frequency copy 1. If programmed to a non-zero, a timing violation will cause an interrupt and bit (1) to be set to 1 in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.115 DDRSS_CTL_116 Register (Offset = 1D0h) [reset = 0h]

DDRSS_CTL_116 is shown in Figure 8-207 and described in Table 8-422.

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Table 8-421 DDRSS_CTL_116 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01D0h

Figure 8-207 DDRSS_CTL_116 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-422 DDRSS_CTL_116 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_F2	R/W	0h	Defines the DFI tPHYMSTR_MAX timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack, for frequency copy 2. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.116 DDRSS_CTL_117 Register (Offset = 1D4h) [reset = 0h]

DDRSS_CTL_117 is shown in Figure 8-208 and described in Table 8-424.

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Table 8-423 DDRSS_CTL_117 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01D4h

Figure 8-208 DDRSS_CTL_117 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE0_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-424 DDRSS_CTL_117 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE0_F2	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE0 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=0, for frequency copy 2. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.117 DDRSS_CTL_118 Register (Offset = 1D8h) [reset = 0h]

DDRSS_CTL_118 is shown in Figure 8-209 and described in Table 8-426.

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Table 8-425 DDRSS_CTL_118 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01D8h

Figure 8-209 DDRSS_CTL_118 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE1_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-426 DDRSS_CTL_118 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE1_F2	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE1 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=1, for frequency copy 2. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.118 DDRSS_CTL_119 Register (Offset = 1DCh) [reset = 0h]

DDRSS_CTL_119 is shown in Figure 8-210 and described in Table 8-428.

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Table 8-427 DDRSS_CTL_119 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01DCh

Figure 8-210 DDRSS_CTL_119 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE2_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-428 DDRSS_CTL_119 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE2_F2	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE2 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=2, for frequency copy 2. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.119 DDRSS_CTL_120 Register (Offset = 1E0h) [reset = 0h]

DDRSS_CTL_120 is shown in Figure 8-211 and described in Table 8-430.

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Table 8-429 DDRSS_CTL_120 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01E0h

Figure 8-211 DDRSS_CTL_120 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYMSTR_MAX_TYPE3_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-430 DDRSS_CTL_120 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYMSTR_MAX_TYPE3_F2	R/W	0h	Defines the DFI 4.0v2 tPHYMSTR_MAX_TYPE3 timing parameter (in DFI clocks), the maximum cycles that dfi_phymstr_req can be asserted following the assertion of dfi_phymstr_ack for dfi_phymstr_type=3, for frequency copy 2. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.120 DDRSS_CTL_121 Register (Offset = 1E4h) [reset = X]

DDRSS_CTL_121 is shown in Figure 8-212 and described in Table 8-432.

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Table 8-431 DDRSS_CTL_121 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01E4h

Figure 8-212 DDRSS_CTL_121 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-432 DDRSS_CTL_121 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	X
15-0	PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2	R/W	0h	Defines the DFI(4.0 and 4.0v2) PHY master request promotion number of regular (not long) counts until the high priority request is asserted for frequency copy 2.

2.5.2.121 DDRSS_CTL_122 Register (Offset = 1E8h) [reset = X]

DDRSS_CTL_122 is shown in Figure 8-213 and described in Table 8-434.

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Table 8-433 DDRSS_CTL_122 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01E8h

Figure 8-213 DDRSS_CTL_122 Register

31	30	29	28	27	26	25	24
RESERVED							PHYMSTR_NO_AREF
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED				TDFI_PHYMSTR_RESP_F2
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
TDFI_PHYMSTR_RESP_F2
R/W-0h

7	6	5	4	3	2	1	0
TDFI_PHYMSTR_RESP_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-434 DDRSS_CTL_122 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	PHYMSTR_NO_AREF	R/W	0h	Disables refreshes during the PHY master interface sequence. Set to 1 to disable. Refreshes during reset are only supported for DFI 4.0 and this parameter may be set or cleared for DFI 4.0. For all other DFI versions, this parameter must be set to 1.
23-20	RESERVED	R/W	X
19-0	TDFI_PHYMSTR_RESP_F2	R/W	0h	Defines the DFI tPHYMSTR_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_phymstr_req assertion and a dfi_phymstr_ack assertion, for frequency copy 2. If programmed to a non-zero, a timing violation will cause an interrupt and bit (1) to be set to 1 in the PHYMSTR_ERROR_STATUS parameter.

2.5.2.122 DDRSS_CTL_123 Register (Offset = 1ECh) [reset = X]

DDRSS_CTL_123 is shown in Figure 8-214 and described in Table 8-436.

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Table 8-435 DDRSS_CTL_123 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01ECh

Figure 8-214 DDRSS_CTL_123 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED							PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							PHYMSTR_DFI_VERSION_4P0V1
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED						PHYMSTR_ERROR_STATUS
R/W-X						R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-436 DDRSS_CTL_123 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R/W	X
16	PHYMSTR_TRAIN_AFTER_INIT_COMPLETE	R/W	0h	Defines how the PHY will use the PHY Master Interface for training. Clear to 0 to perform training without the PHY Master Interface, or set to 1 to use the PHY Master Interface to gain control over the DFI bus after the dfi_init_complete signal assertion for the initial training. Default is cleared to 0.
15-9	RESERVED	R/W	X
8	PHYMSTR_DFI_VERSION_4P0V1	R/W	0h	Defines the version of the DFI 4.0 specification supported. Clear to 0 for DFI 4.0 version 2 PHY Master Interface, or set to 1 for DFI 4.0 version 1 PHY Master Interface. Default is cleared to 0 for version 2.
7-2	RESERVED	R/W	X
1-0	PHYMSTR_ERROR_STATUS	R	0h	Identifies the source of any DFI PHY Master Interface errors. Value of 1 indicates a timing violation of the associated timing parameter. Bit (0) set indicates a TDFI_PHYMSTR_MAX or TDFI_PHYMSTR_TYPEn_MAX parmaeter violation and bit (1) set indicates a TDFI_PHYMSTR_RESP parameter violation. READ-ONLY

2.5.2.123 DDRSS_CTL_124 Register (Offset = 1F0h) [reset = 0h]

DDRSS_CTL_124 is shown in Figure 8-215 and described in Table 8-438.

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Table 8-437 DDRSS_CTL_124 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01F0h

Figure 8-215 DDRSS_CTL_124 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MRR_TEMPCHK_HIGH_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MRR_TEMPCHK_NORM_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-438 DDRSS_CTL_124 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MRR_TEMPCHK_HIGH_THRESHOLD_F0	R/W	0h	MRR temp check number of long counts until the high priority request is asserted for frequency copy 0.
15-0	MRR_TEMPCHK_NORM_THRESHOLD_F0	R/W	0h	MRR temp check number of long counts until the normal priority request is asserted for frequency copy 0.

2.5.2.124 DDRSS_CTL_125 Register (Offset = 1F4h) [reset = 0h]

DDRSS_CTL_125 is shown in Figure 8-216 and described in Table 8-440.

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Table 8-439 DDRSS_CTL_125 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01F4h

Figure 8-216 DDRSS_CTL_125 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MRR_TEMPCHK_NORM_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MRR_TEMPCHK_TIMEOUT_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-440 DDRSS_CTL_125 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MRR_TEMPCHK_NORM_THRESHOLD_F1	R/W	0h	MRR temp check number of long counts until the normal priority request is asserted for frequency copy 1.
15-0	MRR_TEMPCHK_TIMEOUT_F0	R/W	0h	MRR temp check number of long counts until the timeout is asserted for frequency copy 0.

2.5.2.125 DDRSS_CTL_126 Register (Offset = 1F8h) [reset = 0h]

DDRSS_CTL_126 is shown in Figure 8-217 and described in Table 8-442.

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Table 8-441 DDRSS_CTL_126 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01F8h

Figure 8-217 DDRSS_CTL_126 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MRR_TEMPCHK_TIMEOUT_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MRR_TEMPCHK_HIGH_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-442 DDRSS_CTL_126 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MRR_TEMPCHK_TIMEOUT_F1	R/W	0h	MRR temp check number of long counts until the timeout is asserted for frequency copy 1.
15-0	MRR_TEMPCHK_HIGH_THRESHOLD_F1	R/W	0h	MRR temp check number of long counts until the high priority request is asserted for frequency copy 1.

2.5.2.126 DDRSS_CTL_127 Register (Offset = 1FCh) [reset = 0h]

DDRSS_CTL_127 is shown in Figure 8-218 and described in Table 8-444.

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Table 8-443 DDRSS_CTL_127 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 01FCh

Figure 8-218 DDRSS_CTL_127 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MRR_TEMPCHK_HIGH_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MRR_TEMPCHK_NORM_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-444 DDRSS_CTL_127 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MRR_TEMPCHK_HIGH_THRESHOLD_F2	R/W	0h	MRR temp check number of long counts until the high priority request is asserted for frequency copy 2.
15-0	MRR_TEMPCHK_NORM_THRESHOLD_F2	R/W	0h	MRR temp check number of long counts until the normal priority request is asserted for frequency copy 2.

2.5.2.127 DDRSS_CTL_128 Register (Offset = 200h) [reset = X]

DDRSS_CTL_128 is shown in Figure 8-219 and described in Table 8-446.

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Table 8-445 DDRSS_CTL_128 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0200h

Figure 8-219 DDRSS_CTL_128 Register

31	30	29	28	27	26	25	24
RESERVED					PPR_COMMAND
R/W-X					W-0h

23	22	21	20	19	18	17	16
RESERVED							PPR_CONTROL
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
MRR_TEMPCHK_TIMEOUT_F2
R/W-0h

7	6	5	4	3	2	1	0
MRR_TEMPCHK_TIMEOUT_F2
R/W-0h

LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-446 DDRSS_CTL_128 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-24	PPR_COMMAND	W	0h	Specifies the type of PPR command. Program to 1 for pre-charge all, program to 2 for MRW, program to 3 for activate, or program to 5 for write. All other values are reserved. WRITE-ONLY
23-17	RESERVED	R/W	X
16	PPR_CONTROL	R/W	0h	Enables the post-package repair feature. Set to 1 to enable. This parameter may only be programmed before initialization begins.
15-0	MRR_TEMPCHK_TIMEOUT_F2	R/W	0h	MRR temp check number of long counts until the timeout is asserted for frequency copy 2.

2.5.2.128 DDRSS_CTL_129 Register (Offset = 204h) [reset = X]

DDRSS_CTL_129 is shown in Figure 8-220 and described in Table 8-448.

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Table 8-447 DDRSS_CTL_129 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0204h

Figure 8-220 DDRSS_CTL_129 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED							PPR_ROW_ADDRESS
R/W-X							R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PPR_ROW_ADDRESS								PPR_COMMAND_MRW
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-448 DDRSS_CTL_129 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24-8	PPR_ROW_ADDRESS	R/W	0h	Specifies the encoded row address to be repaired.
7-0	PPR_COMMAND_MRW	R/W	0h	Specifies the mode register to be used. Clear to 0 for MRW0 or program to 4 for MRW4. All other values are reserved.

2.5.2.129 DDRSS_CTL_130 Register (Offset = 208h) [reset = X]

DDRSS_CTL_130 is shown in Figure 8-221 and described in Table 8-450.

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Table 8-449 DDRSS_CTL_130 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0208h

Figure 8-221 DDRSS_CTL_130 Register

31	30	29	28	27	26	25	24
RESERVED							FM_OVRIDE_CONTROL
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED						PPR_STATUS
R/W-X						R-0h

15	14	13	12	11	10	9	8
RESERVED							PPR_CS_ADDRESS
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED					PPR_BANK_ADDRESS
R/W-X					R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-450 DDRSS_CTL_130 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	FM_OVRIDE_CONTROL	R/W	0h	Enables the FM Override feature. Set to 1 to enable.
23-18	RESERVED	R/W	X
17-16	PPR_STATUS	R	0h	Reports the status of the PPR operation. Bit (0) set indicates that PPR operations are now allowed and bit (1) set indicates if the last PPR command is complete. READ-ONLY
15-9	RESERVED	R/W	X
8	PPR_CS_ADDRESS	R/W	0h	Specifies the chip select for the row to be repaired.
7-3	RESERVED	R/W	X
2-0	PPR_BANK_ADDRESS	R/W	0h	Specifies the bank for the row to be repaired.

2.5.2.130 DDRSS_CTL_131 Register (Offset = 20Ch) [reset = X]

DDRSS_CTL_131 is shown in Figure 8-222 and described in Table 8-452.

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Table 8-451 DDRSS_CTL_131 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 020Ch

Figure 8-222 DDRSS_CTL_131 Register

31	30	29	28	27	26	25	24
CKSRE_F1
R/W-0h

23	22	21	20	19	18	17	16
CKSRX_F0
R/W-0h

15	14	13	12	11	10	9	8
CKSRE_F0
R/W-0h

7	6	5	4	3	2	1	0
RESERVED						LOWPOWER_REFRESH_ENABLE
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-452 DDRSS_CTL_131 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	CKSRE_F1	R/W	0h	Clock hold delay on self-refresh entry for frequency copy 1.
23-16	CKSRX_F0	R/W	0h	Clock stable delay on self-refresh exit for frequency copy 0.
15-8	CKSRE_F0	R/W	0h	Clock hold delay on self-refresh entry for frequency copy 0.
7-2	RESERVED	R/W	X
1-0	LOWPOWER_REFRESH_ENABLE	R/W	0h	Enable refreshes while in low power mode. Bit (0) controls cs0, bit (1) controls cs1, etc. Set each bit to 1 to disable.

2.5.2.131 DDRSS_CTL_132 Register (Offset = 210h) [reset = X]

DDRSS_CTL_132 is shown in Figure 8-223 and described in Table 8-454.

Return to Summary Table.

Table 8-453 DDRSS_CTL_132 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0210h

Figure 8-223 DDRSS_CTL_132 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED	LP_CMD							CKSRX_F2								CKSRE_F2								CKSRX_F1
R/W-X	W-0h							R/W-0h								R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-454 DDRSS_CTL_132 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30-24	LP_CMD	W	0h	Low power software command request interface. Bit (0) controls exit, bit (1) controls entry, bits ( 4:2) define the low power state, bit (5) controls memory clock gating, bit (6) controls controller clock gating, and bit (7) controls lock. WRITE-ONLY
23-16	CKSRX_F2	R/W	0h	Clock stable delay on self-refresh exit for frequency copy 2.
15-8	CKSRE_F2	R/W	0h	Clock hold delay on self-refresh entry for frequency copy 2.
7-0	CKSRX_F1	R/W	0h	Clock stable delay on self-refresh exit for frequency copy 1.

2.5.2.132 DDRSS_CTL_133 Register (Offset = 214h) [reset = X]

DDRSS_CTL_133 is shown in Figure 8-224 and described in Table 8-456.

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Table 8-455 DDRSS_CTL_133 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0214h

Figure 8-224 DDRSS_CTL_133 Register

31	30	29	28	27	26	25	24
RESERVED				LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED				LPI_SR_LONG_WAKEUP_F0
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED				LPI_SR_SHORT_WAKEUP_F0
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED				LPI_CTRL_IDLE_WAKEUP_F0
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-456 DDRSS_CTL_133 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long with memory and controller clock gating state, for frequency copy 0.
23-20	RESERVED	R/W	X
19-16	LPI_SR_LONG_WAKEUP_F0	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long state (with or without memory clock gating) for frequency copy 0.
15-12	RESERVED	R/W	X
11-8	LPI_SR_SHORT_WAKEUP_F0	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when LPDDR4 memory is in the self-refresh short state (with or without memory clock gating) for frequency copy 0. For LPDDR4, SR_SHORT is used to send few commands so this wakeup time must be cleared to ZERO and no LPI request needs to be asserted.
7-4	RESERVED	R/W	X
3-0	LPI_CTRL_IDLE_WAKEUP_F0	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when controller is idle for frequency copy 0.

2.5.2.133 DDRSS_CTL_134 Register (Offset = 218h) [reset = X]

DDRSS_CTL_134 is shown in Figure 8-225 and described in Table 8-458.

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Table 8-457 DDRSS_CTL_134 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0218h

Figure 8-225 DDRSS_CTL_134 Register

31	30	29	28	27	26	25	24
RESERVED				LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED				LPI_SRPD_LONG_WAKEUP_F0
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED				LPI_SRPD_SHORT_WAKEUP_F0
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED				LPI_PD_WAKEUP_F0
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-458 DDRSS_CTL_134 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long with memory and controller clock gating state, for frequency copy 0.
23-20	RESERVED	R/W	X
19-16	LPI_SRPD_LONG_WAKEUP_F0	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long state (with or without memory clock gating), for frequency copy 0.
15-12	RESERVED	R/W	X
11-8	LPI_SRPD_SHORT_WAKEUP_F0	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down short state (with or without memory clock gating), for frequency copy 0.
7-4	RESERVED	R/W	X
3-0	LPI_PD_WAKEUP_F0	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in any of the power-down states (with or without memory clock gating) for frequency copy 0.

2.5.2.134 DDRSS_CTL_135 Register (Offset = 21Ch) [reset = X]

DDRSS_CTL_135 is shown in Figure 8-226 and described in Table 8-460.

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Table 8-459 DDRSS_CTL_135 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 021Ch

Figure 8-226 DDRSS_CTL_135 Register

31	30	29	28	27	26	25	24
RESERVED				LPI_SR_LONG_WAKEUP_F1
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED				LPI_SR_SHORT_WAKEUP_F1
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED				LPI_CTRL_IDLE_WAKEUP_F1
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED				LPI_TIMER_WAKEUP_F0
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-460 DDRSS_CTL_135 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	LPI_SR_LONG_WAKEUP_F1	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long state (with or without memory clock gating) for frequency copy 1.
23-20	RESERVED	R/W	X
19-16	LPI_SR_SHORT_WAKEUP_F1	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when LPDDR4 memory is in the self-refresh short state (with or without memory clock gating) for frequency copy 1. For LPDDR4, SR_SHORT is used to send few commands so this wakeup time must be cleared to ZERO and no LPI request needs to be asserted.
15-12	RESERVED	R/W	X
11-8	LPI_CTRL_IDLE_WAKEUP_F1	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when controller is idle for frequency copy 1.
7-4	RESERVED	R/W	X
3-0	LPI_TIMER_WAKEUP_F0	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when the LPI timer expires for frequency copy 0.

2.5.2.135 DDRSS_CTL_136 Register (Offset = 220h) [reset = X]

DDRSS_CTL_136 is shown in Figure 8-227 and described in Table 8-462.

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Table 8-461 DDRSS_CTL_136 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0220h

Figure 8-227 DDRSS_CTL_136 Register

31	30	29	28	27	26	25	24
RESERVED				LPI_SRPD_LONG_WAKEUP_F1
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED				LPI_SRPD_SHORT_WAKEUP_F1
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED				LPI_PD_WAKEUP_F1
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED				LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-462 DDRSS_CTL_136 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	LPI_SRPD_LONG_WAKEUP_F1	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long state (with or without memory clock gating), for frequency copy 1.
23-20	RESERVED	R/W	X
19-16	LPI_SRPD_SHORT_WAKEUP_F1	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down short state (with or without memory clock gating), for frequency copy 1.
15-12	RESERVED	R/W	X
11-8	LPI_PD_WAKEUP_F1	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in any of the power-down states (with or without memory clock gating) for frequency copy 1.
7-4	RESERVED	R/W	X
3-0	LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long with memory and controller clock gating state, for frequency copy 1.

2.5.2.136 DDRSS_CTL_137 Register (Offset = 224h) [reset = X]

DDRSS_CTL_137 is shown in Figure 8-228 and described in Table 8-464.

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Table 8-463 DDRSS_CTL_137 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0224h

Figure 8-228 DDRSS_CTL_137 Register

31	30	29	28	27	26	25	24
RESERVED				LPI_SR_SHORT_WAKEUP_F2
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED				LPI_CTRL_IDLE_WAKEUP_F2
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED				LPI_TIMER_WAKEUP_F1
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED				LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-464 DDRSS_CTL_137 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	LPI_SR_SHORT_WAKEUP_F2	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when LPDDR4 memory is in the self-refresh short state (with or without memory clock gating) for frequency copy 2. For LPDDR4, SR_SHORT is used to send few commands so this wakeup time must be cleared to ZERO and no LPI request needs to be asserted.
23-20	RESERVED	R/W	X
19-16	LPI_CTRL_IDLE_WAKEUP_F2	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when controller is idle for frequency copy 2.
15-12	RESERVED	R/W	X
11-8	LPI_TIMER_WAKEUP_F1	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when the LPI timer expires for frequency copy 1.
7-4	RESERVED	R/W	X
3-0	LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long with memory and controller clock gating state, for frequency copy 1.

2.5.2.137 DDRSS_CTL_138 Register (Offset = 228h) [reset = X]

DDRSS_CTL_138 is shown in Figure 8-229 and described in Table 8-466.

Return to Summary Table.

Table 8-465 DDRSS_CTL_138 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0228h

Figure 8-229 DDRSS_CTL_138 Register

31	30	29	28	27	26	25	24
RESERVED				LPI_SRPD_SHORT_WAKEUP_F2
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED				LPI_PD_WAKEUP_F2
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED				LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED				LPI_SR_LONG_WAKEUP_F2
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-466 DDRSS_CTL_138 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	LPI_SRPD_SHORT_WAKEUP_F2	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down short state (with or without memory clock gating), for frequency copy 2.
23-20	RESERVED	R/W	X
19-16	LPI_PD_WAKEUP_F2	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in any of the power-down states (with or without memory clock gating) for frequency copy 2.
15-12	RESERVED	R/W	X
11-8	LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long with memory and controller clock gating state, for frequency copy 2.
7-4	RESERVED	R/W	X
3-0	LPI_SR_LONG_WAKEUP_F2	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh long state (with or without memory clock gating) for frequency copy 2.

2.5.2.138 DDRSS_CTL_139 Register (Offset = 22Ch) [reset = X]

DDRSS_CTL_139 is shown in Figure 8-230 and described in Table 8-468.

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Table 8-467 DDRSS_CTL_139 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 022Ch

Figure 8-230 DDRSS_CTL_139 Register

31	30	29	28	27	26	25	24
RESERVED		LPI_WAKEUP_EN
R/W-X		R/W-0h

23	22	21	20	19	18	17	16
RESERVED				LPI_TIMER_WAKEUP_F2
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED				LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED				LPI_SRPD_LONG_WAKEUP_F2
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-468 DDRSS_CTL_139 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R/W	X
29-24	LPI_WAKEUP_EN	R/W	0h	Enables the various low power state wakeup parameters for LPI request uses. Bit (0) enables controller idle wakeup, bit (1) enables power-down wakeup, bit (2) enables either self-refresh short, self-refresh long with or without mem clk gating, either self-refresh power-down short, or self-refresh power-down long with or without mem clk gating, bit (3) enables self-refresh long with mem and ctlr clk gating or self-refresh power-down long with mem and ctlr clk gating, bit (4) enables the LPI timer expiry wakeup, and bit (5) is reserved. Set each bit to 1 to enable the respective LP_WAKEUP value for the LPI request.
23-20	RESERVED	R/W	X
19-16	LPI_TIMER_WAKEUP_F2	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when the LPI timer expires for frequency copy 2.
15-12	RESERVED	R/W	X
11-8	LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long with memory and controller clock gating state, for frequency copy 2.
7-4	RESERVED	R/W	X
3-0	LPI_SRPD_LONG_WAKEUP_F2	R/W	0h	Defines the DFI tLP_WAKEUP timing parameter (in DFI clocks) to be driven when memory is in the self-refresh power-down long state (with or without memory clock gating), for frequency copy 2.

2.5.2.139 DDRSS_CTL_140 Register (Offset = 230h) [reset = X]

DDRSS_CTL_140 is shown in Figure 8-231 and described in Table 8-470.

Return to Summary Table.

Table 8-469 DDRSS_CTL_140 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0230h

Figure 8-231 DDRSS_CTL_140 Register

31	30	29	28	27	26	25	24
RESERVED					TDFI_LP_RESP
R/W-X					R/W-0h

23	22	21	20	19	18	17	16
RESERVED				LPI_WAKEUP_TIMEOUT
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
LPI_WAKEUP_TIMEOUT
R/W-0h

7	6	5	4	3	2	1	0
RESERVED							LPI_CTRL_REQ_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-470 DDRSS_CTL_140 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-24	TDFI_LP_RESP	R/W	0h	Defines the DFI tLP_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_lp_req assertion and a dfi_lp_ack assertion.
23-20	RESERVED	R/W	X
19-8	LPI_WAKEUP_TIMEOUT	R/W	0h	Defines the LPI timeout time, the maximum cycles between a dfi_lp_req de-assertion and a dfi_lp_ack de-assertion. If this value is exceeded, an interrupt will occur.
7-1	RESERVED	R/W	X
0	LPI_CTRL_REQ_EN	R/W	0h	Enables the dfi_lpi_ctrl_req signal for the LPI. This signal is only relevant for DFI versions 3.1 and beyond. Set to 1 to enable or clear to 0 to disable.

2.5.2.140 DDRSS_CTL_141 Register (Offset = 234h) [reset = X]

DDRSS_CTL_141 is shown in Figure 8-232 and described in Table 8-472.

Return to Summary Table.

Table 8-471 DDRSS_CTL_141 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0234h

Figure 8-232 DDRSS_CTL_141 Register

31	30	29	28	27	26	25	24
RESERVED				LP_AUTO_EXIT_EN
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED				LP_AUTO_ENTRY_EN
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED	LP_STATE_CS1
R/W-X	R-40h

7	6	5	4	3	2	1	0
RESERVED	LP_STATE_CS0
R/W-X	R-40h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-472 DDRSS_CTL_141 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	LP_AUTO_EXIT_EN	R/W	0h	Enable auto exit from each of the low power states when a read or write command enters the command queue. Bit (0) controls power-down, bit (1) controls self-refresh long or self-refresh power-down long, bit (2) controls self-refresh long with memory and controller clock gating or self-refresh power-down long with memory and controller clock gating, and bit (3) controls self-refresh short or self-refresh power-down short. Set each bit to 1 to enable.
23-20	RESERVED	R/W	X
19-16	LP_AUTO_ENTRY_EN	R/W	0h	Enable auto entry into each of the low power states when the associated idle timer expires. Bit (0) controls power-down, bit (1) controls self-refresh long or self-refresh power-down long, bit (2) controls self-refresh long with memory and controller clock gating or self-refresh power-down long with memory and controller clock gating, and bit (3) controls self-refresh short or self-refresh power-down short. Set each bit to 1 to enable.
15	RESERVED	R/W	X
14-8	LP_STATE_CS1	R	40h	Low power state status parameter for chip select 1. Bits ( 5:0) indicate the current low power state and bit (6) set indicates that status bits are valid. READ-ONLY
7	RESERVED	R/W	X
6-0	LP_STATE_CS0	R	40h	Low power state status parameter for chip select 0. Bits ( 5:0) indicate the current low power state and bit (6) set indicates that status bits are valid. READ-ONLY

2.5.2.141 DDRSS_CTL_142 Register (Offset = 238h) [reset = X]

DDRSS_CTL_142 is shown in Figure 8-233 and described in Table 8-474.

Return to Summary Table.

Table 8-473 DDRSS_CTL_142 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0238h

Figure 8-233 DDRSS_CTL_142 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED				LP_AUTO_PD_IDLE
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
LP_AUTO_PD_IDLE
R/W-0h

7	6	5	4	3	2	1	0
RESERVED					LP_AUTO_MEM_GATE_EN
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-474 DDRSS_CTL_142 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-8	LP_AUTO_PD_IDLE	R/W	0h	Defines the idle time (in controller clocks) until the controller will automatically issue an entry into one of the power-down low power states.
7-3	RESERVED	R/W	X
2-0	LP_AUTO_MEM_GATE_EN	R/W	0h	Enable memory clock gating when entering a low power state via the auto low power counters. Bit (0) controls power-down, bit (1) controls self-refresh long or self-refresh power-down long, and bit (2) controls self-refresh short or self-refresh power-down short. Set each bit to 1 to enable.

2.5.2.142 DDRSS_CTL_143 Register (Offset = 23Ch) [reset = X]

DDRSS_CTL_143 is shown in Figure 8-234 and described in Table 8-476.

Return to Summary Table.

Table 8-475 DDRSS_CTL_143 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 023Ch

Figure 8-234 DDRSS_CTL_143 Register

31	30	29	28	27	26	25	24
LP_AUTO_SR_LONG_MC_GATE_IDLE
R/W-0h

23	22	21	20	19	18	17	16
LP_AUTO_SR_LONG_IDLE
R/W-0h

15	14	13	12	11	10	9	8
RESERVED				LP_AUTO_SR_SHORT_IDLE
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
LP_AUTO_SR_SHORT_IDLE
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-476 DDRSS_CTL_143 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	LP_AUTO_SR_LONG_MC_GATE_IDLE	R/W	0h	Defines the idle time (in long counts) until the controller will automatically issue an entry into the self-refresh long with memory and controller clock gating or self-refresh power-down long with memory and controller clock gating low power states.
23-16	LP_AUTO_SR_LONG_IDLE	R/W	0h	Defines the idle time (in long counts) until the controller will automatically issue an entry into the self-refresh long or self-refresh power-down long (with or without memory clock gating) low power states.
15-12	RESERVED	R/W	X
11-0	LP_AUTO_SR_SHORT_IDLE	R/W	0h	Defines the idle time (in controller clocks) until the controller will automatically issue an entry into the self-refresh short or self-refresh power-down short (with or without memory clock gating) low power states.

2.5.2.143 DDRSS_CTL_144 Register (Offset = 240h) [reset = 0h]

DDRSS_CTL_144 is shown in Figure 8-235 and described in Table 8-478.

Return to Summary Table.

Table 8-477 DDRSS_CTL_144 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0240h

Figure 8-235 DDRSS_CTL_144 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
HW_PROMOTE_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HW_PROMOTE_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-478 DDRSS_CTL_144 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	HW_PROMOTE_THRESHOLD_F1	R/W	0h	HW interface promotion number of long counts until the high priority request is asserted for frequency copy 1.
15-0	HW_PROMOTE_THRESHOLD_F0	R/W	0h	HW interface promotion number of long counts until the high priority request is asserted for frequency copy 0.

2.5.2.144 DDRSS_CTL_145 Register (Offset = 244h) [reset = 0h]

DDRSS_CTL_145 is shown in Figure 8-236 and described in Table 8-480.

Return to Summary Table.

Table 8-479 DDRSS_CTL_145 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0244h

Figure 8-236 DDRSS_CTL_145 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPC_PROMOTE_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HW_PROMOTE_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-480 DDRSS_CTL_145 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	LPC_PROMOTE_THRESHOLD_F0	R/W	0h	LPC promotion number of long counts until the high priority request is asserted for frequency copy 0. Applies to SW and auto low power commands.
15-0	HW_PROMOTE_THRESHOLD_F2	R/W	0h	HW interface promotion number of long counts until the high priority request is asserted for frequency copy 2.

2.5.2.145 DDRSS_CTL_146 Register (Offset = 248h) [reset = 0h]

DDRSS_CTL_146 is shown in Figure 8-237 and described in Table 8-482.

Return to Summary Table.

Table 8-481 DDRSS_CTL_146 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0248h

Figure 8-237 DDRSS_CTL_146 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPC_PROMOTE_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LPC_PROMOTE_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-482 DDRSS_CTL_146 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	LPC_PROMOTE_THRESHOLD_F2	R/W	0h	LPC promotion number of long counts until the high priority request is asserted for frequency copy 2. Applies to SW and auto low power commands.
15-0	LPC_PROMOTE_THRESHOLD_F1	R/W	0h	LPC promotion number of long counts until the high priority request is asserted for frequency copy 1. Applies to SW and auto low power commands.

2.5.2.146 DDRSS_CTL_147 Register (Offset = 24Ch) [reset = X]

DDRSS_CTL_147 is shown in Figure 8-238 and described in Table 8-484.

Return to Summary Table.

Table 8-483 DDRSS_CTL_147 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 024Ch

Figure 8-238 DDRSS_CTL_147 Register

31	30	29	28	27	26	25	24
RESERVED							RESERVED
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							LPC_SR_PHYMSTR_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							LPC_SR_PHYUPD_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							LPC_SR_CTRLUPD_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-484 DDRSS_CTL_147 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	RESERVED	R/W	0h	Reserved
23-17	RESERVED	R/W	X
16	LPC_SR_PHYMSTR_EN	R/W	0h	Enable LPC to execute a DFI PHY Master request on a self-refresh exit sequence. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	LPC_SR_PHYUPD_EN	R/W	0h	Enable LPC to execute a DFI PHY update on a self-refresh exit sequence. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	LPC_SR_CTRLUPD_EN	R/W	0h	Enable LPC to execute a DFI control update on a self-refresh exit sequence. Set to 1 to enable.

2.5.2.147 DDRSS_CTL_148 Register (Offset = 250h) [reset = X]

DDRSS_CTL_148 is shown in Figure 8-239 and described in Table 8-486.

Return to Summary Table.

Table 8-485 DDRSS_CTL_148 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0250h

Figure 8-239 DDRSS_CTL_148 Register

31	30	29	28	27	26	25	24
RESERVED		PCPCS_PD_EXIT_DEPTH
R/W-X		R/W-0h

23	22	21	20	19	18	17	16
RESERVED		PCPCS_PD_ENTER_DEPTH
R/W-X		R/W-0h

15	14	13	12	11	10	9	8
RESERVED							PCPCS_PD_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							LPC_SR_ZQ_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-486 DDRSS_CTL_148 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R/W	X
29-24	PCPCS_PD_EXIT_DEPTH	R/W	0h	Defines the number of entries of the command queue that the PCPCS logic will consider for dynamic power-down exit decode. A non-zero value limits the decode to a subset of the full command pipeline.
23-22	RESERVED	R/W	X
21-16	PCPCS_PD_ENTER_DEPTH	R/W	0h	Defines the number of entries of the command queue that the PCPCS logic will consider for dynamic power-down entry decode. A non-zero value limits the decode to a subset of the full command pipeline.
15-9	RESERVED	R/W	X
8	PCPCS_PD_EN	R/W	0h	Enable dynamic PCPCS to allow chip selects to dynamically enter and exit power-down. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	LPC_SR_ZQ_EN	R/W	0h	Enable LPC to execute a ZQ calibration on a self-refresh exit sequence. Set to 1 to enable.

2.5.2.148 DDRSS_CTL_149 Register (Offset = 254h) [reset = X]

DDRSS_CTL_149 is shown in Figure 8-240 and described in Table 8-488.

Return to Summary Table.

Table 8-487 DDRSS_CTL_149 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0254h

Figure 8-240 DDRSS_CTL_149 Register

31	30	29	28	27	26	25	24
RESERVED							DFS_ENABLE
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED
R/W-0h

15	14	13	12	11	10	9	8
RESERVED						PCPCS_PD_MASK
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
PCPCS_PD_ENTER_TIMER
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-488 DDRSS_CTL_149 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	DFS_ENABLE	R/W	0h	Enable hardware dynamic frequency scaling. Set to 1 to enable.
23-16	RESERVED	R/W	0h	Reserved
15-10	RESERVED	R/W	X
9-8	PCPCS_PD_MASK	R/W	0h	Disables dynamic PCPCS power-down entry/exit for particular chip selects if the PCPCS_PD_EN parameter is set. Bit (0) controls cs0, bit (1) controls cs1, etc. Set each bit to 1 to disable the chip select from allowing dynamic PCPCS.
7-0	PCPCS_PD_ENTER_TIMER	R/W	0h	Sets the delay used by dynamic PCPCS from when the decode logic determines that a chip select has no outstanding transactions to when the power-down entry command is issued. A zero value disables the timer and issues the power-down entry immediately on decode.

2.5.2.149 DDRSS_CTL_150 Register (Offset = 258h) [reset = X]

DDRSS_CTL_150 is shown in Figure 8-241 and described in Table 8-490.

Return to Summary Table.

Table 8-489 DDRSS_CTL_150 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0258h

Figure 8-241 DDRSS_CTL_150 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TDFI_INIT_COMPLETE_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TDFI_INIT_START_F0
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-490 DDRSS_CTL_150 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TDFI_INIT_COMPLETE_F0	R/W	0h	Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency copy 0, the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY.
15-10	RESERVED	R/W	X
9-0	TDFI_INIT_START_F0	R/W	0h	Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency copy 0, the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY.

2.5.2.150 DDRSS_CTL_151 Register (Offset = 25Ch) [reset = X]

DDRSS_CTL_151 is shown in Figure 8-242 and described in Table 8-492.

Return to Summary Table.

Table 8-491 DDRSS_CTL_151 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 025Ch

Figure 8-242 DDRSS_CTL_151 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TDFI_INIT_COMPLETE_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TDFI_INIT_START_F1
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-492 DDRSS_CTL_151 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TDFI_INIT_COMPLETE_F1	R/W	0h	Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency copy 1, the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY.
15-10	RESERVED	R/W	X
9-0	TDFI_INIT_START_F1	R/W	0h	Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency copy 1, the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY.

2.5.2.151 DDRSS_CTL_152 Register (Offset = 260h) [reset = X]

DDRSS_CTL_152 is shown in Figure 8-243 and described in Table 8-494.

Return to Summary Table.

Table 8-493 DDRSS_CTL_152 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0260h

Figure 8-243 DDRSS_CTL_152 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TDFI_INIT_COMPLETE_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TDFI_INIT_START_F2
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-494 DDRSS_CTL_152 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TDFI_INIT_COMPLETE_F2	R/W	0h	Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency copy 2, the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY.
15-10	RESERVED	R/W	X
9-0	TDFI_INIT_START_F2	R/W	0h	Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency copy 2, the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY.

2.5.2.152 DDRSS_CTL_153 Register (Offset = 264h) [reset = X]

DDRSS_CTL_153 is shown in Figure 8-244 and described in Table 8-496.

Return to Summary Table.

Table 8-495 DDRSS_CTL_153 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0264h

Figure 8-244 DDRSS_CTL_153 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED							DFS_PHY_REG_WRITE_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED						CURRENT_REG_COPY
R/W-X						R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-496 DDRSS_CTL_153 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R/W	X
8	DFS_PHY_REG_WRITE_EN	R/W	0h	Enable a register write to the PHY during a frequency change. Set to 1 to enable.
7-2	RESERVED	R/W	X
1-0	CURRENT_REG_COPY	R	0h	Indicates the current copy of timing parameters that is in use by the controller. READ-ONLY

2.5.2.153 DDRSS_CTL_154 Register (Offset = 268h) [reset = 0h]

DDRSS_CTL_154 is shown in Figure 8-245 and described in Table 8-498.

Return to Summary Table.

Table 8-497 DDRSS_CTL_154 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0268h

Figure 8-245 DDRSS_CTL_154 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DFS_PHY_REG_WRITE_ADDR
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-498 DDRSS_CTL_154 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DFS_PHY_REG_WRITE_ADDR	R/W	0h	Register address which will be written during a frequency change. Must be a PHY register address.

2.5.2.154 DDRSS_CTL_155 Register (Offset = 26Ch) [reset = 0h]

DDRSS_CTL_155 is shown in Figure 8-246 and described in Table 8-500.

Return to Summary Table.

Table 8-499 DDRSS_CTL_155 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 026Ch

Figure 8-246 DDRSS_CTL_155 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DFS_PHY_REG_WRITE_DATA_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-500 DDRSS_CTL_155 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DFS_PHY_REG_WRITE_DATA_F0	R/W	0h	Register data which will be written during a frequency change for frequency copy 0.

2.5.2.155 DDRSS_CTL_156 Register (Offset = 270h) [reset = 0h]

DDRSS_CTL_156 is shown in Figure 8-247 and described in Table 8-502.

Return to Summary Table.

Table 8-501 DDRSS_CTL_156 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0270h

Figure 8-247 DDRSS_CTL_156 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DFS_PHY_REG_WRITE_DATA_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-502 DDRSS_CTL_156 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DFS_PHY_REG_WRITE_DATA_F1	R/W	0h	Register data which will be written during a frequency change for frequency copy 1.

2.5.2.156 DDRSS_CTL_157 Register (Offset = 274h) [reset = 0h]

DDRSS_CTL_157 is shown in Figure 8-248 and described in Table 8-504.

Return to Summary Table.

Table 8-503 DDRSS_CTL_157 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0274h

Figure 8-248 DDRSS_CTL_157 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DFS_PHY_REG_WRITE_DATA_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-504 DDRSS_CTL_157 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	DFS_PHY_REG_WRITE_DATA_F2	R/W	0h	Register data which will be written during a frequency change for frequency copy 2.

2.5.2.157 DDRSS_CTL_158 Register (Offset = 278h) [reset = X]

DDRSS_CTL_158 is shown in Figure 8-249 and described in Table 8-506.

Return to Summary Table.

Table 8-505 DDRSS_CTL_158 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0278h

Figure 8-249 DDRSS_CTL_158 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
DFS_PHY_REG_WRITE_WAIT
R/W-0h

15	14	13	12	11	10	9	8
DFS_PHY_REG_WRITE_WAIT
R/W-0h

7	6	5	4	3	2	1	0
RESERVED				DFS_PHY_REG_WRITE_MASK
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-506 DDRSS_CTL_158 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-8	DFS_PHY_REG_WRITE_WAIT	R/W	0h	Defines the number of DFI PHY clocks that the controller will wait after issuing the register write to the PHY during a frequency change.
7-4	RESERVED	R/W	X
3-0	DFS_PHY_REG_WRITE_MASK	R/W	0h	Register mask which will be written during a frequency change.

2.5.2.158 DDRSS_CTL_159 Register (Offset = 27Ch) [reset = X]

DDRSS_CTL_159 is shown in Figure 8-250 and described in Table 8-508.

Return to Summary Table.

Table 8-507 DDRSS_CTL_159 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 027Ch

Figure 8-250 DDRSS_CTL_159 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED					WRITE_MODEREG
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-508 DDRSS_CTL_159 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-0	WRITE_MODEREG	R/W	0h	Write memory mode register data to the DRAMs. Bits ( 7:0) define the memory mode register number if bit (23) is set, bits ( 15:8) define the chip select if bit (24) is clear, bits ( 23:16) define which memory mode register/s to write, bit (24) defines whether all chip selects will be written, and bit (25) triggers the write.

2.5.2.159 DDRSS_CTL_160 Register (Offset = 280h) [reset = X]

DDRSS_CTL_160 is shown in Figure 8-251 and described in Table 8-510.

Return to Summary Table.

Table 8-509 DDRSS_CTL_160 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0280h

Figure 8-251 DDRSS_CTL_160 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED							READ_MODEREG
R/W-X							R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
READ_MODEREG								MRW_STATUS
R/W-0h								R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-510 DDRSS_CTL_160 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24-8	READ_MODEREG	R/W	0h	Read the specified memory mode register from specified chip when start bit set. Bits ( 7:0) define the memory mode register and bits ( 15:8) define the chip select. Set bit (16) to 1 to trigger.
7-0	MRW_STATUS	R	0h	Write memory mode register status. Bit (0) set indicates a WRITE_MODEREG parameter programming error. Bit (1) set indicates a PASR error. Bit (2) is Reserved. Bit (3) set indicates a self-refresh or deep power-down error. Bit (4) set indicates that a write to MR3 or MR11 was attempted (WRITE_MODEREG bit (25) was asserted with bit (17) set, or bit (23) was asserted with bits ( 7:0) defining MR3 or MR11) during tZQCAL after a ZQ calibration start command. READ-ONLY

2.5.2.160 DDRSS_CTL_161 Register (Offset = 284h) [reset = 0h]

DDRSS_CTL_161 is shown in Figure 8-252 and described in Table 8-512.

Return to Summary Table.

Table 8-511 DDRSS_CTL_161 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0284h

Figure 8-252 DDRSS_CTL_161 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PERIPHERAL_MRR_DATA_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-512 DDRSS_CTL_161 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PERIPHERAL_MRR_DATA_0	R	0h	Data and chip returned from memory mode register read requested by the READ_MODEREG parameter. Bits (7:0) indicate the read data and bits (15:8) indicate the chip. READ-ONLY

2.5.2.161 DDRSS_CTL_162 Register (Offset = 288h) [reset = X]

DDRSS_CTL_162 is shown in Figure 8-253 and described in Table 8-514.

Return to Summary Table.

Table 8-513 DDRSS_CTL_162 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0288h

Figure 8-253 DDRSS_CTL_162 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED								AUTO_TEMPCHK_VAL_0
R-X								R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AUTO_TEMPCHK_VAL_0								PERIPHERAL_MRR_DATA_1
R-0h								R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-514 DDRSS_CTL_162 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X
23-8	AUTO_TEMPCHK_VAL_0	R	0h	MR4 data for all devices on chip 0 accessed by automatic MRR commands. Bits (3:0) correlate to the device on the lower byte, bits (7:4) correlate to the devices on the 2nd byte etc. Value indicates the OP7, OP2, OP1 and OP0 bits. READ-ONLY
7-0	PERIPHERAL_MRR_DATA_1	R	0h	Data and chip returned from memory mode register read requested by the READ_MODEREG parameter. Bits (7:0) indicate the read data and bits (15:8) indicate the chip. READ-ONLY

2.5.2.162 DDRSS_CTL_163 Register (Offset = 28Ch) [reset = X]

DDRSS_CTL_163 is shown in Figure 8-254 and described in Table 8-516.

Return to Summary Table.

Table 8-515 DDRSS_CTL_163 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 028Ch

Figure 8-254 DDRSS_CTL_163 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED							DISABLE_UPDATE_TVRCG
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
AUTO_TEMPCHK_VAL_1
R-0h

7	6	5	4	3	2	1	0
AUTO_TEMPCHK_VAL_1
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-516 DDRSS_CTL_163 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R/W	X
16	DISABLE_UPDATE_TVRCG	R/W	0h	Bypass changing for TVRCG during a DFS operation. Set to 1 to skip TVRCG.
15-0	AUTO_TEMPCHK_VAL_1	R	0h	MR4 data for all devices on chip 1 accessed by automatic MRR commands. Bits (3:0) correlate to the device on the lower byte, bits (7:4) correlate to the devices on the 2nd byte etc. Value indicates the OP7, OP2, OP1 and OP0 bits. READ-ONLY

2.5.2.163 DDRSS_CTL_164 Register (Offset = 290h) [reset = X]

DDRSS_CTL_164 is shown in Figure 8-255 and described in Table 8-518.

Return to Summary Table.

Table 8-517 DDRSS_CTL_164 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0290h

Figure 8-255 DDRSS_CTL_164 Register

31	30	29	28	27	26	25	24
RESERVED						TVRCG_ENABLE_F0
R/W-X						R/W-0h

23	22	21	20	19	18	17	16
TVRCG_ENABLE_F0
R/W-0h

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED						MRW_DFS_UPDATE_FRC
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-518 DDRSS_CTL_164 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TVRCG_ENABLE_F0	R/W	0h	JEDEC TVRCG_ENABLE time.
15-2	RESERVED	R/W	X
1-0	MRW_DFS_UPDATE_FRC	R/W	0h	Defines the frequency register set to use when doing a software MRW with WRITE_MODEREG bit (26).

2.5.2.164 DDRSS_CTL_165 Register (Offset = 294h) [reset = X]

DDRSS_CTL_165 is shown in Figure 8-256 and described in Table 8-520.

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Table 8-519 DDRSS_CTL_165 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0294h

Figure 8-256 DDRSS_CTL_165 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED						TFC_F0
R/W-X						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TVRCG_DISABLE_F0
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-520 DDRSS_CTL_165 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TFC_F0	R/W	0h	JEDEC TFC, the frequency set point switching time.
15-10	RESERVED	R/W	X
9-0	TVRCG_DISABLE_F0	R/W	0h	JEDEC TVRCG_DISABLE time.

2.5.2.165 DDRSS_CTL_166 Register (Offset = 298h) [reset = X]

DDRSS_CTL_166 is shown in Figure 8-257 and described in Table 8-522.

Return to Summary Table.

Table 8-521 DDRSS_CTL_166 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0298h

Figure 8-257 DDRSS_CTL_166 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TVREF_LONG_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCKFSPX_F0					RESERVED			TCKFSPE_F0
R/W-X			R/W-0h					R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-522 DDRSS_CTL_166 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TVREF_LONG_F0	R/W	0h	JEDEC TVREF, design will always use the long value.
15-13	RESERVED	R/W	X
12-8	TCKFSPX_F0	R/W	0h	JEDEC TCKFSPX, the valid clock requirement before 1st valid command after FSP change.
7-5	RESERVED	R/W	X
4-0	TCKFSPE_F0	R/W	0h	JEDEC TCKFSPE, the valid clock requirement after entering SDP change.

2.5.2.166 DDRSS_CTL_167 Register (Offset = 29Ch) [reset = X]

DDRSS_CTL_167 is shown in Figure 8-258 and described in Table 8-524.

Return to Summary Table.

Table 8-523 DDRSS_CTL_167 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 029Ch

Figure 8-258 DDRSS_CTL_167 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED						TVRCG_DISABLE_F1
R/W-X						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TVRCG_ENABLE_F1
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-524 DDRSS_CTL_167 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TVRCG_DISABLE_F1	R/W	0h	JEDEC TVRCG_DISABLE time.
15-10	RESERVED	R/W	X
9-0	TVRCG_ENABLE_F1	R/W	0h	JEDEC TVRCG_ENABLE time.

2.5.2.167 DDRSS_CTL_168 Register (Offset = 2A0h) [reset = X]

DDRSS_CTL_168 is shown in Figure 8-259 and described in Table 8-526.

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Table 8-525 DDRSS_CTL_168 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02A0h

Figure 8-259 DDRSS_CTL_168 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED			TCKFSPX_F1					RESERVED			TCKFSPE_F1
R/W-X			R/W-0h					R/W-X			R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TFC_F1
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-526 DDRSS_CTL_168 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	TCKFSPX_F1	R/W	0h	JEDEC TCKFSPX, the valid clock requirement before 1st valid command after FSP change.
23-21	RESERVED	R/W	X
20-16	TCKFSPE_F1	R/W	0h	JEDEC TCKFSPE, the valid clock requirement after entering SDP change.
15-10	RESERVED	R/W	X
9-0	TFC_F1	R/W	0h	JEDEC TFC, the frequency set point switching time.

2.5.2.168 DDRSS_CTL_169 Register (Offset = 2A4h) [reset = X]

DDRSS_CTL_169 is shown in Figure 8-260 and described in Table 8-528.

Return to Summary Table.

Table 8-527 DDRSS_CTL_169 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02A4h

Figure 8-260 DDRSS_CTL_169 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED						TVRCG_ENABLE_F2
R/W-X						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TVREF_LONG_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-528 DDRSS_CTL_169 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TVRCG_ENABLE_F2	R/W	0h	JEDEC TVRCG_ENABLE time.
15-0	TVREF_LONG_F1	R/W	0h	JEDEC TVREF, design will always use the long value.

2.5.2.169 DDRSS_CTL_170 Register (Offset = 2A8h) [reset = X]

DDRSS_CTL_170 is shown in Figure 8-261 and described in Table 8-530.

Return to Summary Table.

Table 8-529 DDRSS_CTL_170 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02A8h

Figure 8-261 DDRSS_CTL_170 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED						TFC_F2
R/W-X						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TVRCG_DISABLE_F2
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-530 DDRSS_CTL_170 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TFC_F2	R/W	0h	JEDEC TFC, the frequency set point switching time.
15-10	RESERVED	R/W	X
9-0	TVRCG_DISABLE_F2	R/W	0h	JEDEC TVRCG_DISABLE time.

2.5.2.170 DDRSS_CTL_171 Register (Offset = 2ACh) [reset = X]

DDRSS_CTL_171 is shown in Figure 8-262 and described in Table 8-532.

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Table 8-531 DDRSS_CTL_171 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02ACh

Figure 8-262 DDRSS_CTL_171 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TVREF_LONG_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED			TCKFSPX_F2					RESERVED			TCKFSPE_F2
R/W-X			R/W-0h					R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-532 DDRSS_CTL_171 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	TVREF_LONG_F2	R/W	0h	JEDEC TVREF, design will always use the long value.
15-13	RESERVED	R/W	X
12-8	TCKFSPX_F2	R/W	0h	JEDEC TCKFSPX, the valid clock requirement before 1st valid command after FSP change.
7-5	RESERVED	R/W	X
4-0	TCKFSPE_F2	R/W	0h	JEDEC TCKFSPE, the valid clock requirement after entering SDP change.

2.5.2.171 DDRSS_CTL_172 Register (Offset = 2B0h) [reset = 0h]

DDRSS_CTL_172 is shown in Figure 8-263 and described in Table 8-534.

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Table 8-533 DDRSS_CTL_172 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02B0h

Figure 8-263 DDRSS_CTL_172 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MRR_PROMOTE_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MRR_PROMOTE_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-534 DDRSS_CTL_172 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MRR_PROMOTE_THRESHOLD_F1	R/W	0h	MRR promotion number of long counts until the high priority request is asserted for frequency copy 1. Applies to SW MRR commands.
15-0	MRR_PROMOTE_THRESHOLD_F0	R/W	0h	MRR promotion number of long counts until the high priority request is asserted for frequency copy 0. Applies to SW MRR commands.

2.5.2.172 DDRSS_CTL_173 Register (Offset = 2B4h) [reset = 0h]

DDRSS_CTL_173 is shown in Figure 8-264 and described in Table 8-536.

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Table 8-535 DDRSS_CTL_173 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02B4h

Figure 8-264 DDRSS_CTL_173 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MRW_PROMOTE_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MRR_PROMOTE_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-536 DDRSS_CTL_173 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MRW_PROMOTE_THRESHOLD_F0	R/W	0h	MRW promotion number of long counts until the high priority request is asserted for frequency copy 0. Applies to SW MRW commands.
15-0	MRR_PROMOTE_THRESHOLD_F2	R/W	0h	MRR promotion number of long counts until the high priority request is asserted for frequency copy 2. Applies to SW MRR commands.

2.5.2.173 DDRSS_CTL_174 Register (Offset = 2B8h) [reset = 0h]

DDRSS_CTL_174 is shown in Figure 8-265 and described in Table 8-538.

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Table 8-537 DDRSS_CTL_174 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02B8h

Figure 8-265 DDRSS_CTL_174 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MRW_PROMOTE_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MRW_PROMOTE_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-538 DDRSS_CTL_174 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MRW_PROMOTE_THRESHOLD_F2	R/W	0h	MRW promotion number of long counts until the high priority request is asserted for frequency copy 2. Applies to SW MRW commands.
15-0	MRW_PROMOTE_THRESHOLD_F1	R/W	0h	MRW promotion number of long counts until the high priority request is asserted for frequency copy 1. Applies to SW MRW commands.

2.5.2.174 DDRSS_CTL_175 Register (Offset = 2BCh) [reset = 0h]

DDRSS_CTL_175 is shown in Figure 8-266 and described in Table 8-540.

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Table 8-539 DDRSS_CTL_175 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02BCh

Figure 8-266 DDRSS_CTL_175 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR2_DATA_F1_0								MR1_DATA_F1_0
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR2_DATA_F0_0								MR1_DATA_F0_0
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-540 DDRSS_CTL_175 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR2_DATA_F1_0	R/W	0h	Data to program into memory mode register 2 for chip select 0 for frequency copy 1.
23-16	MR1_DATA_F1_0	R/W	0h	Data to program into memory mode register 1 for chip select 0 for frequency copy 1.
15-8	MR2_DATA_F0_0	R/W	0h	Data to program into memory mode register 2 for chip select 0 for frequency copy 0.
7-0	MR1_DATA_F0_0	R/W	0h	Data to program into memory mode register 1 for chip select 0 for frequency copy 0.

2.5.2.175 DDRSS_CTL_176 Register (Offset = 2C0h) [reset = 0h]

DDRSS_CTL_176 is shown in Figure 8-267 and described in Table 8-542.

Return to Summary Table.

Table 8-541 DDRSS_CTL_176 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02C0h

Figure 8-267 DDRSS_CTL_176 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR3_DATA_F0_0								MRSINGLE_DATA_0
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR2_DATA_F2_0								MR1_DATA_F2_0
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-542 DDRSS_CTL_176 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR3_DATA_F0_0	R/W	0h	Data to program into memory mode register 3 for chip select 0 for frequency copy 0.
23-16	MRSINGLE_DATA_0	R/W	0h	Data to program into memory mode register single write to chip select 0.
15-8	MR2_DATA_F2_0	R/W	0h	Data to program into memory mode register 2 for chip select 0 for frequency copy 2.
7-0	MR1_DATA_F2_0	R/W	0h	Data to program into memory mode register 1 for chip select 0 for frequency copy 2.

2.5.2.176 DDRSS_CTL_177 Register (Offset = 2C4h) [reset = 0h]

DDRSS_CTL_177 is shown in Figure 8-268 and described in Table 8-544.

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Table 8-543 DDRSS_CTL_177 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02C4h

Figure 8-268 DDRSS_CTL_177 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR4_DATA_F1_0								MR4_DATA_F0_0
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR3_DATA_F2_0								MR3_DATA_F1_0
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-544 DDRSS_CTL_177 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR4_DATA_F1_0	R/W	0h	Data to program into memory mode register 4 for chip select 0 for frequency copy 1.
23-16	MR4_DATA_F0_0	R/W	0h	Data to program into memory mode register 4 for chip select 0 for frequency copy 0.
15-8	MR3_DATA_F2_0	R/W	0h	Data to program into memory mode register 3 for chip select 0 for frequency copy 2.
7-0	MR3_DATA_F1_0	R/W	0h	Data to program into memory mode register 3 for chip select 0 for frequency copy 1.

2.5.2.177 DDRSS_CTL_178 Register (Offset = 2C8h) [reset = 0h]

DDRSS_CTL_178 is shown in Figure 8-269 and described in Table 8-546.

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Table 8-545 DDRSS_CTL_178 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02C8h

Figure 8-269 DDRSS_CTL_178 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR11_DATA_F1_0								MR11_DATA_F0_0
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR8_DATA_0								MR4_DATA_F2_0
R-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-546 DDRSS_CTL_178 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR11_DATA_F1_0	R/W	0h	Data to program into memory mode register 11 for chip select 0 for frequency copy 1.
23-16	MR11_DATA_F0_0	R/W	0h	Data to program into memory mode register 11 for chip select 0 for frequency copy 0.
15-8	MR8_DATA_0	R	0h	Data read from MR8 for chip select 0. READ-ONLY
7-0	MR4_DATA_F2_0	R/W	0h	Data to program into memory mode register 4 for chip select 0 for frequency copy 2.

2.5.2.178 DDRSS_CTL_179 Register (Offset = 2CCh) [reset = 0h]

DDRSS_CTL_179 is shown in Figure 8-270 and described in Table 8-548.

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Table 8-547 DDRSS_CTL_179 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02CCh

Figure 8-270 DDRSS_CTL_179 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR12_DATA_F2_0								MR12_DATA_F1_0
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR12_DATA_F0_0								MR11_DATA_F2_0
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-548 DDRSS_CTL_179 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR12_DATA_F2_0	R/W	0h	Data to program into memory mode register 12 for chip select 0.
23-16	MR12_DATA_F1_0	R/W	0h	Data to program into memory mode register 12 for chip select 0.
15-8	MR12_DATA_F0_0	R/W	0h	Data to program into memory mode register 12 for chip select 0.
7-0	MR11_DATA_F2_0	R/W	0h	Data to program into memory mode register 11 for chip select 0 for frequency copy 2.

2.5.2.179 DDRSS_CTL_180 Register (Offset = 2D0h) [reset = 0h]

DDRSS_CTL_180 is shown in Figure 8-271 and described in Table 8-550.

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Table 8-549 DDRSS_CTL_180 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02D0h

Figure 8-271 DDRSS_CTL_180 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR14_DATA_F2_0								MR14_DATA_F1_0
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR14_DATA_F0_0								MR13_DATA_0
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-550 DDRSS_CTL_180 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR14_DATA_F2_0	R/W	0h	Data to program into memory mode register 14 for chip select 0.
23-16	MR14_DATA_F1_0	R/W	0h	Data to program into memory mode register 14 for chip select 0.
15-8	MR14_DATA_F0_0	R/W	0h	Data to program into memory mode register 14 for chip select 0.
7-0	MR13_DATA_0	R/W	0h	Data to program into memory mode register 13 for chip select 0.

2.5.2.180 DDRSS_CTL_181 Register (Offset = 2D4h) [reset = 0h]

DDRSS_CTL_181 is shown in Figure 8-272 and described in Table 8-552.

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Table 8-551 DDRSS_CTL_181 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02D4h

Figure 8-272 DDRSS_CTL_181 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR22_DATA_F0_0								MR20_DATA_0
R/W-0h								R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR17_DATA_0								MR16_DATA_0
R/W-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-552 DDRSS_CTL_181 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR22_DATA_F0_0	R/W	0h	Data to program into memory mode register 22 for chip select 0.
23-16	MR20_DATA_0	R	0h	Data read from MR20 for chip select 0. READ-ONLY
15-8	MR17_DATA_0	R/W	0h	Data to program into memory mode register 17 for chip select 0.
7-0	MR16_DATA_0	R/W	0h	Data to program into memory mode register 16 for chip select 0.

2.5.2.181 DDRSS_CTL_182 Register (Offset = 2D8h) [reset = 0h]

DDRSS_CTL_182 is shown in Figure 8-273 and described in Table 8-554.

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Table 8-553 DDRSS_CTL_182 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02D8h

Figure 8-273 DDRSS_CTL_182 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR2_DATA_F0_1								MR1_DATA_F0_1
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR22_DATA_F2_0								MR22_DATA_F1_0
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-554 DDRSS_CTL_182 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR2_DATA_F0_1	R/W	0h	Data to program into memory mode register 2 for chip select 1 for frequency copy 0.
23-16	MR1_DATA_F0_1	R/W	0h	Data to program into memory mode register 1 for chip select 1 for frequency copy 0.
15-8	MR22_DATA_F2_0	R/W	0h	Data to program into memory mode register 22 for chip select 0.
7-0	MR22_DATA_F1_0	R/W	0h	Data to program into memory mode register 22 for chip select 0.

2.5.2.182 DDRSS_CTL_183 Register (Offset = 2DCh) [reset = 0h]

DDRSS_CTL_183 is shown in Figure 8-274 and described in Table 8-556.

Return to Summary Table.

Table 8-555 DDRSS_CTL_183 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02DCh

Figure 8-274 DDRSS_CTL_183 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR2_DATA_F2_1								MR1_DATA_F2_1
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR2_DATA_F1_1								MR1_DATA_F1_1
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-556 DDRSS_CTL_183 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR2_DATA_F2_1	R/W	0h	Data to program into memory mode register 2 for chip select 1 for frequency copy 2.
23-16	MR1_DATA_F2_1	R/W	0h	Data to program into memory mode register 1 for chip select 1 for frequency copy 2.
15-8	MR2_DATA_F1_1	R/W	0h	Data to program into memory mode register 2 for chip select 1 for frequency copy 1.
7-0	MR1_DATA_F1_1	R/W	0h	Data to program into memory mode register 1 for chip select 1 for frequency copy 1.

2.5.2.183 DDRSS_CTL_184 Register (Offset = 2E0h) [reset = 0h]

DDRSS_CTL_184 is shown in Figure 8-275 and described in Table 8-558.

Return to Summary Table.

Table 8-557 DDRSS_CTL_184 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02E0h

Figure 8-275 DDRSS_CTL_184 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR3_DATA_F2_1								MR3_DATA_F1_1
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR3_DATA_F0_1								MRSINGLE_DATA_1
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-558 DDRSS_CTL_184 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR3_DATA_F2_1	R/W	0h	Data to program into memory mode register 3 for chip select 1 for frequency copy 2.
23-16	MR3_DATA_F1_1	R/W	0h	Data to program into memory mode register 3 for chip select 1 for frequency copy 1.
15-8	MR3_DATA_F0_1	R/W	0h	Data to program into memory mode register 3 for chip select 1 for frequency copy 0.
7-0	MRSINGLE_DATA_1	R/W	0h	Data to program into memory mode register single write to chip select 1.

2.5.2.184 DDRSS_CTL_185 Register (Offset = 2E4h) [reset = 0h]

DDRSS_CTL_185 is shown in Figure 8-276 and described in Table 8-560.

Return to Summary Table.

Table 8-559 DDRSS_CTL_185 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02E4h

Figure 8-276 DDRSS_CTL_185 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR8_DATA_1								MR4_DATA_F2_1
R-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR4_DATA_F1_1								MR4_DATA_F0_1
R/W-0h								R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-560 DDRSS_CTL_185 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR8_DATA_1	R	0h	Data read from MR8 for chip select 1. READ-ONLY
23-16	MR4_DATA_F2_1	R/W	0h	Data to program into memory mode register 4 for chip select 1 for frequency copy 2.
15-8	MR4_DATA_F1_1	R/W	0h	Data to program into memory mode register 4 for chip select 1 for frequency copy 1.
7-0	MR4_DATA_F0_1	R/W	0h	Data to program into memory mode register 4 for chip select 1 for frequency copy 0.

2.5.2.185 DDRSS_CTL_186 Register (Offset = 2E8h) [reset = 0h]

DDRSS_CTL_186 is shown in Figure 8-277 and described in Table 8-562.

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Table 8-561 DDRSS_CTL_186 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02E8h

Figure 8-277 DDRSS_CTL_186 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR12_DATA_F0_1								MR11_DATA_F2_1
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR11_DATA_F1_1								MR11_DATA_F0_1
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-562 DDRSS_CTL_186 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR12_DATA_F0_1	R/W	0h	Data to program into memory mode register 12 for chip select 1.
23-16	MR11_DATA_F2_1	R/W	0h	Data to program into memory mode register 11 for chip select 1 for frequency copy 2.
15-8	MR11_DATA_F1_1	R/W	0h	Data to program into memory mode register 11 for chip select 1 for frequency copy 1.
7-0	MR11_DATA_F0_1	R/W	0h	Data to program into memory mode register 11 for chip select 1 for frequency copy 0.

2.5.2.186 DDRSS_CTL_187 Register (Offset = 2ECh) [reset = 0h]

DDRSS_CTL_187 is shown in Figure 8-278 and described in Table 8-564.

Return to Summary Table.

Table 8-563 DDRSS_CTL_187 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02ECh

Figure 8-278 DDRSS_CTL_187 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR14_DATA_F0_1								MR13_DATA_1
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR12_DATA_F2_1								MR12_DATA_F1_1
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-564 DDRSS_CTL_187 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR14_DATA_F0_1	R/W	0h	Data to program into memory mode register 14 for chip select 1.
23-16	MR13_DATA_1	R/W	0h	Data to program into memory mode register 13 for chip select 1.
15-8	MR12_DATA_F2_1	R/W	0h	Data to program into memory mode register 12 for chip select 1.
7-0	MR12_DATA_F1_1	R/W	0h	Data to program into memory mode register 12 for chip select 1.

2.5.2.187 DDRSS_CTL_188 Register (Offset = 2F0h) [reset = 0h]

DDRSS_CTL_188 is shown in Figure 8-279 and described in Table 8-566.

Return to Summary Table.

Table 8-565 DDRSS_CTL_188 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02F0h

Figure 8-279 DDRSS_CTL_188 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR17_DATA_1								MR16_DATA_1
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR14_DATA_F2_1								MR14_DATA_F1_1
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-566 DDRSS_CTL_188 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR17_DATA_1	R/W	0h	Data to program into memory mode register 17 for chip select 1.
23-16	MR16_DATA_1	R/W	0h	Data to program into memory mode register 16 for chip select 1.
15-8	MR14_DATA_F2_1	R/W	0h	Data to program into memory mode register 14 for chip select 1.
7-0	MR14_DATA_F1_1	R/W	0h	Data to program into memory mode register 14 for chip select 1.

2.5.2.188 DDRSS_CTL_189 Register (Offset = 2F4h) [reset = 0h]

DDRSS_CTL_189 is shown in Figure 8-280 and described in Table 8-568.

Return to Summary Table.

Table 8-567 DDRSS_CTL_189 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02F4h

Figure 8-280 DDRSS_CTL_189 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MR22_DATA_F2_1								MR22_DATA_F1_1
R/W-0h								R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MR22_DATA_F0_1								MR20_DATA_1
R/W-0h								R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-568 DDRSS_CTL_189 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	MR22_DATA_F2_1	R/W	0h	Data to program into memory mode register 22 for chip select 1.
23-16	MR22_DATA_F1_1	R/W	0h	Data to program into memory mode register 22 for chip select 1.
15-8	MR22_DATA_F0_1	R/W	0h	Data to program into memory mode register 22 for chip select 1.
7-0	MR20_DATA_1	R	0h	Data read from MR20 for chip select 1. READ-ONLY

2.5.2.189 DDRSS_CTL_190 Register (Offset = 2F8h) [reset = X]

DDRSS_CTL_190 is shown in Figure 8-281 and described in Table 8-570.

Return to Summary Table.

Table 8-569 DDRSS_CTL_190 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02F8h

Figure 8-281 DDRSS_CTL_190 Register

31	30	29	28	27	26	25	24
RESERVED							MR_FSP_DATA_VALID_F2
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							MR_FSP_DATA_VALID_F1
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							MR_FSP_DATA_VALID_F0
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
MR23_DATA
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-570 DDRSS_CTL_190 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	MR_FSP_DATA_VALID_F2	R/W	0h	Indicates that, at this frequency, memory was trained and the associated data has been loaded into the MRx_DATA parameter(s). Value of 1 means memory was trained.
23-17	RESERVED	R/W	X
16	MR_FSP_DATA_VALID_F1	R/W	0h	Indicates that, at this frequency, memory was trained and the associated data has been loaded into the MRx_DATA parameter(s). Value of 1 means memory was trained.
15-9	RESERVED	R/W	X
8	MR_FSP_DATA_VALID_F0	R/W	0h	Indicates that, at this frequency, memory was trained and the associated data has been loaded into the MRx_DATA parameter(s). Value of 1 means memory was trained.
7-0	MR23_DATA	R/W	0h	Data to program into memory mode register 23.

2.5.2.190 DDRSS_CTL_191 Register (Offset = 2FCh) [reset = X]

DDRSS_CTL_191 is shown in Figure 8-282 and described in Table 8-572.

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Table 8-571 DDRSS_CTL_191 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 02FCh

Figure 8-282 DDRSS_CTL_191 Register

31	30	29	28	27	26	25	24
RESERVED							FSP_PHY_UPDATE_MRW
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							RESERVED
R/W-X							R-0h

15	14	13	12	11	10	9	8
RESERVED							RESERVED
R/W-X							R-0h

7	6	5	4	3	2	1	0
RESERVED						RL3_SUPPORT_EN
R/W-X						R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-572 DDRSS_CTL_191 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	FSP_PHY_UPDATE_MRW	R/W	0h	Identifies the logic responsible for updating MR12 and MR14 in memory. Clear to 0 for the controller, or set to 1 for the PHY or PI.
23-17	RESERVED	R/W	X
16	RESERVED	R	0h	Reserved
15-9	RESERVED	R/W	X
8	RESERVED	R	0h	Reserved
7-2	RESERVED	R/W	X
1-0	RL3_SUPPORT_EN	R	0h	Indicates if RL3 is supported by a connected LPDDR3 memory. Data read from MR0 bit 7. READ-ONLY

2.5.2.191 DDRSS_CTL_192 Register (Offset = 300h) [reset = X]

DDRSS_CTL_192 is shown in Figure 8-283 and described in Table 8-574.

Return to Summary Table.

Table 8-573 DDRSS_CTL_192 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0300h

Figure 8-283 DDRSS_CTL_192 Register

31	30	29	28	27	26	25	24
RESERVED							FSP_WR_CURRENT
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							FSP_OP_CURRENT
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							FSP_STATUS
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							DFS_ALWAYS_WRITE_FSP
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-574 DDRSS_CTL_192 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	FSP_WR_CURRENT	R/W	0h	Reports which FSP set the memory will target with write commands.
23-17	RESERVED	R/W	X
16	FSP_OP_CURRENT	R/W	0h	Reports which FSP set the memory is currently using.
15-9	RESERVED	R/W	X
8	FSP_STATUS	R/W	0h	Indicates that a DFS event caused the FSP mode registers to be updated. Value of 1 means that the FSP mode registers were changed.
7-1	RESERVED	R/W	X
0	DFS_ALWAYS_WRITE_FSP	R/W	0h	Forces all FSP mode registers to be written by the controller during a DFS event. Set to 1 to force the write.

2.5.2.192 DDRSS_CTL_193 Register (Offset = 304h) [reset = X]

DDRSS_CTL_193 is shown in Figure 8-284 and described in Table 8-576.

Return to Summary Table.

Table 8-575 DDRSS_CTL_193 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0304h

Figure 8-284 DDRSS_CTL_193 Register

31	30	29	28	27	26	25	24
RESERVED						FSP1_FRC
R/W-X						R/W-0h

23	22	21	20	19	18	17	16
RESERVED						FSP0_FRC
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
RESERVED							FSP1_FRC_VALID
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							FSP0_FRC_VALID
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-576 DDRSS_CTL_193 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-24	FSP1_FRC	R/W	0h	Identifies which of the controller's frequency copy is associated with FSP1.
23-18	RESERVED	R/W	X
17-16	FSP0_FRC	R/W	0h	Identifies which of the controller's frequency copy is associated with FSP0.
15-9	RESERVED	R/W	X
8	FSP1_FRC_VALID	R/W	0h	Specifies whether the FSP set defined in the FSP1_FRC parameter reflects the frequency used to program the FSP1 registers.
7-1	RESERVED	R/W	X
0	FSP0_FRC_VALID	R/W	0h	Specifies whether the FSP set defined in the FSP0_FRC parameter reflects the frequency used to program the FSP0 registers.

2.5.2.193 DDRSS_CTL_194 Register (Offset = 308h) [reset = X]

DDRSS_CTL_194 is shown in Figure 8-285 and described in Table 8-578.

Return to Summary Table.

Table 8-577 DDRSS_CTL_194 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0308h

Figure 8-285 DDRSS_CTL_194 Register

31	30	29	28	27	26	25	24
RESERVED							BIST_DATA_CHECK
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED		ADDR_SPACE
R/W-X		R/W-0h

15	14	13	12	11	10	9	8
RESERVED						BIST_RESULT
R/W-X						R-0h

7	6	5	4	3	2	1	0
RESERVED							BIST_GO
R/W-X							W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-578 DDRSS_CTL_194 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	BIST_DATA_CHECK	R/W	0h	Enable data checking with BIST operation. Set to 1 to enable.
23-22	RESERVED	R/W	X
21-16	ADDR_SPACE	R/W	0h	Sets the number of address bits to check during BIST operation.
15-10	RESERVED	R/W	X
9-8	BIST_RESULT	R	0h	BIST operation status (pass/fail). Bit (0) indicates data check status and bit (1) indicates address check status. Value of 1 is a passing result. READ-ONLY
7-1	RESERVED	R/W	X
0	BIST_GO	W	0h	Initiate a BIST operation. Set to 1 to trigger. WRITE-ONLY

2.5.2.194 DDRSS_CTL_195 Register (Offset = 30Ch) [reset = X]

DDRSS_CTL_195 is shown in Figure 8-286 and described in Table 8-580.

Return to Summary Table.

Table 8-579 DDRSS_CTL_195 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 030Ch

Figure 8-286 DDRSS_CTL_195 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED							BIST_ADDR_CHECK
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-580 DDRSS_CTL_195 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	X
0	BIST_ADDR_CHECK	R/W	0h	Enable address checking with BIST operation. Set to 1 to enable.

2.5.2.195 DDRSS_CTL_196 Register (Offset = 310h) [reset = 0h]

DDRSS_CTL_196 is shown in Figure 8-287 and described in Table 8-582.

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Table 8-581 DDRSS_CTL_196 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0310h

Figure 8-287 DDRSS_CTL_196 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_START_ADDRESS_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-582 DDRSS_CTL_196 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_START_ADDRESS_0	R/W	0h	Start BIST checking at this address.

2.5.2.196 DDRSS_CTL_197 Register (Offset = 314h) [reset = X]

DDRSS_CTL_197 is shown in Figure 8-288 and described in Table 8-584.

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Table 8-583 DDRSS_CTL_197 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0314h

Figure 8-288 DDRSS_CTL_197 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED					BIST_START_ADDRESS_1
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-584 DDRSS_CTL_197 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R/W	X
2-0	BIST_START_ADDRESS_1	R/W	0h	Start BIST checking at this address.

2.5.2.197 DDRSS_CTL_198 Register (Offset = 318h) [reset = 0h]

DDRSS_CTL_198 is shown in Figure 8-289 and described in Table 8-586.

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Table 8-585 DDRSS_CTL_198 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0318h

Figure 8-289 DDRSS_CTL_198 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_DATA_MASK_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-586 DDRSS_CTL_198 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_DATA_MASK_0	R/W	0h	Mask applied to data for BIST error checking. Bit (0) controls memory data path bit (0), bit (1) controls memory data path bit (1), etc. Set each bit to 1 to mask.

2.5.2.198 DDRSS_CTL_199 Register (Offset = 31Ch) [reset = 0h]

DDRSS_CTL_199 is shown in Figure 8-290 and described in Table 8-588.

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Table 8-587 DDRSS_CTL_199 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 031Ch

Figure 8-290 DDRSS_CTL_199 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_DATA_MASK_1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-588 DDRSS_CTL_199 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_DATA_MASK_1	R/W	0h	Mask applied to data for BIST error checking. Bit (0) controls memory data path bit (0), bit (1) controls memory data path bit (1), etc. Set each bit to 1 to mask.

2.5.2.199 DDRSS_CTL_200 Register (Offset = 320h) [reset = X]

DDRSS_CTL_200 is shown in Figure 8-291 and described in Table 8-590.

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Table 8-589 DDRSS_CTL_200 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0320h

Figure 8-291 DDRSS_CTL_200 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED					BIST_TEST_MODE
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-590 DDRSS_CTL_200 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R/W	X
2-0	BIST_TEST_MODE	R/W	0h	Sets the BIST test mode. Value of 0 specifies standard BIST operation, value of 1 specifies a reduced BIST operation, value of 2 specifies a self-refresh retention test, value of 3 specifies an idle retention test, and value of 4 specifies memory initalization function. All other values are reserved.

2.5.2.200 DDRSS_CTL_201 Register (Offset = 324h) [reset = 0h]

DDRSS_CTL_201 is shown in Figure 8-292 and described in Table 8-592.

Return to Summary Table.

Table 8-591 DDRSS_CTL_201 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0324h

Figure 8-292 DDRSS_CTL_201 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_DATA_PATTERN_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-592 DDRSS_CTL_201 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_DATA_PATTERN_0	R/W	0h	Data pattern to be used when the BIST_TEST_MODE parameter is programmed to 1, 2, 3 or 4.

2.5.2.201 DDRSS_CTL_202 Register (Offset = 328h) [reset = 0h]

DDRSS_CTL_202 is shown in Figure 8-293 and described in Table 8-594.

Return to Summary Table.

Table 8-593 DDRSS_CTL_202 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0328h

Figure 8-293 DDRSS_CTL_202 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_DATA_PATTERN_1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-594 DDRSS_CTL_202 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_DATA_PATTERN_1	R/W	0h	Data pattern to be used when the BIST_TEST_MODE parameter is programmed to 1, 2, 3 or 4.

2.5.2.202 DDRSS_CTL_203 Register (Offset = 32Ch) [reset = 0h]

DDRSS_CTL_203 is shown in Figure 8-294 and described in Table 8-596.

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Table 8-595 DDRSS_CTL_203 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 032Ch

Figure 8-294 DDRSS_CTL_203 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_DATA_PATTERN_2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-596 DDRSS_CTL_203 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_DATA_PATTERN_2	R/W	0h	Data pattern to be used when the BIST_TEST_MODE parameter is programmed to 1, 2, 3 or 4.

2.5.2.203 DDRSS_CTL_204 Register (Offset = 330h) [reset = 0h]

DDRSS_CTL_204 is shown in Figure 8-295 and described in Table 8-598.

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Table 8-597 DDRSS_CTL_204 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0330h

Figure 8-295 DDRSS_CTL_204 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_DATA_PATTERN_3
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-598 DDRSS_CTL_204 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_DATA_PATTERN_3	R/W	0h	Data pattern to be used when the BIST_TEST_MODE parameter is programmed to 1, 2, 3 or 4.

2.5.2.204 DDRSS_CTL_205 Register (Offset = 334h) [reset = X]

DDRSS_CTL_205 is shown in Figure 8-296 and described in Table 8-600.

Return to Summary Table.

Table 8-599 DDRSS_CTL_205 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0334h

Figure 8-296 DDRSS_CTL_205 Register

31	30	29	28	27	26	25	24
RESERVED				BIST_ERR_STOP
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
BIST_ERR_STOP
R/W-0h

15	14	13	12	11	10	9	8
RESERVED							BIST_RET_STATE
R/W-X							R-0h

7	6	5	4	3	2	1	0
RESERVED							BIST_RET_STATE_EXIT
R/W-X							W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-600 DDRSS_CTL_205 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-16	BIST_ERR_STOP	R/W	0h	Defines the maximum number of error occurrences allowed prior to quitting when the BIST_TEST_MODE parameter is programmed to 1, 2 or 3. A value of 0 will allow the test to run to completion.
15-9	RESERVED	R/W	X
8	BIST_RET_STATE	R	0h	Indicates if BIST is in a retention wait state, used when the BIST_TEST_MODE parameter is programmed to 2 or 3. Value of 1 indicates BIST is waiting. READ-ONLY
7-1	RESERVED	R/W	X
0	BIST_RET_STATE_EXIT	W	0h	Exit self-refresh or idle retention state, used when the BIST_TEST_MODE parameter is programmed to 2 or 3. Set to 1 to trigger. WRITE-ONLY

2.5.2.205 DDRSS_CTL_206 Register (Offset = 338h) [reset = X]

DDRSS_CTL_206 is shown in Figure 8-297 and described in Table 8-602.

Return to Summary Table.

Note:

The ECC Engine block of the DDR controller is not supported.

Table 8-601 DDRSS_CTL_206 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0338h

Figure 8-297 DDRSS_CTL_206 Register

31	30	29	28	27	26	25	24
RESERVED					INLINE_ECC_BANK_OFFSET
R/W-X					R/W-0h

23	22	21	20	19	18	17	16
RESERVED						ECC_ENABLE
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
RESERVED				BIST_ERR_COUNT
R/W-X				R-0h

7	6	5	4	3	2	1	0
BIST_ERR_COUNT
R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-602 DDRSS_CTL_206 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-24	INLINE_ECC_BANK_OFFSET	R/W	0h	Inline ECC Bank Offset defines the bank shift between data and ECC commands associated with the same sequence the bank is offset to prevent inefficiencies due to opening an closing the pages on the same bank during transition between data and ECC commands.
23-18	RESERVED	R/W	X
17-16	ECC_ENABLE	R/W	0h	ECC error checking and correcting control register. Clear to 0 to fully disable ECC, program to 1 to enable ECC with no error detection or error correction, program to 2 to enable ECC with error detection without error correction, or program to 3 to enable ECC with both error detection and error correction.
15-12	RESERVED	R/W	X
11-0	BIST_ERR_COUNT	R	0h	Indicates the number of BIST errors found when the BIST_TEST_MODE parameter is programmed to 1, 2 or 3. READ-ONLY

2.5.2.206 DDRSS_CTL_207 Register (Offset = 33Ch) [reset = X]

DDRSS_CTL_207 is shown in Figure 8-298 and described in Table 8-604.

Return to Summary Table.

Table 8-603 DDRSS_CTL_207 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 033Ch

Figure 8-298 DDRSS_CTL_207 Register

31	30	29	28	27	26	25	24
RESERVED							RESERVED
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED				RESERVED
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED							ECC_WRITE_COMBINING_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							ECC_READ_CACHING_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-604 DDRSS_CTL_207 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	RESERVED	R/W	0h	Reserved
23-20	RESERVED	R/W	X
19-16	RESERVED	R/W	0h	Reserved
15-9	RESERVED	R/W	X
8	ECC_WRITE_COMBINING_EN	R/W	0h	Allows ECC write data within a given ECC buffer to be combined across commands so that in certain cases where we see multiple ECC writes to the same ECC address, the controller may end up only issuing one final ECC write command to memory.
7-1	RESERVED	R/W	X
0	ECC_READ_CACHING_EN	R/W	0h	Allows ECC read data already in one of the ECC buffers to be used when possible in place of issuing an ECC read command to memory. This implies that some ECC read commands will be dropped in the command queue when it can pull the read data from the buffer instead.

2.5.2.207 DDRSS_CTL_208 Register (Offset = 340h) [reset = X]

DDRSS_CTL_208 is shown in Figure 8-299 and described in Table 8-606.

Return to Summary Table.

Table 8-605 DDRSS_CTL_208 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0340h

Figure 8-299 DDRSS_CTL_208 Register

31	30	29	28	27	26	25	24
RESERVED							ECC_WRITEBACK_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
XOR_CHECK_BITS
R/W-0h

15	14	13	12	11	10	9	8
XOR_CHECK_BITS
R/W-0h

7	6	5	4	3	2	1	0
RESERVED							FWC
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-606 DDRSS_CTL_208 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	ECC_WRITEBACK_EN	R/W	0h	ECC writeback will occur on detection of single bit errors for reads. The ECC_ENABLE parameter must be programmed to 3 for this to take any effect. Note that no writebacks will be issued during BIST.
23-8	XOR_CHECK_BITS	R/W	0h	Value to xor with generated ECC codes for forced write check.
7-1	RESERVED	R/W	X
0	FWC	R/W	0h	Force a write check. Xor the XOR_CHECK_BITS parameter with the ECC code and write to memory. Set to 1 to trigger.

2.5.2.208 DDRSS_CTL_209 Register (Offset = 344h) [reset = X]

DDRSS_CTL_209 is shown in Figure 8-300 and described in Table 8-608.

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Table 8-607 DDRSS_CTL_209 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0344h

Figure 8-300 DDRSS_CTL_209 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED							ECC_DISABLE_W_UC_ERR
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-608 DDRSS_CTL_209 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R/W	X
0	ECC_DISABLE_W_UC_ERR	R/W	0h	Controls auto-corruption of ECC when un-correctable errors occur in R/M/W operations. Set to 1 to disable corruption.

2.5.2.209 DDRSS_CTL_210 Register (Offset = 348h) [reset = 0h]

DDRSS_CTL_210 is shown in Figure 8-301 and described in Table 8-610.

Return to Summary Table.

Table 8-609 DDRSS_CTL_210 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0348h

Figure 8-301 DDRSS_CTL_210 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC_U_ADDR_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-610 DDRSS_CTL_210 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ECC_U_ADDR_0	R	0h	Address of uncorrectable ECC event. READ-ONLY

2.5.2.210 DDRSS_CTL_211 Register (Offset = 34Ch) [reset = X]

DDRSS_CTL_211 is shown in Figure 8-302 and described in Table 8-612.

Return to Summary Table.

Table 8-611 DDRSS_CTL_211 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 034Ch

Figure 8-302 DDRSS_CTL_211 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
ECC_U_SYND
R-0h

7	6	5	4	3	2	1	0
RESERVED					ECC_U_ADDR_1
R-X					R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-612 DDRSS_CTL_211 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	X
15-8	ECC_U_SYND	R	0h	Syndrome for uncorrectable ECC event. READ-ONLY
7-3	RESERVED	R	X
2-0	ECC_U_ADDR_1	R	0h	Address of uncorrectable ECC event. READ-ONLY

2.5.2.211 DDRSS_CTL_212 Register (Offset = 350h) [reset = 0h]

DDRSS_CTL_212 is shown in Figure 8-303 and described in Table 8-614.

Return to Summary Table.

Table 8-613 DDRSS_CTL_212 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0350h

Figure 8-303 DDRSS_CTL_212 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC_U_DATA_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-614 DDRSS_CTL_212 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ECC_U_DATA_0	R	0h	Data associated with uncorrectable ECC event. READ-ONLY

2.5.2.212 DDRSS_CTL_213 Register (Offset = 354h) [reset = 0h]

DDRSS_CTL_213 is shown in Figure 8-304 and described in Table 8-616.

Return to Summary Table.

Table 8-615 DDRSS_CTL_213 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0354h

Figure 8-304 DDRSS_CTL_213 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC_U_DATA_1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-616 DDRSS_CTL_213 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ECC_U_DATA_1	R	0h	Data associated with uncorrectable ECC event. READ-ONLY

2.5.2.213 DDRSS_CTL_214 Register (Offset = 358h) [reset = 0h]

DDRSS_CTL_214 is shown in Figure 8-305 and described in Table 8-618.

Return to Summary Table.

Table 8-617 DDRSS_CTL_214 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0358h

Figure 8-305 DDRSS_CTL_214 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC_C_ADDR_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-618 DDRSS_CTL_214 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ECC_C_ADDR_0	R	0h	Address of correctable ECC event. READ-ONLY

2.5.2.214 DDRSS_CTL_215 Register (Offset = 35Ch) [reset = X]

DDRSS_CTL_215 is shown in Figure 8-306 and described in Table 8-620.

Return to Summary Table.

Table 8-619 DDRSS_CTL_215 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 035Ch

Figure 8-306 DDRSS_CTL_215 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
ECC_C_SYND
R-0h

7	6	5	4	3	2	1	0
RESERVED					ECC_C_ADDR_1
R-X					R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-620 DDRSS_CTL_215 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	X
15-8	ECC_C_SYND	R	0h	Syndrome for correctable ECC event. READ-ONLY
7-3	RESERVED	R	X
2-0	ECC_C_ADDR_1	R	0h	Address of correctable ECC event. READ-ONLY

2.5.2.215 DDRSS_CTL_216 Register (Offset = 360h) [reset = 0h]

DDRSS_CTL_216 is shown in Figure 8-307 and described in Table 8-622.

Return to Summary Table.

Table 8-621 DDRSS_CTL_216 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0360h

Figure 8-307 DDRSS_CTL_216 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC_C_DATA_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-622 DDRSS_CTL_216 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ECC_C_DATA_0	R	0h	Data associated with correctable ECC event. READ-ONLY

2.5.2.216 DDRSS_CTL_217 Register (Offset = 364h) [reset = 0h]

DDRSS_CTL_217 is shown in Figure 8-308 and described in Table 8-624.

Return to Summary Table.

Table 8-623 DDRSS_CTL_217 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0364h

Figure 8-308 DDRSS_CTL_217 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC_C_DATA_1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-624 DDRSS_CTL_217 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ECC_C_DATA_1	R	0h	Data associated with correctable ECC event. READ-ONLY

2.5.2.217 DDRSS_CTL_218 Register (Offset = 368h) [reset = X]

DDRSS_CTL_218 is shown in Figure 8-309 and described in Table 8-626.

Return to Summary Table.

Table 8-625 DDRSS_CTL_218 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0368h

Figure 8-309 DDRSS_CTL_218 Register

31	30	29	28	27	26	25	24
RESERVED	NON_ECC_REGION_START_ADDR_0
R/W-X	R/W-0h

23	22	21	20	19	18	17	16
NON_ECC_REGION_START_ADDR_0
R/W-0h

15	14	13	12	11	10	9	8
RESERVED		ECC_C_ID
R/W-X		R-0h

7	6	5	4	3	2	1	0
RESERVED		ECC_U_ID
R/W-X		R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-626 DDRSS_CTL_218 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30-16	NON_ECC_REGION_START_ADDR_0	R/W	0h	Set the base address of the soft-designated non-ECC region 0. The address written is 1Mbyte aligned.
15-14	RESERVED	R/W	X
13-8	ECC_C_ID	R	0h	Source ID associated with correctable ECC event. READ-ONLY
7-6	RESERVED	R/W	X
5-0	ECC_U_ID	R	0h	Source ID associated with the uncorrectable ECC event. READ-ONLY

2.5.2.218 DDRSS_CTL_219 Register (Offset = 36Ch) [reset = X]

DDRSS_CTL_219 is shown in Figure 8-310 and described in Table 8-628.

Return to Summary Table.

Table 8-627 DDRSS_CTL_219 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 036Ch

Figure 8-310 DDRSS_CTL_219 Register

31	30	29	28	27	26	25	24
RESERVED	NON_ECC_REGION_START_ADDR_1
R/W-X	R/W-0h

23	22	21	20	19	18	17	16
NON_ECC_REGION_START_ADDR_1
R/W-0h

15	14	13	12	11	10	9	8
RESERVED	NON_ECC_REGION_END_ADDR_0
R/W-X	R/W-0h

7	6	5	4	3	2	1	0
NON_ECC_REGION_END_ADDR_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-628 DDRSS_CTL_219 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30-16	NON_ECC_REGION_START_ADDR_1	R/W	0h	Set the base address of the soft-designated non-ECC region 1. The address written is 1Mbyte aligned.
15	RESERVED	R/W	X
14-0	NON_ECC_REGION_END_ADDR_0	R/W	0h	Set the base address of the soft-designated non-ECC region 0. The address written is 1Mbyte aligned.

2.5.2.219 DDRSS_CTL_220 Register (Offset = 370h) [reset = X]

DDRSS_CTL_220 is shown in Figure 8-311 and described in Table 8-630.

Return to Summary Table.

Table 8-629 DDRSS_CTL_220 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0370h

Figure 8-311 DDRSS_CTL_220 Register

31	30	29	28	27	26	25	24
RESERVED	NON_ECC_REGION_START_ADDR_2
R/W-X	R/W-0h

23	22	21	20	19	18	17	16
NON_ECC_REGION_START_ADDR_2
R/W-0h

15	14	13	12	11	10	9	8
RESERVED	NON_ECC_REGION_END_ADDR_1
R/W-X	R/W-0h

7	6	5	4	3	2	1	0
NON_ECC_REGION_END_ADDR_1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-630 DDRSS_CTL_220 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30-16	NON_ECC_REGION_START_ADDR_2	R/W	0h	Set the base address of the soft-designated non-ECC region 2. The address written is 1Mbyte aligned.
15	RESERVED	R/W	X
14-0	NON_ECC_REGION_END_ADDR_1	R/W	0h	Set the base address of the soft-designated non-ECC region 1. The address written is 1Mbyte aligned.

2.5.2.220 DDRSS_CTL_221 Register (Offset = 374h) [reset = X]

DDRSS_CTL_221 is shown in Figure 8-312 and described in Table 8-632.

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Table 8-631 DDRSS_CTL_221 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0374h

Figure 8-312 DDRSS_CTL_221 Register

31	30	29	28	27	26	25	24
RESERVED							ECC_SCRUB_START
R/W-X							W-0h

23	22	21	20	19	18	17	16
RESERVED					NON_ECC_REGION_ENABLE
R/W-X					R/W-0h

15	14	13	12	11	10	9	8
RESERVED	NON_ECC_REGION_END_ADDR_2
R/W-X	R/W-0h

7	6	5	4	3	2	1	0
NON_ECC_REGION_END_ADDR_2
R/W-0h

LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-632 DDRSS_CTL_221 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	ECC_SCRUB_START	W	0h	ECC scrubbing control. Set to 1 to kick start the scrubbing operation. WRITE-ONLY
23-19	RESERVED	R/W	X
18-16	NON_ECC_REGION_ENABLE	R/W	0h	Enables each soft-designated non-ECC region. Bit (0) correlates to region 0, bit (1) correlates to region 1, etc. Set each bit to 1 to enable.
15	RESERVED	R/W	X
14-0	NON_ECC_REGION_END_ADDR_2	R/W	0h	Set the base address of the soft-designated non-ECC region 2. The address written is 1Mbyte aligned.

2.5.2.221 DDRSS_CTL_222 Register (Offset = 378h) [reset = X]

DDRSS_CTL_222 is shown in Figure 8-313 and described in Table 8-634.

Return to Summary Table.

Table 8-633 DDRSS_CTL_222 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0378h

Figure 8-313 DDRSS_CTL_222 Register

31	30	29	28	27	26	25	24
RESERVED							ECC_SCRUB_MODE
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED				ECC_SCRUB_LEN
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
ECC_SCRUB_LEN
R/W-0h

7	6	5	4	3	2	1	0
RESERVED							ECC_SCRUB_IN_PROGRESS
R/W-X							R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-634 DDRSS_CTL_222 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	ECC_SCRUB_MODE	R/W	0h	Defines how often ECC scrubbing operations will occur. Clear to 0 to scrub at regular intervals as dictated by the ECC_SCRUB_INTERVAL parameter, or set to 1 to scrub only when the controller is idle.
23-20	RESERVED	R/W	X
19-8	ECC_SCRUB_LEN	R/W	0h	Defines the length of the ECC scrubbing read command that the controller will issue.
7-1	RESERVED	R/W	X
0	ECC_SCRUB_IN_PROGRESS	R	0h	Reports the scrubbing operation status. A value of 1 indicates that the controller is in the process of performing a scrubbing operation. READ-ONLY

2.5.2.222 DDRSS_CTL_223 Register (Offset = 37Ch) [reset = 0h]

DDRSS_CTL_223 is shown in Figure 8-314 and described in Table 8-636.

Return to Summary Table.

Table 8-635 DDRSS_CTL_223 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 037Ch

Figure 8-314 DDRSS_CTL_223 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ECC_SCRUB_IDLE_CNT
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC_SCRUB_INTERVAL
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-636 DDRSS_CTL_223 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ECC_SCRUB_IDLE_CNT	R/W	0h	The number of controller clock cycles that the scrubbing engine will wait in controller idle state before starting scrubbing operations. Valid when the ECC_SCRUB_MODE parameter is set to 1.
15-0	ECC_SCRUB_INTERVAL	R/W	0h	The minimum interval between two ECC scrubbing commands in number of controller clock cycles. Valid when the ECC_SCRUB_MODE parameter is cleared to 0.

2.5.2.223 DDRSS_CTL_224 Register (Offset = 380h) [reset = 0h]

DDRSS_CTL_224 is shown in Figure 8-315 and described in Table 8-638.

Return to Summary Table.

Table 8-637 DDRSS_CTL_224 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0380h

Figure 8-315 DDRSS_CTL_224 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC_SCRUB_START_ADDR_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-638 DDRSS_CTL_224 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ECC_SCRUB_START_ADDR_0	R/W	0h	The starting address from where scrubbing operations will begin.

2.5.2.224 DDRSS_CTL_225 Register (Offset = 384h) [reset = X]

DDRSS_CTL_225 is shown in Figure 8-316 and described in Table 8-640.

Return to Summary Table.

Table 8-639 DDRSS_CTL_225 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0384h

Figure 8-316 DDRSS_CTL_225 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED					ECC_SCRUB_START_ADDR_1
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-640 DDRSS_CTL_225 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R/W	X
2-0	ECC_SCRUB_START_ADDR_1	R/W	0h	The starting address from where scrubbing operations will begin.

2.5.2.225 DDRSS_CTL_226 Register (Offset = 388h) [reset = 0h]

DDRSS_CTL_226 is shown in Figure 8-317 and described in Table 8-642.

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Table 8-641 DDRSS_CTL_226 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0388h

Figure 8-317 DDRSS_CTL_226 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC_SCRUB_END_ADDR_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-642 DDRSS_CTL_226 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	ECC_SCRUB_END_ADDR_0	R/W	0h	The end address where scrubbing operations will wrap around to the start address. If this parameter is cleared to 0, the maximum physical address will be considered as the end address.

2.5.2.226 DDRSS_CTL_227 Register (Offset = 38Ch) [reset = X]

DDRSS_CTL_227 is shown in Figure 8-318 and described in Table 8-644.

Return to Summary Table.

Table 8-643 DDRSS_CTL_227 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 038Ch

Figure 8-318 DDRSS_CTL_227 Register

31	30	29	28	27	26	25	24
RESERVED			AREF_HIGH_THRESHOLD
R/W-X			R/W-0h

23	22	21	20	19	18	17	16
RESERVED			AREF_NORM_THRESHOLD
R/W-X			R/W-0h

15	14	13	12	11	10	9	8
RESERVED			LONG_COUNT_MASK
R/W-X			R/W-0h

7	6	5	4	3	2	1	0
RESERVED					ECC_SCRUB_END_ADDR_1
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-644 DDRSS_CTL_227 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	AREF_HIGH_THRESHOLD	R/W	0h	AREF number of pending refreshes until the high priority request is asserted.
23-21	RESERVED	R/W	X
20-16	AREF_NORM_THRESHOLD	R/W	0h	AREF number of pending refreshes until the normal priority request is asserted.
15-13	RESERVED	R/W	X
12-8	LONG_COUNT_MASK	R/W	0h	Reduces the length of the long counter from 1024 cycles. The only supported values are 0x00 (1024 cycles), 0x10 (512 clocks), 0x18 (256 clocks), 0x1C (128 clocks), 0x1E (64 clocks) and 0x1F (32 clocks).
7-3	RESERVED	R/W	X
2-0	ECC_SCRUB_END_ADDR_1	R/W	0h	The end address where scrubbing operations will wrap around to the start address. If this parameter is cleared to 0, the maximum physical address will be considered as the end address.

2.5.2.227 DDRSS_CTL_228 Register (Offset = 390h) [reset = X]

DDRSS_CTL_228 is shown in Figure 8-319 and described in Table 8-646.

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Table 8-645 DDRSS_CTL_228 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0390h

Figure 8-319 DDRSS_CTL_228 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED				AREF_CMD_MAX_PER_TREFI
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED			AREF_MAX_CREDIT
R/W-X			R/W-0h

7	6	5	4	3	2	1	0
RESERVED			AREF_MAX_DEFICIT
R/W-X			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-646 DDRSS_CTL_228 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-16	AREF_CMD_MAX_PER_TREFI	R/W	0h	Sets the maximum number of auto-refreshes that will be executed in a TREFI period - both normal and high priority. This does not prevent refreshes generated by sub-task requests such as a self-refresh exit and enter.
15-13	RESERVED	R/W	X
12-8	AREF_MAX_CREDIT	R/W	0h	AREF number of posted refreshes until the maximum number of refresh credits has been reached.
7-5	RESERVED	R/W	X
4-0	AREF_MAX_DEFICIT	R/W	0h	AREF number of pending refreshes until the maximum number of refreshes has been exceeded.

2.5.2.228 DDRSS_CTL_229 Register (Offset = 394h) [reset = 0h]

DDRSS_CTL_229 is shown in Figure 8-320 and described in Table 8-648.

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Table 8-647 DDRSS_CTL_229 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0394h

Figure 8-320 DDRSS_CTL_229 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CALSTART_HIGH_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CALSTART_NORM_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-648 DDRSS_CTL_229 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CALSTART_HIGH_THRESHOLD_F0	R/W	0h	ZQ START number of long counts until the high priority request is asserted for frequency copy 0.
15-0	ZQ_CALSTART_NORM_THRESHOLD_F0	R/W	0h	ZQ START number of long counts until the normal priority request is asserted for frequency copy 0. This value should be scaled based on the number of ranks (chip selects) the controller handles. The more chip selects there are, the more rotations there are to go through, and the smaller this threshold should be.

2.5.2.229 DDRSS_CTL_230 Register (Offset = 398h) [reset = 0h]

DDRSS_CTL_230 is shown in Figure 8-321 and described in Table 8-650.

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Table 8-649 DDRSS_CTL_230 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0398h

Figure 8-321 DDRSS_CTL_230 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CS_NORM_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CALLATCH_HIGH_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-650 DDRSS_CTL_230 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CS_NORM_THRESHOLD_F0	R/W	0h	ZQ CS number of long counts until the normal priority request is asserted for frequency copy 0.
15-0	ZQ_CALLATCH_HIGH_THRESHOLD_F0	R/W	0h	ZQ LATCH number of long counts until the high priority request is asserted for frequency copy 0.

2.5.2.230 DDRSS_CTL_231 Register (Offset = 39Ch) [reset = 0h]

DDRSS_CTL_231 is shown in Figure 8-322 and described in Table 8-652.

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Table 8-651 DDRSS_CTL_231 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 039Ch

Figure 8-322 DDRSS_CTL_231 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CALSTART_TIMEOUT_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CS_HIGH_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-652 DDRSS_CTL_231 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CALSTART_TIMEOUT_F0	R/W	0h	ZQ START number of long counts until the timeout is asserted for frequency copy 0.
15-0	ZQ_CS_HIGH_THRESHOLD_F0	R/W	0h	ZQ CS number of long counts until the high priority request is asserted for frequency copy 0.

2.5.2.231 DDRSS_CTL_232 Register (Offset = 3A0h) [reset = 0h]

DDRSS_CTL_232 is shown in Figure 8-323 and described in Table 8-654.

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Table 8-653 DDRSS_CTL_232 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03A0h

Figure 8-323 DDRSS_CTL_232 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CS_TIMEOUT_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CALLATCH_TIMEOUT_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-654 DDRSS_CTL_232 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CS_TIMEOUT_F0	R/W	0h	ZQ CS number of long counts until the timeout is asserted for frequency copy 0.
15-0	ZQ_CALLATCH_TIMEOUT_F0	R/W	0h	ZQ LATCH number of long counts until the timeout is asserted for frequency copy 0.

2.5.2.232 DDRSS_CTL_233 Register (Offset = 3A4h) [reset = 0h]

DDRSS_CTL_233 is shown in Figure 8-324 and described in Table 8-656.

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Table 8-655 DDRSS_CTL_233 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03A4h

Figure 8-324 DDRSS_CTL_233 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CALSTART_NORM_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_PROMOTE_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-656 DDRSS_CTL_233 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CALSTART_NORM_THRESHOLD_F1	R/W	0h	ZQ START number of long counts until the normal priority request is asserted for frequency copy 1. This value should be scaled based on the number of ranks (chip selects) the controller handles. The more chip selects there are, the more rotations there are to go through, and the smaller this threshold should be.
15-0	ZQ_PROMOTE_THRESHOLD_F0	R/W	0h	ZQ SW promotion number of long counts until the high priority request is asserted for frequency copy 0.

2.5.2.233 DDRSS_CTL_234 Register (Offset = 3A8h) [reset = 0h]

DDRSS_CTL_234 is shown in Figure 8-325 and described in Table 8-658.

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Table 8-657 DDRSS_CTL_234 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03A8h

Figure 8-325 DDRSS_CTL_234 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CALLATCH_HIGH_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CALSTART_HIGH_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-658 DDRSS_CTL_234 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CALLATCH_HIGH_THRESHOLD_F1	R/W	0h	ZQ LATCH number of long counts until the high priority request is asserted for frequency copy 1.
15-0	ZQ_CALSTART_HIGH_THRESHOLD_F1	R/W	0h	ZQ START number of long counts until the high priority request is asserted for frequency copy 1.

2.5.2.234 DDRSS_CTL_235 Register (Offset = 3ACh) [reset = 0h]

DDRSS_CTL_235 is shown in Figure 8-326 and described in Table 8-660.

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Table 8-659 DDRSS_CTL_235 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03ACh

Figure 8-326 DDRSS_CTL_235 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CS_HIGH_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CS_NORM_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-660 DDRSS_CTL_235 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CS_HIGH_THRESHOLD_F1	R/W	0h	ZQ CS number of long counts until the high priority request is asserted for frequency copy 1.
15-0	ZQ_CS_NORM_THRESHOLD_F1	R/W	0h	ZQ CS number of long counts until the normal priority request is asserted for frequency copy 1.

2.5.2.235 DDRSS_CTL_236 Register (Offset = 3B0h) [reset = 0h]

DDRSS_CTL_236 is shown in Figure 8-327 and described in Table 8-662.

Return to Summary Table.

Table 8-661 DDRSS_CTL_236 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03B0h

Figure 8-327 DDRSS_CTL_236 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CALLATCH_TIMEOUT_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CALSTART_TIMEOUT_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-662 DDRSS_CTL_236 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CALLATCH_TIMEOUT_F1	R/W	0h	ZQ LATCH number of long counts until the timeout is asserted for frequency copy 1.
15-0	ZQ_CALSTART_TIMEOUT_F1	R/W	0h	ZQ START number of long counts until the timeout is asserted for frequency copy 1.

2.5.2.236 DDRSS_CTL_237 Register (Offset = 3B4h) [reset = 0h]

DDRSS_CTL_237 is shown in Figure 8-328 and described in Table 8-664.

Return to Summary Table.

Table 8-663 DDRSS_CTL_237 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03B4h

Figure 8-328 DDRSS_CTL_237 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_PROMOTE_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CS_TIMEOUT_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-664 DDRSS_CTL_237 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_PROMOTE_THRESHOLD_F1	R/W	0h	ZQ SW promotion number of long counts until the high priority request is asserted for frequency copy 1.
15-0	ZQ_CS_TIMEOUT_F1	R/W	0h	ZQ CS number of long counts until the timeout is asserted for frequency copy 1.

2.5.2.237 DDRSS_CTL_238 Register (Offset = 3B8h) [reset = 0h]

DDRSS_CTL_238 is shown in Figure 8-329 and described in Table 8-666.

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Table 8-665 DDRSS_CTL_238 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03B8h

Figure 8-329 DDRSS_CTL_238 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CALSTART_HIGH_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CALSTART_NORM_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-666 DDRSS_CTL_238 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CALSTART_HIGH_THRESHOLD_F2	R/W	0h	ZQ START number of long counts until the high priority request is asserted for frequency copy 2.
15-0	ZQ_CALSTART_NORM_THRESHOLD_F2	R/W	0h	ZQ START number of long counts until the normal priority request is asserted for frequency copy 2. This value should be scaled based on the number of ranks (chip selects) the controller handles. The more chip selects there are, the more rotations there are to go through, and the smaller this threshold should be.

2.5.2.238 DDRSS_CTL_239 Register (Offset = 3BCh) [reset = 0h]

DDRSS_CTL_239 is shown in Figure 8-330 and described in Table 8-668.

Return to Summary Table.

Table 8-667 DDRSS_CTL_239 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03BCh

Figure 8-330 DDRSS_CTL_239 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CS_NORM_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CALLATCH_HIGH_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-668 DDRSS_CTL_239 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CS_NORM_THRESHOLD_F2	R/W	0h	ZQ CS number of long counts until the normal priority request is asserted for frequency copy 2.
15-0	ZQ_CALLATCH_HIGH_THRESHOLD_F2	R/W	0h	ZQ LATCH number of long counts until the high priority request is asserted for frequency copy 2.

2.5.2.239 DDRSS_CTL_240 Register (Offset = 3C0h) [reset = 0h]

DDRSS_CTL_240 is shown in Figure 8-331 and described in Table 8-670.

Return to Summary Table.

Table 8-669 DDRSS_CTL_240 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03C0h

Figure 8-331 DDRSS_CTL_240 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CALSTART_TIMEOUT_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CS_HIGH_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-670 DDRSS_CTL_240 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CALSTART_TIMEOUT_F2	R/W	0h	ZQ START number of long counts until the timeout is asserted for frequency copy 2.
15-0	ZQ_CS_HIGH_THRESHOLD_F2	R/W	0h	ZQ CS number of long counts until the high priority request is asserted for frequency copy 2.

2.5.2.240 DDRSS_CTL_241 Register (Offset = 3C4h) [reset = 0h]

DDRSS_CTL_241 is shown in Figure 8-332 and described in Table 8-672.

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Table 8-671 DDRSS_CTL_241 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03C4h

Figure 8-332 DDRSS_CTL_241 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ZQ_CS_TIMEOUT_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_CALLATCH_TIMEOUT_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-672 DDRSS_CTL_241 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	ZQ_CS_TIMEOUT_F2	R/W	0h	ZQ CS number of long counts until the timeout is asserted for frequency copy 2.
15-0	ZQ_CALLATCH_TIMEOUT_F2	R/W	0h	ZQ LATCH number of long counts until the timeout is asserted for frequency copy 2.

2.5.2.241 DDRSS_CTL_242 Register (Offset = 3C8h) [reset = X]

DDRSS_CTL_242 is shown in Figure 8-333 and described in Table 8-674.

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Table 8-673 DDRSS_CTL_242 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03C8h

Figure 8-333 DDRSS_CTL_242 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED													RESERVED
R/W-X													R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ZQ_PROMOTE_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-674 DDRSS_CTL_242 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R/W	X
18-16	RESERVED	R/W	0h	Reserved
15-0	ZQ_PROMOTE_THRESHOLD_F2	R/W	0h	ZQ SW promotion number of long counts until the high priority request is asserted for frequency copy 2.

2.5.2.242 DDRSS_CTL_243 Register (Offset = 3CCh) [reset = 0h]

DDRSS_CTL_243 is shown in Figure 8-334 and described in Table 8-676.

Return to Summary Table.

Table 8-675 DDRSS_CTL_243 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03CCh

Figure 8-334 DDRSS_CTL_243 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_BUS_ARB_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_TASK_ARB_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-676 DDRSS_CTL_243 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_BUS_ARB_F0	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 0.
15-0	WATCHDOG_THRESHOLD_TASK_ARB_F0	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 0.

2.5.2.243 DDRSS_CTL_244 Register (Offset = 3D0h) [reset = 0h]

DDRSS_CTL_244 is shown in Figure 8-335 and described in Table 8-678.

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Table 8-677 DDRSS_CTL_244 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03D0h

Figure 8-335 DDRSS_CTL_244 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_SPLIT_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-678 DDRSS_CTL_244 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_SPLIT_F0	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 0.
15-0	WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 0.

2.5.2.244 DDRSS_CTL_245 Register (Offset = 3D4h) [reset = 0h]

DDRSS_CTL_245 is shown in Figure 8-336 and described in Table 8-680.

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Table 8-679 DDRSS_CTL_245 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03D4h

Figure 8-336 DDRSS_CTL_245 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_STRATEGY_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-680 DDRSS_CTL_245 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 0.
15-0	WATCHDOG_THRESHOLD_STRATEGY_F0	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 0.

2.5.2.245 DDRSS_CTL_246 Register (Offset = 3D8h) [reset = 0h]

DDRSS_CTL_246 is shown in Figure 8-337 and described in Table 8-682.

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Table 8-681 DDRSS_CTL_246 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03D8h

Figure 8-337 DDRSS_CTL_246 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-682 DDRSS_CTL_246 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 0.
15-0	WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 0.

2.5.2.246 DDRSS_CTL_247 Register (Offset = 3DCh) [reset = 0h]

DDRSS_CTL_247 is shown in Figure 8-338 and described in Table 8-684.

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Table 8-683 DDRSS_CTL_247 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03DCh

Figure 8-338 DDRSS_CTL_247 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_BUS_ARB_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_TASK_ARB_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-684 DDRSS_CTL_247 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_BUS_ARB_F1	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 1.
15-0	WATCHDOG_THRESHOLD_TASK_ARB_F1	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 1.

2.5.2.247 DDRSS_CTL_248 Register (Offset = 3E0h) [reset = 0h]

DDRSS_CTL_248 is shown in Figure 8-339 and described in Table 8-686.

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Table 8-685 DDRSS_CTL_248 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03E0h

Figure 8-339 DDRSS_CTL_248 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_SPLIT_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-686 DDRSS_CTL_248 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_SPLIT_F1	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 1.
15-0	WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 1.

2.5.2.248 DDRSS_CTL_249 Register (Offset = 3E4h) [reset = 0h]

DDRSS_CTL_249 is shown in Figure 8-340 and described in Table 8-688.

Return to Summary Table.

Table 8-687 DDRSS_CTL_249 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03E4h

Figure 8-340 DDRSS_CTL_249 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_STRATEGY_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-688 DDRSS_CTL_249 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 1.
15-0	WATCHDOG_THRESHOLD_STRATEGY_F1	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 1.

2.5.2.249 DDRSS_CTL_250 Register (Offset = 3E8h) [reset = 0h]

DDRSS_CTL_250 is shown in Figure 8-341 and described in Table 8-690.

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Table 8-689 DDRSS_CTL_250 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03E8h

Figure 8-341 DDRSS_CTL_250 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-690 DDRSS_CTL_250 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 1.
15-0	WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 1.

2.5.2.250 DDRSS_CTL_251 Register (Offset = 3ECh) [reset = 0h]

DDRSS_CTL_251 is shown in Figure 8-342 and described in Table 8-692.

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Table 8-691 DDRSS_CTL_251 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03ECh

Figure 8-342 DDRSS_CTL_251 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_BUS_ARB_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_TASK_ARB_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-692 DDRSS_CTL_251 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_BUS_ARB_F2	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 2.
15-0	WATCHDOG_THRESHOLD_TASK_ARB_F2	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 2.

2.5.2.251 DDRSS_CTL_252 Register (Offset = 3F0h) [reset = 0h]

DDRSS_CTL_252 is shown in Figure 8-343 and described in Table 8-694.

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Table 8-693 DDRSS_CTL_252 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03F0h

Figure 8-343 DDRSS_CTL_252 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_SPLIT_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-694 DDRSS_CTL_252 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_SPLIT_F2	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 2.
15-0	WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 2.

2.5.2.252 DDRSS_CTL_253 Register (Offset = 3F4h) [reset = 0h]

DDRSS_CTL_253 is shown in Figure 8-344 and described in Table 8-696.

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Table 8-695 DDRSS_CTL_253 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03F4h

Figure 8-344 DDRSS_CTL_253 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_STRATEGY_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-696 DDRSS_CTL_253 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 2.
15-0	WATCHDOG_THRESHOLD_STRATEGY_F2	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 2.

2.5.2.253 DDRSS_CTL_254 Register (Offset = 3F8h) [reset = 0h]

DDRSS_CTL_254 is shown in Figure 8-345 and described in Table 8-698.

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Table 8-697 DDRSS_CTL_254 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03F8h

Figure 8-345 DDRSS_CTL_254 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-698 DDRSS_CTL_254 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 2.
15-0	WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2	R/W	0h	When watchdog's counter reaches this threshold, it will assert an error when using frequency copy 2.

2.5.2.254 DDRSS_CTL_255 Register (Offset = 3FCh) [reset = X]

DDRSS_CTL_255 is shown in Figure 8-346 and described in Table 8-700.

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Table 8-699 DDRSS_CTL_255 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 03FCh

Figure 8-346 DDRSS_CTL_255 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WATCHDOG_DIAGNOSTIC_MODE								WATCHDOG_RELOAD
R/W-0h								W-0h

LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-700 DDRSS_CTL_255 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R/W	X
15-8	WATCHDOG_DIAGNOSTIC_MODE	R/W	0h	Used to test watchdog timers or to force a failure. There is one bit for each watchdog timer. Under normal operation, a watchdog timer will increment its counter after every long counter cycle. To aid in generating watchdog faults for testing, a watchdog's counter can increment every controller clock cycle instead by setting the corresponding bit in this register to 1.
7-0	WATCHDOG_RELOAD	W	0h	Forces reload to assert on all watchdog timers, effectively restarting all watchdog counters and clearing any existing watchdog error assertions. WRITE-ONLY

2.5.2.255 DDRSS_CTL_256 Register (Offset = 400h) [reset = X]

DDRSS_CTL_256 is shown in Figure 8-347 and described in Table 8-702.

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Table 8-701 DDRSS_CTL_256 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0400h

Figure 8-347 DDRSS_CTL_256 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												TIMEOUT_TIMER_LOG
R-X												R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-702 DDRSS_CTL_256 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R	X
19-0	TIMEOUT_TIMER_LOG	R	0h	Reflects which timers experienced a timeout error (or had an uncleared error) when the timeout interrupt fired. Task arbiter watchdog error is reflected in bit 0. Bus arbiter watchdog error is reflected in bit 1. Port 0 command arbiter watchdog error is reflected in bit 2. Split watchdog error is reflected in bit 3. Strategy watchdog error is reflected in bit 4. Port to strategy watchdog error is reflected in bit 5. Write data FIFO watchdog error is reflected in bit 7. ZQ calstart FM timeout is reflected in bit 9. ZQ callatch FM timeout is reflected in bit 10. ZQ cal init, cs, cl, or reset FM timeout is reflected in bit 8. Read leveling FM timeout is reflected in bit 11. Read gate leveling FM timeout is reflected in bit 12. Write leveling FM timeout is reflected in bit 13. CA training FM timeout is reflected in bit 14. DQS oscillator FM timeout is reflected in bit 16. MRR temperature check FM timeout is reflected in bit 15. DFI update FM timeout is reflected in bit 17. Low power interface wakeup timeout is reflected in bit 18. Auto refresh max deficit timeout is reflected in bit 19. READ-ONLY

2.5.2.256 DDRSS_CTL_257 Register (Offset = 404h) [reset = X]

DDRSS_CTL_257 is shown in Figure 8-348 and described in Table 8-704.

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Table 8-703 DDRSS_CTL_257 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0404h

Figure 8-348 DDRSS_CTL_257 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				ZQCL_F0
R/W-X				R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				ZQINIT_F0
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-704 DDRSS_CTL_257 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-16	ZQCL_F0	R/W	0h	Number of cycles needed for a ZQCL command for frequency copy 0.
15-12	RESERVED	R/W	X
11-0	ZQINIT_F0	R/W	0h	Number of cycles needed for a ZQINIT command for frequency copy 0.

2.5.2.257 DDRSS_CTL_258 Register (Offset = 408h) [reset = X]

DDRSS_CTL_258 is shown in Figure 8-349 and described in Table 8-706.

Return to Summary Table.

Table 8-705 DDRSS_CTL_258 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0408h

Figure 8-349 DDRSS_CTL_258 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				TZQCAL_F0
R/W-X				R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				ZQCS_F0
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-706 DDRSS_CTL_258 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-16	TZQCAL_F0	R/W	0h	Holds the DRAM ZQCAL value for frequency copy 0 in cycles.
15-12	RESERVED	R/W	X
11-0	ZQCS_F0	R/W	0h	Number of cycles needed for a ZQCS command for frequency copy 0.

2.5.2.258 DDRSS_CTL_259 Register (Offset = 40Ch) [reset = X]

DDRSS_CTL_259 is shown in Figure 8-350 and described in Table 8-708.

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Table 8-707 DDRSS_CTL_259 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 040Ch

Figure 8-350 DDRSS_CTL_259 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED				ZQINIT_F1
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
ZQINIT_F1
R/W-0h

7	6	5	4	3	2	1	0
RESERVED	TZQLAT_F0
R/W-X	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-708 DDRSS_CTL_259 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-8	ZQINIT_F1	R/W	0h	Number of cycles needed for a ZQINIT command for frequency copy 1.
7	RESERVED	R/W	X
6-0	TZQLAT_F0	R/W	0h	Holds the DRAM ZQLAT value for frequency copy 0 in cycles.

2.5.2.259 DDRSS_CTL_260 Register (Offset = 410h) [reset = X]

DDRSS_CTL_260 is shown in Figure 8-351 and described in Table 8-710.

Return to Summary Table.

Table 8-709 DDRSS_CTL_260 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0410h

Figure 8-351 DDRSS_CTL_260 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				ZQCS_F1
R/W-X				R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				ZQCL_F1
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-710 DDRSS_CTL_260 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-16	ZQCS_F1	R/W	0h	Number of cycles needed for a ZQCS command for frequency copy 1.
15-12	RESERVED	R/W	X
11-0	ZQCL_F1	R/W	0h	Number of cycles needed for a ZQCL command for frequency copy 1.

2.5.2.260 DDRSS_CTL_261 Register (Offset = 414h) [reset = X]

DDRSS_CTL_261 is shown in Figure 8-352 and described in Table 8-712.

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Table 8-711 DDRSS_CTL_261 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0414h

Figure 8-352 DDRSS_CTL_261 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED									TZQLAT_F1
R/W-X									R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				TZQCAL_F1
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-712 DDRSS_CTL_261 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22-16	TZQLAT_F1	R/W	0h	Holds the DRAM ZQLAT value for frequency copy 1 in cycles.
15-12	RESERVED	R/W	X
11-0	TZQCAL_F1	R/W	0h	Holds the DRAM ZQCAL value for frequency copy 1 in cycles.

2.5.2.261 DDRSS_CTL_262 Register (Offset = 418h) [reset = X]

DDRSS_CTL_262 is shown in Figure 8-353 and described in Table 8-714.

Return to Summary Table.

Table 8-713 DDRSS_CTL_262 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0418h

Figure 8-353 DDRSS_CTL_262 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				ZQCL_F2
R/W-X				R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				ZQINIT_F2
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-714 DDRSS_CTL_262 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-16	ZQCL_F2	R/W	0h	Number of cycles needed for a ZQCL command for frequency copy 2.
15-12	RESERVED	R/W	X
11-0	ZQINIT_F2	R/W	0h	Number of cycles needed for a ZQINIT command for frequency copy 2.

2.5.2.262 DDRSS_CTL_263 Register (Offset = 41Ch) [reset = X]

DDRSS_CTL_263 is shown in Figure 8-354 and described in Table 8-716.

Return to Summary Table.

Table 8-715 DDRSS_CTL_263 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 041Ch

Figure 8-354 DDRSS_CTL_263 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				TZQCAL_F2
R/W-X				R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				ZQCS_F2
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-716 DDRSS_CTL_263 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-16	TZQCAL_F2	R/W	0h	Holds the DRAM ZQCAL value for frequency copy 2 in cycles.
15-12	RESERVED	R/W	X
11-0	ZQCS_F2	R/W	0h	Number of cycles needed for a ZQCS command for frequency copy 2.

2.5.2.263 DDRSS_CTL_264 Register (Offset = 420h) [reset = X]

DDRSS_CTL_264 is shown in Figure 8-355 and described in Table 8-718.

Return to Summary Table.

Table 8-717 DDRSS_CTL_264 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0420h

Figure 8-355 DDRSS_CTL_264 Register

31	30	29	28	27	26	25	24
RESERVED							ZQ_REQ_PENDING
R/W-X							R-0h

23	22	21	20	19	18	17	16
RESERVED				ZQ_REQ
R/W-X				W-0h

15	14	13	12	11	10	9	8
RESERVED						ZQ_SW_REQ_START_LATCH_MAP
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	TZQLAT_F2
R/W-X	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-718 DDRSS_CTL_264 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	ZQ_REQ_PENDING	R	0h	Indicates that a ZQ command is currently in progress or waiting to run. Value of 1 indicates command in progress or waiting to run. When this is asserted, no writes to ZQ_REQ should occur. READ-ONLY
23-20	RESERVED	R/W	X
19-16	ZQ_REQ	W	0h	User request to initiate a ZQ calibration. Program to 1 for ZQ Short (ZQCS), program to 2 for ZQ Long (ZQCL), program to 3 for ZQ Start, program to 4 for ZQ Initialization (ZQINIT), program to 5 for ZQ Latch, or program to 8 for ZQ Reset. Clearing to 0 will not trigger any ZQ command. This parameter should only be written when the ZQ_REQ_PENDING parameter is cleared to 0. WRITE-ONLY
15-10	RESERVED	R/W	X
9-8	ZQ_SW_REQ_START_LATCH_MAP	R/W	0h	Specifies which chip selects will simultaneously receive a ZQ start or latch command once the ZQ_REQ parameter is written with a ZQ Start or ZQ Latch command.
7	RESERVED	R/W	X
6-0	TZQLAT_F2	R/W	0h	Holds the DRAM ZQLAT value for frequency copy 2 in cycles.

2.5.2.264 DDRSS_CTL_265 Register (Offset = 424h) [reset = X]

DDRSS_CTL_265 is shown in Figure 8-356 and described in Table 8-720.

Return to Summary Table.

Table 8-719 DDRSS_CTL_265 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0424h

Figure 8-356 DDRSS_CTL_265 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				ZQRESET_F1
R/W-X				R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				ZQRESET_F0
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-720 DDRSS_CTL_265 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-16	ZQRESET_F1	R/W	0h	Number of cycles needed for a ZQRESET command for frequency copy 1.
15-12	RESERVED	R/W	X
11-0	ZQRESET_F0	R/W	0h	Number of cycles needed for a ZQRESET command for frequency copy 0.

2.5.2.265 DDRSS_CTL_266 Register (Offset = 428h) [reset = X]

DDRSS_CTL_266 is shown in Figure 8-357 and described in Table 8-722.

Return to Summary Table.

Table 8-721 DDRSS_CTL_266 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0428h

Figure 8-357 DDRSS_CTL_266 Register

31	30	29	28	27	26	25	24
RESERVED							ZQCS_ROTATE
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							NO_ZQ_INIT
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED				ZQRESET_F2
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
ZQRESET_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-722 DDRSS_CTL_266 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	ZQCS_ROTATE	R/W	0h	For non-LPDDR4 memories, selects whether a ZQCS command will calibrate just one chip select or all chip selects. When rotation is off, all chip selects will be calibrated, requiring a longer time frame, but ZQ calibration will need to be performed less frequently. Set to 1 for rotating CS. For LPDDR4 memories, this parameter is ignored.
23-17	RESERVED	R/W	X
16	NO_ZQ_INIT	R/W	0h	Disable ZQ operations during initialization. Set to 1 to disable.
15-12	RESERVED	R/W	X
11-0	ZQRESET_F2	R/W	0h	Number of cycles needed for a ZQRESET command for frequency copy 2.

2.5.2.266 DDRSS_CTL_267 Register (Offset = 42Ch) [reset = X]

DDRSS_CTL_267 is shown in Figure 8-358 and described in Table 8-724.

Return to Summary Table.

Table 8-723 DDRSS_CTL_267 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 042Ch

Figure 8-358 DDRSS_CTL_267 Register

31	30	29	28	27	26	25	24
RESERVED						ZQ_CAL_LATCH_MAP_1
R/W-X						R/W-0h

23	22	21	20	19	18	17	16
RESERVED						ZQ_CAL_START_MAP_1
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
RESERVED						ZQ_CAL_LATCH_MAP_0
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED						ZQ_CAL_START_MAP_0
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-724 DDRSS_CTL_267 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-24	ZQ_CAL_LATCH_MAP_1	R/W	0h	Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 1 of the ZQ LATCH initialization and periodic command sequences. Clear to all zeros for no ZQ LATCH commands.
23-18	RESERVED	R/W	X
17-16	ZQ_CAL_START_MAP_1	R/W	0h	Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 1 of the ZQ START initialization and periodic command sequences. Clear to all zeros for no ZQ START commands.
15-10	RESERVED	R/W	X
9-8	ZQ_CAL_LATCH_MAP_0	R/W	0h	Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 0 of the ZQ LATCH initialization and periodic command sequences. Clear to all zeros for no ZQ LATCH commands.
7-2	RESERVED	R/W	X
1-0	ZQ_CAL_START_MAP_0	R/W	0h	Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 0 of the ZQ START initialization and periodic command sequences. Clear to all zeros for no ZQ START commands.

2.5.2.267 DDRSS_CTL_268 Register (Offset = 430h) [reset = X]

DDRSS_CTL_268 is shown in Figure 8-359 and described in Table 8-726.

Return to Summary Table.

Table 8-725 DDRSS_CTL_268 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0430h

Figure 8-359 DDRSS_CTL_268 Register

31	30	29	28	27	26	25	24
RESERVED					ROW_DIFF_1
R/W-X					R/W-0h

23	22	21	20	19	18	17	16
RESERVED					ROW_DIFF_0
R/W-X					R/W-0h

15	14	13	12	11	10	9	8
RESERVED						BANK_DIFF_1
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED						BANK_DIFF_0
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-726 DDRSS_CTL_268 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-24	ROW_DIFF_1	R/W	0h	Difference between number of address pins available and number being used for chip select 1.
23-19	RESERVED	R/W	X
18-16	ROW_DIFF_0	R/W	0h	Difference between number of address pins available and number being used for chip select 0.
15-10	RESERVED	R/W	X
9-8	BANK_DIFF_1	R/W	0h	Encoded number of banks on the DRAM for chip select 1.
7-2	RESERVED	R/W	X
1-0	BANK_DIFF_0	R/W	0h	Encoded number of banks on the DRAM for chip select 0.

2.5.2.268 DDRSS_CTL_269 Register (Offset = 434h) [reset = X]

DDRSS_CTL_269 is shown in Figure 8-360 and described in Table 8-728.

Return to Summary Table.

Table 8-727 DDRSS_CTL_269 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0434h

Figure 8-360 DDRSS_CTL_269 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CS_VAL_LOWER_0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				COL_DIFF_1				RESERVED				COL_DIFF_0
R/W-X				R/W-0h				R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-728 DDRSS_CTL_269 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CS_VAL_LOWER_0	R/W	0h	Lower bound address for chip select 0.
15-12	RESERVED	R/W	X
11-8	COL_DIFF_1	R/W	0h	Difference between number of column pins available and number being used for chip select 1.
7-4	RESERVED	R/W	X
3-0	COL_DIFF_0	R/W	0h	Difference between number of column pins available and number being used for chip select 0.

2.5.2.269 DDRSS_CTL_270 Register (Offset = 438h) [reset = X]

DDRSS_CTL_270 is shown in Figure 8-361 and described in Table 8-730.

Return to Summary Table.

Table 8-729 DDRSS_CTL_270 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0438h

Figure 8-361 DDRSS_CTL_270 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED					ROW_START_VAL_0
R/W-X					R/W-0h

15	14	13	12	11	10	9	8
CS_VAL_UPPER_0
R/W-0h

7	6	5	4	3	2	1	0
CS_VAL_UPPER_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-730 DDRSS_CTL_270 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R/W	X
18-16	ROW_START_VAL_0	R/W	0h	Row start value for chip select 0.
15-0	CS_VAL_UPPER_0	R/W	0h	Upper bound address for chip select 0.

2.5.2.270 DDRSS_CTL_271 Register (Offset = 43Ch) [reset = 0h]

DDRSS_CTL_271 is shown in Figure 8-362 and described in Table 8-732.

Return to Summary Table.

Table 8-731 DDRSS_CTL_271 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 043Ch

Figure 8-362 DDRSS_CTL_271 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CS_VAL_UPPER_1																CS_VAL_LOWER_1
R/W-0h																R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-732 DDRSS_CTL_271 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CS_VAL_UPPER_1	R/W	0h	Upper bound address for chip select 1.
15-0	CS_VAL_LOWER_1	R/W	0h	Lower bound address for chip select 1.

2.5.2.271 DDRSS_CTL_272 Register (Offset = 440h) [reset = X]

DDRSS_CTL_272 is shown in Figure 8-363 and described in Table 8-734.

Return to Summary Table.

Table 8-733 DDRSS_CTL_272 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0440h

Figure 8-363 DDRSS_CTL_272 Register

31	30	29	28	27	26	25	24
CS_MSK_0
R/W-0h

23	22	21	20	19	18	17	16
CS_MSK_0
R/W-0h

15	14	13	12	11	10	9	8
RESERVED						CS_MAP_NON_POW2
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED					ROW_START_VAL_1
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-734 DDRSS_CTL_272 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CS_MSK_0	R/W	0h	Mask applied to the address decode for chip select 0.
15-10	RESERVED	R/W	X
9-8	CS_MAP_NON_POW2	R/W	0h	Defines which chip selects are non-power-of-2 memory sizes.
7-3	RESERVED	R/W	X
2-0	ROW_START_VAL_1	R/W	0h	Row start value for chip select 1.

2.5.2.272 DDRSS_CTL_273 Register (Offset = 444h) [reset = X]

DDRSS_CTL_273 is shown in Figure 8-364 and described in Table 8-736.

Return to Summary Table.

Table 8-735 DDRSS_CTL_273 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0444h

Figure 8-364 DDRSS_CTL_273 Register

31	30	29	28	27	26	25	24
RESERVED			RESERVED
R/W-X			R/W-0h

23	22	21	20	19	18	17	16
RESERVED							CS_LOWER_ADDR_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
CS_MSK_1
R/W-0h

7	6	5	4	3	2	1	0
CS_MSK_1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-736 DDRSS_CTL_273 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	RESERVED	R/W	0h	Reserved
23-17	RESERVED	R/W	X
16	CS_LOWER_ADDR_EN	R/W	0h	Enables moving the CS field to lower in the address map. When set to 1, the memory address map will be changed to ROW__CS__BANK. Please refer to the limitations before setting this bit.
15-0	CS_MSK_1	R/W	0h	Mask applied to the address decode for chip select 1.

2.5.2.273 DDRSS_CTL_274 Register (Offset = 448h) [reset = X]

DDRSS_CTL_274 is shown in Figure 8-365 and described in Table 8-738.

Return to Summary Table.

Table 8-737 DDRSS_CTL_274 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0448h

Figure 8-365 DDRSS_CTL_274 Register

31	30	29	28	27	26	25	24
COMMAND_AGE_COUNT
R/W-0h

23	22	21	20	19	18	17	16
AGE_COUNT
R/W-0h

15	14	13	12	11	10	9	8
RESERVED			APREBIT
R/W-X			R/W-Ah

7	6	5	4	3	2	1	0
RESERVED							RESERVED
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-738 DDRSS_CTL_274 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	COMMAND_AGE_COUNT	R/W	0h	Initial value of individual command aging counters for command aging.
23-16	AGE_COUNT	R/W	0h	Initial value of master aging-rate counter for command aging.
15-13	RESERVED	R/W	X
12-8	APREBIT	R/W	Ah	Location of the auto pre-charge bit in the DRAM address.
7-1	RESERVED	R/W	X
0	RESERVED	R/W	0h	Reserved

2.5.2.274 DDRSS_CTL_275 Register (Offset = 44Ch) [reset = X]

DDRSS_CTL_275 is shown in Figure 8-366 and described in Table 8-740.

Return to Summary Table.

Table 8-739 DDRSS_CTL_275 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 044Ch

Figure 8-366 DDRSS_CTL_275 Register

31	30	29	28	27	26	25	24
RESERVED							PLACEMENT_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							BANK_SPLIT_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							ADDR_COLLISION_MPM_DIS
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							ADDR_CMP_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-740 DDRSS_CTL_275 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	PLACEMENT_EN	R/W	0h	Enable placement logic for command queue. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	BANK_SPLIT_EN	R/W	0h	Enable bank splitting as a rule for command queue placement. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	ADDR_COLLISION_MPM_DIS	R/W	0h	Disable address collision detection extension using micro page mask for command queue placement and selection. Set to 1 to disable.
7-1	RESERVED	R/W	X
0	ADDR_CMP_EN	R/W	0h	Enable address collision detection as a rule for command queue placement. Set to 1 to enable.

2.5.2.275 DDRSS_CTL_276 Register (Offset = 450h) [reset = X]

DDRSS_CTL_276 is shown in Figure 8-367 and described in Table 8-742.

Return to Summary Table.

Table 8-741 DDRSS_CTL_276 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0450h

Figure 8-367 DDRSS_CTL_276 Register

31	30	29	28	27	26	25	24
RESERVED							CS_SAME_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							RW_SAME_PAGE_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							RW_SAME_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							PRIORITY_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-742 DDRSS_CTL_276 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	CS_SAME_EN	R/W	0h	Enable chip select grouping when read/write grouping as a rule for command queue placement. This is only valid when the RW_SAME_EN parameter is set. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	RW_SAME_PAGE_EN	R/W	0h	Enable page grouping when read/write grouping as a rule for command queue placement. This is only valid when the RW_SAME_EN parameter is set. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	RW_SAME_EN	R/W	0h	Enable read/write grouping as a rule for command queue placement. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	PRIORITY_EN	R/W	0h	Enable priority as a rule for command queue placement. Set to 1 to enable.

2.5.2.276 DDRSS_CTL_277 Register (Offset = 454h) [reset = X]

DDRSS_CTL_277 is shown in Figure 8-368 and described in Table 8-744.

Return to Summary Table.

Table 8-743 DDRSS_CTL_277 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0454h

Figure 8-368 DDRSS_CTL_277 Register

31	30	29	28	27	26	25	24
RESERVED							SWAP_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED			NUM_Q_ENTRIES_ACT_DISABLE
R/W-X			R/W-0h

15	14	13	12	11	10	9	8
RESERVED						DISABLE_RW_GROUP_W_BNK_CONFLICT
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED							W2R_SPLIT_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-744 DDRSS_CTL_277 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	SWAP_EN	R/W	0h	Enable command swapping logic in execution unit. Set to 1 to enable. If inline ECC is enabled (if the ECC_ENABLE parameter is programmed to 1, 2 or 3), the SWAP_EN parameter must be cleared to 0 because these two features are not supported together.
23-21	RESERVED	R/W	X
20-16	NUM_Q_ENTRIES_ACT_DISABLE	R/W	0h	Number of queue entries in which ACT requests will be disabled. Programming to X will disable ACT requests from the X entries lowest in the command queue.
15-10	RESERVED	R/W	X
9-8	DISABLE_RW_GROUP_W_BNK_CONFLICT	R/W	0h	Disables placement to read/write group when grouping creates a bank collision. Bit (0) controls placement next to bank conflict command and bit (1) controls placement 2 away from bank conflict command. Set each bit to 1 to disable.
7-1	RESERVED	R/W	X
0	W2R_SPLIT_EN	R/W	0h	Enable splitting of commands to the same chip select from a write to a read command as a rule for command queue placement.

2.5.2.277 DDRSS_CTL_278 Register (Offset = 458h) [reset = X]

DDRSS_CTL_278 is shown in Figure 8-369 and described in Table 8-746.

Return to Summary Table.

Table 8-745 DDRSS_CTL_278 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0458h

Figure 8-369 DDRSS_CTL_278 Register

31	30	29	28	27	26	25	24
RESERVED							REDUC
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED						CS_MAP
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
RESERVED						INHIBIT_DRAM_CMD
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED							DISABLE_RD_INTERLEAVE
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-746 DDRSS_CTL_278 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	REDUC	R/W	0h	Enable the half datapath feature of the controller. Set to 1 to enable.
23-18	RESERVED	R/W	X
17-16	CS_MAP	R/W	0h	Defines which chip selects are active.
15-10	RESERVED	R/W	X
9-8	INHIBIT_DRAM_CMD	R/W	0h	Inhibit command types from being executed from the command queue. Clear to 0 to enable any command, program to 1 to inhibit read/write and bank commands, program to 2 to inhibit MRR and peripheral MRR commands, or program to 3 to inhibit MRR and read/write commands.
7-1	RESERVED	R/W	X
0	DISABLE_RD_INTERLEAVE	R/W	0h	Disable read data interleaving for commands from the same port, regardless of the requestor ID. If inline ECC is enabled (if the ECC_ENABLE parameter is programmed to either of 1, 2 or 3), the DISABLE_RD_INTERLEAVE parameter must be cleared to 0 because these two features are not supported together.

2.5.2.278 DDRSS_CTL_279 Register (Offset = 45Ch) [reset = X]

DDRSS_CTL_279 is shown in Figure 8-370 and described in Table 8-748.

Return to Summary Table.

Table 8-747 DDRSS_CTL_279 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 045Ch

Figure 8-370 DDRSS_CTL_279 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED														FAULT_FIFO_PROTECTION_EN
R/W-X														R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FAULT_FIFO_PROTECTION_EN
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-748 DDRSS_CTL_279 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R/W	X
17-0	FAULT_FIFO_PROTECTION_EN	R/W	0h	Enables fault fifo protection features. Set to 1 to enable.

2.5.2.279 DDRSS_CTL_280 Register (Offset = 460h) [reset = X]

DDRSS_CTL_280 is shown in Figure 8-371 and described in Table 8-750.

Return to Summary Table.

Table 8-749 DDRSS_CTL_280 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0460h

Figure 8-371 DDRSS_CTL_280 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED														FAULT_FIFO_PROTECTION_STATUS
R-X														R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FAULT_FIFO_PROTECTION_STATUS
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-750 DDRSS_CTL_280 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R	X
17-0	FAULT_FIFO_PROTECTION_STATUS	R	0h	Status of fault fifo protection modules. Value of 1 indicates an error occurred. READ ONLY

2.5.2.280 DDRSS_CTL_281 Register (Offset = 464h) [reset = X]

DDRSS_CTL_281 is shown in Figure 8-372 and described in Table 8-752.

Return to Summary Table.

Table 8-751 DDRSS_CTL_281 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0464h

Figure 8-372 DDRSS_CTL_281 Register

31	30	29	28	27	26	25	24
RESERVED							WRITE_ADDR_CHAN_PARITY_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED						FAULT_FIFO_PROTECTION_INJECTION_EN
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
FAULT_FIFO_PROTECTION_INJECTION_EN
R/W-0h

7	6	5	4	3	2	1	0
FAULT_FIFO_PROTECTION_INJECTION_EN
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-752 DDRSS_CTL_281 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	WRITE_ADDR_CHAN_PARITY_EN	R/W	0h	Enables parity checking on the AXI write command (address) channel. Set to 1 to enable.
23-18	RESERVED	R/W	X
17-0	FAULT_FIFO_PROTECTION_INJECTION_EN	R/W	0h	Triggers error injection for fault fifo protection modules. Set to 1 to trigger.

2.5.2.281 DDRSS_CTL_282 Register (Offset = 468h) [reset = X]

DDRSS_CTL_282 is shown in Figure 8-373 and described in Table 8-754.

Return to Summary Table.

Table 8-753 DDRSS_CTL_282 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0468h

Figure 8-373 DDRSS_CTL_282 Register

31	30	29	28	27	26	25	24
RESERVED							READ_DATA_CHAN_PARITY_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							READ_ADDR_CHAN_PARITY_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							WRITE_RESP_CHAN_PARITY_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED						WRITE_DATA_CHAN_PARITY_EN
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-754 DDRSS_CTL_282 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	READ_DATA_CHAN_PARITY_EN	R/W	0h	Enables parity checking on the AXI read data channel. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	READ_ADDR_CHAN_PARITY_EN	R/W	0h	Enables parity checking on the AXI read command (address) channel. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	WRITE_RESP_CHAN_PARITY_EN	R/W	0h	Enables parity checking on the AXI write response channel. Set to 1 to enable.
7-2	RESERVED	R/W	X
1-0	WRITE_DATA_CHAN_PARITY_EN	R/W	0h	Enables parity checking on the AXI write data channel. Bit (0) controls the write data bus and bit (1) controls the write strobe and last signals. Set each bit to 1 to enable.

2.5.2.282 DDRSS_CTL_283 Register (Offset = 46Ch) [reset = X]

DDRSS_CTL_283 is shown in Figure 8-374 and described in Table 8-756.

Return to Summary Table.

Table 8-755 DDRSS_CTL_283 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 046Ch

Figure 8-374 DDRSS_CTL_283 Register

31	30	29	28	27	26	25	24
RESERVED							READ_PARITY_ERR_RRESP_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							WRITE_PARITY_ERR_BRESP_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							RESERVED
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							RESERVED
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-756 DDRSS_CTL_283 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	READ_PARITY_ERR_RRESP_EN	R/W	0h	Enables AXI ERROR responses on the AXI read data channel for any parity errors that occurred on the read command (address) channel. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	WRITE_PARITY_ERR_BRESP_EN	R/W	0h	Enables AXI ERROR responses on the AXI write response channel for any parity errors that occured on either the write command (address) or write data channels. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	RESERVED	R/W	0h	Reserved
7-1	RESERVED	R/W	X
0	RESERVED	R/W	0h	Reserved

2.5.2.283 DDRSS_CTL_284 Register (Offset = 470h) [reset = X]

DDRSS_CTL_284 is shown in Figure 8-375 and described in Table 8-758.

Return to Summary Table.

Table 8-757 DDRSS_CTL_284 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0470h

Figure 8-375 DDRSS_CTL_284 Register

31	30	29	28	27	26	25	24
RESERVED							READ_ADDR_CHAN_TRIGGER_PARITY_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							WRITE_RESP_CHAN_CORRUPT_PARITY_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							WRITE_DATA_CHAN_TRIGGER_PARITY_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							WRITE_ADDR_CHAN_TRIGGER_PARITY_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-758 DDRSS_CTL_284 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	READ_ADDR_CHAN_TRIGGER_PARITY_EN	R/W	0h	Triggers a parity error on the AXI read command (address) channel. Set to 1 to introduce an error.
23-17	RESERVED	R/W	X
16	WRITE_RESP_CHAN_CORRUPT_PARITY_EN	R/W	0h	Corrupts the parity on the AXI write response channel. Set to 1 to introduce an error.
15-9	RESERVED	R/W	X
8	WRITE_DATA_CHAN_TRIGGER_PARITY_EN	R/W	0h	Triggers a parity error on the AXI write data channel. Set to 1 to introduce an error.
7-1	RESERVED	R/W	X
0	WRITE_ADDR_CHAN_TRIGGER_PARITY_EN	R/W	0h	Triggers a parity error on the AXI write command (address) channel. Set to 1 to introduce an error.

2.5.2.284 DDRSS_CTL_285 Register (Offset = 474h) [reset = X]

DDRSS_CTL_285 is shown in Figure 8-376 and described in Table 8-760.

Return to Summary Table.

Table 8-759 DDRSS_CTL_285 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0474h

Figure 8-376 DDRSS_CTL_285 Register

31	30	29	28	27	26	25	24
RESERVED							ENHANCED_PARITY_PROTECTION_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							WRITE_PARITY_ERR_CORRUPT_ECC_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							ECC_AXI_ERROR_RESPONSE_INHIBIT
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							READ_DATA_CHAN_CORRUPT_PARITY_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-760 DDRSS_CTL_285 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	ENHANCED_PARITY_PROTECTION_EN	R/W	0h	Enable byte parity implementation on addr/data channels.
23-17	RESERVED	R/W	X
16	WRITE_PARITY_ERR_CORRUPT_ECC_EN	R/W	0h	Enables corruption of ECC code if an AXI parity error is detected. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	ECC_AXI_ERROR_RESPONSE_INHIBIT	R/W	0h	Inhibits AXI ERROR responses when an ECC error occurs on the AXI read data channel. Set to 1 to inhibit errors.
7-1	RESERVED	R/W	X
0	READ_DATA_CHAN_CORRUPT_PARITY_EN	R/W	0h	Corrupts the parity on the AXI read data channel. Set to 1 to introduce an error.

2.5.2.285 DDRSS_CTL_286 Register (Offset = 478h) [reset = X]

DDRSS_CTL_286 is shown in Figure 8-377 and described in Table 8-762.

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Table 8-761 DDRSS_CTL_286 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0478h

Figure 8-377 DDRSS_CTL_286 Register

31	30	29	28	27	26	25	24
RESERVED				DEVICE2_BYTE0_CS0
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED				DEVICE1_BYTE0_CS0
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED				DEVICE0_BYTE0_CS0
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED					MEMDATA_RATIO_0
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-762 DDRSS_CTL_286 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	DEVICE2_BYTE0_CS0	R/W	0h	Defines the byte location of byte0 in the memory datapath for device 2 on chip 0. Used for MRRs to identify where data will be returned.
23-20	RESERVED	R/W	X
19-16	DEVICE1_BYTE0_CS0	R/W	0h	Defines the byte location of byte0 in the memory datapath for device 1 on chip 0. Used for MRRs to identify where data will be returned.
15-12	RESERVED	R/W	X
11-8	DEVICE0_BYTE0_CS0	R/W	0h	Defines the byte location of byte0 in the memory datapath for device 0 on chip 0. Used for MRRs to identify where data will be returned.
7-3	RESERVED	R/W	X
2-0	MEMDATA_RATIO_0	R/W	0h	Defines the ratio of the DRAM device size on chip select 0 to the memory data width. Program with the log2 ratio of the memory data width to the device data width.

2.5.2.286 DDRSS_CTL_287 Register (Offset = 47Ch) [reset = X]

DDRSS_CTL_287 is shown in Figure 8-378 and described in Table 8-764.

Return to Summary Table.

Table 8-763 DDRSS_CTL_287 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 047Ch

Figure 8-378 DDRSS_CTL_287 Register

31	30	29	28	27	26	25	24
RESERVED				DEVICE1_BYTE0_CS1
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED				DEVICE0_BYTE0_CS1
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED					MEMDATA_RATIO_1
R/W-X					R/W-0h

7	6	5	4	3	2	1	0
RESERVED				DEVICE3_BYTE0_CS0
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-764 DDRSS_CTL_287 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	DEVICE1_BYTE0_CS1	R/W	0h	Defines the byte location of byte0 in the memory datapath for device 1 on chip 1. Used for MRRs to identify where data will be returned.
23-20	RESERVED	R/W	X
19-16	DEVICE0_BYTE0_CS1	R/W	0h	Defines the byte location of byte0 in the memory datapath for device 0 on chip 1. Used for MRRs to identify where data will be returned.
15-11	RESERVED	R/W	X
10-8	MEMDATA_RATIO_1	R/W	0h	Defines the ratio of the DRAM device size on chip select 1 to the memory data width. Program with the log2 ratio of the memory data width to the device data width.
7-4	RESERVED	R/W	X
3-0	DEVICE3_BYTE0_CS0	R/W	0h	Defines the byte location of byte0 in the memory datapath for device 3 on chip 0. Used for MRRs to identify where data will be returned.

2.5.2.287 DDRSS_CTL_288 Register (Offset = 480h) [reset = X]

DDRSS_CTL_288 is shown in Figure 8-379 and described in Table 8-766.

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Table 8-765 DDRSS_CTL_288 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0480h

Figure 8-379 DDRSS_CTL_288 Register

31	30	29	28	27	26	25	24
RESERVED							IN_ORDER_ACCEPT
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED			Q_FULLNESS
R/W-X			R/W-0h

15	14	13	12	11	10	9	8
RESERVED				DEVICE3_BYTE0_CS1
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED				DEVICE2_BYTE0_CS1
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-766 DDRSS_CTL_288 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	IN_ORDER_ACCEPT	R/W	0h	Forces the controller to accept commands in the order in which they are placed in the command queue. If inline ECC is enabled (if the ECC_ENABLE parameter is programmed to 1, 2 or 3), the IN_ORDER_ACCEPT parameter must be set to 1.
23-21	RESERVED	R/W	X
20-16	Q_FULLNESS	R/W	0h	Quantity that determines command queue almost full assertion(q_almost_full). When set to 0 then q_almost_full will be set to 0 irrespective of number of entries in command queueu.
15-12	RESERVED	R/W	X
11-8	DEVICE3_BYTE0_CS1	R/W	0h	Defines the byte location of byte0 in the memory datapath for device 3 on chip 1. Used for MRRs to identify where data will be returned.
7-4	RESERVED	R/W	X
3-0	DEVICE2_BYTE0_CS1	R/W	0h	Defines the byte location of byte0 in the memory datapath for device 2 on chip 1. Used for MRRs to identify where data will be returned.

2.5.2.288 DDRSS_CTL_289 Register (Offset = 484h) [reset = X]

DDRSS_CTL_289 is shown in Figure 8-380 and described in Table 8-768.

Return to Summary Table.

Table 8-767 DDRSS_CTL_289 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0484h

Figure 8-380 DDRSS_CTL_289 Register

31	30	29	28	27	26	25	24
RESERVED							CTRLUPD_REQ_PER_AREF_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							CTRLUPD_REQ
R/W-X							W-0h

15	14	13	12	11	10	9	8
RESERVED							CONTROLLER_BUSY
R/W-X							R-0h

7	6	5	4	3	2	1	0
RESERVED						WR_ORDER_REQ
R/W-X						R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-768 DDRSS_CTL_289 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	CTRLUPD_REQ_PER_AREF_EN	R/W	0h	Enable an automatic controller-initiated update (dfi_ctrlupd_req) after every refresh. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	CTRLUPD_REQ	W	0h	Assert the DFI controller-initiated update request signal dfi_ctrlupd_req. Set to 1 to trigger. WRITE-ONLY
15-9	RESERVED	R/W	X
8	CONTROLLER_BUSY	R	0h	Indicator that the controller is processing a command. Evaluates all ports for outstanding transactions. Value of 1 indicates controller busy. READ-ONLY
7-2	RESERVED	R/W	X
1-0	WR_ORDER_REQ	R/W	0h	Determines if the controller can re-order write commands from the same source ID and/or the same port. Bit (0) controls source ID usage and bit (1) controls port ID usage. Set each bit to 1 to enable usage in placement logic.

2.5.2.289 DDRSS_CTL_290 Register (Offset = 488h) [reset = X]

DDRSS_CTL_290 is shown in Figure 8-381 and described in Table 8-770.

Return to Summary Table.

Table 8-769 DDRSS_CTL_290 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0488h

Figure 8-381 DDRSS_CTL_290 Register

31	30	29	28	27	26	25	24
RESERVED						PREAMBLE_SUPPORT_F2
R/W-X						R/W-0h

23	22	21	20	19	18	17	16
RESERVED						PREAMBLE_SUPPORT_F1
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
RESERVED						PREAMBLE_SUPPORT_F0
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED							CTRLUPD_AREF_HP_ENABLE
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-770 DDRSS_CTL_290 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-24	PREAMBLE_SUPPORT_F2	R/W	0h	Selection of one or two cycle preamble for read and write burst transfers for frequency copy 2.
23-18	RESERVED	R/W	X
17-16	PREAMBLE_SUPPORT_F1	R/W	0h	Selection of one or two cycle preamble for read and write burst transfers for frequency copy 1.
15-10	RESERVED	R/W	X
9-8	PREAMBLE_SUPPORT_F0	R/W	0h	Selection of one or two cycle preamble for read and write burst transfers for frequency copy 0.
7-1	RESERVED	R/W	X
0	CTRLUPD_AREF_HP_ENABLE	R/W	0h	Enable an automatic controller-initiated update (dfi_ctrlupd_req) after every high priority refresh when executing as a subtask request. Set to 1 to enable.

2.5.2.290 DDRSS_CTL_291 Register (Offset = 48Ch) [reset = X]

DDRSS_CTL_291 is shown in Figure 8-382 and described in Table 8-772.

Return to Summary Table.

Table 8-771 DDRSS_CTL_291 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 048Ch

Figure 8-382 DDRSS_CTL_291 Register

31	30	29	28	27	26	25	24
RESERVED			DFI_ERROR
R/W-X			R-0h

23	22	21	20	19	18	17	16
RESERVED							RD_DBI_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							WR_DBI_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							RD_PREAMBLE_TRAINING_EN
R/W-X							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-772 DDRSS_CTL_291 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	DFI_ERROR	R	0h	Indicates that the DFI error flag has been asserted. READ-ONLY
23-17	RESERVED	R/W	X
16	RD_DBI_EN	R/W	0h	Enables controller support of DRAM DBI feature for read data with DDR4 devices. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	WR_DBI_EN	R/W	0h	Enables controller support of DRAM DBI feature for write data with DDR4 devices. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	RD_PREAMBLE_TRAINING_EN	R/W	0h	Enable read preamble training during gate training. Set to 1 to enable.

2.5.2.291 DDRSS_CTL_292 Register (Offset = 490h) [reset = X]

DDRSS_CTL_292 is shown in Figure 8-383 and described in Table 8-774.

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Table 8-773 DDRSS_CTL_292 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0490h

Figure 8-383 DDRSS_CTL_292 Register

31	30	29	28	27	26	25	24
RESERVED							RESERVED
R/W-X							W-0h

23	22	21	20	19	18	17	16
RESERVED				DFI_ERROR_INFO
R/W-X				R-0h

15	14	13	12	11	10	9	8
DFI_ERROR_INFO
R-0h

7	6	5	4	3	2	1	0
DFI_ERROR_INFO
R-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-774 DDRSS_CTL_292 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	RESERVED	W	0h	Reserved
23-20	RESERVED	R/W	X
19-0	DFI_ERROR_INFO	R	0h	Holds the encoded DFI error type associated with the DFI_ERROR parameter assertion. READ-ONLY

2.5.2.292 DDRSS_CTL_293 Register (Offset = 494h) [reset = 0h]

DDRSS_CTL_293 is shown in Figure 8-384 and described in Table 8-776.

Return to Summary Table.

Table 8-775 DDRSS_CTL_293 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0494h

Figure 8-384 DDRSS_CTL_293 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INT_STATUS_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-776 DDRSS_CTL_293 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	INT_STATUS_0	R	0h	Status of interrupt features in the controller. READ-ONLY

2.5.2.293 DDRSS_CTL_294 Register (Offset = 498h) [reset = X]

DDRSS_CTL_294 is shown in Figure 8-385 and described in Table 8-778.

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Table 8-777 DDRSS_CTL_294 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0498h

Figure 8-385 DDRSS_CTL_294 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																			INT_STATUS_1
R-X																			R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-778 DDRSS_CTL_294 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R	X
12-0	INT_STATUS_1	R	0h	Status of interrupt features in the controller. READ-ONLY

2.5.2.294 DDRSS_CTL_295 Register (Offset = 49Ch) [reset = 0h]

DDRSS_CTL_295 is shown in Figure 8-386 and described in Table 8-780.

Return to Summary Table.

Table 8-779 DDRSS_CTL_295 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 049Ch

Figure 8-386 DDRSS_CTL_295 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INT_ACK_0
W-0h

LEGEND: W = Write Only; -n = value after reset

Table 8-780 DDRSS_CTL_295 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	INT_ACK_0	W	0h	Clear mask of the INT_STATUS parameter. WRITE-ONLY

2.5.2.295 DDRSS_CTL_296 Register (Offset = 4A0h) [reset = X]

DDRSS_CTL_296 is shown in Figure 8-387 and described in Table 8-782.

Return to Summary Table.

Table 8-781 DDRSS_CTL_296 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04A0h

Figure 8-387 DDRSS_CTL_296 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				INT_ACK_1
W-X																				W-0h

LEGEND: W = Write Only; -n = value after reset

Table 8-782 DDRSS_CTL_296 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	W	X
11-0	INT_ACK_1	W	0h	Clear mask of the INT_STATUS parameter. WRITE-ONLY

2.5.2.296 DDRSS_CTL_297 Register (Offset = 4A4h) [reset = 0h]

DDRSS_CTL_297 is shown in Figure 8-388 and described in Table 8-784.

Return to Summary Table.

Table 8-783 DDRSS_CTL_297 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04A4h

Figure 8-388 DDRSS_CTL_297 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INT_MASK_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-784 DDRSS_CTL_297 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	INT_MASK_0	R/W	0h	Mask for the controller_int signal from the INT_STATUS parameter.

2.5.2.297 DDRSS_CTL_298 Register (Offset = 4A8h) [reset = X]

DDRSS_CTL_298 is shown in Figure 8-389 and described in Table 8-786.

Return to Summary Table.

Table 8-785 DDRSS_CTL_298 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04A8h

Figure 8-389 DDRSS_CTL_298 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																			INT_MASK_1
R/W-X																			R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-786 DDRSS_CTL_298 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-13	RESERVED	R/W	X
12-0	INT_MASK_1	R/W	0h	Mask for the controller_int signal from the INT_STATUS parameter.

2.5.2.298 DDRSS_CTL_299 Register (Offset = 4ACh) [reset = 0h]

DDRSS_CTL_299 is shown in Figure 8-390 and described in Table 8-788.

Return to Summary Table.

Table 8-787 DDRSS_CTL_299 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04ACh

Figure 8-390 DDRSS_CTL_299 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OUT_OF_RANGE_ADDR_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-788 DDRSS_CTL_299 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	OUT_OF_RANGE_ADDR_0	R	0h	Address of command that caused an out-of-range interrupt. READ-ONLY

2.5.2.299 DDRSS_CTL_300 Register (Offset = 4B0h) [reset = X]

DDRSS_CTL_300 is shown in Figure 8-391 and described in Table 8-790.

Return to Summary Table.

Table 8-789 DDRSS_CTL_300 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04B0h

Figure 8-391 DDRSS_CTL_300 Register

31	30	29	28	27	26	25	24
RESERVED	OUT_OF_RANGE_TYPE
R-X	R-0h

23	22	21	20	19	18	17	16
RESERVED				OUT_OF_RANGE_LENGTH
R-X				R-0h

15	14	13	12	11	10	9	8
OUT_OF_RANGE_LENGTH
R-0h

7	6	5	4	3	2	1	0
RESERVED					OUT_OF_RANGE_ADDR_1
R-X					R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-790 DDRSS_CTL_300 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	X
30-24	OUT_OF_RANGE_TYPE	R	0h	Type of command that caused an out-of-range interrupt. READ-ONLY
23-20	RESERVED	R	X
19-8	OUT_OF_RANGE_LENGTH	R	0h	Length of command that caused an out-of-range interrupt. READ-ONLY
7-3	RESERVED	R	X
2-0	OUT_OF_RANGE_ADDR_1	R	0h	Address of command that caused an out-of-range interrupt. READ-ONLY

2.5.2.300 DDRSS_CTL_301 Register (Offset = 4B4h) [reset = X]

DDRSS_CTL_301 is shown in Figure 8-392 and described in Table 8-792.

Return to Summary Table.

Table 8-791 DDRSS_CTL_301 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04B4h

Figure 8-392 DDRSS_CTL_301 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED		OUT_OF_RANGE_SOURCE_ID
R-X		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-792 DDRSS_CTL_301 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	X
5-0	OUT_OF_RANGE_SOURCE_ID	R	0h	Source ID of command that caused an out-of-range interrupt. READ-ONLY

2.5.2.301 DDRSS_CTL_302 Register (Offset = 4B8h) [reset = 0h]

DDRSS_CTL_302 is shown in Figure 8-393 and described in Table 8-794.

Return to Summary Table.

Table 8-793 DDRSS_CTL_302 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04B8h

Figure 8-393 DDRSS_CTL_302 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_EXP_DATA_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-794 DDRSS_CTL_302 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_EXP_DATA_0	R	0h	Expected data on BIST error. READ-ONLY

2.5.2.302 DDRSS_CTL_303 Register (Offset = 4BCh) [reset = 0h]

DDRSS_CTL_303 is shown in Figure 8-394 and described in Table 8-796.

Return to Summary Table.

Table 8-795 DDRSS_CTL_303 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04BCh

Figure 8-394 DDRSS_CTL_303 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_EXP_DATA_1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-796 DDRSS_CTL_303 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_EXP_DATA_1	R	0h	Expected data on BIST error. READ-ONLY

2.5.2.303 DDRSS_CTL_304 Register (Offset = 4C0h) [reset = 0h]

DDRSS_CTL_304 is shown in Figure 8-395 and described in Table 8-798.

Return to Summary Table.

Table 8-797 DDRSS_CTL_304 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04C0h

Figure 8-395 DDRSS_CTL_304 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_EXP_DATA_2
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-798 DDRSS_CTL_304 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_EXP_DATA_2	R	0h	Expected data on BIST error. READ-ONLY

2.5.2.304 DDRSS_CTL_305 Register (Offset = 4C4h) [reset = 0h]

DDRSS_CTL_305 is shown in Figure 8-396 and described in Table 8-800.

Return to Summary Table.

Table 8-799 DDRSS_CTL_305 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04C4h

Figure 8-396 DDRSS_CTL_305 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_EXP_DATA_3
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-800 DDRSS_CTL_305 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_EXP_DATA_3	R	0h	Expected data on BIST error. READ-ONLY

2.5.2.305 DDRSS_CTL_306 Register (Offset = 4C8h) [reset = 0h]

DDRSS_CTL_306 is shown in Figure 8-397 and described in Table 8-802.

Return to Summary Table.

Table 8-801 DDRSS_CTL_306 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04C8h

Figure 8-397 DDRSS_CTL_306 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_FAIL_DATA_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-802 DDRSS_CTL_306 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_FAIL_DATA_0	R	0h	Actual data on BIST error. READ-ONLY

2.5.2.306 DDRSS_CTL_307 Register (Offset = 4CCh) [reset = 0h]

DDRSS_CTL_307 is shown in Figure 8-398 and described in Table 8-804.

Return to Summary Table.

Table 8-803 DDRSS_CTL_307 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04CCh

Figure 8-398 DDRSS_CTL_307 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_FAIL_DATA_1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-804 DDRSS_CTL_307 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_FAIL_DATA_1	R	0h	Actual data on BIST error. READ-ONLY

2.5.2.307 DDRSS_CTL_308 Register (Offset = 4D0h) [reset = 0h]

DDRSS_CTL_308 is shown in Figure 8-399 and described in Table 8-806.

Return to Summary Table.

Table 8-805 DDRSS_CTL_308 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04D0h

Figure 8-399 DDRSS_CTL_308 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_FAIL_DATA_2
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-806 DDRSS_CTL_308 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_FAIL_DATA_2	R	0h	Actual data on BIST error. READ-ONLY

2.5.2.308 DDRSS_CTL_309 Register (Offset = 4D4h) [reset = 0h]

DDRSS_CTL_309 is shown in Figure 8-400 and described in Table 8-808.

Return to Summary Table.

Table 8-807 DDRSS_CTL_309 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04D4h

Figure 8-400 DDRSS_CTL_309 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_FAIL_DATA_3
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-808 DDRSS_CTL_309 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_FAIL_DATA_3	R	0h	Actual data on BIST error. READ-ONLY

2.5.2.309 DDRSS_CTL_310 Register (Offset = 4D8h) [reset = 0h]

DDRSS_CTL_310 is shown in Figure 8-401 and described in Table 8-810.

Return to Summary Table.

Table 8-809 DDRSS_CTL_310 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04D8h

Figure 8-401 DDRSS_CTL_310 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIST_FAIL_ADDR_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-810 DDRSS_CTL_310 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	BIST_FAIL_ADDR_0	R	0h	Address of BIST error. READ-ONLY

2.5.2.310 DDRSS_CTL_311 Register (Offset = 4DCh) [reset = X]

DDRSS_CTL_311 is shown in Figure 8-402 and described in Table 8-812.

Return to Summary Table.

Table 8-811 DDRSS_CTL_311 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04DCh

Figure 8-402 DDRSS_CTL_311 Register

31	30	29	28	27	26	25	24
RESERVED
R-X

23	22	21	20	19	18	17	16
RESERVED
R-X

15	14	13	12	11	10	9	8
RESERVED
R-X

7	6	5	4	3	2	1	0
RESERVED					BIST_FAIL_ADDR_1
R-X					R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-812 DDRSS_CTL_311 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R	X
2-0	BIST_FAIL_ADDR_1	R	0h	Address of BIST error. READ-ONLY

2.5.2.311 DDRSS_CTL_312 Register (Offset = 4E0h) [reset = 0h]

DDRSS_CTL_312 is shown in Figure 8-403 and described in Table 8-814.

Return to Summary Table.

Table 8-813 DDRSS_CTL_312 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04E0h

Figure 8-403 DDRSS_CTL_312 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PORT_CMD_ERROR_ADDR_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-814 DDRSS_CTL_312 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PORT_CMD_ERROR_ADDR_0	R	0h	Address of command that caused the PORT command error. READ-ONLY

2.5.2.312 DDRSS_CTL_313 Register (Offset = 4E4h) [reset = X]

DDRSS_CTL_313 is shown in Figure 8-404 and described in Table 8-816.

Return to Summary Table.

Table 8-815 DDRSS_CTL_313 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04E4h

Figure 8-404 DDRSS_CTL_313 Register

31	30	29	28	27	26	25	24
RESERVED						ODT_RD_MAP_CS0
R/W-X						R/W-0h

23	22	21	20	19	18	17	16
RESERVED						PORT_CMD_ERROR_TYPE
R/W-X						R-0h

15	14	13	12	11	10	9	8
RESERVED		PORT_CMD_ERROR_ID
R/W-X		R-0h

7	6	5	4	3	2	1	0
RESERVED					PORT_CMD_ERROR_ADDR_1
R/W-X					R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-816 DDRSS_CTL_313 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-24	ODT_RD_MAP_CS0	R/W	0h	Determines which chip(s) will have termination when a read occurs on chip select 0. Set bit X to enable termination on csX when cs0 is performing a read.
23-18	RESERVED	R/W	X
17-16	PORT_CMD_ERROR_TYPE	R	0h	Type of error and access type that caused the PORT command error. READ-ONLY
15-14	RESERVED	R/W	X
13-8	PORT_CMD_ERROR_ID	R	0h	Source ID of command that caused the PORT command error. READ-ONLY
7-3	RESERVED	R/W	X
2-0	PORT_CMD_ERROR_ADDR_1	R	0h	Address of command that caused the PORT command error. READ-ONLY

2.5.2.313 DDRSS_CTL_314 Register (Offset = 4E8h) [reset = X]

DDRSS_CTL_314 is shown in Figure 8-405 and described in Table 8-818.

Return to Summary Table.

Table 8-817 DDRSS_CTL_314 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04E8h

Figure 8-405 DDRSS_CTL_314 Register

31	30	29	28	27	26	25	24
TODTL_2CMD_F0
R/W-0h

23	22	21	20	19	18	17	16
RESERVED						ODT_WR_MAP_CS1
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
RESERVED						ODT_RD_MAP_CS1
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED						ODT_WR_MAP_CS0
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-818 DDRSS_CTL_314 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TODTL_2CMD_F0	R/W	0h	Defines the DRAM delay from an ODT de-assertion to the next non-write, non-read command.
23-18	RESERVED	R/W	X
17-16	ODT_WR_MAP_CS1	R/W	0h	Determines which chip(s) will have termination when a write occurs on chip select 1. Set bit X to enable termination on csX when cs1 is performing a write.
15-10	RESERVED	R/W	X
9-8	ODT_RD_MAP_CS1	R/W	0h	Determines which chip(s) will have termination when a read occurs on chip select 1. Set bit X to enable termination on csX when cs1 is performing a read.
7-2	RESERVED	R/W	X
1-0	ODT_WR_MAP_CS0	R/W	0h	Determines which chip(s) will have termination when a write occurs on chip select 0. Set bit X to enable termination on csX when cs0 is performing a write.

2.5.2.314 DDRSS_CTL_315 Register (Offset = 4ECh) [reset = X]

DDRSS_CTL_315 is shown in Figure 8-406 and described in Table 8-820.

Return to Summary Table.

Table 8-819 DDRSS_CTL_315 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04ECh

Figure 8-406 DDRSS_CTL_315 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				TODTH_WR_F1				TODTL_2CMD_F1
R/W-X				R/W-0h				R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				TODTH_RD_F0				RESERVED				TODTH_WR_F0
R/W-X				R/W-0h				R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-820 DDRSS_CTL_315 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	TODTH_WR_F1	R/W	0h	Defines the DRAM minimum ODT high time after an ODT assertion for a write command.
23-16	TODTL_2CMD_F1	R/W	0h	Defines the DRAM delay from an ODT de-assertion to the next non-write, non-read command.
15-12	RESERVED	R/W	X
11-8	TODTH_RD_F0	R/W	0h	Defines the DRAM minimum ODT high time after an ODT assertion for a read command.
7-4	RESERVED	R/W	X
3-0	TODTH_WR_F0	R/W	0h	Defines the DRAM minimum ODT high time after an ODT assertion for a write command.

2.5.2.315 DDRSS_CTL_316 Register (Offset = 4F0h) [reset = X]

DDRSS_CTL_316 is shown in Figure 8-407 and described in Table 8-822.

Return to Summary Table.

Table 8-821 DDRSS_CTL_316 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04F0h

Figure 8-407 DDRSS_CTL_316 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED				TODTH_RD_F2				RESERVED				TODTH_WR_F2
R/W-X				R/W-0h				R/W-X				R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TODTL_2CMD_F2								RESERVED				TODTH_RD_F1
R/W-0h								R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-822 DDRSS_CTL_316 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	TODTH_RD_F2	R/W	0h	Defines the DRAM minimum ODT high time after an ODT assertion for a read command.
23-20	RESERVED	R/W	X
19-16	TODTH_WR_F2	R/W	0h	Defines the DRAM minimum ODT high time after an ODT assertion for a write command.
15-8	TODTL_2CMD_F2	R/W	0h	Defines the DRAM delay from an ODT de-assertion to the next non-write, non-read command.
7-4	RESERVED	R/W	X
3-0	TODTH_RD_F1	R/W	0h	Defines the DRAM minimum ODT high time after an ODT assertion for a read command.

2.5.2.316 DDRSS_CTL_317 Register (Offset = 4F4h) [reset = X]

DDRSS_CTL_317 is shown in Figure 8-408 and described in Table 8-824.

Return to Summary Table.

Table 8-823 DDRSS_CTL_317 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04F4h

Figure 8-408 DDRSS_CTL_317 Register

31	30	29	28	27	26	25	24
RESERVED							EN_ODT_ASSERT_EXCEPT_RD
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							ODT_EN_F2
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							ODT_EN_F1
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							ODT_EN_F0
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-824 DDRSS_CTL_317 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	EN_ODT_ASSERT_EXCEPT_RD	R/W	0h	Enable controller to assert ODT at all times except during reads. Assumes single ODT pin connected. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	ODT_EN_F2	R/W	0h	Enable support of DRAM ODT. When enabled, controller will assert and de-assert ODT output to DRAM as needed.
15-9	RESERVED	R/W	X
8	ODT_EN_F1	R/W	0h	Enable support of DRAM ODT. When enabled, controller will assert and de-assert ODT output to DRAM as needed.
7-1	RESERVED	R/W	X
0	ODT_EN_F0	R/W	0h	Enable support of DRAM ODT. When enabled, controller will assert and de-assert ODT output to DRAM as needed.

2.5.2.317 DDRSS_CTL_318 Register (Offset = 4F8h) [reset = X]

DDRSS_CTL_318 is shown in Figure 8-409 and described in Table 8-826.

Return to Summary Table.

Table 8-825 DDRSS_CTL_318 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04F8h

Figure 8-409 DDRSS_CTL_318 Register

31	30	29	28	27	26	25	24
RESERVED		RD_TO_ODTH_F0
R/W-X		R/W-0h

23	22	21	20	19	18	17	16
RESERVED		WR_TO_ODTH_F2
R/W-X		R/W-0h

15	14	13	12	11	10	9	8
RESERVED		WR_TO_ODTH_F1
R/W-X		R/W-0h

7	6	5	4	3	2	1	0
RESERVED		WR_TO_ODTH_F0
R/W-X		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-826 DDRSS_CTL_318 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R/W	X
29-24	RD_TO_ODTH_F0	R/W	0h	Defines the delay from a read command to ODT assertion.
23-22	RESERVED	R/W	X
21-16	WR_TO_ODTH_F2	R/W	0h	Defines the delay from a write command to ODT assertion.
15-14	RESERVED	R/W	X
13-8	WR_TO_ODTH_F1	R/W	0h	Defines the delay from a write command to ODT assertion.
7-6	RESERVED	R/W	X
5-0	WR_TO_ODTH_F0	R/W	0h	Defines the delay from a write command to ODT assertion.

2.5.2.318 DDRSS_CTL_319 Register (Offset = 4FCh) [reset = X]

DDRSS_CTL_319 is shown in Figure 8-410 and described in Table 8-828.

Return to Summary Table.

Table 8-827 DDRSS_CTL_319 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 04FCh

Figure 8-410 DDRSS_CTL_319 Register

31	30	29	28	27	26	25	24
RESERVED			RW2MRW_DLY_F1
R/W-X			R/W-8h

23	22	21	20	19	18	17	16
RESERVED			RW2MRW_DLY_F0
R/W-X			R/W-8h

15	14	13	12	11	10	9	8
RESERVED		RD_TO_ODTH_F2
R/W-X		R/W-0h

7	6	5	4	3	2	1	0
RESERVED		RD_TO_ODTH_F1
R/W-X		R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-828 DDRSS_CTL_319 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	RW2MRW_DLY_F1	R/W	8h	Additional delay to insert between read or write and mode_reg_write. Allowed programming dependent on memory system.
23-21	RESERVED	R/W	X
20-16	RW2MRW_DLY_F0	R/W	8h	Additional delay to insert between read or write and mode_reg_write. Allowed programming dependent on memory system.
15-14	RESERVED	R/W	X
13-8	RD_TO_ODTH_F2	R/W	0h	Defines the delay from a read command to ODT assertion.
7-6	RESERVED	R/W	X
5-0	RD_TO_ODTH_F1	R/W	0h	Defines the delay from a read command to ODT assertion.

2.5.2.319 DDRSS_CTL_320 Register (Offset = 500h) [reset = X]

DDRSS_CTL_320 is shown in Figure 8-411 and described in Table 8-830.

Return to Summary Table.

Table 8-829 DDRSS_CTL_320 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0500h

Figure 8-411 DDRSS_CTL_320 Register

31	30	29	28	27	26	25	24
RESERVED			W2R_DIFFCS_DLY_F0
R/W-X			R/W-1h

23	22	21	20	19	18	17	16
RESERVED			R2W_DIFFCS_DLY_F0
R/W-X			R/W-1h

15	14	13	12	11	10	9	8
RESERVED			R2R_DIFFCS_DLY_F0
R/W-X			R/W-1h

7	6	5	4	3	2	1	0
RESERVED			RW2MRW_DLY_F2
R/W-X			R/W-8h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-830 DDRSS_CTL_320 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	W2R_DIFFCS_DLY_F0	R/W	1h	Additional delay to insert between writes and reads to different chip selects. Allowed programming dependent on memory system.
23-21	RESERVED	R/W	X
20-16	R2W_DIFFCS_DLY_F0	R/W	1h	Additional delay to insert between reads and writes to different chip selects. Program to a non-zero value.
15-13	RESERVED	R/W	X
12-8	R2R_DIFFCS_DLY_F0	R/W	1h	Additional delay to insert between reads to different chip selects. Allowed programming dependent on memory system.
7-5	RESERVED	R/W	X
4-0	RW2MRW_DLY_F2	R/W	8h	Additional delay to insert between read or write and mode_reg_write. Allowed programming dependent on memory system.

2.5.2.320 DDRSS_CTL_321 Register (Offset = 504h) [reset = X]

DDRSS_CTL_321 is shown in Figure 8-412 and described in Table 8-832.

Return to Summary Table.

Table 8-831 DDRSS_CTL_321 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0504h

Figure 8-412 DDRSS_CTL_321 Register

31	30	29	28	27	26	25	24
RESERVED			W2R_DIFFCS_DLY_F1
R/W-X			R/W-1h

23	22	21	20	19	18	17	16
RESERVED			R2W_DIFFCS_DLY_F1
R/W-X			R/W-1h

15	14	13	12	11	10	9	8
RESERVED			R2R_DIFFCS_DLY_F1
R/W-X			R/W-1h

7	6	5	4	3	2	1	0
RESERVED			W2W_DIFFCS_DLY_F0
R/W-X			R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-832 DDRSS_CTL_321 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	W2R_DIFFCS_DLY_F1	R/W	1h	Additional delay to insert between writes and reads to different chip selects. Allowed programming dependent on memory system.
23-21	RESERVED	R/W	X
20-16	R2W_DIFFCS_DLY_F1	R/W	1h	Additional delay to insert between reads and writes to different chip selects. Program to a non-zero value.
15-13	RESERVED	R/W	X
12-8	R2R_DIFFCS_DLY_F1	R/W	1h	Additional delay to insert between reads to different chip selects. Allowed programming dependent on memory system.
7-5	RESERVED	R/W	X
4-0	W2W_DIFFCS_DLY_F0	R/W	1h	Additional delay to insert between writes to different chip selects. Program to a non-zero value.

2.5.2.321 DDRSS_CTL_322 Register (Offset = 508h) [reset = X]

DDRSS_CTL_322 is shown in Figure 8-413 and described in Table 8-834.

Return to Summary Table.

Table 8-833 DDRSS_CTL_322 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0508h

Figure 8-413 DDRSS_CTL_322 Register

31	30	29	28	27	26	25	24
RESERVED			W2R_DIFFCS_DLY_F2
R/W-X			R/W-1h

23	22	21	20	19	18	17	16
RESERVED			R2W_DIFFCS_DLY_F2
R/W-X			R/W-1h

15	14	13	12	11	10	9	8
RESERVED			R2R_DIFFCS_DLY_F2
R/W-X			R/W-1h

7	6	5	4	3	2	1	0
RESERVED			W2W_DIFFCS_DLY_F1
R/W-X			R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-834 DDRSS_CTL_322 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	W2R_DIFFCS_DLY_F2	R/W	1h	Additional delay to insert between writes and reads to different chip selects. Allowed programming dependent on memory system.
23-21	RESERVED	R/W	X
20-16	R2W_DIFFCS_DLY_F2	R/W	1h	Additional delay to insert between reads and writes to different chip selects. Program to a non-zero value.
15-13	RESERVED	R/W	X
12-8	R2R_DIFFCS_DLY_F2	R/W	1h	Additional delay to insert between reads to different chip selects. Allowed programming dependent on memory system.
7-5	RESERVED	R/W	X
4-0	W2W_DIFFCS_DLY_F1	R/W	1h	Additional delay to insert between writes to different chip selects. Program to a non-zero value.

2.5.2.322 DDRSS_CTL_323 Register (Offset = 50Ch) [reset = X]

DDRSS_CTL_323 is shown in Figure 8-414 and described in Table 8-836.

Return to Summary Table.

Table 8-835 DDRSS_CTL_323 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 050Ch

Figure 8-414 DDRSS_CTL_323 Register

31	30	29	28	27	26	25	24
RESERVED			R2W_SAMECS_DLY_F1
R/W-X			R/W-2h

23	22	21	20	19	18	17	16
RESERVED			R2W_SAMECS_DLY_F0
R/W-X			R/W-2h

15	14	13	12	11	10	9	8
RESERVED			R2R_SAMECS_DLY
R/W-X			R/W-0h

7	6	5	4	3	2	1	0
RESERVED			W2W_DIFFCS_DLY_F2
R/W-X			R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-836 DDRSS_CTL_323 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R/W	X
28-24	R2W_SAMECS_DLY_F1	R/W	2h	Additional delay to insert between reads and writes to the same chip select. Program to a non-zero value.
23-21	RESERVED	R/W	X
20-16	R2W_SAMECS_DLY_F0	R/W	2h	Additional delay to insert between reads and writes to the same chip select. Program to a non-zero value.
15-13	RESERVED	R/W	X
12-8	R2R_SAMECS_DLY	R/W	0h	Additional delay to insert between two reads to the same chip select. Any value including 0 supported.
7-5	RESERVED	R/W	X
4-0	W2W_DIFFCS_DLY_F2	R/W	1h	Additional delay to insert between writes to different chip selects. Program to a non-zero value.

2.5.2.323 DDRSS_CTL_324 Register (Offset = 510h) [reset = X]

DDRSS_CTL_324 is shown in Figure 8-415 and described in Table 8-838.

Return to Summary Table.

Table 8-837 DDRSS_CTL_324 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0510h

Figure 8-415 DDRSS_CTL_324 Register

31	30	29	28	27	26	25	24
RESERVED				TDQSCK_MAX_F0
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED			W2W_SAMECS_DLY
R/W-X			R/W-0h

15	14	13	12	11	10	9	8
RESERVED			W2R_SAMECS_DLY
R/W-X			R/W-0h

7	6	5	4	3	2	1	0
RESERVED			R2W_SAMECS_DLY_F2
R/W-X			R/W-2h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-838 DDRSS_CTL_324 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	TDQSCK_MAX_F0	R/W	0h	Additional delay needed for tDQSCK.
23-21	RESERVED	R/W	X
20-16	W2W_SAMECS_DLY	R/W	0h	Additional delay to insert between two writes to the same chip select. Any value including 0 supported.
15-13	RESERVED	R/W	X
12-8	W2R_SAMECS_DLY	R/W	0h	Additional delay to insert between writes and reads to the same chip select.
7-5	RESERVED	R/W	X
4-0	R2W_SAMECS_DLY_F2	R/W	2h	Additional delay to insert between reads and writes to the same chip select. Program to a non-zero value.

2.5.2.324 DDRSS_CTL_325 Register (Offset = 514h) [reset = X]

DDRSS_CTL_325 is shown in Figure 8-416 and described in Table 8-840.

Return to Summary Table.

Table 8-839 DDRSS_CTL_325 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0514h

Figure 8-416 DDRSS_CTL_325 Register

31	30	29	28	27	26	25	24
RESERVED				TDQSCK_MAX_F2
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED					TDQSCK_MIN_F1
R/W-X					R/W-0h

15	14	13	12	11	10	9	8
RESERVED				TDQSCK_MAX_F1
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED					TDQSCK_MIN_F0
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-840 DDRSS_CTL_325 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	TDQSCK_MAX_F2	R/W	0h	Additional delay needed for tDQSCK.
23-19	RESERVED	R/W	X
18-16	TDQSCK_MIN_F1	R/W	0h	Additional delay needed for tDQSCK.
15-12	RESERVED	R/W	X
11-8	TDQSCK_MAX_F1	R/W	0h	Additional delay needed for tDQSCK.
7-3	RESERVED	R/W	X
2-0	TDQSCK_MIN_F0	R/W	0h	Additional delay needed for tDQSCK.

2.5.2.325 DDRSS_CTL_326 Register (Offset = 518h) [reset = X]

DDRSS_CTL_326 is shown in Figure 8-417 and described in Table 8-842.

Return to Summary Table.

Table 8-841 DDRSS_CTL_326 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0518h

Figure 8-417 DDRSS_CTL_326 Register

31	30	29	28	27	26	25	24
RESERVED							SWLVL_START
R/W-X							W-0h

23	22	21	20	19	18	17	16
RESERVED							SWLVL_LOAD
R/W-X							W-0h

15	14	13	12	11	10	9	8
RESERVED					SW_LEVELING_MODE
R/W-X					R/W-0h

7	6	5	4	3	2	1	0
RESERVED					TDQSCK_MIN_F2
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-842 DDRSS_CTL_326 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	SWLVL_START	W	0h	User request to initiate software leveling of type in the SW_LEVELING_MODE parameter. Set to 1 to trigger. WRITE-ONLY
23-17	RESERVED	R/W	X
16	SWLVL_LOAD	W	0h	User request to load delays and execute software leveling. Set to 1 to trigger. WRITE-ONLY
15-11	RESERVED	R/W	X
10-8	SW_LEVELING_MODE	R/W	0h	Defines the leveling operation for software leveling. Clear to 0 for none, program to 1 for write leveling, program to 2 for data eye training, or program to 3 for gate training.
7-3	RESERVED	R/W	X
2-0	TDQSCK_MIN_F2	R/W	0h	Additional delay needed for tDQSCK.

2.5.2.326 DDRSS_CTL_327 Register (Offset = 51Ch) [reset = X]

DDRSS_CTL_327 is shown in Figure 8-418 and described in Table 8-844.

Return to Summary Table.

Table 8-843 DDRSS_CTL_327 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 051Ch

Figure 8-418 DDRSS_CTL_327 Register

31	30	29	28	27	26	25	24
RESERVED							SWLVL_RESP_1
R/W-X							R-0h

23	22	21	20	19	18	17	16
RESERVED							SWLVL_RESP_0
R/W-X							R-0h

15	14	13	12	11	10	9	8
RESERVED							SWLVL_OP_DONE
R/W-X							R-0h

7	6	5	4	3	2	1	0
RESERVED							SWLVL_EXIT
R/W-X							W-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-844 DDRSS_CTL_327 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	SWLVL_RESP_1	R	0h	Leveling response for data slice 1. READ-ONLY
23-17	RESERVED	R/W	X
16	SWLVL_RESP_0	R	0h	Leveling response for data slice 0. READ-ONLY
15-9	RESERVED	R/W	X
8	SWLVL_OP_DONE	R	0h	Signals that software leveling is currently in progress. Value of 1 indicates operation complete. READ-ONLY
7-1	RESERVED	R/W	X
0	SWLVL_EXIT	W	0h	User request to exit software leveling. Set to 1 to exit. WRITE-ONLY

2.5.2.327 DDRSS_CTL_328 Register (Offset = 520h) [reset = X]

DDRSS_CTL_328 is shown in Figure 8-419 and described in Table 8-846.

Return to Summary Table.

Table 8-845 DDRSS_CTL_328 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0520h

Figure 8-419 DDRSS_CTL_328 Register

31	30	29	28	27	26	25	24
RESERVED							WRLVL_REQ
R/W-X							W-0h

23	22	21	20	19	18	17	16
RESERVED							PHYUPD_APPEND_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							SWLVL_RESP_3
R/W-X							R-0h

7	6	5	4	3	2	1	0
RESERVED							SWLVL_RESP_2
R/W-X							R-0h

LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-846 DDRSS_CTL_328 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	WRLVL_REQ	W	0h	User request to initiate write leveling. Set to 1 to trigger. WRITE-ONLY
23-17	RESERVED	R/W	X
16	PHYUPD_APPEND_EN	R/W	0h	Specifies if a PHY update will be run prior to completing a training sequence. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	SWLVL_RESP_3	R	0h	Leveling response for data slice 3. READ-ONLY
7-1	RESERVED	R/W	X
0	SWLVL_RESP_2	R	0h	Leveling response for data slice 2. READ-ONLY

2.5.2.328 DDRSS_CTL_329 Register (Offset = 524h) [reset = X]

DDRSS_CTL_329 is shown in Figure 8-420 and described in Table 8-848.

Return to Summary Table.

Table 8-847 DDRSS_CTL_329 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0524h

Figure 8-420 DDRSS_CTL_329 Register

31	30	29	28	27	26	25	24
RESERVED							WRLVL_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED		WLMRD
R/W-X		R/W-0h

15	14	13	12	11	10	9	8
RESERVED		WLDQSEN
R/W-X		R/W-0h

7	6	5	4	3	2	1	0
RESERVED							WRLVL_CS
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-848 DDRSS_CTL_329 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	WRLVL_EN	R/W	0h	Enable the MC write leveling module. Set to 1 to enable.
23-22	RESERVED	R/W	X
21-16	WLMRD	R/W	0h	Delay from issuing MRS to first write leveling strobe.
15-14	RESERVED	R/W	X
13-8	WLDQSEN	R/W	0h	Delay from issuing MRS to first DQS strobe for write leveling.
7-1	RESERVED	R/W	X
0	WRLVL_CS	R/W	0h	Specifies the target chip select for the write leveling operation initiated through the WRLVL_REQ parameter.

2.5.2.329 DDRSS_CTL_330 Register (Offset = 528h) [reset = X]

DDRSS_CTL_330 is shown in Figure 8-421 and described in Table 8-850.

Return to Summary Table.

Table 8-849 DDRSS_CTL_330 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0528h

Figure 8-421 DDRSS_CTL_330 Register

31	30	29	28	27	26	25	24
RESERVED				WRLVL_RESP_MASK
R/W-X				R/W-0h

23	22	21	20	19	18	17	16
RESERVED							WRLVL_ON_SREF_EXIT
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							WRLVL_PERIODIC
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							DFI_PHY_WRLVL_MODE
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-850 DDRSS_CTL_330 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	WRLVL_RESP_MASK	R/W	0h	Mask for the dfi_wrlvl_resp signal during write leveling.
23-17	RESERVED	R/W	X
16	WRLVL_ON_SREF_EXIT	R/W	0h	Enables automatic write leveling on a self-refresh exit. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	WRLVL_PERIODIC	R/W	0h	Enables the use of the dfi_lvl_periodic signal during write leveling. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	DFI_PHY_WRLVL_MODE	R/W	0h	Specifies the PHY support for DFI write leveling. Set to 1 for supported.

2.5.2.330 DDRSS_CTL_331 Register (Offset = 52Ch) [reset = X]

DDRSS_CTL_331 is shown in Figure 8-422 and described in Table 8-852.

Return to Summary Table.

Table 8-851 DDRSS_CTL_331 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 052Ch

Figure 8-422 DDRSS_CTL_331 Register

31	30	29	28	27	26	25	24
RESERVED					WRLVL_ERROR_STATUS
R/W-X					R-0h

23	22	21	20	19	18	17	16
RESERVED						WRLVL_CS_MAP
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
RESERVED							WRLVL_ROTATE
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							WRLVL_AREF_EN
R/W-X							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-852 DDRSS_CTL_331 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-24	WRLVL_ERROR_STATUS	R	0h	Holds the error associated with the write level error interrupt. Bit (0) set indicates a TDFI_WRLVL_MAX parameter violation, bit (1) set indicates a TDFI_WRLVL_RESP parameter violation, bit (2) set indicates that a write leveling operation was attempted while memory was in self-refresh mode or self-refresh power-down mode. READ-ONLY
23-18	RESERVED	R/W	X
17-16	WRLVL_CS_MAP	R/W	0h	Defines the chip select map for write leveling operations. Bit (0) controls cs0, bit (1) controls cs1, etc. Set each bit to 1 to enable chip for write leveling.
15-9	RESERVED	R/W	X
8	WRLVL_ROTATE	R/W	0h	Enables rotational CS for interval write leveling. Set to 1 for rotating CS.
7-1	RESERVED	R/W	X
0	WRLVL_AREF_EN	R/W	0h	Enables refreshes and other non-data commands to execute in the middle of write leveling. Set to 1 to enable.

2.5.2.331 DDRSS_CTL_332 Register (Offset = 530h) [reset = 0h]

DDRSS_CTL_332 is shown in Figure 8-423 and described in Table 8-854.

Return to Summary Table.

Table 8-853 DDRSS_CTL_332 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0530h

Figure 8-423 DDRSS_CTL_332 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WRLVL_HIGH_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WRLVL_NORM_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-854 DDRSS_CTL_332 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WRLVL_HIGH_THRESHOLD_F0	R/W	0h	Write leveling high threshold number of long counts until the high priority request is asserted.
15-0	WRLVL_NORM_THRESHOLD_F0	R/W	0h	Write leveling normal threshold number of long counts until the normal priority request is asserted.

2.5.2.332 DDRSS_CTL_333 Register (Offset = 534h) [reset = 0h]

DDRSS_CTL_333 is shown in Figure 8-424 and described in Table 8-856.

Return to Summary Table.

Table 8-855 DDRSS_CTL_333 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0534h

Figure 8-424 DDRSS_CTL_333 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WRLVL_SW_PROMOTE_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WRLVL_TIMEOUT_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-856 DDRSS_CTL_333 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WRLVL_SW_PROMOTE_THRESHOLD_F0	R/W	0h	Write leveling promotion number of long counts until the high priority request is asserted. Applies to SW commands.
15-0	WRLVL_TIMEOUT_F0	R/W	0h	Write leveling timeout number of long counts until the timeout is asserted.

2.5.2.333 DDRSS_CTL_334 Register (Offset = 538h) [reset = 0h]

DDRSS_CTL_334 is shown in Figure 8-425 and described in Table 8-858.

Return to Summary Table.

Table 8-857 DDRSS_CTL_334 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0538h

Figure 8-425 DDRSS_CTL_334 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WRLVL_NORM_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WRLVL_DFI_PROMOTE_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-858 DDRSS_CTL_334 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WRLVL_NORM_THRESHOLD_F1	R/W	0h	Write leveling normal threshold number of long counts until the normal priority request is asserted.
15-0	WRLVL_DFI_PROMOTE_THRESHOLD_F0	R/W	0h	Write leveling promotion number of long counts until the high priority request is asserted. Applies to DFI commands.

2.5.2.334 DDRSS_CTL_335 Register (Offset = 53Ch) [reset = 0h]

DDRSS_CTL_335 is shown in Figure 8-426 and described in Table 8-860.

Return to Summary Table.

Table 8-859 DDRSS_CTL_335 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 053Ch

Figure 8-426 DDRSS_CTL_335 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WRLVL_TIMEOUT_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WRLVL_HIGH_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-860 DDRSS_CTL_335 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WRLVL_TIMEOUT_F1	R/W	0h	Write leveling timeout number of long counts until the timeout is asserted.
15-0	WRLVL_HIGH_THRESHOLD_F1	R/W	0h	Write leveling high threshold number of long counts until the high priority request is asserted.

2.5.2.335 DDRSS_CTL_336 Register (Offset = 540h) [reset = 0h]

DDRSS_CTL_336 is shown in Figure 8-427 and described in Table 8-862.

Return to Summary Table.

Table 8-861 DDRSS_CTL_336 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0540h

Figure 8-427 DDRSS_CTL_336 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WRLVL_DFI_PROMOTE_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WRLVL_SW_PROMOTE_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-862 DDRSS_CTL_336 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WRLVL_DFI_PROMOTE_THRESHOLD_F1	R/W	0h	Write leveling promotion number of long counts until the high priority request is asserted. Applies to DFI commands.
15-0	WRLVL_SW_PROMOTE_THRESHOLD_F1	R/W	0h	Write leveling promotion number of long counts until the high priority request is asserted. Applies to SW commands.

2.5.2.336 DDRSS_CTL_337 Register (Offset = 544h) [reset = 0h]

DDRSS_CTL_337 is shown in Figure 8-428 and described in Table 8-864.

Return to Summary Table.

Table 8-863 DDRSS_CTL_337 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0544h

Figure 8-428 DDRSS_CTL_337 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WRLVL_HIGH_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WRLVL_NORM_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-864 DDRSS_CTL_337 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WRLVL_HIGH_THRESHOLD_F2	R/W	0h	Write leveling high threshold number of long counts until the high priority request is asserted.
15-0	WRLVL_NORM_THRESHOLD_F2	R/W	0h	Write leveling normal threshold number of long counts until the normal priority request is asserted.

2.5.2.337 DDRSS_CTL_338 Register (Offset = 548h) [reset = 0h]

DDRSS_CTL_338 is shown in Figure 8-429 and described in Table 8-866.

Return to Summary Table.

Table 8-865 DDRSS_CTL_338 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0548h

Figure 8-429 DDRSS_CTL_338 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
WRLVL_SW_PROMOTE_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WRLVL_TIMEOUT_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-866 DDRSS_CTL_338 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	WRLVL_SW_PROMOTE_THRESHOLD_F2	R/W	0h	Write leveling promotion number of long counts until the high priority request is asserted. Applies to SW commands.
15-0	WRLVL_TIMEOUT_F2	R/W	0h	Write leveling timeout number of long counts until the timeout is asserted.

2.5.2.338 DDRSS_CTL_339 Register (Offset = 54Ch) [reset = X]

DDRSS_CTL_339 is shown in Figure 8-430 and described in Table 8-868.

Return to Summary Table.

Table 8-867 DDRSS_CTL_339 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 054Ch

Figure 8-430 DDRSS_CTL_339 Register

31	30	29	28	27	26	25	24
RESERVED							RDLVL_GATE_REQ
R/W-X							W-0h

23	22	21	20	19	18	17	16
RESERVED							RDLVL_REQ
R/W-X							W-0h

15	14	13	12	11	10	9	8
WRLVL_DFI_PROMOTE_THRESHOLD_F2
R/W-0h

7	6	5	4	3	2	1	0
WRLVL_DFI_PROMOTE_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-868 DDRSS_CTL_339 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	RDLVL_GATE_REQ	W	0h	User request to initiate gate training. Set to 1 to trigger. WRITE-ONLY
23-17	RESERVED	R/W	X
16	RDLVL_REQ	W	0h	User request to initiate data eye training. Set to 1 to trigger. WRITE-ONLY
15-0	WRLVL_DFI_PROMOTE_THRESHOLD_F2	R/W	0h	Write leveling promotion number of long counts until the high priority request is asserted. Applies to DFI commands.

2.5.2.339 DDRSS_CTL_340 Register (Offset = 550h) [reset = X]

DDRSS_CTL_340 is shown in Figure 8-431 and described in Table 8-870.

Return to Summary Table.

Table 8-869 DDRSS_CTL_340 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0550h

Figure 8-431 DDRSS_CTL_340 Register

31	30	29	28	27	26	25	24
RESERVED							DFI_PHY_RDLVL_MODE
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED				RDLVL_GATE_SEQ_EN
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED				RDLVL_SEQ_EN
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED							RDLVL_CS
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-870 DDRSS_CTL_340 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	DFI_PHY_RDLVL_MODE	R/W	0h	Specifies the PHY support for DFI data eye training. Set to 1 for supported.
23-20	RESERVED	R/W	X
19-16	RDLVL_GATE_SEQ_EN	R/W	0h	Specifies the pattern, format and MPR for gate training.
15-12	RESERVED	R/W	X
11-8	RDLVL_SEQ_EN	R/W	0h	Specifies the pattern, format and MPR for data eye training.
7-1	RESERVED	R/W	X
0	RDLVL_CS	R/W	0h	Specifies the target chip select for the data eye training operation initiated through the RDLVL_REQ parameter or the gate training operation initiated through the RDLVL_GATE_REQ parameter.

2.5.2.340 DDRSS_CTL_341 Register (Offset = 554h) [reset = X]

DDRSS_CTL_341 is shown in Figure 8-432 and described in Table 8-872.

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Table 8-871 DDRSS_CTL_341 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0554h

Figure 8-432 DDRSS_CTL_341 Register

31	30	29	28	27	26	25	24
RESERVED							RDLVL_GATE_PERIODIC
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							RDLVL_ON_SREF_EXIT
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							RDLVL_PERIODIC
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							DFI_PHY_RDLVL_GATE_MODE
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-872 DDRSS_CTL_341 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	RDLVL_GATE_PERIODIC	R/W	0h	Enables the use of the dfi_lvl_periodic signal during gate training. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	RDLVL_ON_SREF_EXIT	R/W	0h	Enables automatic data eye training on a self-refresh exit. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	RDLVL_PERIODIC	R/W	0h	Enables the use of the dfi_lvl_periodic signal during data eye training. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	DFI_PHY_RDLVL_GATE_MODE	R/W	0h	Specifies the PHY support for DFI gate training. Set to 1 for supported.

2.5.2.341 DDRSS_CTL_342 Register (Offset = 558h) [reset = X]

DDRSS_CTL_342 is shown in Figure 8-433 and described in Table 8-874.

Return to Summary Table.

Table 8-873 DDRSS_CTL_342 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0558h

Figure 8-433 DDRSS_CTL_342 Register

31	30	29	28	27	26	25	24
RESERVED							RESERVED
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							RDLVL_GATE_AREF_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							RDLVL_AREF_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							RDLVL_GATE_ON_SREF_EXIT
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-874 DDRSS_CTL_342 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	RESERVED	R/W	0h	Reserved
23-17	RESERVED	R/W	X
16	RDLVL_GATE_AREF_EN	R/W	0h	Enables refreshes and other non-data commands to execute in the middle of gate training. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	RDLVL_AREF_EN	R/W	0h	Enables refreshes and other non-data commands to execute in the middle of data eye training. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	RDLVL_GATE_ON_SREF_EXIT	R/W	0h	Enables automatic gate training on a self-refresh exit. Set to 1 to enable.

2.5.2.342 DDRSS_CTL_343 Register (Offset = 55Ch) [reset = X]

DDRSS_CTL_343 is shown in Figure 8-434 and described in Table 8-876.

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Table 8-875 DDRSS_CTL_343 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 055Ch

Figure 8-434 DDRSS_CTL_343 Register

31	30	29	28	27	26	25	24
RESERVED						RDLVL_GATE_CS_MAP
R/W-X						R/W-0h

23	22	21	20	19	18	17	16
RESERVED						RDLVL_CS_MAP
R/W-X						R/W-0h

15	14	13	12	11	10	9	8
RESERVED							RDLVL_GATE_ROTATE
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							RDLVL_ROTATE
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-876 DDRSS_CTL_343 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-24	RDLVL_GATE_CS_MAP	R/W	0h	Defines the chip select map for gate training operations. Bit (0) controls cs0, bit (1) controls cs1, etc. Set each bit to 1 to enable chip for gate training.
23-18	RESERVED	R/W	X
17-16	RDLVL_CS_MAP	R/W	0h	Defines the chip select map for data eye training operations. Bit (0) controls cs0, bit (1) controls cs1, etc. Set each bit to 1 to enable chip for data eye training.
15-9	RESERVED	R/W	X
8	RDLVL_GATE_ROTATE	R/W	0h	Enables rotational CS for interval gate training. Set to 1 for rotating CS.
7-1	RESERVED	R/W	X
0	RDLVL_ROTATE	R/W	0h	Enables rotational CS for interval data eye training. Set to 1 for rotating CS.

2.5.2.343 DDRSS_CTL_344 Register (Offset = 560h) [reset = 0h]

DDRSS_CTL_344 is shown in Figure 8-435 and described in Table 8-878.

Return to Summary Table.

Table 8-877 DDRSS_CTL_344 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0560h

Figure 8-435 DDRSS_CTL_344 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_HIGH_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_NORM_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-878 DDRSS_CTL_344 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_HIGH_THRESHOLD_F0	R/W	0h	Read leveling high threshold number of long counts until the high priority request is asserted.
15-0	RDLVL_NORM_THRESHOLD_F0	R/W	0h	Read leveling normal threshold number of long counts until the normal priority request is asserted.

2.5.2.344 DDRSS_CTL_345 Register (Offset = 564h) [reset = 0h]

DDRSS_CTL_345 is shown in Figure 8-436 and described in Table 8-880.

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Table 8-879 DDRSS_CTL_345 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0564h

Figure 8-436 DDRSS_CTL_345 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_SW_PROMOTE_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_TIMEOUT_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-880 DDRSS_CTL_345 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_SW_PROMOTE_THRESHOLD_F0	R/W	0h	Read leveling promotion number of long counts until the high priority request is asserted. Applies to SW commands.
15-0	RDLVL_TIMEOUT_F0	R/W	0h	Read leveling timeout number of long counts until the timeout is asserted.

2.5.2.345 DDRSS_CTL_346 Register (Offset = 568h) [reset = 0h]

DDRSS_CTL_346 is shown in Figure 8-437 and described in Table 8-882.

Return to Summary Table.

Table 8-881 DDRSS_CTL_346 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0568h

Figure 8-437 DDRSS_CTL_346 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_GATE_NORM_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_DFI_PROMOTE_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-882 DDRSS_CTL_346 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_GATE_NORM_THRESHOLD_F0	R/W	0h	Gate training normal threshold number of long counts until the normal priority request is asserted.
15-0	RDLVL_DFI_PROMOTE_THRESHOLD_F0	R/W	0h	Read leveling promotion number of long counts until the high priority request is asserted. Applies to DFI commands.

2.5.2.346 DDRSS_CTL_347 Register (Offset = 56Ch) [reset = 0h]

DDRSS_CTL_347 is shown in Figure 8-438 and described in Table 8-884.

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Table 8-883 DDRSS_CTL_347 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 056Ch

Figure 8-438 DDRSS_CTL_347 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_GATE_TIMEOUT_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_GATE_HIGH_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-884 DDRSS_CTL_347 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_GATE_TIMEOUT_F0	R/W	0h	Gate training timeout number of long counts until the timeout is asserted.
15-0	RDLVL_GATE_HIGH_THRESHOLD_F0	R/W	0h	Gate training high threshold number of long counts until the high priority request is asserted.

2.5.2.347 DDRSS_CTL_348 Register (Offset = 570h) [reset = 0h]

DDRSS_CTL_348 is shown in Figure 8-439 and described in Table 8-886.

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Table 8-885 DDRSS_CTL_348 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0570h

Figure 8-439 DDRSS_CTL_348 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-886 DDRSS_CTL_348 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0	R/W	0h	Gate training promotion number of long counts until the high priority request is asserted. Applies to DFI commands.
15-0	RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0	R/W	0h	Gate training promotion number of long counts until the high priority request is asserted. Applies to SW commands.

2.5.2.348 DDRSS_CTL_349 Register (Offset = 574h) [reset = 0h]

DDRSS_CTL_349 is shown in Figure 8-440 and described in Table 8-888.

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Table 8-887 DDRSS_CTL_349 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0574h

Figure 8-440 DDRSS_CTL_349 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_HIGH_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_NORM_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-888 DDRSS_CTL_349 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_HIGH_THRESHOLD_F1	R/W	0h	Read leveling high threshold number of long counts until the high priority request is asserted.
15-0	RDLVL_NORM_THRESHOLD_F1	R/W	0h	Read leveling normal threshold number of long counts until the normal priority request is asserted.

2.5.2.349 DDRSS_CTL_350 Register (Offset = 578h) [reset = 0h]

DDRSS_CTL_350 is shown in Figure 8-441 and described in Table 8-890.

Return to Summary Table.

Table 8-889 DDRSS_CTL_350 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0578h

Figure 8-441 DDRSS_CTL_350 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_SW_PROMOTE_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_TIMEOUT_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-890 DDRSS_CTL_350 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_SW_PROMOTE_THRESHOLD_F1	R/W	0h	Read leveling promotion number of long counts until the high priority request is asserted. Applies to SW commands.
15-0	RDLVL_TIMEOUT_F1	R/W	0h	Read leveling timeout number of long counts until the timeout is asserted.

2.5.2.350 DDRSS_CTL_351 Register (Offset = 57Ch) [reset = 0h]

DDRSS_CTL_351 is shown in Figure 8-442 and described in Table 8-892.

Return to Summary Table.

Table 8-891 DDRSS_CTL_351 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 057Ch

Figure 8-442 DDRSS_CTL_351 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_GATE_NORM_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_DFI_PROMOTE_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-892 DDRSS_CTL_351 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_GATE_NORM_THRESHOLD_F1	R/W	0h	Gate training normal threshold number of long counts until the normal priority request is asserted.
15-0	RDLVL_DFI_PROMOTE_THRESHOLD_F1	R/W	0h	Read leveling promotion number of long counts until the high priority request is asserted. Applies to DFI commands.

2.5.2.351 DDRSS_CTL_352 Register (Offset = 580h) [reset = 0h]

DDRSS_CTL_352 is shown in Figure 8-443 and described in Table 8-894.

Return to Summary Table.

Table 8-893 DDRSS_CTL_352 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0580h

Figure 8-443 DDRSS_CTL_352 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_GATE_TIMEOUT_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_GATE_HIGH_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-894 DDRSS_CTL_352 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_GATE_TIMEOUT_F1	R/W	0h	Gate training timeout number of long counts until the timeout is asserted.
15-0	RDLVL_GATE_HIGH_THRESHOLD_F1	R/W	0h	Gate training high threshold number of long counts until the high priority request is asserted.

2.5.2.352 DDRSS_CTL_353 Register (Offset = 584h) [reset = 0h]

DDRSS_CTL_353 is shown in Figure 8-444 and described in Table 8-896.

Return to Summary Table.

Table 8-895 DDRSS_CTL_353 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0584h

Figure 8-444 DDRSS_CTL_353 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-896 DDRSS_CTL_353 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1	R/W	0h	Gate training promotion number of long counts until the high priority request is asserted. Applies to DFI commands.
15-0	RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1	R/W	0h	Gate training promotion number of long counts until the high priority request is asserted. Applies to SW commands.

2.5.2.353 DDRSS_CTL_354 Register (Offset = 588h) [reset = 0h]

DDRSS_CTL_354 is shown in Figure 8-445 and described in Table 8-898.

Return to Summary Table.

Table 8-897 DDRSS_CTL_354 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0588h

Figure 8-445 DDRSS_CTL_354 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_HIGH_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_NORM_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-898 DDRSS_CTL_354 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_HIGH_THRESHOLD_F2	R/W	0h	Read leveling high threshold number of long counts until the high priority request is asserted.
15-0	RDLVL_NORM_THRESHOLD_F2	R/W	0h	Read leveling normal threshold number of long counts until the normal priority request is asserted.

2.5.2.354 DDRSS_CTL_355 Register (Offset = 58Ch) [reset = 0h]

DDRSS_CTL_355 is shown in Figure 8-446 and described in Table 8-900.

Return to Summary Table.

Table 8-899 DDRSS_CTL_355 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 058Ch

Figure 8-446 DDRSS_CTL_355 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_SW_PROMOTE_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_TIMEOUT_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-900 DDRSS_CTL_355 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_SW_PROMOTE_THRESHOLD_F2	R/W	0h	Read leveling promotion number of long counts until the high priority request is asserted. Applies to SW commands.
15-0	RDLVL_TIMEOUT_F2	R/W	0h	Read leveling timeout number of long counts until the timeout is asserted.

2.5.2.355 DDRSS_CTL_356 Register (Offset = 590h) [reset = 0h]

DDRSS_CTL_356 is shown in Figure 8-447 and described in Table 8-902.

Return to Summary Table.

Table 8-901 DDRSS_CTL_356 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0590h

Figure 8-447 DDRSS_CTL_356 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_GATE_NORM_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_DFI_PROMOTE_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-902 DDRSS_CTL_356 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_GATE_NORM_THRESHOLD_F2	R/W	0h	Gate training normal threshold number of long counts until the normal priority request is asserted.
15-0	RDLVL_DFI_PROMOTE_THRESHOLD_F2	R/W	0h	Read leveling promotion number of long counts until the high priority request is asserted. Applies to DFI commands.

2.5.2.356 DDRSS_CTL_357 Register (Offset = 594h) [reset = 0h]

DDRSS_CTL_357 is shown in Figure 8-448 and described in Table 8-904.

Return to Summary Table.

Table 8-903 DDRSS_CTL_357 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0594h

Figure 8-448 DDRSS_CTL_357 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_GATE_TIMEOUT_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_GATE_HIGH_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-904 DDRSS_CTL_357 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_GATE_TIMEOUT_F2	R/W	0h	Gate training timeout number of long counts until the timeout is asserted.
15-0	RDLVL_GATE_HIGH_THRESHOLD_F2	R/W	0h	Gate training high threshold number of long counts until the high priority request is asserted.

2.5.2.357 DDRSS_CTL_358 Register (Offset = 598h) [reset = 0h]

DDRSS_CTL_358 is shown in Figure 8-449 and described in Table 8-906.

Return to Summary Table.

Table 8-905 DDRSS_CTL_358 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0598h

Figure 8-449 DDRSS_CTL_358 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-906 DDRSS_CTL_358 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2	R/W	0h	Gate training promotion number of long counts until the high priority request is asserted. Applies to DFI commands.
15-0	RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2	R/W	0h	Gate training promotion number of long counts until the high priority request is asserted. Applies to SW commands.

2.5.2.358 DDRSS_CTL_359 Register (Offset = 59Ch) [reset = X]

DDRSS_CTL_359 is shown in Figure 8-450 and described in Table 8-908.

Return to Summary Table.

Table 8-907 DDRSS_CTL_359 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 059Ch

Figure 8-450 DDRSS_CTL_359 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED							CALVL_CS
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							CALVL_REQ
R/W-X							W-0h

LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset

Table 8-908 DDRSS_CTL_359 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R/W	X
8	CALVL_CS	R/W	0h	Specifies the target chip select for the CA training operation initiated through the CALVL_REQ parameter.
7-1	RESERVED	R/W	X
0	CALVL_REQ	W	0h	User request to initiate CA training. Set to 1 to trigger. WRITE-ONLY

2.5.2.359 DDRSS_CTL_360 Register (Offset = 5A0h) [reset = X]

DDRSS_CTL_360 is shown in Figure 8-451 and described in Table 8-910.

Return to Summary Table.

Table 8-909 DDRSS_CTL_360 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05A0h

Figure 8-451 DDRSS_CTL_360 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												CALVL_PAT_0
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-910 DDRSS_CTL_360 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	CALVL_PAT_0	R/W	0h	CA Training pattern 0 driven on the CA bus during a calibration command.

2.5.2.360 DDRSS_CTL_361 Register (Offset = 5A4h) [reset = X]

DDRSS_CTL_361 is shown in Figure 8-452 and described in Table 8-912.

Return to Summary Table.

Table 8-911 DDRSS_CTL_361 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05A4h

Figure 8-452 DDRSS_CTL_361 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												CALVL_BG_PAT_0
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-912 DDRSS_CTL_361 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	CALVL_BG_PAT_0	R/W	0h	CA Training pattern 0 driven on the CA bus before and after a calibration command.

2.5.2.361 DDRSS_CTL_362 Register (Offset = 5A8h) [reset = X]

DDRSS_CTL_362 is shown in Figure 8-453 and described in Table 8-914.

Return to Summary Table.

Table 8-913 DDRSS_CTL_362 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05A8h

Figure 8-453 DDRSS_CTL_362 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												CALVL_PAT_1
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-914 DDRSS_CTL_362 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	CALVL_PAT_1	R/W	0h	CA Training pattern 1 driven on the CA bus during a calibration command.

2.5.2.362 DDRSS_CTL_363 Register (Offset = 5ACh) [reset = X]

DDRSS_CTL_363 is shown in Figure 8-454 and described in Table 8-916.

Return to Summary Table.

Table 8-915 DDRSS_CTL_363 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05ACh

Figure 8-454 DDRSS_CTL_363 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												CALVL_BG_PAT_1
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-916 DDRSS_CTL_363 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	CALVL_BG_PAT_1	R/W	0h	CA Training pattern 1 driven on the CA bus before and after a calibration command.

2.5.2.363 DDRSS_CTL_364 Register (Offset = 5B0h) [reset = X]

DDRSS_CTL_364 is shown in Figure 8-455 and described in Table 8-918.

Return to Summary Table.

Table 8-917 DDRSS_CTL_364 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05B0h

Figure 8-455 DDRSS_CTL_364 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												CALVL_PAT_2
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-918 DDRSS_CTL_364 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	CALVL_PAT_2	R/W	0h	CA Training pattern 2 driven on the CA bus during a calibration command.

2.5.2.364 DDRSS_CTL_365 Register (Offset = 5B4h) [reset = X]

DDRSS_CTL_365 is shown in Figure 8-456 and described in Table 8-920.

Return to Summary Table.

Table 8-919 DDRSS_CTL_365 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05B4h

Figure 8-456 DDRSS_CTL_365 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												CALVL_BG_PAT_2
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-920 DDRSS_CTL_365 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	CALVL_BG_PAT_2	R/W	0h	CA Training pattern 2 driven on the CA bus before and after a calibration command.

2.5.2.365 DDRSS_CTL_366 Register (Offset = 5B8h) [reset = X]

DDRSS_CTL_366 is shown in Figure 8-457 and described in Table 8-922.

Return to Summary Table.

Table 8-921 DDRSS_CTL_366 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05B8h

Figure 8-457 DDRSS_CTL_366 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED												CALVL_PAT_3
R/W-X												R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-922 DDRSS_CTL_366 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-20	RESERVED	R/W	X
19-0	CALVL_PAT_3	R/W	0h	CA Training pattern 3 driven on the CA bus during a calibration command.

2.5.2.366 DDRSS_CTL_367 Register (Offset = 5BCh) [reset = X]

DDRSS_CTL_367 is shown in Figure 8-458 and described in Table 8-924.

Return to Summary Table.

Table 8-923 DDRSS_CTL_367 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05BCh

Figure 8-458 DDRSS_CTL_367 Register

31	30	29	28	27	26	25	24
RESERVED							RESERVED
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED				CALVL_BG_PAT_3
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
CALVL_BG_PAT_3
R/W-0h

7	6	5	4	3	2	1	0
CALVL_BG_PAT_3
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-924 DDRSS_CTL_367 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	RESERVED	R/W	0h	Reserved
23-20	RESERVED	R/W	X
19-0	CALVL_BG_PAT_3	R/W	0h	CA Training pattern 3 driven on the CA bus before and after a calibration command.

2.5.2.367 DDRSS_CTL_368 Register (Offset = 5C0h) [reset = X]

DDRSS_CTL_368 is shown in Figure 8-459 and described in Table 8-926.

Return to Summary Table.

Table 8-925 DDRSS_CTL_368 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05C0h

Figure 8-459 DDRSS_CTL_368 Register

31	30	29	28	27	26	25	24
RESERVED							CALVL_PERIODIC
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							DFI_PHY_CALVL_MODE
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED						CALVL_SEQ_EN
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED				RESERVED
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-926 DDRSS_CTL_368 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	CALVL_PERIODIC	R/W	0h	Enables the use of the dfi_lvl_periodic signal during CA training. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	DFI_PHY_CALVL_MODE	R/W	0h	Specifies the PHY support for DFI CA training. Set to 1 for supported.
15-10	RESERVED	R/W	X
9-8	CALVL_SEQ_EN	R/W	0h	Specifies which CA training patterns will be used. Clear to 0 for pattern 0 only, program to 1 for patterns 0 and 1, program to 2 for patterns 0, 1 and 2, or program to 3 for all patterns.
7-4	RESERVED	R/W	X
3-0	RESERVED	R/W	0h	Reserved

2.5.2.368 DDRSS_CTL_369 Register (Offset = 5C4h) [reset = X]

DDRSS_CTL_369 is shown in Figure 8-460 and described in Table 8-928.

Return to Summary Table.

Table 8-927 DDRSS_CTL_369 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05C4h

Figure 8-460 DDRSS_CTL_369 Register

31	30	29	28	27	26	25	24
RESERVED						CALVL_CS_MAP
R/W-X						R/W-0h

23	22	21	20	19	18	17	16
RESERVED							CALVL_ROTATE
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							CALVL_AREF_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							CALVL_ON_SREF_EXIT
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-928 DDRSS_CTL_369 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-24	CALVL_CS_MAP	R/W	0h	Defines the chip select map for CA training operations. Bit (0) controls cs0, bit (1) controls cs1, etc. Set each bit to 1 to enable chip for CA training.
23-17	RESERVED	R/W	X
16	CALVL_ROTATE	R/W	0h	Enables rotational CS for interval CA training. Set to 1 for rotating CS.
15-9	RESERVED	R/W	X
8	CALVL_AREF_EN	R/W	0h	Enables refreshes and other non-data commands to execute in the middle of CA training. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	CALVL_ON_SREF_EXIT	R/W	0h	Enables automatic CA training on a self-refresh exit. Set to 1 to enable.

2.5.2.369 DDRSS_CTL_370 Register (Offset = 5C8h) [reset = 0h]

DDRSS_CTL_370 is shown in Figure 8-461 and described in Table 8-930.

Return to Summary Table.

Table 8-929 DDRSS_CTL_370 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05C8h

Figure 8-461 DDRSS_CTL_370 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CALVL_HIGH_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALVL_NORM_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-930 DDRSS_CTL_370 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CALVL_HIGH_THRESHOLD_F0	R/W	0h	CA training high threshold number of long counts until the high priority request is asserted.
15-0	CALVL_NORM_THRESHOLD_F0	R/W	0h	CA training normal threshold number of long counts until the normal priority request is asserted.

2.5.2.370 DDRSS_CTL_371 Register (Offset = 5CCh) [reset = 0h]

DDRSS_CTL_371 is shown in Figure 8-462 and described in Table 8-932.

Return to Summary Table.

Table 8-931 DDRSS_CTL_371 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05CCh

Figure 8-462 DDRSS_CTL_371 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CALVL_SW_PROMOTE_THRESHOLD_F0
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALVL_TIMEOUT_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-932 DDRSS_CTL_371 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CALVL_SW_PROMOTE_THRESHOLD_F0	R/W	0h	CA training promotion number of long counts until the high priority request is asserted. Applies to SW commands.
15-0	CALVL_TIMEOUT_F0	R/W	0h	CA training timeout number of long counts until the timeout is asserted.

2.5.2.371 DDRSS_CTL_372 Register (Offset = 5D0h) [reset = 0h]

DDRSS_CTL_372 is shown in Figure 8-463 and described in Table 8-934.

Return to Summary Table.

Table 8-933 DDRSS_CTL_372 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05D0h

Figure 8-463 DDRSS_CTL_372 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CALVL_NORM_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALVL_DFI_PROMOTE_THRESHOLD_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-934 DDRSS_CTL_372 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CALVL_NORM_THRESHOLD_F1	R/W	0h	CA training normal threshold number of long counts until the normal priority request is asserted.
15-0	CALVL_DFI_PROMOTE_THRESHOLD_F0	R/W	0h	CA training promotion number of long counts until the high priority request is asserted. Applies to DFI commands.

2.5.2.372 DDRSS_CTL_373 Register (Offset = 5D4h) [reset = 0h]

DDRSS_CTL_373 is shown in Figure 8-464 and described in Table 8-936.

Return to Summary Table.

Table 8-935 DDRSS_CTL_373 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05D4h

Figure 8-464 DDRSS_CTL_373 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CALVL_TIMEOUT_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALVL_HIGH_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-936 DDRSS_CTL_373 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CALVL_TIMEOUT_F1	R/W	0h	CA training timeout number of long counts until the timeout is asserted.
15-0	CALVL_HIGH_THRESHOLD_F1	R/W	0h	CA training high threshold number of long counts until the high priority request is asserted.

2.5.2.373 DDRSS_CTL_374 Register (Offset = 5D8h) [reset = 0h]

DDRSS_CTL_374 is shown in Figure 8-465 and described in Table 8-938.

Return to Summary Table.

Table 8-937 DDRSS_CTL_374 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05D8h

Figure 8-465 DDRSS_CTL_374 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CALVL_DFI_PROMOTE_THRESHOLD_F1
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALVL_SW_PROMOTE_THRESHOLD_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-938 DDRSS_CTL_374 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CALVL_DFI_PROMOTE_THRESHOLD_F1	R/W	0h	CA training promotion number of long counts until the high priority request is asserted. Applies to DFI commands.
15-0	CALVL_SW_PROMOTE_THRESHOLD_F1	R/W	0h	CA training promotion number of long counts until the high priority request is asserted. Applies to SW commands.

2.5.2.374 DDRSS_CTL_375 Register (Offset = 5DCh) [reset = 0h]

DDRSS_CTL_375 is shown in Figure 8-466 and described in Table 8-940.

Return to Summary Table.

Table 8-939 DDRSS_CTL_375 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05DCh

Figure 8-466 DDRSS_CTL_375 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CALVL_HIGH_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALVL_NORM_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-940 DDRSS_CTL_375 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CALVL_HIGH_THRESHOLD_F2	R/W	0h	CA training high threshold number of long counts until the high priority request is asserted.
15-0	CALVL_NORM_THRESHOLD_F2	R/W	0h	CA training normal threshold number of long counts until the normal priority request is asserted.

2.5.2.375 DDRSS_CTL_376 Register (Offset = 5E0h) [reset = 0h]

DDRSS_CTL_376 is shown in Figure 8-467 and described in Table 8-942.

Return to Summary Table.

Table 8-941 DDRSS_CTL_376 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05E0h

Figure 8-467 DDRSS_CTL_376 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CALVL_SW_PROMOTE_THRESHOLD_F2
R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALVL_TIMEOUT_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-942 DDRSS_CTL_376 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	CALVL_SW_PROMOTE_THRESHOLD_F2	R/W	0h	CA training promotion number of long counts until the high priority request is asserted. Applies to SW commands.
15-0	CALVL_TIMEOUT_F2	R/W	0h	CA training timeout number of long counts until the timeout is asserted.

2.5.2.376 DDRSS_CTL_377 Register (Offset = 5E4h) [reset = X]

DDRSS_CTL_377 is shown in Figure 8-468 and described in Table 8-944.

Return to Summary Table.

Table 8-943 DDRSS_CTL_377 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05E4h

Figure 8-468 DDRSS_CTL_377 Register

31	30	29	28	27	26	25	24
RESERVED							AXI0_FIXED_PORT_PRIORITY_ENABLE
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							AXI0_ALL_STROBES_USED_ENABLE
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
CALVL_DFI_PROMOTE_THRESHOLD_F2
R/W-0h

7	6	5	4	3	2	1	0
CALVL_DFI_PROMOTE_THRESHOLD_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-944 DDRSS_CTL_377 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	AXI0_FIXED_PORT_PRIORITY_ENABLE	R/W	0h	Defines the priority control for AXI port 0 as per-port or per-command. Set to 1 for per-port with priority defined through the AXI.4._R_PRIORITY and AXI.4._W_PRIORITY parameters. Clear to 0 for per-command.
23-17	RESERVED	R/W	X
16	AXI0_ALL_STROBES_USED_ENABLE	R/W	0h	Enables use of the AWALLSTRB signal for AXI port 0. Set to 1 to enable.
15-0	CALVL_DFI_PROMOTE_THRESHOLD_F2	R/W	0h	CA training promotion number of long counts until the high priority request is asserted. Applies to DFI commands.

2.5.2.377 DDRSS_CTL_378 Register (Offset = 5E8h) [reset = X]

DDRSS_CTL_378 is shown in Figure 8-469 and described in Table 8-946.

Return to Summary Table.

Table 8-945 DDRSS_CTL_378 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05E8h

Figure 8-469 DDRSS_CTL_378 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED					AXI0_W_PRIORITY
R/W-X					R/W-0h

7	6	5	4	3	2	1	0
RESERVED					AXI0_R_PRIORITY
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-946 DDRSS_CTL_378 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-11	RESERVED	R/W	X
10-8	AXI0_W_PRIORITY	R/W	0h	Priority of write commands from AXI port 0. 0 is the highest priority. This may only be changed before initialization begins or when the controller is quiescent, there is no data in the port FIFOs, and the AXI0_FIXED_PORT_PRIORITY_ENABLE parameter is low.
7-3	RESERVED	R/W	X
2-0	AXI0_R_PRIORITY	R/W	0h	Priority of read commands from AXI port 0. 0 is the highest priority. This may only be changed before initialization begins or when the controller is quiescent, there is no data in the port FIFOs, and the AXI0_FIXED_PORT_PRIORITY_ENABLE parameter is low.

2.5.2.378 DDRSS_CTL_379 Register (Offset = 5ECh) [reset = 0h]

DDRSS_CTL_379 is shown in Figure 8-470 and described in Table 8-948.

Return to Summary Table.

Table 8-947 DDRSS_CTL_379 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05ECh

Figure 8-470 DDRSS_CTL_379 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PARITY_ERROR_ADDRESS_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-948 DDRSS_CTL_379 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PARITY_ERROR_ADDRESS_0	R	0h	Address of the AXI command that resulted in the parity error. READ-ONLY

2.5.2.379 DDRSS_CTL_380 Register (Offset = 5F0h) [reset = X]

DDRSS_CTL_380 is shown in Figure 8-471 and described in Table 8-950.

Return to Summary Table.

Table 8-949 DDRSS_CTL_380 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05F0h

Figure 8-471 DDRSS_CTL_380 Register

31	30	29	28	27	26	25	24
RESERVED			PARITY_ERROR_BUS_CHANNEL
R-X			R-0h

23	22	21	20	19	18	17	16
PARITY_ERROR_BUS_CHANNEL
R-0h

15	14	13	12	11	10	9	8
RESERVED		PARITY_ERROR_MASTER_ID
R-X		R-0h

7	6	5	4	3	2	1	0
RESERVED					PARITY_ERROR_ADDRESS_1
R-X					R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-950 DDRSS_CTL_380 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-29	RESERVED	R	X
28-16	PARITY_ERROR_BUS_CHANNEL	R	0h	Reports the AXI field that resulted in the parity error. Bit (0) specifies if the error was on the read channel (value of 0) or the write channel (value of 1). Subsequent bits specify the exact signal that had a parity error. Bit (1): ARADDR/AWADDR, Bit (2): ARID/AWID, Bit (3): ARLEN/AWLEN, Bit (4): ARSIZE/AWSIZE, Bit (5): ARBURST/AWBURST, Bit (6): ARQOS/AWQOS, Bit (7): Misc group signals, Bit (8): Reserved, Bit (9): Reserved, Bit (10): WDATA, Bit (11): (WLAST,WSTRB), and Bit (12): Reserved. READ-ONLY
15-14	RESERVED	R	X
13-8	PARITY_ERROR_MASTER_ID	R	0h	Port ID and Master ID of the AXI command that resulted in the parity error. READ-ONLY
7-3	RESERVED	R	X
2-0	PARITY_ERROR_ADDRESS_1	R	0h	Address of the AXI command that resulted in the parity error. READ-ONLY

2.5.2.380 DDRSS_CTL_381 Register (Offset = 5F4h) [reset = 0h]

DDRSS_CTL_381 is shown in Figure 8-472 and described in Table 8-952.

Return to Summary Table.

Table 8-951 DDRSS_CTL_381 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05F4h

Figure 8-472 DDRSS_CTL_381 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PARITY_ERROR_WRITE_DATA_0
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-952 DDRSS_CTL_381 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PARITY_ERROR_WRITE_DATA_0	R	0h	Write data of the AXI command that resulted in the parity error. READ-ONLY

2.5.2.381 DDRSS_CTL_382 Register (Offset = 5F8h) [reset = 0h]

DDRSS_CTL_382 is shown in Figure 8-473 and described in Table 8-954.

Return to Summary Table.

Table 8-953 DDRSS_CTL_382 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05F8h

Figure 8-473 DDRSS_CTL_382 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PARITY_ERROR_WRITE_DATA_1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-954 DDRSS_CTL_382 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PARITY_ERROR_WRITE_DATA_1	R	0h	Write data of the AXI command that resulted in the parity error. READ-ONLY

2.5.2.382 DDRSS_CTL_383 Register (Offset = 5FCh) [reset = 0h]

DDRSS_CTL_383 is shown in Figure 8-474 and described in Table 8-956.

Return to Summary Table.

Table 8-955 DDRSS_CTL_383 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 05FCh

Figure 8-474 DDRSS_CTL_383 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PARITY_ERROR_WRITE_DATA_2
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-956 DDRSS_CTL_383 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PARITY_ERROR_WRITE_DATA_2	R	0h	Write data of the AXI command that resulted in the parity error. READ-ONLY

2.5.2.383 DDRSS_CTL_384 Register (Offset = 600h) [reset = 0h]

DDRSS_CTL_384 is shown in Figure 8-475 and described in Table 8-958.

Return to Summary Table.

Table 8-957 DDRSS_CTL_384 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0600h

Figure 8-475 DDRSS_CTL_384 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PARITY_ERROR_WRITE_DATA_3
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-958 DDRSS_CTL_384 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PARITY_ERROR_WRITE_DATA_3	R	0h	Write data of the AXI command that resulted in the parity error. READ-ONLY

2.5.2.384 DDRSS_CTL_385 Register (Offset = 604h) [reset = X]

DDRSS_CTL_385 is shown in Figure 8-476 and described in Table 8-960.

Return to Summary Table.

Table 8-959 DDRSS_CTL_385 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0604h

Figure 8-476 DDRSS_CTL_385 Register

31	30	29	28	27	26	25	24
RESERVED							MEM_RST_VALID
R-X							R-0h

23	22	21	20	19	18	17	16
RESERVED						CKE_STATUS
R-X						R-0h

15	14	13	12	11	10	9	8
PARITY_ERROR_WRITE_DATA_PARITY_VECTOR
R-0h

7	6	5	4	3	2	1	0
PARITY_ERROR_WRITE_DATA_PARITY_VECTOR
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-960 DDRSS_CTL_385 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	X
24	MEM_RST_VALID	R	0h	Register access to mem_rst_valid signal. READ-ONLY
23-18	RESERVED	R	X
17-16	CKE_STATUS	R	0h	Register access to cke_status signal. READ-ONLY
15-0	PARITY_ERROR_WRITE_DATA_PARITY_VECTOR	R	0h	Write data parity vector associated with the AXI command that resulted in the parity error. READ-ONLY

2.5.2.385 DDRSS_CTL_386 Register (Offset = 608h) [reset = X]

DDRSS_CTL_386 is shown in Figure 8-477 and described in Table 8-962.

Return to Summary Table.

Table 8-961 DDRSS_CTL_386 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0608h

Figure 8-477 DDRSS_CTL_386 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED	TDFI_PHY_WRLAT							DLL_RST_ADJ_DLY
R/W-X	R-0h							R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DLL_RST_DELAY
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-962 DDRSS_CTL_386 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30-24	TDFI_PHY_WRLAT	R	0h	Holds the calculated DFI tPHY_WRLAT timing parameter (in DFI PHY clocks), the maximum cycles between a write command and a dfi_wrdata_en assertion. READ-ONLY
23-16	DLL_RST_ADJ_DLY	R/W	0h	Minimum cycles after setting master delay in DLL until the DLL reset signal dll_rst_n may be asserted. If this signal is not being used by the PHY, this parameter may be ignored.
15-0	DLL_RST_DELAY	R/W	0h	Minimum cycles required for DLL reset signal dll_rst_n to be held. If this signal is not being used by the PHY, this parameter may be ignored.

2.5.2.386 DDRSS_CTL_387 Register (Offset = 60Ch) [reset = X]

DDRSS_CTL_387 is shown in Figure 8-478 and described in Table 8-964.

Return to Summary Table.

Table 8-963 DDRSS_CTL_387 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 060Ch

Figure 8-478 DDRSS_CTL_387 Register

31	30	29	28	27	26	25	24
RESERVED	TDFI_PHY_RDLAT_F2
R/W-X	R/W-6h

23	22	21	20	19	18	17	16
RESERVED	TDFI_PHY_RDLAT_F1
R/W-X	R/W-6h

15	14	13	12	11	10	9	8
RESERVED	TDFI_PHY_RDLAT_F0
R/W-X	R/W-6h

7	6	5	4	3	2	1	0
RESERVED	UPDATE_ERROR_STATUS
R/W-X	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-964 DDRSS_CTL_387 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30-24	TDFI_PHY_RDLAT_F2	R/W	6h	Defines the DFI tPHY_RDLAT timing parameter (in DFI PHY clocks), the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion.
23	RESERVED	R/W	X
22-16	TDFI_PHY_RDLAT_F1	R/W	6h	Defines the DFI tPHY_RDLAT timing parameter (in DFI PHY clocks), the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion.
15	RESERVED	R/W	X
14-8	TDFI_PHY_RDLAT_F0	R/W	6h	Defines the DFI tPHY_RDLAT timing parameter (in DFI PHY clocks), the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion.
7	RESERVED	R/W	X
6-0	UPDATE_ERROR_STATUS	R	0h	Identifies the source of any DFI MC-initiated or PHY-initiated update errors. Value of 1 indicates a timing violation of the associated timing parameter. READ-ONLY

2.5.2.387 DDRSS_CTL_388 Register (Offset = 610h) [reset = X]

DDRSS_CTL_388 is shown in Figure 8-479 and described in Table 8-966.

Return to Summary Table.

Table 8-965 DDRSS_CTL_388 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0610h

Figure 8-479 DDRSS_CTL_388 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
TDFI_CTRLUPD_MIN
R/W-0h

15	14	13	12	11	10	9	8
RESERVED						DRAM_CLK_DISABLE
R/W-X						R/W-0h

7	6	5	4	3	2	1	0
RESERVED	TDFI_RDDATA_EN
R/W-X	R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-966 DDRSS_CTL_388 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-16	TDFI_CTRLUPD_MIN	R/W	0h	Defines the DFI tCTRLUPD_MIN timing parameter (in DFI clocks), the minimum cycles that dfi_ctrlupd_req must be asserted.
15-10	RESERVED	R/W	X
9-8	DRAM_CLK_DISABLE	R/W	0h	Set value for the dfi_dram_clk_disable signal. Bit (0) controls cs0, bit (1) controls cs1, etc. Set each bit to 1 to disable.
7	RESERVED	R/W	X
6-0	TDFI_RDDATA_EN	R	0h	Holds the calculated DFI tRDDATA_EN timing parameter (in DFI PHY clocks), the maximum cycles between a read command and a dfi_rddata_en assertion. READ-ONLY

2.5.2.388 DDRSS_CTL_389 Register (Offset = 614h) [reset = X]

DDRSS_CTL_389 is shown in Figure 8-480 and described in Table 8-968.

Return to Summary Table.

Table 8-967 DDRSS_CTL_389 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0614h

Figure 8-480 DDRSS_CTL_389 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											TDFI_CTRLUPD_MAX_F0
R/W-X											R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-968 DDRSS_CTL_389 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-21	RESERVED	R/W	X
20-0	TDFI_CTRLUPD_MAX_F0	R/W	0h	Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks), the maximum cycles that dfi_ctrlupd_req can be asserted. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.389 DDRSS_CTL_390 Register (Offset = 618h) [reset = 0h]

DDRSS_CTL_390 is shown in Figure 8-481 and described in Table 8-970.

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Table 8-969 DDRSS_CTL_390 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0618h

Figure 8-481 DDRSS_CTL_390 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE0_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-970 DDRSS_CTL_390 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE0_F0	R/W	0h	Defines the DFI tPHYUPD_TYPE0 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 0. If programmed to a non-zero, a timing violation will cause an interrupt and bit (1) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.390 DDRSS_CTL_391 Register (Offset = 61Ch) [reset = 0h]

DDRSS_CTL_391 is shown in Figure 8-482 and described in Table 8-972.

Return to Summary Table.

Table 8-971 DDRSS_CTL_391 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 061Ch

Figure 8-482 DDRSS_CTL_391 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE1_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-972 DDRSS_CTL_391 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE1_F0	R/W	0h	Defines the DFI tPHYUPD_TYPE1 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 1. If programmed to a non-zero, a timing violation will cause an interrupt and bit (2) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.391 DDRSS_CTL_392 Register (Offset = 620h) [reset = 0h]

DDRSS_CTL_392 is shown in Figure 8-483 and described in Table 8-974.

Return to Summary Table.

Table 8-973 DDRSS_CTL_392 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0620h

Figure 8-483 DDRSS_CTL_392 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE2_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-974 DDRSS_CTL_392 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE2_F0	R/W	0h	Defines the DFI tPHYUPD_TYPE2 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 2. If programmed to a non-zero, a timing violation will cause an interrupt and bit (3) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.392 DDRSS_CTL_393 Register (Offset = 624h) [reset = 0h]

DDRSS_CTL_393 is shown in Figure 8-484 and described in Table 8-976.

Return to Summary Table.

Table 8-975 DDRSS_CTL_393 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0624h

Figure 8-484 DDRSS_CTL_393 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE3_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-976 DDRSS_CTL_393 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE3_F0	R/W	0h	Defines the DFI tPHYUPD_TYPE3 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 3. If programmed to a non-zero, a timing violation will cause an interrupt and bit (4) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.393 DDRSS_CTL_394 Register (Offset = 628h) [reset = X]

DDRSS_CTL_394 is shown in Figure 8-485 and described in Table 8-978.

Return to Summary Table.

Table 8-977 DDRSS_CTL_394 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0628h

Figure 8-485 DDRSS_CTL_394 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED									TDFI_PHYUPD_RESP_F0
R/W-X									R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-978 DDRSS_CTL_394 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22-0	TDFI_PHYUPD_RESP_F0	R/W	0h	Defines the DFI tPHYUPD_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_phyupd_req assertion and a dfi_phyupd_ack assertion. If programmed to a non-zero, a timing violation will cause an interrupt and bit (5) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.394 DDRSS_CTL_395 Register (Offset = 62Ch) [reset = 0h]

DDRSS_CTL_395 is shown in Figure 8-486 and described in Table 8-980.

Return to Summary Table.

Table 8-979 DDRSS_CTL_395 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 062Ch

Figure 8-486 DDRSS_CTL_395 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_CTRLUPD_INTERVAL_F0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-980 DDRSS_CTL_395 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_CTRLUPD_INTERVAL_F0	R/W	0h	Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks), the maximum cycles between dfi_ctrlupd_req assertions. If programmed to a non-zero, a timing violation will cause an interrupt and bit (6) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.395 DDRSS_CTL_396 Register (Offset = 630h) [reset = X]

DDRSS_CTL_396 is shown in Figure 8-487 and described in Table 8-982.

Return to Summary Table.

Table 8-981 DDRSS_CTL_396 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0630h

Figure 8-487 DDRSS_CTL_396 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED	WRLAT_ADJ_F0
R/W-X	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	RDLAT_ADJ_F0
R/W-X	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-982 DDRSS_CTL_396 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-15	RESERVED	R/W	X
14-8	WRLAT_ADJ_F0	R/W	0h	Adjustment value for PHY write timing.
7	RESERVED	R/W	X
6-0	RDLAT_ADJ_F0	R/W	0h	Adjustment value for PHY read timing.

2.5.2.396 DDRSS_CTL_397 Register (Offset = 634h) [reset = X]

DDRSS_CTL_397 is shown in Figure 8-488 and described in Table 8-984.

Return to Summary Table.

Table 8-983 DDRSS_CTL_397 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0634h

Figure 8-488 DDRSS_CTL_397 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											TDFI_CTRLUPD_MAX_F1
R/W-X											R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-984 DDRSS_CTL_397 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-21	RESERVED	R/W	X
20-0	TDFI_CTRLUPD_MAX_F1	R/W	0h	Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks), the maximum cycles that dfi_ctrlupd_req can be asserted. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.397 DDRSS_CTL_398 Register (Offset = 638h) [reset = 0h]

DDRSS_CTL_398 is shown in Figure 8-489 and described in Table 8-986.

Return to Summary Table.

Table 8-985 DDRSS_CTL_398 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0638h

Figure 8-489 DDRSS_CTL_398 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE0_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-986 DDRSS_CTL_398 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE0_F1	R/W	0h	Defines the DFI tPHYUPD_TYPE0 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 0. If programmed to a non-zero, a timing violation will cause an interrupt and bit (1) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.398 DDRSS_CTL_399 Register (Offset = 63Ch) [reset = 0h]

DDRSS_CTL_399 is shown in Figure 8-490 and described in Table 8-988.

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Table 8-987 DDRSS_CTL_399 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 063Ch

Figure 8-490 DDRSS_CTL_399 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE1_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-988 DDRSS_CTL_399 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE1_F1	R/W	0h	Defines the DFI tPHYUPD_TYPE1 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 1. If programmed to a non-zero, a timing violation will cause an interrupt and bit (2) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.399 DDRSS_CTL_400 Register (Offset = 640h) [reset = 0h]

DDRSS_CTL_400 is shown in Figure 8-491 and described in Table 8-990.

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Table 8-989 DDRSS_CTL_400 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0640h

Figure 8-491 DDRSS_CTL_400 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE2_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-990 DDRSS_CTL_400 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE2_F1	R/W	0h	Defines the DFI tPHYUPD_TYPE2 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 2. If programmed to a non-zero, a timing violation will cause an interrupt and bit (3) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.400 DDRSS_CTL_401 Register (Offset = 644h) [reset = 0h]

DDRSS_CTL_401 is shown in Figure 8-492 and described in Table 8-992.

Return to Summary Table.

Table 8-991 DDRSS_CTL_401 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0644h

Figure 8-492 DDRSS_CTL_401 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE3_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-992 DDRSS_CTL_401 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE3_F1	R/W	0h	Defines the DFI tPHYUPD_TYPE3 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 3. If programmed to a non-zero, a timing violation will cause an interrupt and bit (4) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.401 DDRSS_CTL_402 Register (Offset = 648h) [reset = X]

DDRSS_CTL_402 is shown in Figure 8-493 and described in Table 8-994.

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Table 8-993 DDRSS_CTL_402 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0648h

Figure 8-493 DDRSS_CTL_402 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED									TDFI_PHYUPD_RESP_F1
R/W-X									R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-994 DDRSS_CTL_402 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22-0	TDFI_PHYUPD_RESP_F1	R/W	0h	Defines the DFI tPHYUPD_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_phyupd_req assertion and a dfi_phyupd_ack assertion. If programmed to a non-zero, a timing violation will cause an interrupt and bit (5) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.402 DDRSS_CTL_403 Register (Offset = 64Ch) [reset = 0h]

DDRSS_CTL_403 is shown in Figure 8-494 and described in Table 8-996.

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Table 8-995 DDRSS_CTL_403 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 064Ch

Figure 8-494 DDRSS_CTL_403 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_CTRLUPD_INTERVAL_F1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-996 DDRSS_CTL_403 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_CTRLUPD_INTERVAL_F1	R/W	0h	Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks), the maximum cycles between dfi_ctrlupd_req assertions. If programmed to a non-zero, a timing violation will cause an interrupt and bit (6) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.403 DDRSS_CTL_404 Register (Offset = 650h) [reset = X]

DDRSS_CTL_404 is shown in Figure 8-495 and described in Table 8-998.

Return to Summary Table.

Table 8-997 DDRSS_CTL_404 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0650h

Figure 8-495 DDRSS_CTL_404 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED	WRLAT_ADJ_F1
R/W-X	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	RDLAT_ADJ_F1
R/W-X	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-998 DDRSS_CTL_404 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-15	RESERVED	R/W	X
14-8	WRLAT_ADJ_F1	R/W	0h	Adjustment value for PHY write timing.
7	RESERVED	R/W	X
6-0	RDLAT_ADJ_F1	R/W	0h	Adjustment value for PHY read timing.

2.5.2.404 DDRSS_CTL_405 Register (Offset = 654h) [reset = X]

DDRSS_CTL_405 is shown in Figure 8-496 and described in Table 8-1000.

Return to Summary Table.

Table 8-999 DDRSS_CTL_405 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0654h

Figure 8-496 DDRSS_CTL_405 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED											TDFI_CTRLUPD_MAX_F2
R/W-X											R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1000 DDRSS_CTL_405 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-21	RESERVED	R/W	X
20-0	TDFI_CTRLUPD_MAX_F2	R/W	0h	Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks), the maximum cycles that dfi_ctrlupd_req can be asserted. If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.405 DDRSS_CTL_406 Register (Offset = 658h) [reset = 0h]

DDRSS_CTL_406 is shown in Figure 8-497 and described in Table 8-1002.

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Table 8-1001 DDRSS_CTL_406 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0658h

Figure 8-497 DDRSS_CTL_406 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE0_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1002 DDRSS_CTL_406 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE0_F2	R/W	0h	Defines the DFI tPHYUPD_TYPE0 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 0. If programmed to a non-zero, a timing violation will cause an interrupt and bit (1) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.406 DDRSS_CTL_407 Register (Offset = 65Ch) [reset = 0h]

DDRSS_CTL_407 is shown in Figure 8-498 and described in Table 8-1004.

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Table 8-1003 DDRSS_CTL_407 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 065Ch

Figure 8-498 DDRSS_CTL_407 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE1_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1004 DDRSS_CTL_407 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE1_F2	R/W	0h	Defines the DFI tPHYUPD_TYPE1 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 1. If programmed to a non-zero, a timing violation will cause an interrupt and bit (2) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.407 DDRSS_CTL_408 Register (Offset = 660h) [reset = 0h]

DDRSS_CTL_408 is shown in Figure 8-499 and described in Table 8-1006.

Return to Summary Table.

Table 8-1005 DDRSS_CTL_408 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0660h

Figure 8-499 DDRSS_CTL_408 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE2_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1006 DDRSS_CTL_408 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE2_F2	R/W	0h	Defines the DFI tPHYUPD_TYPE2 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 2. If programmed to a non-zero, a timing violation will cause an interrupt and bit (3) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.408 DDRSS_CTL_409 Register (Offset = 664h) [reset = 0h]

DDRSS_CTL_409 is shown in Figure 8-500 and described in Table 8-1008.

Return to Summary Table.

Table 8-1007 DDRSS_CTL_409 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0664h

Figure 8-500 DDRSS_CTL_409 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_PHYUPD_TYPE3_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1008 DDRSS_CTL_409 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_PHYUPD_TYPE3_F2	R/W	0h	Defines the DFI tPHYUPD_TYPE3 timing parameter (in DFI clocks), the maximum cycles that dfi_phyupd_req can assert after dfi_phyupd_ack for dfi_phyupd_type 3. If programmed to a non-zero, a timing violation will cause an interrupt and bit (4) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.409 DDRSS_CTL_410 Register (Offset = 668h) [reset = X]

DDRSS_CTL_410 is shown in Figure 8-501 and described in Table 8-1010.

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Table 8-1009 DDRSS_CTL_410 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0668h

Figure 8-501 DDRSS_CTL_410 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED									TDFI_PHYUPD_RESP_F2
R/W-X									R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1010 DDRSS_CTL_410 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-23	RESERVED	R/W	X
22-0	TDFI_PHYUPD_RESP_F2	R/W	0h	Defines the DFI tPHYUPD_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_phyupd_req assertion and a dfi_phyupd_ack assertion. If programmed to a non-zero, a timing violation will cause an interrupt and bit (5) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.410 DDRSS_CTL_411 Register (Offset = 66Ch) [reset = 0h]

DDRSS_CTL_411 is shown in Figure 8-502 and described in Table 8-1012.

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Table 8-1011 DDRSS_CTL_411 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 066Ch

Figure 8-502 DDRSS_CTL_411 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_CTRLUPD_INTERVAL_F2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1012 DDRSS_CTL_411 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_CTRLUPD_INTERVAL_F2	R/W	0h	Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks), the maximum cycles between dfi_ctrlupd_req assertions. If programmed to a non-zero, a timing violation will cause an interrupt and bit (6) set in the UPDATE_ERROR_STATUS parameter.

2.5.2.411 DDRSS_CTL_412 Register (Offset = 670h) [reset = X]

DDRSS_CTL_412 is shown in Figure 8-503 and described in Table 8-1014.

Return to Summary Table.

Table 8-1013 DDRSS_CTL_412 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0670h

Figure 8-503 DDRSS_CTL_412 Register

31	30	29	28	27	26	25	24
RESERVED				TDFI_CTRL_DELAY_F1
R/W-X				R/W-2h

23	22	21	20	19	18	17	16
RESERVED				TDFI_CTRL_DELAY_F0
R/W-X				R/W-2h

15	14	13	12	11	10	9	8
RESERVED	WRLAT_ADJ_F2
R/W-X	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	RDLAT_ADJ_F2
R/W-X	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1014 DDRSS_CTL_412 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-28	RESERVED	R/W	X
27-24	TDFI_CTRL_DELAY_F1	R/W	2h	Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks), the delay between a DFI command change and a memory command.
23-20	RESERVED	R/W	X
19-16	TDFI_CTRL_DELAY_F0	R/W	2h	Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks), the delay between a DFI command change and a memory command.
15	RESERVED	R/W	X
14-8	WRLAT_ADJ_F2	R/W	0h	Adjustment value for PHY write timing.
7	RESERVED	R/W	X
6-0	RDLAT_ADJ_F2	R/W	0h	Adjustment value for PHY read timing.

2.5.2.412 DDRSS_CTL_413 Register (Offset = 674h) [reset = X]

DDRSS_CTL_413 is shown in Figure 8-504 and described in Table 8-1016.

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Table 8-1015 DDRSS_CTL_413 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0674h

Figure 8-504 DDRSS_CTL_413 Register

31	30	29	28	27	26	25	24
TDFI_WRLVL_EN
R/W-0h

23	22	21	20	19	18	17	16
RESERVED				TDFI_DRAM_CLK_ENABLE
R/W-X				R/W-0h

15	14	13	12	11	10	9	8
RESERVED				TDFI_DRAM_CLK_DISABLE
R/W-X				R/W-0h

7	6	5	4	3	2	1	0
RESERVED				TDFI_CTRL_DELAY_F2
R/W-X				R/W-2h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1016 DDRSS_CTL_413 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	TDFI_WRLVL_EN	R/W	0h	Defines the DFI tWRLVL_EN timing parameter (in DFI clocks), the minimum cycles from a dfi_wrlvl_en assertion to the first dfi_wrlvl_strobe assertion.
23-20	RESERVED	R/W	X
19-16	TDFI_DRAM_CLK_ENABLE	R/W	0h	Defines the DFI tDRAM_CLK_ENABLE timing parameter (in DFI clocks), the delay between a dfi_dram_clk_disable de-assertion and the memory clock enable.
15-12	RESERVED	R/W	X
11-8	TDFI_DRAM_CLK_DISABLE	R/W	0h	Defines the DFI tDRAM_CLK_DISABLE timing parameter (in DFI clocks), the delay between a dfi_dram_clock_disable assertion and the memory clock disable.
7-4	RESERVED	R/W	X
3-0	TDFI_CTRL_DELAY_F2	R/W	2h	Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks), the delay between a DFI command change and a memory command.

2.5.2.413 DDRSS_CTL_414 Register (Offset = 678h) [reset = X]

DDRSS_CTL_414 is shown in Figure 8-505 and described in Table 8-1018.

Return to Summary Table.

Table 8-1017 DDRSS_CTL_414 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0678h

Figure 8-505 DDRSS_CTL_414 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TDFI_WRLVL_WW
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1018 DDRSS_CTL_414 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-10	RESERVED	R/W	X
9-0	TDFI_WRLVL_WW	R/W	0h	Defines the DFI tWRLVL_WW timing parameter (in DFI clocks), the minimum cycles between dfi_wrlvl_strobe assertions.

2.5.2.414 DDRSS_CTL_415 Register (Offset = 67Ch) [reset = 0h]

DDRSS_CTL_415 is shown in Figure 8-506 and described in Table 8-1020.

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Table 8-1019 DDRSS_CTL_415 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 067Ch

Figure 8-506 DDRSS_CTL_415 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_WRLVL_RESP
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1020 DDRSS_CTL_415 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_WRLVL_RESP	R/W	0h	Defines the DFI tWRLVL_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_wrlvl_req assertion and a dfi_wrlvl_en assertion.

2.5.2.415 DDRSS_CTL_416 Register (Offset = 680h) [reset = 0h]

DDRSS_CTL_416 is shown in Figure 8-507 and described in Table 8-1022.

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Table 8-1021 DDRSS_CTL_416 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0680h

Figure 8-507 DDRSS_CTL_416 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_WRLVL_MAX
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1022 DDRSS_CTL_416 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_WRLVL_MAX	R/W	0h	Defines the DFI tWRLVL_MAX timing parameter (in DFI clocks), the maximum cycles between a dfi_wrlvl_en assertion and a valid dfi_wrlvl_resp.

2.5.2.416 DDRSS_CTL_417 Register (Offset = 684h) [reset = X]

DDRSS_CTL_417 is shown in Figure 8-508 and described in Table 8-1024.

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Table 8-1023 DDRSS_CTL_417 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0684h

Figure 8-508 DDRSS_CTL_417 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED														TDFI_RDLVL_RR
R/W-X														R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_RDLVL_RR								TDFI_RDLVL_EN
R/W-0h								R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1024 DDRSS_CTL_417 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R/W	X
17-8	TDFI_RDLVL_RR	R/W	0h	Defines the DFI tRDLVL_RR timing parameter (in DFI clocks), the minimum cycles between read commands.
7-0	TDFI_RDLVL_EN	R/W	0h	Defines the DFI tRDLVL_EN timing parameter (in DFI clocks), the minimum cycles from a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion to the first read or MRR.

2.5.2.417 DDRSS_CTL_418 Register (Offset = 688h) [reset = 0h]

DDRSS_CTL_418 is shown in Figure 8-509 and described in Table 8-1026.

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Table 8-1025 DDRSS_CTL_418 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0688h

Figure 8-509 DDRSS_CTL_418 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_RDLVL_RESP
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1026 DDRSS_CTL_418 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_RDLVL_RESP	R/W	0h	Defines the DFI tRDLVL_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_rdlvl_req or dfi_rdlvl_gate_req assertion and a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion.

2.5.2.418 DDRSS_CTL_419 Register (Offset = 68Ch) [reset = X]

DDRSS_CTL_419 is shown in Figure 8-510 and described in Table 8-1028.

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Table 8-1027 DDRSS_CTL_419 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 068Ch

Figure 8-510 DDRSS_CTL_419 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED							RDLVL_GATE_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							RDLVL_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RDLVL_RESP_MASK
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1028 DDRSS_CTL_419 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R/W	X
16	RDLVL_GATE_EN	R/W	0h	Enable the MC gate training module. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	RDLVL_EN	R/W	0h	Enable the MC data eye training module. Set to 1 to enable.
7-0	RDLVL_RESP_MASK	R/W	0h	Mask for the dfi_rdlvl_resp signal during data eye training.

2.5.2.419 DDRSS_CTL_420 Register (Offset = 690h) [reset = 0h]

DDRSS_CTL_420 is shown in Figure 8-511 and described in Table 8-1030.

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Table 8-1029 DDRSS_CTL_420 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0690h

Figure 8-511 DDRSS_CTL_420 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_RDLVL_MAX
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1030 DDRSS_CTL_420 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_RDLVL_MAX	R/W	0h	Defines the DFI tRDLVL_MAX timing parameter (in DFI clocks), the maximum cycles between a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion and a valid dfi_rdlvl_resp.

2.5.2.420 DDRSS_CTL_421 Register (Offset = 694h) [reset = X]

DDRSS_CTL_421 is shown in Figure 8-512 and described in Table 8-1032.

Return to Summary Table.

Table 8-1031 DDRSS_CTL_421 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0694h

Figure 8-512 DDRSS_CTL_421 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
TDFI_CALVL_EN
R/W-0h

15	14	13	12	11	10	9	8
RESERVED					RDLVL_GATE_ERROR_STATUS
R/W-X					R-0h

7	6	5	4	3	2	1	0
RESERVED					RDLVL_ERROR_STATUS
R/W-X					R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-1032 DDRSS_CTL_421 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R/W	X
23-16	TDFI_CALVL_EN	R/W	0h	Defines the DFI tCALVL_EN timing parameter (in DFI clocks), the minimum cycles between a dfi_calvl_en assertion and a dfi_cke de-assertion.
15-11	RESERVED	R/W	X
10-8	RDLVL_GATE_ERROR_STATUS	R	0h	Holds the error associated with the read gate training error or gate training error interrupt. Bit (0) set indicates a TDFI_RDLVL_MAX parameter violation, bit (1) set indicates a TDFI_RDLVL_RESP parameter violation, and bit (2) set indicates a gate training operation was attempted while memory was in self-refresh mode or self-refresh power-down mode and therefore a false rdlvl_done was signaled to move the state machine back to idle state. READ-ONLY
7-3	RESERVED	R/W	X
2-0	RDLVL_ERROR_STATUS	R	0h	Holds the error associated with the data eye training error or gate training error interrupt. Bit (0) set indicates a TDFI_RDLVL_MAX parameter violation, bit (1) set indicates a TDFI_RDLVL_RESP parameter violation, and bit (2) set indicates a read leveling operation was attempted while memory was in self-refresh mode or self-refresh power-down mode and therefore a false rdlvl_done was signaled to move the state machine back to idle state. READ-ONLY

2.5.2.421 DDRSS_CTL_422 Register (Offset = 698h) [reset = X]

DDRSS_CTL_422 is shown in Figure 8-513 and described in Table 8-1034.

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Table 8-1033 DDRSS_CTL_422 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0698h

Figure 8-513 DDRSS_CTL_422 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED						TDFI_CALVL_CAPTURE_F0
R/W-X						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TDFI_CALVL_CC_F0
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1034 DDRSS_CTL_422 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TDFI_CALVL_CAPTURE_F0	R/W	0h	Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks), the minimum cycles between a calibration command and a dfi_calvl_capture pulse.
15-10	RESERVED	R/W	X
9-0	TDFI_CALVL_CC_F0	R/W	0h	Defines the DFI tCALVL_CC timing parameter (in DFI clocks), the minimum cycles between calibration commands.

2.5.2.422 DDRSS_CTL_423 Register (Offset = 69Ch) [reset = X]

DDRSS_CTL_423 is shown in Figure 8-514 and described in Table 8-1036.

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Table 8-1035 DDRSS_CTL_423 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 069Ch

Figure 8-514 DDRSS_CTL_423 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED						TDFI_CALVL_CAPTURE_F1
R/W-X						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TDFI_CALVL_CC_F1
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1036 DDRSS_CTL_423 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TDFI_CALVL_CAPTURE_F1	R/W	0h	Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks), the minimum cycles between a calibration command and a dfi_calvl_capture pulse.
15-10	RESERVED	R/W	X
9-0	TDFI_CALVL_CC_F1	R/W	0h	Defines the DFI tCALVL_CC timing parameter (in DFI clocks), the minimum cycles between calibration commands.

2.5.2.423 DDRSS_CTL_424 Register (Offset = 6A0h) [reset = X]

DDRSS_CTL_424 is shown in Figure 8-515 and described in Table 8-1038.

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Table 8-1037 DDRSS_CTL_424 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06A0h

Figure 8-515 DDRSS_CTL_424 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED						TDFI_CALVL_CAPTURE_F2
R/W-X						R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED						TDFI_CALVL_CC_F2
R/W-X						R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1038 DDRSS_CTL_424 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-26	RESERVED	R/W	X
25-16	TDFI_CALVL_CAPTURE_F2	R/W	0h	Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks), the minimum cycles between a calibration command and a dfi_calvl_capture pulse.
15-10	RESERVED	R/W	X
9-0	TDFI_CALVL_CC_F2	R/W	0h	Defines the DFI tCALVL_CC timing parameter (in DFI clocks), the minimum cycles between calibration commands.

2.5.2.424 DDRSS_CTL_425 Register (Offset = 6A4h) [reset = 0h]

DDRSS_CTL_425 is shown in Figure 8-516 and described in Table 8-1040.

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Table 8-1039 DDRSS_CTL_425 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06A4h

Figure 8-516 DDRSS_CTL_425 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_CALVL_RESP
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1040 DDRSS_CTL_425 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_CALVL_RESP	R/W	0h	Defines the DFI tCALVL_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_calvl_req assertion and a dfi_calvl_en assertion.

2.5.2.425 DDRSS_CTL_426 Register (Offset = 6A8h) [reset = 0h]

DDRSS_CTL_426 is shown in Figure 8-517 and described in Table 8-1042.

Return to Summary Table.

Table 8-1041 DDRSS_CTL_426 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06A8h

Figure 8-517 DDRSS_CTL_426 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TDFI_CALVL_MAX
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1042 DDRSS_CTL_426 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	TDFI_CALVL_MAX	R/W	0h	Defines the DFI tCALVL_MAX timing parameter (in DFI clocks), the maximum cycles between a dfi_calvl_en assertion and a valid dfi_calvl_resp.

2.5.2.426 DDRSS_CTL_427 Register (Offset = 6ACh) [reset = X]

DDRSS_CTL_427 is shown in Figure 8-518 and described in Table 8-1044.

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Table 8-1043 DDRSS_CTL_427 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06ACh

Figure 8-518 DDRSS_CTL_427 Register

31	30	29	28	27	26	25	24
RESERVED					TDFI_PHY_WRDATA_F0
R/W-X					R/W-1h

23	22	21	20	19	18	17	16
RESERVED				CALVL_ERROR_STATUS
R/W-X				R-0h

15	14	13	12	11	10	9	8
RESERVED							CALVL_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							CALVL_RESP_MASK
R/W-X							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-1044 DDRSS_CTL_427 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-27	RESERVED	R/W	X
26-24	TDFI_PHY_WRDATA_F0	R/W	1h	Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks), the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal.
23-20	RESERVED	R/W	X
19-16	CALVL_ERROR_STATUS	R	0h	Holds the error associated with the CA training error interrupt. Bit (0) set indicates a TDFI_CALVL_MAX parameter violation, bit (1) set indicates a TDFI_CALVL_RESP parameter violation, and bit (2) set indicates that a CA leveling operation was attempted while memory was in self-refresh mode or self-refresh power-down mode. READ-ONLY
15-9	RESERVED	R/W	X
8	CALVL_EN	R/W	0h	Enable the MC CA training module. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	CALVL_RESP_MASK	R/W	0h	Mask for the dfi_calvl_resp signal during CA training.

2.5.2.427 DDRSS_CTL_428 Register (Offset = 6B0h) [reset = X]

DDRSS_CTL_428 is shown in Figure 8-519 and described in Table 8-1046.

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Table 8-1045 DDRSS_CTL_428 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06B0h

Figure 8-519 DDRSS_CTL_428 Register

31	30	29	28	27	26	25	24
RESERVED	TDFI_WRCSLAT_F0
R/W-X	R/W-0h

23	22	21	20	19	18	17	16
RESERVED	TDFI_RDCSLAT_F0
R/W-X	R/W-0h

15	14	13	12	11	10	9	8
RESERVED					TDFI_PHY_WRDATA_F2
R/W-X					R/W-1h

7	6	5	4	3	2	1	0
RESERVED					TDFI_PHY_WRDATA_F1
R/W-X					R/W-1h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1046 DDRSS_CTL_428 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30-24	TDFI_WRCSLAT_F0	R/W	0h	Defines the DFI tPHY_WRCSLAT timing parameter (in DFI PHY clocks), the maximum cycles between a write command and a dfi_wrdata_cs_n assertion.
23	RESERVED	R/W	X
22-16	TDFI_RDCSLAT_F0	R/W	0h	Defines the DFI tPHY_RDCSLAT timing parameter (in DFI PHY clocks), the maximum cycles between a read command and a dfi_rddata_cs_n assertion.
15-11	RESERVED	R/W	X
10-8	TDFI_PHY_WRDATA_F2	R/W	1h	Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks), the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal.
7-3	RESERVED	R/W	X
2-0	TDFI_PHY_WRDATA_F1	R/W	1h	Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks), the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal.

2.5.2.428 DDRSS_CTL_429 Register (Offset = 6B4h) [reset = X]

DDRSS_CTL_429 is shown in Figure 8-520 and described in Table 8-1048.

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Table 8-1047 DDRSS_CTL_429 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06B4h

Figure 8-520 DDRSS_CTL_429 Register

31	30	29	28	27	26	25	24
RESERVED	TDFI_WRCSLAT_F2
R/W-X	R/W-0h

23	22	21	20	19	18	17	16
RESERVED	TDFI_RDCSLAT_F2
R/W-X	R/W-0h

15	14	13	12	11	10	9	8
RESERVED	TDFI_WRCSLAT_F1
R/W-X	R/W-0h

7	6	5	4	3	2	1	0
RESERVED	TDFI_RDCSLAT_F1
R/W-X	R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1048 DDRSS_CTL_429 Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R/W	X
30-24	TDFI_WRCSLAT_F2	R/W	0h	Defines the DFI tPHY_WRCSLAT timing parameter (in DFI PHY clocks), the maximum cycles between a write command and a dfi_wrdata_cs_n assertion.
23	RESERVED	R/W	X
22-16	TDFI_RDCSLAT_F2	R/W	0h	Defines the DFI tPHY_RDCSLAT timing parameter (in DFI PHY clocks), the maximum cycles between a read command and a dfi_rddata_cs_n assertion.
15	RESERVED	R/W	X
14-8	TDFI_WRCSLAT_F1	R/W	0h	Defines the DFI tPHY_WRCSLAT timing parameter (in DFI PHY clocks), the maximum cycles between a write command and a dfi_wrdata_cs_n assertion.
7	RESERVED	R/W	X
6-0	TDFI_RDCSLAT_F1	R/W	0h	Defines the DFI tPHY_RDCSLAT timing parameter (in DFI PHY clocks), the maximum cycles between a read command and a dfi_rddata_cs_n assertion.

2.5.2.429 DDRSS_CTL_430 Register (Offset = 6B8h) [reset = X]

DDRSS_CTL_430 is shown in Figure 8-521 and described in Table 8-1050.

Return to Summary Table.

Table 8-1049 DDRSS_CTL_430 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06B8h

Figure 8-521 DDRSS_CTL_430 Register

31	30	29	28	27	26	25	24
RESERVED							BL_ON_FLY_ENABLE
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							DISABLE_MEMORY_MASKED_WRITE
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							EN_1T_TIMING
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
TDFI_WRDATA_DELAY
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1050 DDRSS_CTL_430 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	BL_ON_FLY_ENABLE	R/W	0h	Enables the burst length on the fly feature. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	DISABLE_MEMORY_MASKED_WRITE	R/W	0h	Restricts the controller from masked write commands. Set to 1 to not issue these commands. Only used if connected to an LPDDR4 device.
15-9	RESERVED	R/W	X
8	EN_1T_TIMING	R/W	0h	Enable 1T timing in a system supporting both 1T and 2T timing. Set to 1 to enable.
7-0	TDFI_WRDATA_DELAY	R/W	0h	Defines the tWRDATA_DELAY timing parameter (in DFI PHY clocks), the maximum cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.

2.5.2.430 DDRSS_CTL_437 Register (Offset = 6D4h) [reset = X]

DDRSS_CTL_437 is shown in Figure 8-522 and described in Table 8-1052.

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Table 8-1051 DDRSS_CTL_437 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06D4h

Figure 8-522 DDRSS_CTL_437 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GLOBAL_ERROR_INFO								RESERVED				RESERVED
R/W-0h								R/W-X				R/W-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				RESERVED				RESERVED				RESERVED
R/W-X				R/W-2h				R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1052 DDRSS_CTL_437 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	GLOBAL_ERROR_INFO	R/W	0h	Indicates the source of DDR controller safety error interrupts. Write a 1 to a bit to clear the error.
23-20	RESERVED	R/W	X
19-16	RESERVED	R/W	0h	Reserved
15-12	RESERVED	R/W	X
11-8	RESERVED	R/W	2h	Reserved
7-4	RESERVED	R/W	X
3-0	RESERVED	R/W	0h	Reserved

2.5.2.431 DDRSS_CTL_438 Register (Offset = 6D8h) [reset = X]

DDRSS_CTL_438 is shown in Figure 8-523 and described in Table 8-1054.

Return to Summary Table.

Table 8-1053 DDRSS_CTL_438 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06D8h

Figure 8-523 DDRSS_CTL_438 Register

31	30	29	28	27	26	25	24
NWR_F1
R/W-28h

23	22	21	20	19	18	17	16
NWR_F0
R/W-28h

15	14	13	12	11	10	9	8
RESERVED						AXI_PARITY_ERROR_STATUS
R/W-X						R-0h

7	6	5	4	3	2	1	0
GLOBAL_ERROR_MASK
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-1054 DDRSS_CTL_438 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	NWR_F1	R/W	28h	DRAM NWR value in cycles for chip select 2.
23-16	NWR_F0	R/W	28h	DRAM NWR value in cycles for chip select 2.
15-10	RESERVED	R/W	X
9-8	AXI_PARITY_ERROR_STATUS	R	0h	Specifies the source of the GLOBAL_ERROR_INFO bit (3) error. Bit (0) correlates to an overlapping write data parity error and bit (1) correlates to a write data parity error or an AXI command parity error. Value of 1 indicates that violation occurs. Both bits may be set simultaneously. READ-ONLY
7-0	GLOBAL_ERROR_MASK	R/W	0h	Mask for the DDR0_DDRSS_CONTROLLER_GLOBAL_ERROR_FATAL_0 and DDR0_DDRSS_CONTROLLER_GLOBAL_ERROR_NONFATAL_0 signals from the GLOBAL_ERROR_INFO parameter. Set each bit to 1 to mask interrupt from the output signal.

2.5.2.432 DDRSS_CTL_439 Register (Offset = 6DCh) [reset = X]

DDRSS_CTL_439 is shown in Figure 8-524 and described in Table 8-1056.

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Table 8-1055 DDRSS_CTL_439 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06DCh

Figure 8-524 DDRSS_CTL_439 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED			REGPORT_PARAM_PARITY_PROTECTION_STATUS
R/W-X			R-0h

15	14	13	12	11	10	9	8
RESERVED							RESERVED
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
NWR_F2
R/W-28h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-1056 DDRSS_CTL_439 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-21	RESERVED	R/W	X
20-16	REGPORT_PARAM_PARITY_PROTECTION_STATUS	R	0h	Specifies the source of the GLOBAL_ERROR_INFO bit (5) error. Bit (0) correlates to an address parity error, bit (1) correlates to a write data mask parity error, bit (2) correlates to a write data parity error, bit (3) correlates to a read data parity error, and bit (4) correlates to a param register parity error. Value of 1 indicates a violation. READ-ONLY
15-9	RESERVED	R/W	X
8	RESERVED	R/W	0h	Reserved
7-0	NWR_F2	R/W	28h	DRAM NWR value in cycles for chip select 2.

2.5.2.433 DDRSS_CTL_440 Register (Offset = 6E0h) [reset = 0h]

DDRSS_CTL_440 is shown in Figure 8-525 and described in Table 8-1058.

Return to Summary Table.

Table 8-1057 DDRSS_CTL_440 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06E0h

Figure 8-525 DDRSS_CTL_440 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MC_PARITY_INJECTION_BYTE_ENABLE_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1058 DDRSS_CTL_440 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MC_PARITY_INJECTION_BYTE_ENABLE_0	R/W	0h	Enables a parity error injection on the assocated byte. This parameter is a global parameter that affects all MC fault logic. To actually inject an error, the user would need to set this parameter and then set the logic injection enable parameter. Set each bit to 1 to enable the associated byte to have an error injected.

2.5.2.434 DDRSS_CTL_441 Register (Offset = 6E4h) [reset = 0h]

DDRSS_CTL_441 is shown in Figure 8-526 and described in Table 8-1060.

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Table 8-1059 DDRSS_CTL_441 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06E4h

Figure 8-526 DDRSS_CTL_441 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MC_PARITY_INJECTION_BYTE_ENABLE_1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1060 DDRSS_CTL_441 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	MC_PARITY_INJECTION_BYTE_ENABLE_1	R/W	0h	Enables a parity error injection on the assocated byte. This parameter is a global parameter that affects all MC fault logic. To actually inject an error, the user would need to set this parameter and then set the logic injection enable parameter. Set each bit to 1 to enable the associated byte to have an error injected.

2.5.2.435 DDRSS_CTL_442 Register (Offset = 6E8h) [reset = X]

DDRSS_CTL_442 is shown in Figure 8-527 and described in Table 8-1062.

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Table 8-1061 DDRSS_CTL_442 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06E8h

Figure 8-527 DDRSS_CTL_442 Register

31	30	29	28	27	26	25	24
RESERVED							REGPORT_WRITE_PARITY_PROTECTION_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							REGPORT_WRITEMASK_PARITY_PROTECTION_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							REGPORT_ADDR_PARITY_PROTECTION_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							MC_PARITY_ERROR_TYPE
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1062 DDRSS_CTL_442 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	REGPORT_WRITE_PARITY_PROTECTION_EN	R/W	0h	Enables regport write data parity checking from the regport to the param block. Set to 1 to enable.
23-17	RESERVED	R/W	X
16	REGPORT_WRITEMASK_PARITY_PROTECTION_EN	R/W	0h	Enables regport write data mask parity checking from the regport to the param block. Set to 1 to enable.
15-9	RESERVED	R/W	X
8	REGPORT_ADDR_PARITY_PROTECTION_EN	R/W	0h	Enables regport address/command parity checking from the regport to the param block. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	MC_PARITY_ERROR_TYPE	R/W	0h	Defines if the parity error injected is a transient (one-time) or stuck-at (every time) error. Clear to 0 for transient or set to 1 for stuck-at.

2.5.2.436 DDRSS_CTL_443 Register (Offset = 6ECh) [reset = X]

DDRSS_CTL_443 is shown in Figure 8-528 and described in Table 8-1064.

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Table 8-1063 DDRSS_CTL_443 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06ECh

Figure 8-528 DDRSS_CTL_443 Register

31	30	29	28	27	26	25	24
RESERVED							REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN
R/W-X							R/W-0h

23	22	21	20	19	18	17	16
RESERVED							REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							PARAMREG_PARITY_PROTECTION_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							REGPORT_READ_PARITY_PROTECTION_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1064 DDRSS_CTL_443 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R/W	X
24	REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN	R/W	0h	Enables regport write mask data parity error injection from the regport to the param block. Set to 1 to enable. Only the bytes enabled in the MC_PARITY_INJECTION_BYTE_ENABLE parameter will be injected with an error on the next use of this signal/logic. This parameter is only meaningful if the REGPORT_WRITEMASK_PARITY_PROTECTION_EN parameter is also set to 1.
23-17	RESERVED	R/W	X
16	REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN	R/W	0h	Enables regport address/command parity error injection from the regport to the param block. Set to 1 to enable. Only the bytes enabled in the MC_PARITY_INJECTION_BYTE_ENABLE parameter will be injected with an error on the next use of this signal/logic. This parameter is only meaningful if the REGPORT_ADDR_PARITY_PROTECTION_EN parameter is also set to 1.
15-9	RESERVED	R/W	X
8	PARAMREG_PARITY_PROTECTION_EN	R/W	0h	Enables parity checking on the param registers. Set to 1 to enable.
7-1	RESERVED	R/W	X
0	REGPORT_READ_PARITY_PROTECTION_EN	R/W	0h	Enables regport read data parity checking from the param block to the regport. Set to 1 to enable.

2.5.2.437 DDRSS_CTL_444 Register (Offset = 6F0h) [reset = X]

DDRSS_CTL_444 is shown in Figure 8-529 and described in Table 8-1066.

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Table 8-1065 DDRSS_CTL_444 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06F0h

Figure 8-529 DDRSS_CTL_444 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED							PARAMREG_PARITY_PROTECTION_INJECTION_EN
R/W-X							R/W-0h

15	14	13	12	11	10	9	8
RESERVED							REGPORT_READ_PARITY_PROTECTION_INJECTION_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED							REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN
R/W-X							R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1066 DDRSS_CTL_444 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-17	RESERVED	R/W	X
16	PARAMREG_PARITY_PROTECTION_INJECTION_EN	R/W	0h	Enables parity error injection on the param registers. Set to 1 to enable. Only the bytes enabled in the MC_PARITY_INJECTION_BYTE_ENABLE parameter will be injected with an error on the next use of this signal/logic. This parameter is only meaningful if the PARAMREG_PARITY_PROTECTION_EN parameter is also set to 1.
15-9	RESERVED	R/W	X
8	REGPORT_READ_PARITY_PROTECTION_INJECTION_EN	R/W	0h	Enables regport read data parity error injection from the param block to the regport. Set to 1 to enable. Only the bytes enabled in the MC_PARITY_INJECTION_BYTE_ENABLE parameter will be injected with an error on the next use of this signal/logic. This parameter is only meaningful if the REGPORT_READ_PARITY_PROTECTION_EN parameter is also set to 1.
7-1	RESERVED	R/W	X
0	REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN	R/W	0h	Enables regport write data parity error injection from the regport to the param block. Set to 1 to enable. Only the bytes enabled in the MC_PARITY_INJECTION_BYTE_ENABLE parameter will be injected with an error on the next use of this signal/logic. This parameter is only meaningful if the REGPORT_WRITE_PARITY_PROTECTION_EN parameter is also set to 1.

2.5.2.438 DDRSS_CTL_447 Register (Offset = 6FCh) [reset = X]

DDRSS_CTL_447 is shown in Figure 8-530 and described in Table 8-1068.

Return to Summary Table.

Table 8-1067 DDRSS_CTL_447 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 06FCh

Figure 8-530 DDRSS_CTL_447 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED							PORT_TO_CORE_PROTECTION_EN
R/W-X							R/W-0h

7	6	5	4	3	2	1	0
RESERVED					RESERVED
R/W-X					R-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-1068 DDRSS_CTL_447 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-9	RESERVED	R/W	X
8	PORT_TO_CORE_PROTECTION_EN	R/W	0h	Enables parity checking and logic replication protection from the port to the controller core. Set to 1 to enable.
7-3	RESERVED	R/W	X
2-0	RESERVED	R	0h	Reserved

2.5.2.439 DDRSS_CTL_448 Register (Offset = 700h) [reset = 0h]

DDRSS_CTL_448 is shown in Figure 8-531 and described in Table 8-1070.

Return to Summary Table.

Table 8-1069 DDRSS_CTL_448 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0700h

Figure 8-531 DDRSS_CTL_448 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PORT_TO_CORE_PROTECTION_INJECTION_EN_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1070 DDRSS_CTL_448 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PORT_TO_CORE_PROTECTION_INJECTION_EN_0	R/W	0h	Enables parity error injection from the port to the controller core. Set to 1 to enable. Only the bytes enabled in the MC_PARITY_INJECTION_BYTE_ENABLE parameter will be injected with an error on the next use of this signal/logic. This parameter is only meaningful if the PORT_TO_CORE_PROTECTION_EN parameter is also set to 1.

2.5.2.440 DDRSS_CTL_449 Register (Offset = 704h) [reset = 0h]

DDRSS_CTL_449 is shown in Figure 8-532 and described in Table 8-1072.

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Table 8-1071 DDRSS_CTL_449 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0704h

Figure 8-532 DDRSS_CTL_449 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PORT_TO_CORE_PROTECTION_INJECTION_EN_1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1072 DDRSS_CTL_449 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PORT_TO_CORE_PROTECTION_INJECTION_EN_1	R/W	0h	Enables parity error injection from the port to the controller core. Set to 1 to enable. Only the bytes enabled in the MC_PARITY_INJECTION_BYTE_ENABLE parameter will be injected with an error on the next use of this signal/logic. This parameter is only meaningful if the PORT_TO_CORE_PROTECTION_EN parameter is also set to 1.

2.5.2.441 DDRSS_CTL_450 Register (Offset = 708h) [reset = X]

DDRSS_CTL_450 is shown in Figure 8-533 and described in Table 8-1074.

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Table 8-1073 DDRSS_CTL_450 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0708h

Figure 8-533 DDRSS_CTL_450 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED					PORT_TO_CORE_PROTECTION_INJECTION_EN_2
R/W-X					R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1074 DDRSS_CTL_450 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-3	RESERVED	R/W	X
2-0	PORT_TO_CORE_PROTECTION_INJECTION_EN_2	R/W	0h	Enables parity error injection from the port to the controller core. Set to 1 to enable. Only the bytes enabled in the MC_PARITY_INJECTION_BYTE_ENABLE parameter will be injected with an error on the next use of this signal/logic. This parameter is only meaningful if the PORT_TO_CORE_PROTECTION_EN parameter is also set to 1.

2.5.2.442 DDRSS_CTL_455 Register (Offset = 71Ch) [reset = 0h]

DDRSS_CTL_455 is shown in Figure 8-534 and described in Table 8-1076.

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Table 8-1075 DDRSS_CTL_455 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 071Ch

Figure 8-534 DDRSS_CTL_455 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PORT_TO_CORE_LR_ERR_INJ_EN_0
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1076 DDRSS_CTL_455 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PORT_TO_CORE_LR_ERR_INJ_EN_0	R/W	0h	Enables error injection from the port to the controller core. Set to 1 to enable. This parameter is only meaningful if the PORT_TO_CORE_PROTECTION_EN parameter is also set to 1.

2.5.2.443 DDRSS_CTL_456 Register (Offset = 720h) [reset = 0h]

DDRSS_CTL_456 is shown in Figure 8-535 and described in Table 8-1078.

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Table 8-1077 DDRSS_CTL_456 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0720h

Figure 8-535 DDRSS_CTL_456 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PORT_TO_CORE_LR_ERR_INJ_EN_1
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1078 DDRSS_CTL_456 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PORT_TO_CORE_LR_ERR_INJ_EN_1	R/W	0h	Enables error injection from the port to the controller core. Set to 1 to enable. This parameter is only meaningful if the PORT_TO_CORE_PROTECTION_EN parameter is also set to 1.

2.5.2.444 DDRSS_CTL_457 Register (Offset = 724h) [reset = 0h]

DDRSS_CTL_457 is shown in Figure 8-536 and described in Table 8-1080.

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Table 8-1079 DDRSS_CTL_457 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0724h

Figure 8-536 DDRSS_CTL_457 Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PORT_TO_CORE_LR_ERR_INJ_EN_2
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1080 DDRSS_CTL_457 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	PORT_TO_CORE_LR_ERR_INJ_EN_2	R/W	0h	Enables error injection from the port to the controller core. Set to 1 to enable. This parameter is only meaningful if the PORT_TO_CORE_PROTECTION_EN parameter is also set to 1.

2.5.2.445 DDRSS_CTL_458 Register (Offset = 728h) [reset = X]

DDRSS_CTL_458 is shown in Figure 8-537 and described in Table 8-1082.

Return to Summary Table.

Table 8-1081 DDRSS_CTL_458 Instances

Instance	Physical Address
COMPUTE_CLUSTER0_CTL_CFG	0299 0728h

Figure 8-537 DDRSS_CTL_458 Register

31	30	29	28	27	26	25	24
RESERVED
R/W-X

23	22	21	20	19	18	17	16
RESERVED
R/W-X

15	14	13	12	11	10	9	8
RESERVED
R/W-X

7	6	5	4	3	2	1	0
RESERVED				PORT_TO_CORE_LR_ERR_INJ_EN_3
R/W-X				R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-1082 DDRSS_CTL_458 Register Field Descriptions

Bit	Field	Type	Reset	Description
31-4	RESERVED	R/W	X
3-0	PORT_TO_CORE_LR_ERR_INJ_EN_3	R/W	0h	Enables error injection from the port to the controller core. Set to 1 to enable. This parameter is only meaningful if the PORT_TO_CORE_PROTECTION_EN parameter is also set to 1.