SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The Unexpected Response Info Register contains information about the number of Timeout errors that have occurred.
Bits | Field | Type | Reset | Description |
---|---|---|---|---|
31:2 | Reserved | r | 0x0 | Reserved. Read as 0. |
1:0 | unexps | r/wtd | 0x0 |
This field contains information about how many unexpected responses have been received since the last one was serviced. Writing to this register decrements the contents by the value written. For instance, if the value is 2 and a 1 is written, the value will decrement to 1. If this field is non-0 when the interrupt is cleared by writing to the Error Interrupt Enabled Status/Clear Register (Base Address + 0x24) the interrupt will be re-issued. The value saturates at 3, so if there are more than three pending it will be unknown exactly how many have occurred. If the value is saturated at 3 and a value of 3 is written, the value will turn to 0. Read 0 – No pending unexpected response interrupts 1 – One pending unexpected response interrupt 2 – Two pending unexpected response interrupts 3 – Three or more pending unexpected response interrupts |