SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 3-4 through Table 3-6 summarize the integration of MCU_CBASS0 in device MCU domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | ||
MCU_CBASS0 | WKUP_PSC0 | PD0 | LPSC0 | |
MCU_CBASS_FW0 | WKUP_PSC0 | PD0 | LPSC0 |
Clocks | |||
Module Instance | Source Clock Signal | Source | Description |
MCU_CBASS0 | MCU_SYSCLK0/3 | WKUP_PLLCTRL0 | MCU_CBASS0 clocks |
MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | ||
MCU_SYSCLK0/12 | WKUP_PLLCTRL0 | ||
MCU_CBASS_FW0 | MCU_SYSCLK0/3 or MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | Clocks for all MCU_CBASS0 firewalls |
Resets | |||
Module Instance | Source Reset Signal | Source | Description |
MCU_CBASS0 | MOD_G_RST | LPSC0 | MCU_CBASS0 reset |
MCU_CBASS_FW0 | MOD_G_RST | LPSC0 | Reset for all MCU_CBASS0 firewalls |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCU_CBASS0 | MCU_COMMON_ERR_INTR | GIC500_SPI_IN_920 | GIC500 | MCU CBASS null endpoint error interrupt | Level |
WKUP_DMSC0_INTR_IN_37 | WKUP_DMSC0 | ||||
R5FSS0_CORE0_INTR_IN_481 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_481 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_148 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_148 | MCU_R5FSS0_CORE1 | ||||
MCU_FW_COMMON_ERR_INTR | GIC500_SPI_IN_953 | GIC500 | MCU FW CBASS null endpoint error interrupt | Level | |
WKUP_DMSC0_INTR_IN_3 | WKUP_DMSC0 | ||||
R5FSS0_CORE0_INTR_IN_483 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_483 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_150 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_150 | MCU_R5FSS0_CORE1 | ||||
MCU_MTOG0 | MCU_MASTER_SAFETY_GASKET0_TIMED_OUT_0 | MCU_ESM0_LVL_IN_39 | MCU_ESM0 | MCU_MTOG0 timeout interrupt | Level |
MCU_TIMEOUT_64B3 | MCU_TIMEOUT_64B3_TRANS_ERR_LVL_0 | MCU_ESM0_LVL_IN_48 | MCU_ESM0 | MCU_TIMEOUT_64B3 timeout interrupt | Level |
MCU_TIMEOUT_64B2 | MCU_TIMEOUT_64B2_TRANS_ERR_LVL_0 | MCU_ESM0_LVL_IN_76 | MCU_ESM0 | MCU_TIMEOUT_64B2 timeout interrupt | Level |
MCU_TIMEOUT_INFRA0 | MCU_TIMEOUT_INFRA0_SAFEG_TRANS_ERR_LVL_0 | MCU_ESM0_LVL_IN_77 | MCU_ESM0 | MCU_TIMEOUT_INFRA0 timeout interrupt | Level |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
MCU_CBASS0 | - | - | - | - | - |
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.