SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Writing data at the GPMC_NAND_ADDRESS_i location (where i = 0 to 3) places the data as the NAND partial address value on the bus, using a regular asynchronous write access.
Figure 12-2102 shows the NAND address latch cycle.
ALE is shared with the nADV output signal and has an inverted polarity from ADV. The NAND qualifier deals with this. During the asynchronous NAND data access cycle, ALE is kept stable.