SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
To send a CCC message, I3C controller uses Host Command Format.
Following are the only relevant Command Word fields for CCC message:
The payload for CCC commands writing data to the slaves needs to be written to the TX FIFO prior to sending the two Command Words. The payload received by reading CCC commands can be read after receiving the COMP interrupt corresponding to the command. Note that ENTDAA command uses payload of 0, since the data it receives is not stored in RX FIFO; the amount of data depends on the number of slave responding to the command.
When sending a sequence of two identical directed CCC messages to different slaves, the I3C_CMD0_FIFO[29] BCH and I3C_CMD0_FIFO[25] RSBC Command Word fields can be used to send the second message as short CCC. I3C_CMD0_FIFO[29] BCH should be set to 0 for the second CCC message. Instead of sending the broadcast address, waiting for it to be acknowledged and then sending the message code, this will issue restart pattern and immediately transfer the address and payload afterwards. If I3C_CMD0_FIFO[29] BCH is set to 1 the second CCC message is sent with broadcast address and command code in the beginning. In all other CCC message cases the I3C_CMD0_FIFO[29] BCH field is disregarded. Because the short CCC is preceded by restart pattern in order for this to work the I3C_CMD0_FIFO[25] RSBC field for the first command should also be set to 1.
Table 12-334 below summarizes available CCC set along with their payload layout in data FIFOs and Command Word settings.
| CCC(1) | Description | Payload Layout(2) | PL | RNW |
|---|---|---|---|---|
| ENEC_BC (0x00) | Enables slave event driven interrupts | TX FIFO: {28’b0, 1’bHJ, 1’b0, 1’bMR, 1’bINT} | 1 | 0 |
| ENEC_DC (0x80) | (HJ – Hot-Join, MR – Mastership Request IBI, INT – regular IBI) | |||
| DISEC_BC (0x01) | Disables slave event driven interrupts | TX FIFO: {28’b0, 1’bHJ, 1’b0, 1’bMR, 1’bINT} | 1 | 0 |
| DISEC_DC (0x81) | (HJ – Hot-Join, MR – Mastership Request IBI, INT – regular IBI) | |||
| ENTAS0_BC (0x02) | Set activity to State 0 (normal operation) | No payload | 0 | 0 |
| ENTAS0_DC (0x82) | ||||
| RSTDAA_BC (0x06) | Forget current Dynamic Address and wait for new one | No payload | 0 | 0 |
| RSTDAA_DC (0x86) | ||||
| ENTDAA_BC (0x07) | Enter DAA procedure to assign Dynamic Addresses to unassigned devices | See Section 12.1.4.5.3, Initiate DAA Procedure | 0 | 0 |
| SETMWL_BC (0x09) | Set maximum write length of a single private transfer | TX FIFO: {16’b0, LSB, MSB} | 2 | 0 |
| SETMWL_DC (0x89) | (LSB and MSB of 16-bit Max Write Length value) | |||
| SETMRL_BC (0x0A) | Set maximum read length of a single private transfer | TX FIFO: {16’b0, LSB, MSB} | 2 | 0 |
| SETMRL_DC (0x8A) | (LSB and MSB of 16-bit Max Write Length value) | |||
| DEFSLVS_BC (0x08) | Broadcast triples of DA, DCR and SA (or 0) for each slave | No payload | 0 | 0 |
| ENTHDR_BC (0x20) | Switch to HD-DDR mode | No payload | 0 | 0 |
| SETDASA_DC (0x87) | Set Dynamic Address to slave with Static Address | TX FIFO: {24’b0, 7’bDA, 1’bP} | 1 | 0 |
| (DA – new Dynamic Address, P – XNOR of DA bits) | ||||
| SETNEWDA_DC (0x88) | Assign new Dynamic Address | TX FIFO: {24’b0, 7’bDA, 1’bP} | 1 | 0 |
| (DA – new Dynamic Address, P – XNOR of DA bits) | ||||
| GETMWL_DC (0x8B) | Get maximum write length of a single private transfer | RX FIFO: {16’b0, LSB, MSB} | 2 | 1 |
| (LSB and MSB of 16-bit Max Write Length value) | ||||
| GETMRL_DC (0x8C) | Get maximum read length of a single private transfer | RX FIFO: {16’b0, LSB, MSB} | 2 | 1 |
| (LSB and MSB of 16-bit Max Read Length value) | ||||
| GETPID_DC (0x8D) | Get Slave’s Provisional ID value | RX FIFO[n+1]: {16’b0, PID0, PID1} | 6 | 1 |
| RX FIFO[n]: {PID2, PID3, PID4, PID5} | ||||
| GETBCR_DC (0x8E) | Get Device’s Bus Characteristic Register value | RX FIFO: {24’b0, BCR} | 1 | 1 |
| GETDCR_DC (0x8F) | Get Device’s Characteristic Register value | RX FIFO: {24’b0, DCR} | 1 | 1 |
| GETSTATUS_DC (0x90) | Read Device’s operating status | RX FIFO: {16’b0, 2’bAM, 1’bPE, 1’b0, 4’bINT, 8’b0} | ||
| (AM – Activity Mode, PE – Protocol Error, INT – Pending Interrupt number) | ||||
| GETACCMST_DC (0x91) | Get accept mastership | RX FIFO: {24’b0, SlaveAddr} | 1 | 1 |
| GETMXDS_DC (0x94) | Read Maximum SCL Frequency of the slave | RX FIFO: {16’b0, MaxRd, MaxWr} | 1 | 1 |
| (MaxRd – Clock to Data Turnaround Time and Maximum Sustained Read Data Rate, MaxWr – Maximum Sustained Write Data Rate) | ||||
| GETHDRCAP (0x96) | Ask slave for HDR modes it supports (can be sent only if BCR identifies HDR support) | RX FIFO: {24’b0, HDRCAP} | 1 | 1 |
| (HDRCAP – HDR capability modes) |