SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5006 shows the ECAP module control and status register set. All 32-bit registers are aligned on even address boundaries and are organized in little-endian mode.
In APWM mode, writing to the ECAP_CAP1/ECAP_CAP2 active registers also writes the same value to the corresponding shadow registers (ECAP_CAP3/ECAP_CAP4). This emulates immediate mode. Writing to the shadow registers (ECAP_CAP3/ECAP_CAP4) invokes the shadow mode.
Offset | Register Name | Description | Size (×16) |
---|---|---|---|
0h | ECAP_TSCNT | Time-Stamp Counter Register | 2 |
4h | ECAP_CNTPHS | Counter Phase Offset Value Register | 2 |
8h | ECAP_CAP1 | Capture 1 Register | 2 |
Ch | ECAP_CAP2 | Capture 2 Register | 2 |
10h | ECAP_CAP3 | Capture 3 Register | 2 |
14h | ECAP_CAP4 | Capture 4 Register | 2 |
28h | ECAP_ECCTL | Capture Control Register | 2 |
2Ch | ECAP_ECINT_EN_FLG | Capture Interrupt Enable and Flag Register | 2 |
30h | ECAP_ECINT_CLR_FRC | Capture Interrupt Clear and Forcing Register | 2 |
5Ch | ECAP_PID | Revision ID Register | 2 |
For more information on the ECAP registers, see ECAP Registers.