SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This mode is used if the TIMER_TSICR[2] POSTED bit is set to 1 (default value).
This mode uses a posted write scheme to update any internal register (TIMER_TCLR, TIMER_TCRR, TIMER_TLDR, TIMER_TTGR, TIMER_TMAR, TIMER_TPIR, TIMER_TNIR, TIMER_TCVR, TIMER_TOCR, and TIMER_TOWR). Therefore, the write transaction is immediately acknowledged on the configuration interface, although the effective write operation occurs later because of a resynchronization in the timer clock domain. The advantage is that neither the interconnect, nor the device that requested the write transaction is stalled.
For each register, a status bit is provided in the timer write-posted status (TIMER_TWPS) register. In this mode, it is mandatory that software check this status bit before any write access. If a write is attempted to a register with a previous access pending, the previous access is discarded without notice.
The timer module updates the value of the timer counter register synchronously with the interface clock. Consequently, any read access to TIMER_TCRR does not add any resynchronization latency; the current value is always available.
Because the overflow IRQ is generated when the value of TIMER_TCRR reaches 0xFFFF FFFF, and not when it changes its value to the value after overflow, it is necessary to wait a delay of (1 × PS × timer functional clock period) before any read access to TIMER_TCRR to ensure a correct reading of its content.
If TIMER_TTGR register is written during a posted write to TIMER_TCRR, the value to be written to TIMER_TCRR will be discarded.
If a posted write to TIMER_TCVR is started, the user must not write to TIMER_TPIR or TIMER_TNIR before the TIMER_TCVR write is finished, because the value of TIMER_TCVR is re-evaluated, so both the value to be written, and the recalculated value will be discarded.
If a write access is pending for a register, reading from this register does not yield a correct result. Software synchronization must be used to avoid incorrect results.
Functional frequency range: freq(timer clock) < freq(interface clock)/4.