SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
IF: Is FIFO full? | MAILBOX_FIFO_STATUS_y[0] FULL | =0x1 |
Wait until at least one message slot is available | MAILBOX_FIFO_STATUS_y[0] FULL | =0x0 |
ELSE | ||
Write message | MAILBOX_MESSAGE_y[31:0] VALUE | 0x- |
ENDIF |