SPRUIU1 User guide

SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1

8.2.5.1 DDR Subsystem Registers

Table 8-92 lists the DDR subsystem registers. All register offset addresses not listed in Table 8-92 should be considered as reserved locations and the register contents should not be modified.

Table 8-91 DDR Subsystem Instances

Instance	Base Address
COMPUTE_CLUSTER0_SS_CFG	0298 0000h

Table 8-92 DDR Subsystem Registers

Offset	Acronym	Register Name	COMPUTE_CLUSTER0_SS_CFG Physical Address
0h	DDRSS_SS_ID_REV_REG	Subsystem Revision Register	0298 0000h
4h	DDRSS_SS_CTL_REG	Subsystem Control Register	0298 0004h
20h	DDRSS_V2A_CTL_REG	MSMC2DDR Bridge Control Register	0298 0020h
24h	DDRSS_V2A_R1_MAT_REG	MSMC2DDR Bridge Range 1 Match Register	0298 0024h
28h	DDRSS_V2A_R2_MAT_REG	MSMC2DDR Bridge Range 2 Match Register	0298 0028h
2Ch	DDRSS_V2A_R3_MAT_REG	MSMC2DDR Bridge Range 3 Match Register	0298 002Ch
30h	DDRSS_V2A_LPT_DEF_PRI_MAP_REG	MSMC2DDR Bridge LPT Default Priority Mapping Register	0298 0030h
34h	DDRSS_V2A_LPT_R1_PRI_MAP_REG	MSMC2DDR Bridge LPT Range 1 Priority Map Register	0298 0034h
38h	DDRSS_V2A_LPT_R2_PRI_MAP_REG	MSMC2DDR Bridge LPT Range 2 Priority Map Register	0298 0038h
3Ch	DDRSS_V2A_LPT_R3_PRI_MAP_REG	MSMC2DDR Bridge LPT Range 3 Priority Map Register	0298 003Ch
4Ch	DDRSS_V2A_HPT_DEF_PRI_MAP_REG	MSMC2DDR Bridge HPT Default Priority Mapping Register	0298 004Ch
50h	DDRSS_V2A_HPT_R1_PRI_MAP_REG	MSMC2DDR Bridge HPT Range 1 Priority Map Register	0298 0050h
54h	DDRSS_V2A_HPT_R2_PRI_MAP_REG	MSMC2DDR Bridge HPT Range 2 Priority Map Register	0298 0054h
58h	DDRSS_V2A_HPT_R3_PRI_MAP_REG	MSMC2DDR Bridge HPT Range 3 Priority Map Register	0298 0058h
70h	DDRSS_V2A_AERR_LOG1_REG	MSMC2DDR Bridge Address Error Log 1 Register	0298 0070h
74h	DDRSS_V2A_AERR_LOG2_REG	MSMC2DDR Bridge Address Error Log 2 Register	0298 0074h
78h	DDRSS_V2A_OERR_LOG_REG	MSMC2DDR Bridge Opcode Error Log Register	0298 0078h
80h	DDRSS_V2A_1B_ERR_CNT_REG	MSMC2DDR Bridge 1-Bit EDC Error Count Register	0298 0080h
84h	DDRSS_V2A_1B_ERR_LOG1_REG	MSMC2DDR Bridge 1-Bit EDC Error Log 1 Register	0298 0084h
88h	DDRSS_V2A_1B_ERR_LOG2_REG	MSMC2DDR Bridge 1-Bit EDC Error Log 2 Register	0298 0088h
8Ch	DDRSS_V2A_2B_ERR_LOG1_REG	MSMC2DDR Bridge 2-Bit EDC Error Log 1 Register	0298 008Ch
90h	DDRSS_V2A_2B_ERR_LOG2_REG	MSMC2DDR Bridge 2-Bit EDC Error Log 2 Register	0298 0090h
9Ch	DDRSS_V2A_BUS_TO	MSMC2DDR Bridge Bus Timeout Register	0298 009Ch
A0h	DDRSS_V2A_INT_RAW_REG	MSMC2DDR Bridge Interrupt Raw Status Register	0298 00A0h
A4h	DDRSS_V2A_INT_STAT_REG	MSMC2DDR Bridge Interrupt Status Register	0298 00A4h
A8h	DDRSS_V2A_INT_SET_REG	MSMC2DDR Bridge Interrupt Enable Set Register	0298 00A8h
ACh	DDRSS_V2A_INT_CLR_REG	MSMC2DDR Bridge Interrupt Enable Clear Register	0298 00ACh
B0h	DDRSS_V2A_EOI_REG	MSMC2DDR Bridge End of Interrupt Register	0298 00B0h
100h	DDRSS_PERF_CNT_SEL_REG	Performance Counter Select Register	0298 0100h
104h	DDRSS_PERF_CNT1_REG	Performance Counter 1 Register	0298 0104h
108h	DDRSS_PERF_CNT2_REG	Performance Counter 2 Register	0298 0108h
10Ch	DDRSS_PERF_CNT3_REG	Performance Counter 3 Register	0298 010Ch
110h	DDRSS_PERF_CNT4_REG	Performance Counter 4 Register	0298 0110h
120h	DDRSS_ECC_CTRL_REG	ECC Control Register	0298 0120h
124h	DDRSS_ECC_RID_INDX_REG	ECC Cache RouteID Index Register	0298 0124h
128h	DDRSS_ECC_RID_VAL_REG	ECC Cache RouteID Write Value Register	0298 0128h
130h	DDRSS_ECC_R0_STR_ADDR_REG	ECC Range 0 Start Address Register	0298 0130h
134h	DDRSS_ECC_R0_END_ADDR_REG	ECC Range 0 End Address Register	0298 0134h
138h	DDRSS_ECC_R1_STR_ADDR_REG	ECC Range 1 Start Address Register	0298 0138h
13Ch	DDRSS_ECC_R1_END_ADDR_REG	ECC Range 1 End Address Register	0298 013Ch
140h	DDRSS_ECC_R2_STR_ADDR_REG	ECC Range 2 Start Address Register	0298 0140h
144h	DDRSS_ECC_R2_END_ADDR_REG	ECC Range 2 End Address Register	0298 0144h
150h	DDRSS_ECC_1B_ERR_CNT_REG	ECC 1-Bit Error Count Register	0298 0150h
154h	DDRSS_ECC_1B_ERR_THRSH_REG	ECC 1-Bit Error Threshold Register	0298 0154h
158h	DDRSS_ECC_1B_ERR_ADR_LOG_REG	ECC 1-Bit Error Address Log Register	0298 0158h
15Ch	DDRSS_ECC_1B_ERR_MSK_LOG_REG	ECC 1-Bit Error Mask Log Register	0298 015Ch
160h	DDRSS_ECC_2B_ERR_ADR_LOG_REG	ECC 2-Bit Error Address Log Register	0298 0160h
164h	DDRSS_ECC_2B_ERR_MSK_LOG_REG	ECC 2-Bit Error Mask Log Register	0298 0164h
180h	DDRSS_PHY_BIST_CTRL_REG	PHY BIST Control Register	0298 0180h

2.5.1.1 DDRSS_SS_ID_REV_REG Register (Offset = 0h) [reset = 68043100h]

DDRSS_SS_ID_REV_REG is shown in Figure 8-44 and described in Table 8-94.

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The Subsystem ID and Revision Register contains the module ID, major, and minor revisions for the subsystem.

Table 8-93 DDRSS_SS_ID_REV_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0000h

Figure 8-44 DDRSS_SS_ID_REV_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MOD_ID
R-6804h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTL_VER					MAJ_REV			CUSTOM		MIN_REV
R-6h					R-1h			R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-94 DDRSS_SS_ID_REV_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	MOD_ID	R	6804h	Module ID
15-11	RTL_VER	R	6h	RTL version
10-8	MAJ_REV	R	1h	Major revision
7-6	CUSTOM	R	0h	Custom
5-0	MIN_REV	R	0h	Minor revision

2.5.1.2 DDRSS_SS_CTL_REG Register (Offset = 4h) [reset = X]

DDRSS_SS_CTL_REG is shown in Figure 8-45 and described in Table 8-96.

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The Subsystem Control Register contains fields for control functions required for submodules in the subsystem.

Table 8-95 DDRSS_SS_CTL_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0004h

Figure 8-45 DDRSS_SS_CTL_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED							PHY_PLL_BYPASS
R-0h							R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-96 DDRSS_SS_CTL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-1	RESERVED	R	X	Reserved
0	PHY_PLL_BYPASS	R/W	0h	DDR PHY De-Skew PLL bypass. Write 1 to bypass PLL.

2.5.1.3 DDRSS_V2A_CTL_REG Register (Offset = 20h) [reset = X]

DDRSS_V2A_CTL_REG is shown in Figure 8-46 and described in Table 8-98.

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The MSMC2DDR Bridge Control register contains control functions required for the MSMC2DDR Bridge submodule.

Table 8-97 DDRSS_V2A_CTL_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0020h

Figure 8-46 DDRSS_V2A_CTL_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED		WR_LO_BLK_THR					CRIT_THRESH
R-0h		R/W-18h					R/W-18h

15	14	13	12	11	10	9	8
CRIT_THRESH				RESERVED	SDRAM_3QT	SDRAM_IDX
R/W-18h				R-0h	R/W-0h	R/W-13h

7	6	5	4	3	2	1	0
SDRAM_IDX			REGION_IDX
R/W-13h			R/W-13h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-98 DDRSS_V2A_CTL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-22	RESERVED	R	X	Reserved
21-17	WR_LO_BLK_THR	R/W	18h	Write data threshold in 64 byte quantas. The MSMC2DDR bridge will block all Low Priority Thread writes to DDR when the total number of write data bytes sent to the DDR controller is greater than this value. The reset value of this field is optimal however, it can be changed for better traffic shaping.
16-12	CRIT_THRESH	R/W	18h	Critical threshold. The MSMC2DDR bridge will block all Low Priority Thread traffic to DDR when the total number of commands sent to the DDR controller is greater than this value. The reset value of this field is optimal however, it can be changed for better traffic shaping.
11	RESERVED	R	X	Reserved
10	SDRAM_3QT	R/W	0h	Setting this field to a 1 will modify SDRAM Index to be 3/4 its programmed value to support 3, 6, 12 and 24 GB sizes.
9-5	SDRAM_IDX	R/W	13h	SDRAM Index = log2(connected SDRAM size) - 16. The sdram_idx describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Max size supported is 32GB. A programmed value greater than 0x13 will result in this field being reset to 0x13.
4-0	REGION_IDX	R/W	13h	Region Index = log2(CBA region size) - 16. The region_idx describes the number of address bits minus 16 that are used to determine the mask used to detect memory rollover and prevent aliasing and false coherency issues. Max size supported is 32GB. A programmed value greater than 0x13 will result in this field being reset to 0x13.

2.5.1.4 DDRSS_V2A_R1_MAT_REG Register (Offset = 24h) [reset = 0h]

DDRSS_V2A_R1_MAT_REG is shown in Figure 8-47 and described in Table 8-100.

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The Range 1 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 1 Match Register uses the associated Range 1 Priority Map Register. The highest Range Match Register will take priority and will be used in case of multiple range matches.

Table 8-99 DDRSS_V2A_R1_MAT_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0024h

Figure 8-47 DDRSS_V2A_R1_MAT_REG Register

31	30	29	28	27	26	25	24
RANGE1_RANGEEN_A	RANGE1_MASK_A			RANGE1_ROUTEID_A
R/W-0h	R/W-0h			R/W-0h

23	22	21	20	19	18	17	16
RANGE1_ROUTEID_A
R/W-0h

15	14	13	12	11	10	9	8
RANGE1_RANGEEN_B	RANGE1_MASK_B			RANGE1_ROUTEID_B
R/W-0h	R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
RANGE1_ROUTEID_B
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-100 DDRSS_V2A_R1_MAT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RANGE1_RANGEEN_A	R/W	0h	The range1_rangeen_a enables the RouteID AND'd with range1_mask_a to match the range1_routeid_a
30-28	RANGE1_MASK_A	R/W	0h	The range1_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a
27-16	RANGE1_ROUTEID_A	R/W	0h	The range1_routeid_a is the value that is compared to the RouteID arriving on the command interface
15	RANGE1_RANGEEN_B	R/W	0h	The range1_rangeen_b enables the RouteID AND'd with range1_mask_b to match the range1_routeid_b
14-12	RANGE1_MASK_B	R/W	0h	The range1_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b
11-0	RANGE1_ROUTEID_B	R/W	0h	The range1_routeid_b is the value that is compared to the RouteID arriving on the command interface

2.5.1.5 DDRSS_V2A_R2_MAT_REG Register (Offset = 28h) [reset = 0h]

DDRSS_V2A_R2_MAT_REG is shown in Figure 8-48 and described in Table 8-102.

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The Range 2 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 2 Match Register uses the associated Range 2 Priority Map Register. The highest Range Match Register will take priority and will be used in case of multiple range matches.

Table 8-101 DDRSS_V2A_R2_MAT_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0028h

Figure 8-48 DDRSS_V2A_R2_MAT_REG Register

31	30	29	28	27	26	25	24
RANGE2_RANGEEN_A	RANGE2_MASK_A			RANGE2_ROUTEID_A
R/W-0h	R/W-0h			R/W-0h

23	22	21	20	19	18	17	16
RANGE2_ROUTEID_A
R/W-0h

15	14	13	12	11	10	9	8
RANGE2_RANGEEN_B	RANGE2_MASK_B			RANGE2_ROUTEID_B
R/W-0h	R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
RANGE2_ROUTEID_B
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-102 DDRSS_V2A_R2_MAT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RANGE2_RANGEEN_A	R/W	0h	The range2_rangeen_a enables the RouteID AND'd with range2_mask_a to match the range2_routeid_a
30-28	RANGE2_MASK_A	R/W	0h	The range2_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a
27-16	RANGE2_ROUTEID_A	R/W	0h	The range2_routeid_a is the value that is compared to the RouteID arriving on the command interface
15	RANGE2_RANGEEN_B	R/W	0h	The range2_rangeen_b enables the RouteID AND'd with range2_mask_b to match the range2_routeid_b
14-12	RANGE2_MASK_B	R/W	0h	The range2_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b
11-0	RANGE2_ROUTEID_B	R/W	0h	The range2_routeid_b is the value that is compared to the RouteID arriving on the command interface

2.5.1.6 DDRSS_V2A_R3_MAT_REG Register (Offset = 2Ch) [reset = 0h]

DDRSS_V2A_R3_MAT_REG is shown in Figure 8-49 and described in Table 8-104.

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The Range 3 Match Register allows a single master to a range of masters to change their priority mapping. This allows selective masters to be increased or decreased in effective priority. Range 3 Match Register uses the associated Range 3 Priority Map Register. The highest Range Match Register will take priority and will be used in case of multiple range matches.

Table 8-103 DDRSS_V2A_R3_MAT_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 002Ch

Figure 8-49 DDRSS_V2A_R3_MAT_REG Register

31	30	29	28	27	26	25	24
RANGE3_RANGEEN_A	RANGE3_MASK_A			RANGE3_ROUTEID_A
R/W-0h	R/W-0h			R/W-0h

23	22	21	20	19	18	17	16
RANGE3_ROUTEID_A
R/W-0h

15	14	13	12	11	10	9	8
RANGE3_RANGEEN_B	RANGE3_MASK_B			RANGE3_ROUTEID_B
R/W-0h	R/W-0h			R/W-0h

7	6	5	4	3	2	1	0
RANGE3_ROUTEID_B
R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 8-104 DDRSS_V2A_R3_MAT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RANGE3_RANGEEN_A	R/W	0h	The range3_rangeen_a enables the RouteID AND'd with range3_mask_a to match the range3_routeid_a
30-28	RANGE3_MASK_A	R/W	0h	The range3_mask_a allows a number of least significant bits to be ignored prior to the match of the routeid_a
27-16	RANGE3_ROUTEID_A	R/W	0h	The range3_routeid_a is the value that is compared to the RouteID arriving on the command interface
15	RANGE3_RANGEEN_B	R/W	0h	The range3_rangeen_b enables the RouteID AND'd with range3_mask_b to match the range3_routeid_b
14-12	RANGE3_MASK_B	R/W	0h	The range3_mask_b allows a number of least significant bits to be ignored prior to the match of the routeid_b
11-0	RANGE3_ROUTEID_B	R/W	0h	The range3_routeid_b is the value that is compared to the RouteID arriving on the command interface

2.5.1.7 DDRSS_V2A_LPT_DEF_PRI_MAP_REG Register (Offset = 30h) [reset = X]

DDRSS_V2A_LPT_DEF_PRI_MAP_REG is shown in Figure 8-50 and described in Table 8-106.

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The LPT Default Priority Mapping Register is the default map for the inbound VBUSM.C priority on the Low Priority Thread to AXI priority.

Table 8-105 DDRSS_V2A_LPT_DEF_PRI_MAP_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0030h

Figure 8-50 DDRSS_V2A_LPT_DEF_PRI_MAP_REG Register

31	30	29	28	27	26	25	24
RESERVED	LPT_PRIMAP0			RESERVED	LPT_PRIMAP1
R-0h	R/W-2h			R-0h	R/W-3h

23	22	21	20	19	18	17	16
RESERVED	LPT_PRIMAP2			RESERVED	LPT_PRIMAP3
R-0h	R/W-4h			R-0h	R/W-5h

15	14	13	12	11	10	9	8
RESERVED	LPT_PRIMAP4			RESERVED	LPT_PRIMAP5
R-0h	R/W-6h			R-0h	R/W-6h

7	6	5	4	3	2	1	0
RESERVED	LPT_PRIMAP6			RESERVED	LPT_PRIMAP7
R-0h	R/W-7h			R-0h	R/W-7h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-106 DDRSS_V2A_LPT_DEF_PRI_MAP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	X	Reserved
30-28	LPT_PRIMAP0	R/W	2h	The field contains AXI priority value for VBUSM.C priority 0. 0=highest priority. 7=lowest priority
27	RESERVED	R	X	Reserved
26-24	LPT_PRIMAP1	R/W	3h	The field contains AXI priority value for VBUSM.C priority 1. 0=highest priority. 7=lowest priority
23	RESERVED	R	X	Reserved
22-20	LPT_PRIMAP2	R/W	4h	The field contains AXI priority value for VBUSM.C priority 2. 0=highest priority. 7=lowest priority
19	RESERVED	R	X	Reserved
18-16	LPT_PRIMAP3	R/W	5h	The field contains AXI priority value for VBUSM.C priority 3. 0=highest priority. 7=lowest priority
15	RESERVED	R	X	Reserved
14-12	LPT_PRIMAP4	R/W	6h	The field contains AXI priority value for VBUSM.C priority 4. 0=highest priority. 7=lowest priority
11	RESERVED	R	X	Reserved
10-8	LPT_PRIMAP5	R/W	6h	The field contains AXI priority value for VBUSM.C priority 5. 0=highest priority. 7=lowest priority
7	RESERVED	R	X	Reserved
6-4	LPT_PRIMAP6	R/W	7h	The field contains AXI priority value for VBUSM.C priority 6. 0=highest priority. 7=lowest priority
3	RESERVED	R	X	Reserved
2-0	LPT_PRIMAP7	R/W	7h	The field contains AXI priority value for VBUSM.C priority 7. 0=highest priority. 7=lowest priority

2.5.1.8 DDRSS_V2A_LPT_R1_PRI_MAP_REG Register (Offset = 34h) [reset = X]

DDRSS_V2A_LPT_R1_PRI_MAP_REG is shown in Figure 8-51 and described in Table 8-108.

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The LPT Range 1 Priority Mapping Register is used to map the inbound VBUSM.C priority on the Low Priority Thread to AXI priority when a RouteID match 1 occurs. This allows the priority level to be changed from the LPT Default Priority Mapping value.

Table 8-107 DDRSS_V2A_LPT_R1_PRI_MAP_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0034h

Figure 8-51 DDRSS_V2A_LPT_R1_PRI_MAP_REG Register

31	30	29	28	27	26	25	24
RESERVED	LPT_RANGE1_PRIMAP0			RESERVED	LPT_RANGE1_PRIMAP1
R-0h	R/W-2h			R-0h	R/W-3h

23	22	21	20	19	18	17	16
RESERVED	LPT_RANGE1_PRIMAP2			RESERVED	LPT_RANGE1_PRIMAP3
R-0h	R/W-4h			R-0h	R/W-5h

15	14	13	12	11	10	9	8
RESERVED	LPT_RANGE1_PRIMAP4			RESERVED	LPT_RANGE1_PRIMAP5
R-0h	R/W-6h			R-0h	R/W-6h

7	6	5	4	3	2	1	0
RESERVED	LPT_RANGE1_PRIMAP6			RESERVED	LPT_RANGE1_PRIMAP7
R-0h	R/W-7h			R-0h	R/W-7h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-108 DDRSS_V2A_LPT_R1_PRI_MAP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	X	Reserved
30-28	LPT_RANGE1_PRIMAP0	R/W	2h	The field contains AXI priority value for VBUSM.C priority 0 for range match 1. 0=highest priority. 7=lowest priority
27	RESERVED	R	X	Reserved
26-24	LPT_RANGE1_PRIMAP1	R/W	3h	The field contains AXI priority value for VBUSM.C priority 1 for range match 1. 0=highest priority. 7=lowest priority
23	RESERVED	R	X	Reserved
22-20	LPT_RANGE1_PRIMAP2	R/W	4h	The field contains AXI priority value for VBUSM.C priority 2 for range match 1. 0=highest priority. 7=lowest priority
19	RESERVED	R	X	Reserved
18-16	LPT_RANGE1_PRIMAP3	R/W	5h	The field contains AXI priority value for VBUSM.C priority 3 for range match 1. 0=highest priority. 7=lowest priority
15	RESERVED	R	X	Reserved
14-12	LPT_RANGE1_PRIMAP4	R/W	6h	The field contains AXI priority value for VBUSM.C priority 4 for range match 1. 0=highest priority. 7=lowest priority
11	RESERVED	R	X	Reserved
10-8	LPT_RANGE1_PRIMAP5	R/W	6h	The field contains AXI priority value for VBUSM.C priority 5 for range match 1. 0=highest priority. 7=lowest priority
7	RESERVED	R	X	Reserved
6-4	LPT_RANGE1_PRIMAP6	R/W	7h	The field contains AXI priority value for VBUSM.C priority 6 for range match 1. 0=highest priority. 7=lowest priority
3	RESERVED	R	X	Reserved
2-0	LPT_RANGE1_PRIMAP7	R/W	7h	The field contains AXI priority value for VBUSM.C priority 7 for range match 1. 0=highest priority. 7=lowest priority

2.5.1.9 DDRSS_V2A_LPT_R2_PRI_MAP_REG Register (Offset = 38h) [reset = X]

DDRSS_V2A_LPT_R2_PRI_MAP_REG is shown in Figure 8-52 and described in Table 8-110.

Return to the Summary Table.

The LPT Range 2 Priority Mapping Register is used to map the inbound VBUSM.C priority on the Low Priority Thread to AXI priority when a RouteID match 2 occurs. This allows the priority level to be changed from the LPT Default Priority Mapping value.

Table 8-109 DDRSS_V2A_LPT_R2_PRI_MAP_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0038h

Figure 8-52 DDRSS_V2A_LPT_R2_PRI_MAP_REG Register

31	30	29	28	27	26	25	24
RESERVED	LPT_RANGE2_PRIMAP0			RESERVED	LPT_RANGE2_PRIMAP1
R-0h	R/W-2h			R-0h	R/W-3h

23	22	21	20	19	18	17	16
RESERVED	LPT_RANGE2_PRIMAP2			RESERVED	LPT_RANGE2_PRIMAP3
R-0h	R/W-4h			R-0h	R/W-5h

15	14	13	12	11	10	9	8
RESERVED	LPT_RANGE2_PRIMAP4			RESERVED	LPT_RANGE2_PRIMAP5
R-0h	R/W-6h			R-0h	R/W-6h

7	6	5	4	3	2	1	0
RESERVED	LPT_RANGE2_PRIMAP6			RESERVED	LPT_RANGE2_PRIMAP7
R-0h	R/W-7h			R-0h	R/W-7h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-110 DDRSS_V2A_LPT_R2_PRI_MAP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	X	Reserved
30-28	LPT_RANGE2_PRIMAP0	R/W	2h	The field contains AXI priority value for VBUSM.C priority 0 for range match 2. 0=highest priority. 7=lowest priority
27	RESERVED	R	X	Reserved
26-24	LPT_RANGE2_PRIMAP1	R/W	3h	The field contains AXI priority value for VBUSM.C priority 1 for range match 2. 0=highest priority. 7=lowest priority
23	RESERVED	R	X	Reserved
22-20	LPT_RANGE2_PRIMAP2	R/W	4h	The field contains AXI priority value for VBUSM.C priority 2 for range match 2. 0=highest priority. 7=lowest priority
19	RESERVED	R	X	Reserved
18-16	LPT_RANGE2_PRIMAP3	R/W	5h	The field contains AXI priority value for VBUSM.C priority 3 for range match 2. 0=highest priority. 7=lowest priority
15	RESERVED	R	X	Reserved
14-12	LPT_RANGE2_PRIMAP4	R/W	6h	The field contains AXI priority value for VBUSM.C priority 4 for range match 2. 0=highest priority. 7=lowest priority
11	RESERVED	R	X	Reserved
10-8	LPT_RANGE2_PRIMAP5	R/W	6h	The field contains AXI priority value for VBUSM.C priority 5 for range match 2. 0=highest priority. 7=lowest priority
7	RESERVED	R	X	Reserved
6-4	LPT_RANGE2_PRIMAP6	R/W	7h	The field contains AXI priority value for VBUSM.C priority 6 for range match 2. 0=highest priority. 7=lowest priority
3	RESERVED	R	X	Reserved
2-0	LPT_RANGE2_PRIMAP7	R/W	7h	The field contains AXI priority value for VBUSM.C priority 7 for range match 2. 0=highest priority. 7=lowest priority

2.5.1.10 DDRSS_V2A_LPT_R3_PRI_MAP_REG Register (Offset = 3Ch) [reset = X]

DDRSS_V2A_LPT_R3_PRI_MAP_REG is shown in Figure 8-53 and described in Table 8-112.

Return to the Summary Table.

The LPT Range 3 Priority Mapping Register is used to map the inbound VBUSM.C priority on the Low Priority Thread to AXI priority when a RouteID match 3 occurs. This allows the priority level to be changed from the LPT Default Priority Mapping value.

Table 8-111 DDRSS_V2A_LPT_R3_PRI_MAP_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 003Ch

Figure 8-53 DDRSS_V2A_LPT_R3_PRI_MAP_REG Register

31	30	29	28	27	26	25	24
RESERVED	LPT_RANGE3_PRIMAP0			RESERVED	LPT_RANGE3_PRIMAP1
R-0h	R/W-2h			R-0h	R/W-3h

23	22	21	20	19	18	17	16
RESERVED	LPT_RANGE3_PRIMAP2			RESERVED	LPT_RANGE3_PRIMAP3
R-0h	R/W-4h			R-0h	R/W-5h

15	14	13	12	11	10	9	8
RESERVED	LPT_RANGE3_PRIMAP4			RESERVED	LPT_RANGE3_PRIMAP5
R-0h	R/W-6h			R-0h	R/W-6h

7	6	5	4	3	2	1	0
RESERVED	LPT_RANGE3_PRIMAP6			RESERVED	LPT_RANGE3_PRIMAP7
R-0h	R/W-7h			R-0h	R/W-7h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-112 DDRSS_V2A_LPT_R3_PRI_MAP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	X	Reserved
30-28	LPT_RANGE3_PRIMAP0	R/W	2h	The field contains AXI priority value for VBUSM.C priority 0 for range match 3. 0=highest priority. 7=lowest priority
27	RESERVED	R	X	Reserved
26-24	LPT_RANGE3_PRIMAP1	R/W	3h	The field contains AXI priority value for VBUSM.C priority 1 for range match 3. 0=highest priority. 7=lowest priority
23	RESERVED	R	X	Reserved
22-20	LPT_RANGE3_PRIMAP2	R/W	4h	The field contains AXI priority value for VBUSM.C priority 2 for range match 3. 0=highest priority. 7=lowest priority
19	RESERVED	R	X	Reserved
18-16	LPT_RANGE3_PRIMAP3	R/W	5h	The field contains AXI priority value for VBUSM.C priority 3 for range match 3. 0=highest priority. 7=lowest priority
15	RESERVED	R	X	Reserved
14-12	LPT_RANGE3_PRIMAP4	R/W	6h	The field contains AXI priority value for VBUSM.C priority 4 for range match 3. 0=highest priority. 7=lowest priority
11	RESERVED	R	X	Reserved
10-8	LPT_RANGE3_PRIMAP5	R/W	6h	The field contains AXI priority value for VBUSM.C priority 5 for range match 3. 0=highest priority. 7=lowest priority
7	RESERVED	R	X	Reserved
6-4	LPT_RANGE3_PRIMAP6	R/W	7h	The field contains AXI priority value for VBUSM.C priority 6 for range match 3. 0=highest priority. 7=lowest priority
3	RESERVED	R	X	Reserved
2-0	LPT_RANGE3_PRIMAP7	R/W	7h	The field contains AXI priority value for VBUSM.C priority 7 for range match 3. 0=highest priority. 7=lowest priority

2.5.1.11 DDRSS_V2A_HPT_DEF_PRI_MAP_REG Register (Offset = 4Ch) [reset = X]

DDRSS_V2A_HPT_DEF_PRI_MAP_REG is shown in Figure 8-54 and described in Table 8-114.

Return to the Summary Table.

The HPT Default Priority Mapping Register is the default map for the inbound VBUSM.C priority on the High Priority Thread to the AXI priority.

Table 8-113 DDRSS_V2A_HPT_DEF_PRI_MAP_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 004Ch

Figure 8-54 DDRSS_V2A_HPT_DEF_PRI_MAP_REG Register

31	30	29	28	27	26	25	24
RESERVED	HPT_PRIMAP0			RESERVED	HPT_PRIMAP1
R-0h	R/W-0h			R-0h	R/W-0h

23	22	21	20	19	18	17	16
RESERVED	HPT_PRIMAP2			RESERVED	HPT_PRIMAP3
R-0h	R/W-1h			R-0h	R/W-1h

15	14	13	12	11	10	9	8
RESERVED	HPT_PRIMAP4			RESERVED	HPT_PRIMAP5
R-0h	R/W-2h			R-0h	R/W-3h

7	6	5	4	3	2	1	0
RESERVED	HPT_PRIMAP6			RESERVED	HPT_PRIMAP7
R-0h	R/W-4h			R-0h	R/W-5h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-114 DDRSS_V2A_HPT_DEF_PRI_MAP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	X	Reserved
30-28	HPT_PRIMAP0	R/W	0h	The field contains AXI priority value for VBUSM.C priority 0. 0=highest priority. 7=lowest priority
27	RESERVED	R	X	Reserved
26-24	HPT_PRIMAP1	R/W	0h	The field contains AXI priority value for VBUSM.C priority 1. 0=highest priority. 7=lowest priority
23	RESERVED	R	X	Reserved
22-20	HPT_PRIMAP2	R/W	1h	The field contains AXI priority value for VBUSM.C priority 2. 0=highest priority. 7=lowest priority
19	RESERVED	R	X	Reserved
18-16	HPT_PRIMAP3	R/W	1h	The field contains AXI priority value for VBUSM.C priority 3. 0=highest priority. 7=lowest priority
15	RESERVED	R	X	Reserved
14-12	HPT_PRIMAP4	R/W	2h	The field contains AXI priority value for VBUSM.C priority 4. 0=highest priority. 7=lowest priority
11	RESERVED	R	X	Reserved
10-8	HPT_PRIMAP5	R/W	3h	The field contains AXI priority value for VBUSM.C priority 5. 0=highest priority. 7=lowest priority
7	RESERVED	R	X	Reserved
6-4	HPT_PRIMAP6	R/W	4h	The field contains AXI priority value for VBUSM.C priority 6. 0=highest priority. 7=lowest priority
3	RESERVED	R	X	Reserved
2-0	HPT_PRIMAP7	R/W	5h	The field contains AXI priority value for VBUSM.C priority 7. 0=highest priority. 7=lowest priority

2.5.1.12 DDRSS_V2A_HPT_R1_PRI_MAP_REG Register (Offset = 50h) [reset = X]

DDRSS_V2A_HPT_R1_PRI_MAP_REG is shown in Figure 8-55 and described in Table 8-116.

Return to the Summary Table.

The HPT Range 1 Priority Mapping Register is used to map the inbound VBUSM.C priority on the High Priority Thread to AXI priority when a RouteID match 1 occurs. This allows the priority level to be changed from the HPT Default Priority Mapping value.

Table 8-115 DDRSS_V2A_HPT_R1_PRI_MAP_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0050h

Figure 8-55 DDRSS_V2A_HPT_R1_PRI_MAP_REG Register

31	30	29	28	27	26	25	24
RESERVED	HPT_RANGE1_PRIMAP0			RESERVED	HPT_RANGE1_PRIMAP1
R-0h	R/W-0h			R-0h	R/W-0h

23	22	21	20	19	18	17	16
RESERVED	HPT_RANGE1_PRIMAP2			RESERVED	HPT_RANGE1_PRIMAP3
R-0h	R/W-1h			R-0h	R/W-1h

15	14	13	12	11	10	9	8
RESERVED	HPT_RANGE1_PRIMAP4			RESERVED	HPT_RANGE1_PRIMAP5
R-0h	R/W-2h			R-0h	R/W-3h

7	6	5	4	3	2	1	0
RESERVED	HPT_RANGE1_PRIMAP6			RESERVED	HPT_RANGE1_PRIMAP7
R-0h	R/W-4h			R-0h	R/W-5h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-116 DDRSS_V2A_HPT_R1_PRI_MAP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	X	Reserved
30-28	HPT_RANGE1_PRIMAP0	R/W	0h	The field contains AXI priority value for VBUSM.C priority 0 for range match 1. 0=highest priority. 7=lowest priority
27	RESERVED	R	X	Reserved
26-24	HPT_RANGE1_PRIMAP1	R/W	0h	The field contains AXI priority value for VBUSM.C priority 1 for range match 1. 0=highest priority. 7=lowest priority
23	RESERVED	R	X	Reserved
22-20	HPT_RANGE1_PRIMAP2	R/W	1h	The field contains AXI priority value for VBUSM.C priority 2 for range match 1. 0=highest priority. 7=lowest priority
19	RESERVED	R	X	Reserved
18-16	HPT_RANGE1_PRIMAP3	R/W	1h	The field contains AXI priority value for VBUSM.C priority 3 for range match 1. 0=highest priority. 7=lowest priority
15	RESERVED	R	X	Reserved
14-12	HPT_RANGE1_PRIMAP4	R/W	2h	The field contains AXI priority value for VBUSM.C priority 4 for range match 1. 0=highest priority. 7=lowest priority
11	RESERVED	R	X	Reserved
10-8	HPT_RANGE1_PRIMAP5	R/W	3h	The field contains AXI priority value for VBUSM.C priority 5 for range match 1. 0=highest priority. 7=lowest priority
7	RESERVED	R	X	Reserved
6-4	HPT_RANGE1_PRIMAP6	R/W	4h	The field contains AXI priority value for VBUSM.C priority 6 for range match 1. 0=highest priority. 7=lowest priority
3	RESERVED	R	X	Reserved
2-0	HPT_RANGE1_PRIMAP7	R/W	5h	The field contains AXI priority value for VBUSM.C priority 7 for range match 1. 0=highest priority. 7=lowest priority

2.5.1.13 DDRSS_V2A_HPT_R2_PRI_MAP_REG Register (Offset = 54h) [reset = X]

DDRSS_V2A_HPT_R2_PRI_MAP_REG is shown in Figure 8-56 and described in Table 8-118.

Return to the Summary Table.

The HPT Range 2 Priority Mapping Register is used to map the inbound VBUSM.C priority on the High Priority Thread to AXI priority when a RouteID match 2 occurs. This allows the priority level to be changed from the HPT Default Priority Mapping value.

Table 8-117 DDRSS_V2A_HPT_R2_PRI_MAP_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0054h

Figure 8-56 DDRSS_V2A_HPT_R2_PRI_MAP_REG Register

31	30	29	28	27	26	25	24
RESERVED	HPT_RANGE2_PRIMAP0			RESERVED	HPT_RANGE2_PRIMAP1
R-0h	R/W-0h			R-0h	R/W-0h

23	22	21	20	19	18	17	16
RESERVED	HPT_RANGE2_PRIMAP2			RESERVED	HPT_RANGE2_PRIMAP3
R-0h	R/W-1h			R-0h	R/W-1h

15	14	13	12	11	10	9	8
RESERVED	HPT_RANGE2_PRIMAP4			RESERVED	HPT_RANGE2_PRIMAP5
R-0h	R/W-2h			R-0h	R/W-3h

7	6	5	4	3	2	1	0
RESERVED	HPT_RANGE2_PRIMAP6			RESERVED	HPT_RANGE2_PRIMAP7
R-0h	R/W-4h			R-0h	R/W-5h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-118 DDRSS_V2A_HPT_R2_PRI_MAP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	X	Reserved
30-28	HPT_RANGE2_PRIMAP0	R/W	0h	The field contains AXI priority value for VBUSM.C priority 0 for range match 2. 0=highest priority. 7=lowest priority
27	RESERVED	R	X	Reserved
26-24	HPT_RANGE2_PRIMAP1	R/W	0h	The field contains AXI priority value for VBUSM.C priority 1 for range match 2. 0=highest priority. 7=lowest priority
23	RESERVED	R	X	Reserved
22-20	HPT_RANGE2_PRIMAP2	R/W	1h	The field contains AXI priority value for VBUSM.C priority 2 for range match 2. 0=highest priority. 7=lowest priority
19	RESERVED	R	X	Reserved
18-16	HPT_RANGE2_PRIMAP3	R/W	1h	The field contains AXI priority value for VBUSM.C priority 3 for range match 2. 0=highest priority. 7=lowest priority
15	RESERVED	R	X	Reserved
14-12	HPT_RANGE2_PRIMAP4	R/W	2h	The field contains AXI priority value for VBUSM.C priority 4 for range match 2. 0=highest priority. 7=lowest priority
11	RESERVED	R	X	Reserved
10-8	HPT_RANGE2_PRIMAP5	R/W	3h	The field contains AXI priority value for VBUSM.C priority 5 for range match 2. 0=highest priority. 7=lowest priority
7	RESERVED	R	X	Reserved
6-4	HPT_RANGE2_PRIMAP6	R/W	4h	The field contains AXI priority value for VBUSM.C priority 6 for range match 2. 0=highest priority. 7=lowest priority
3	RESERVED	R	X	Reserved
2-0	HPT_RANGE2_PRIMAP7	R/W	5h	The field contains AXI priority value for VBUSM.C priority 7 for range match 2. 0=highest priority. 7=lowest priority

2.5.1.14 DDRSS_V2A_HPT_R3_PRI_MAP_REG Register (Offset = 58h) [reset = X]

DDRSS_V2A_HPT_R3_PRI_MAP_REG is shown in Figure 8-57 and described in Table 8-120.

Return to the Summary Table.

The HPT Range 3 Priority Mapping Register is used to map the inbound VBUSM.C priority on the High Priority Thread to AXI priority when a RouteID match 3 occurs. This allows the priority level to be changed from the HPT Default Priority Mapping value.

Table 8-119 DDRSS_V2A_HPT_R3_PRI_MAP_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0058h

Figure 8-57 DDRSS_V2A_HPT_R3_PRI_MAP_REG Register

31	30	29	28	27	26	25	24
RESERVED	HPT_RANGE3_PRIMAP0			RESERVED	HPT_RANGE3_PRIMAP1
R-0h	R/W-0h			R-0h	R/W-0h

23	22	21	20	19	18	17	16
RESERVED	HPT_RANGE3_PRIMAP2			RESERVED	HPT_RANGE3_PRIMAP3
R-0h	R/W-1h			R-0h	R/W-1h

15	14	13	12	11	10	9	8
RESERVED	HPT_RANGE3_PRIMAP4			RESERVED	HPT_RANGE3_PRIMAP5
R-0h	R/W-2h			R-0h	R/W-3h

7	6	5	4	3	2	1	0
RESERVED	HPT_RANGE3_PRIMAP6			RESERVED	HPT_RANGE3_PRIMAP7
R-0h	R/W-4h			R-0h	R/W-5h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-120 DDRSS_V2A_HPT_R3_PRI_MAP_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31	RESERVED	R	X	Reserved
30-28	HPT_RANGE3_PRIMAP0	R/W	0h	The field contains AXI priority value for VBUSM.C priority 0 for range match 3. 0=highest priority. 7=lowest priority
27	RESERVED	R	X	Reserved
26-24	HPT_RANGE3_PRIMAP1	R/W	0h	The field contains AXI priority value for VBUSM.C priority 1 for range match 3. 0=highest priority. 7=lowest priority
23	RESERVED	R	X	Reserved
22-20	HPT_RANGE3_PRIMAP2	R/W	1h	The field contains AXI priority value for VBUSM.C priority 2 for range match 3. 0=highest priority. 7=lowest priority
19	RESERVED	R	X	Reserved
18-16	HPT_RANGE3_PRIMAP3	R/W	1h	The field contains AXI priority value for VBUSM.C priority 3 for range match 3. 0=highest priority. 7=lowest priority
15	RESERVED	R	X	Reserved
14-12	HPT_RANGE3_PRIMAP4	R/W	2h	The field contains AXI priority value for VBUSM.C priority 4 for range match 3. 0=highest priority. 7=lowest priority
11	RESERVED	R	X	Reserved
10-8	HPT_RANGE3_PRIMAP5	R/W	3h	The field contains AXI priority value for VBUSM.C priority 5 for range match 3. 0=highest priority. 7=lowest priority
7	RESERVED	R	X	Reserved
6-4	HPT_RANGE3_PRIMAP6	R/W	4h	The field contains AXI priority value for VBUSM.C priority 6 for range match 3. 0=highest priority. 7=lowest priority
3	RESERVED	R	X	Reserved
2-0	HPT_RANGE3_PRIMAP7	R/W	5h	The field contains AXI priority value for VBUSM.C priority 7 for range match 3. 0=highest priority. 7=lowest priority

2.5.1.15 DDRSS_V2A_AERR_LOG1_REG Register (Offset = 70h) [reset = X]

DDRSS_V2A_AERR_LOG1_REG is shown in Figure 8-58 and described in Table 8-122.

Return to the Summary Table.

The Address Error Log 1 register displays the RouteID and lsb of the address for the first VBUSM.C command that was outside the programmed addressing range. Writing a 0x1 will clear all fields. Writing any other value has no effect. The Address Error Log 2 register will also be cleared upon writing this register.

Table 8-121 DDRSS_V2A_AERR_LOG1_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0070h

Figure 8-58 DDRSS_V2A_AERR_LOG1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AERR_ADDR_LSB
R/W1C-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				AERR_ROUTE_ID
R-0h				R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 8-122 DDRSS_V2A_AERR_LOG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	AERR_ADDR_LSB	R/W1C	0h	Address [15:0] of the VBUSM.C command
15-12	RESERVED	R	X	Reserved
11-0	AERR_ROUTE_ID	R/W1C	0h	RouteID of the VBUSM.C write command

2.5.1.16 DDRSS_V2A_AERR_LOG2_REG Register (Offset = 74h) [reset = 0h]

DDRSS_V2A_AERR_LOG2_REG is shown in Figure 8-59 and described in Table 8-124.

Return to the Summary Table.

The Address Error Log 2 registers displays the msb of the address for the first VBUSM.C command that was outside the programmed addressing range. This register will be cleared upon writing the Address Error Log 1 register.

Table 8-123 DDRSS_V2A_AERR_LOG2_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0074h

Figure 8-59 DDRSS_V2A_AERR_LOG2_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AERR_ADDR_MSB
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-124 DDRSS_V2A_AERR_LOG2_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	AERR_ADDR_MSB	R	0h	Address[34:16] of the VBUSM.C command

2.5.1.17 DDRSS_V2A_OERR_LOG_REG Register (Offset = 78h) [reset = X]

DDRSS_V2A_OERR_LOG_REG is shown in Figure 8-60 and described in Table 8-126.

Return to the Summary Table.

The Opcode Error Log register displays the RouteID and opcode for the first VBUSM.C command that had an unsupported opcode. Writing a 0x1 will clear all fields. Writing any other value has no effect.

Table 8-125 DDRSS_V2A_OERR_LOG_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0078h

Figure 8-60 DDRSS_V2A_OERR_LOG_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED														OERR_OP_CODE
R-0h														R/W1C-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OERR_OP_CODE				OERR_ROUTE_ID
R/W1C-0h				R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 8-126 DDRSS_V2A_OERR_LOG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-18	RESERVED	R	X	Reserved
17-12	OERR_OP_CODE	R/W1C	0h	Opcode of the VBUSM.C command
11-0	OERR_ROUTE_ID	R/W1C	0h	RouteID of the VBUSM.C command

2.5.1.18 DDRSS_V2A_1B_ERR_CNT_REG Register (Offset = 80h) [reset = X]

DDRSS_V2A_1B_ERR_CNT_REG is shown in Figure 8-61 and described in Table 8-128.

Return to the Summary Table.

MSMC2DDR Bridge 1-Bit EDC Error Count Register

Table 8-127 DDRSS_V2A_1B_ERR_CNT_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0080h

Figure 8-61 DDRSS_V2A_1B_ERR_CNT_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																EDC_1B_ERR_CNT
R-0h																R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 8-128 DDRSS_V2A_1B_ERR_CNT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	X	Reserved
15-0	EDC_1B_ERR_CNT	R/W1C	0h	16-bit counter that displays number of 1-bit EDC errors on write data received on the VBUSM.C interface. Writing a 0x1 will clear this count. Writing any other value has no effect.

2.5.1.19 DDRSS_V2A_1B_ERR_LOG1_REG Register (Offset = 84h) [reset = X]

DDRSS_V2A_1B_ERR_LOG1_REG is shown in Figure 8-62 and described in Table 8-130.

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The 1-Bit EDC Error Log 1 register displays the RouteID and error position of the first VBUSM.C write that incurred 1-bit EDC error. Writing a 0x1 will clear all fields. Writing any other value has no effect. The 1-Bit EDC Error Log 2 register will also be cleared upon writing this register.

Table 8-129 DDRSS_V2A_1B_ERR_LOG1_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0084h

Figure 8-62 DDRSS_V2A_1B_ERR_LOG1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED							ERR_POS_1B
R-0h							R/W1C-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED				ROUTE_ID_1B
R-0h				R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 8-130 DDRSS_V2A_1B_ERR_LOG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-25	RESERVED	R	X	Reserved
24-16	ERR_POS_1B	R/W1C	0h	Bit error position
15-12	RESERVED	R	X	Reserved
11-0	ROUTE_ID_1B	R/W1C	0h	RouteID of the VBUSM.C write command

2.5.1.20 DDRSS_V2A_1B_ERR_LOG2_REG Register (Offset = 88h) [reset = X]

DDRSS_V2A_1B_ERR_LOG2_REG is shown in Figure 8-63 and described in Table 8-132.

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The 1-Bit EDC Error Log 2 registers displays the address of the first VBUSM.C write that incurred 1-bit EDC error. This register will be cleared upon writing the 1-Bit EDC Error Log 1 register.

Table 8-131 DDRSS_V2A_1B_ERR_LOG2_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0088h

Figure 8-63 DDRSS_V2A_1B_ERR_LOG2_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED		ADDR_MSB_1B
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-132 DDRSS_V2A_1B_ERR_LOG2_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	X	Reserved
29-0	ADDR_MSB_1B	R	0h	Address [34:5] of the VBUSM.C write command

2.5.1.21 DDRSS_V2A_2B_ERR_LOG1_REG Register (Offset = 8Ch) [reset = X]

DDRSS_V2A_2B_ERR_LOG1_REG is shown in Figure 8-64 and described in Table 8-134.

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The 2-Bit EDC Error Log 1 register displays the RouteID of the first VBUSM.C write that incurred 2-bit EDC error. Writing a 0x1 clear all fields. Writing any other value has no effect. The 2-Bit EDC Error Log 2 register will also be cleared upon writing this register.

Table 8-133 DDRSS_V2A_2B_ERR_LOG1_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 008Ch

Figure 8-64 DDRSS_V2A_2B_ERR_LOG1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																				ROUTE_ID_2B
R-0h																				R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 8-134 DDRSS_V2A_2B_ERR_LOG1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-0	ROUTE_ID_2B	R/W1C	0h	RouteID of the VBUSM.C write command

2.5.1.22 DDRSS_V2A_2B_ERR_LOG2_REG Register (Offset = 90h) [reset = X]

DDRSS_V2A_2B_ERR_LOG2_REG is shown in Figure 8-65 and described in Table 8-136.

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The 2-Bit EDC Error Log 1 register displays the address of the first VBUSM.C write that incurred 2-bit EDC error. This register will be cleared upon writing the 2-Bit EDC Error Log 1 register.

Table 8-135 DDRSS_V2A_2B_ERR_LOG2_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0090h

Figure 8-65 DDRSS_V2A_2B_ERR_LOG2_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED		ADR_MSB_2B
R-0h		R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-136 DDRSS_V2A_2B_ERR_LOG2_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	X	Reserved
29-0	ADR_MSB_2B	R	0h	Address [34:5] of the VBUSM.C write command

2.5.1.23 DDRSS_V2A_BUS_TO Register (Offset = 9Ch) [reset = X]

DDRSS_V2A_BUS_TO is shown in Figure 8-66 and described in Table 8-138.

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MSMC2DDR Bridge Bus Timeout Register

Table 8-137 DDRSS_V2A_BUS_TO Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 009Ch

Figure 8-66 DDRSS_V2A_BUS_TO Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								BUS_TIMER
R-0h								R/W-00FFFFFFh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-138 DDRSS_V2A_BUS_TO Register Field Descriptions

Bit	Field	Type	Reset	Description
31-24	RESERVED	R	X	Reserved
23-0	BUS_TIMER	R/W	00FFFFFFh	AXI bus timeout value. Number of DDR clock cycles after which the MSMC2DDR bridge times out if a hang on the controller AXI interface is detected. A value of N will be equal to N x 16 clocks. Writing a 0 will disable the timeout feature.

2.5.1.24 DDRSS_V2A_INT_RAW_REG Register (Offset = A0h) [reset = X]

DDRSS_V2A_INT_RAW_REG is shown in Figure 8-67 and described in Table 8-140.

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MSMC2DDR Bridge Interrupt Raw Status Register

Table 8-139 DDRSS_V2A_INT_RAW_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 00A0h

Figure 8-67 DDRSS_V2A_INT_RAW_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		ECCM1BERR	ECC2BERR	ECC1BERR	TOERR	AERR	OERR
R-0h		R/W1S-0h	R/W1S-0h	R/W1S-0h	R/W1S-0h	R/W1S-0h	R/W1S-0h

LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset

Table 8-140 DDRSS_V2A_INT_RAW_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	X	Reserved
5	ECCM1BERR	R/W1S	0h	Raw status of SDRAM ECC multi 1-bit errors in same SDRAM burst. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect.
4	ECC2BERR	R/W1S	0h	Raw status of SDRAM ECC 2-bit error. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect.
3	ECC1BERR	R/W1S	0h	Raw status of SDRAM ECC 1-bit error. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect.
2	TOERR	R/W1S	0h	Raw status of MSMC2DDR Bridge interrupt for controller AXI interface timeout. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect.
1	AERR	R/W1S	0h	Raw status of MSMC2DDR Bridge interrupt for VBUSM.C address outside the programmed range. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect.
0	OERR	R/W1S	0h	Raw status of MSMC2DDR Bridge interrupt for VBUSM.C unsupported opcode. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect.

2.5.1.25 DDRSS_V2A_INT_STAT_REG Register (Offset = A4h) [reset = X]

DDRSS_V2A_INT_STAT_REG is shown in Figure 8-68 and described in Table 8-142.

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MSMC2DDR Bridge Interrupt Status Register

Table 8-141 DDRSS_V2A_INT_STAT_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 00A4h

Figure 8-68 DDRSS_V2A_INT_STAT_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		ECCM1BERR	ECC2BERR	ECC1BERR	TOERR	AERR	OERR
R-0h		R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 8-142 DDRSS_V2A_INT_STAT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	X	Reserved
5	ECCM1BERR	R/W1C	0h	Enabled status of SDRAM ECC multi 1-bit errors in same SDRAM burst. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect.
4	ECC2BERR	R/W1C	0h	Enabled status of SDRAM ECC 2-bit error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect.
3	ECC1BERR	R/W1C	0h	Enabled status of SDRAM ECC 1-bit error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect.
2	TOERR	R/W1C	0h	Enabled status of MSMC2DDR Bridge interrupt for controller AXI interface timeout. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect.
1	AERR	R/W1C	0h	Enabled status of MSMC2DDR Bridge interrupt for VBUSM.C address outside the programmed range. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect.
0	OERR	R/W1C	0h	Enabled status of MSMC2DDR Bridge interrupt for VBUSM.C unsupported opcode. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled). Writing a 0 has no effect.

2.5.1.26 DDRSS_V2A_INT_SET_REG Register (Offset = A8h) [reset = X]

DDRSS_V2A_INT_SET_REG is shown in Figure 8-69 and described in Table 8-144.

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MSMC2DDR Bridge Interrupt Enable Set Register

Table 8-143 DDRSS_V2A_INT_SET_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 00A8h

Figure 8-69 DDRSS_V2A_INT_SET_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		ECCM1BERR_EN	ECC2BERR_EN	ECC1BERR_EN	TOERR_EN	AERR_EN	OERR_EN
R-0h		R/W1S-0h	R/W1S-0h	R/W1S-0h	R/W1S-0h	R/W1S-0h	R/W1S-0h

LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset

Table 8-144 DDRSS_V2A_INT_SET_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	X	Reserved
5	ECCM1BERR_EN	R/W1S	0h	Enable set for SDRAM ECC multi 1-bit errors in same SDRAM burst. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.
4	ECC2BERR_EN	R/W1S	0h	Enable set for SDRAM ECC 2-bit error. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.
3	ECC1BERR_EN	R/W1S	0h	Enable set for SDRAM ECC 1-bit error. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.
2	TOERR_EN	R/W1S	0h	Enable set for MSMC2DDR Bridge interrupt for controller AXI interface timeout. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.
1	AERR_EN	R/W1S	0h	Enable set for MSMC2DDR Bridge interrupt for VBUSM.C address outside the programmed range. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.
0	OERR_EN	R/W1S	0h	Enable set for MSMC2DDR Bridge interrupt for VBUSM.C unsupported opcode. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.

2.5.1.27 DDRSS_V2A_INT_CLR_REG Register (Offset = ACh) [reset = X]

DDRSS_V2A_INT_CLR_REG is shown in Figure 8-70 and described in Table 8-146.

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MSMC2DDR Bridge Interrupt Enable Clear Register

Table 8-145 DDRSS_V2A_INT_CLR_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 00ACh

Figure 8-70 DDRSS_V2A_INT_CLR_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED
R-0h

7	6	5	4	3	2	1	0
RESERVED		ECCM1BERR_EN	ECC2BERR_EN	ECC1BERR_EN	TOERR_EN	AERR_EN	OERR_EN
R-0h		R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h	R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 8-146 DDRSS_V2A_INT_CLR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	X	Reserved
5	ECCM1BERR_EN	R/W1C	0h	Enable clear for SDRAM ECC multi 1-bit errors in same SDRAM burst. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.
4	ECC2BERR_EN	R/W1C	0h	Enable clear for SDRAM ECC 2-bit error. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.
3	ECC1BERR_EN	R/W1C	0h	Enable clear for SDRAM ECC 1-bit error. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.
2	TOERR_EN	R/W1C	0h	Enable clear for MSMC2DDR Bridge interrupt for controller AXI interface timeout. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.
1	AERR_EN	R/W1C	0h	Enable clear for MSMC2DDR Bridge interrupt for VBUSM.C address outside the programmed range. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.
0	OERR_EN	R/W1C	0h	Enable clear for MSMC2DDR Bridge interrupt for VBUSM.C unsupported opcode. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.

2.5.1.28 DDRSS_V2A_EOI_REG Register (Offset = B0h) [reset = X]

DDRSS_V2A_EOI_REG is shown in Figure 8-71 and described in Table 8-148.

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MSMC2DDR Bridge End of Interrupt Register

Table 8-147 DDRSS_V2A_EOI_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 00B0h

Figure 8-71 DDRSS_V2A_EOI_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED														EOI
R-0h														W-0h

LEGEND: R = Read Only; W = Write Only; -n = value after reset

Table 8-148 DDRSS_V2A_EOI_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-2	RESERVED	R	X	Reserved
1-0	EOI	W	0h	Software End Of Interrupt (EOI) control. Write 0 for aerr/oerr/toerr interrupt. Write 1 for ecc1b interrupt. Write 2 for ecc2b interrupt. This field always reads 0 (no EOI memory).

2.5.1.29 DDRSS_PERF_CNT_SEL_REG Register (Offset = 100h) [reset = X]

DDRSS_PERF_CNT_SEL_REG is shown in Figure 8-72 and described in Table 8-150.

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The Performance Counter Select register is used to select the statistic type to be counted in the corresponding Performance Counter register.

Table 8-149 DDRSS_PERF_CNT_SEL_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0100h

Figure 8-72 DDRSS_PERF_CNT_SEL_REG Register

31	30	29	28	27	26	25	24
RESERVED		CNT4_SEL
R-0h		R/W-3h

23	22	21	20	19	18	17	16
RESERVED		CNT3_SEL
R-0h		R/W-2h

15	14	13	12	11	10	9	8
RESERVED		CNT2_SEL
R-0h		R/W-1h

7	6	5	4	3	2	1	0
RESERVED		CNT1_SEL
R-0h		R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-150 DDRSS_PERF_CNT_SEL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	X	Reserved
29-24	CNT4_SEL	R/W	3h	Statistic select for Performance Counter 4 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every Precharge command. 0x5 = Counts every Precharge All command. 0x6 = Counts every Mode Register Read command. 0x7 = Counts every Mode Register Write command. 0x8 = Counts every Per Bank Refresh command. 0x9 = Counts every Auto Refresh command. 0xA = Counts every ZQ Calib Long command. 0xB = Counts every ZQ Calib Short command. 0xC = Counts every Write-to-Read and Read-to-Write bus-turn-around. 0xD = Counts every Write-to-Write address collision. 0xE = Counts every Write-to-Read address collision. 0xF = Counts every Read-to-Write address collision. 0x10 = Counts every Read-to-Read address collision. 0x11 = Counts every exit from Power-Down Self-Refresh mode. 0x12 = Counts every entry into Power-Down Self-Refresh mode. 0x13 = Counts every cycle for which the DDR Controller stays in Power-Down Self-Refresh mode. 0x14 = Counts every exit from Power-Down mode. 0x15 = Counts every entry into Power-Down mode. 0x16 = Counts every cycle for which the DDR Controller stays in Power-Down mode. 0x17 = Counts every exit from Self-Refresh mode. 0x18 = Counts every entry into Self-Refresh mode. 0x19 = Counts every cycle for which the DDR Controller stays in Self-Refresh mode. 0x1A = Reserved 0x1B = Reserved 0x1C = Counts every cycle for which the DDR Controller command queue is full. 0x1D = Counts every cycle for which the DDR Controller info FIFO is full. 0x1E = Counts every cycle for which the DDR Controller write latency FIFO is full. 0x1F = Counts every cycle for which the DDR Controller port command FIFO is full. 0x20 = Counts every cycle for which the DDR Controller write response FIFO is full. 0x21 = Counts every cycle for which the DDR Controller port write FIFO is full. 0x22 = Counts every cycle for which the DDR Controller core read FIFO is full. 0x23 = Counts every cycle for which the DDR Controller port read FIFO is full. 0x24-0x2F = Reserved
23-22	RESERVED	R	X	Reserved
21-16	CNT3_SEL	R/W	2h	Statistic select for Performance Counter 3 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every Precharge command. 0x5 = Counts every Precharge All command. 0x6 = Counts every Mode Register Read command. 0x7 = Counts every Mode Register Write command. 0x8 = Counts every Per Bank Refresh command. 0x9 = Counts every Auto Refresh command. 0xA = Counts every ZQ Calib Long command. 0xB = Counts every ZQ Calib Short command. 0xC = Counts every Write-to-Read and Read-to-Write bus-turn-around. 0xD = Counts every Write-to-Write address collision. 0xE = Counts every Write-to-Read address collision. 0xF = Counts every Read-to-Write address collision. 0x10 = Counts every Read-to-Read address collision. 0x11 = Counts every exit from Power-Down Self-Refresh mode. 0x12 = Counts every entry into Power-Down Self-Refresh mode. 0x13 = Counts every cycle for which the DDR Controller stays in Power-Down Self-Refresh mode. 0x14 = Counts every exit from Power-Down mode. 0x15 = Counts every entry into Power-Down mode. 0x16 = Counts every cycle for which the DDR Controller stays in Power-Down mode. 0x17 = Counts every exit from Self-Refresh mode. 0x18 = Counts every entry into Self-Refresh mode. 0x19 = Counts every cycle for which the DDR Controller stays in Self-Refresh mode. 0x1A = Reserved 0x1B = Reserved 0x1C = Counts every cycle for which the DDR Controller command queue is full. 0x1D = Counts every cycle for which the DDR Controller info FIFO is full. 0x1E = Counts every cycle for which the DDR Controller write latency FIFO is full. 0x1F = Counts every cycle for which the DDR Controller port command FIFO is full. 0x20 = Counts every cycle for which the DDR Controller write response FIFO is full. 0x21 = Counts every cycle for which the DDR Controller port write FIFO is full. 0x22 = Counts every cycle for which the DDR Controller core read FIFO is full. 0x23 = Counts every cycle for which the DDR Controller port read FIFO is full. 0x24-0x2F = Reserved
15-14	RESERVED	R	X	Reserved
13-8	CNT2_SEL	R/W	1h	Statistic select for Performance Counter 2 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every Precharge command. 0x5 = Counts every Precharge All command. 0x6 = Counts every Mode Register Read command. 0x7 = Counts every Mode Register Write command. 0x8 = Counts every Per Bank Refresh command. 0x9 = Counts every Auto Refresh command. 0xA = Counts every ZQ Calib Long command. 0xB = Counts every ZQ Calib Short command. 0xC = Counts every Write-to-Read and Read-to-Write bus-turn-around. 0xD = Counts every Write-to-Write address collision. 0xE = Counts every Write-to-Read address collision. 0xF = Counts every Read-to-Write address collision. 0x10 = Counts every Read-to-Read address collision. 0x11 = Counts every exit from Power-Down Self-Refresh mode. 0x12 = Counts every entry into Power-Down Self-Refresh mode. 0x13 = Counts every cycle for which the DDR Controller stays in Power-Down Self-Refresh mode. 0x14 = Counts every exit from Power-Down mode. 0x15 = Counts every entry into Power-Down mode. 0x16 = Counts every cycle for which the DDR Controller stays in Power-Down mode. 0x17 = Counts every exit from Self-Refresh mode. 0x18 = Counts every entry into Self-Refresh mode. 0x19 = Counts every cycle for which the DDR Controller stays in Self-Refresh mode. 0x1A = Reserved 0x1B = Reserved 0x1C = Counts every cycle for which the DDR Controller command queue is full. 0x1D = Counts every cycle for which the DDR Controller info FIFO is full. 0x1E = Counts every cycle for which the DDR Controller write latency FIFO is full. 0x1F = Counts every cycle for which the DDR Controller port command FIFO is full. 0x20 = Counts every cycle for which the DDR Controller write response FIFO is full. 0x21 = Counts every cycle for which the DDR Controller port write FIFO is full. 0x22 = Counts every cycle for which the DDR Controller core read FIFO is full. 0x23 = Counts every cycle for which the DDR Controller port read FIFO is full. 0x24-0x2F = Reserved
7-6	RESERVED	R	X	Reserved
5-0	CNT1_SEL	R/W	0h	Statistic select for Performance Counter 1 register. 0x0 = Counts every Write command. 0x1 = Counts every Read command. 0x2 = Counts every read as a result of a RMW command. 0x3 = Counts every Activate command. 0x4 = Counts every Precharge command. 0x5 = Counts every Precharge All command. 0x6 = Counts every Mode Register Read command. 0x7 = Counts every Mode Register Write command. 0x8 = Counts every Per Bank Refresh command. 0x9 = Counts every Auto Refresh command. 0xA = Counts every ZQ Calib Long command. 0xB = Counts every ZQ Calib Short command. 0xC = Counts every Write-to-Read and Read-to-Write bus-turn-around. 0xD = Counts every Write-to-Write address collision. 0xE = Counts every Write-to-Read address collision. 0xF = Counts every Read-to-Write address collision. 0x10 = Counts every Read-to-Read address collision. 0x11 = Counts every exit from Power-Down Self-Refresh mode. 0x12 = Counts every entry into Power-Down Self-Refresh mode. 0x13 = Counts every cycle for which the DDR Controller stays in Power-Down Self-Refresh mode. 0x14 = Counts every exit from Power-Down mode. 0x15 = Counts every entry into Power-Down mode. 0x16 = Counts every cycle for which the DDR Controller stays in Power-Down mode. 0x17 = Counts every exit from Self-Refresh mode. 0x18 = Counts every entry into Self-Refresh mode. 0x19 = Counts every cycle for which the DDR Controller stays in Self-Refresh mode. 0x1A = Reserved 0x1B = Reserved 0x1C = Counts every cycle for which the DDR Controller command queue is full. 0x1D = Counts every cycle for which the DDR Controller info FIFO is full. 0x1E = Counts every cycle for which the DDR Controller write latency FIFO is full. 0x1F = Counts every cycle for which the DDR Controller port command FIFO is full. 0x20 = Counts every cycle for which the DDR Controller write response FIFO is full. 0x21 = Counts every cycle for which the DDR Controller port write FIFO is full. 0x22 = Counts every cycle for which the DDR Controller core read FIFO is full. 0x23 = Counts every cycle for which the DDR Controller port read FIFO is full. 0x24-0x2F = Reserved

2.5.1.30 DDRSS_PERF_CNT1_REG Register (Offset = 104h) [reset = 0h]

DDRSS_PERF_CNT1_REG is shown in Figure 8-73 and described in Table 8-152.

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Performance Counter 1 Register

Table 8-151 DDRSS_PERF_CNT1_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0104h

Figure 8-73 DDRSS_PERF_CNT1_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT1
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-152 DDRSS_PERF_CNT1_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CNT1	R	0h	Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register.

2.5.1.31 DDRSS_PERF_CNT2_REG Register (Offset = 108h) [reset = 0h]

DDRSS_PERF_CNT2_REG is shown in Figure 8-74 and described in Table 8-154.

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Performance Counter 2 Register

Table 8-153 DDRSS_PERF_CNT2_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0108h

Figure 8-74 DDRSS_PERF_CNT2_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT2
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-154 DDRSS_PERF_CNT2_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CNT2	R	0h	Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register.

2.5.1.32 DDRSS_PERF_CNT3_REG Register (Offset = 10Ch) [reset = 0h]

DDRSS_PERF_CNT3_REG is shown in Figure 8-75 and described in Table 8-156.

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Performance Counter 3 Register

Table 8-155 DDRSS_PERF_CNT3_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 010Ch

Figure 8-75 DDRSS_PERF_CNT3_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT3
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-156 DDRSS_PERF_CNT3_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CNT3	R	0h	Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register.

2.5.1.33 DDRSS_PERF_CNT4_REG Register (Offset = 110h) [reset = 0h]

DDRSS_PERF_CNT4_REG is shown in Figure 8-76 and described in Table 8-158.

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Performance Counter 4 Register

Table 8-157 DDRSS_PERF_CNT4_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0110h

Figure 8-76 DDRSS_PERF_CNT4_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT4
R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-158 DDRSS_PERF_CNT4_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-0	CNT4	R	0h	Soft 32-bit counter that can be configured as specified in the Performance Counter Select Register.

2.5.1.34 DDRSS_ECC_CTRL_REG Register (Offset = 120h) [reset = X]

DDRSS_ECC_CTRL_REG is shown in Figure 8-77 and described in Table 8-160.

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ECC Control Register

Table 8-159 DDRSS_ECC_CTRL_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0120h

Figure 8-77 DDRSS_ECC_CTRL_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
RESERVED				COR_ECC_THRESH
R-0h				R/W-0h

7	6	5	4	3	2	1	0
RESERVED			WR_ALLOC	RESERVED	ECC_CK	RMW_EN	ECC_EN
R-0h			R/W-0h	R-0h	R/W-0h	R/W-0h	R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-160 DDRSS_ECC_CTRL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-12	RESERVED	R	X	Reserved
11-8	COR_ECC_THRESH	R/W	0h	Threshold for 1-bit ECC errors in multiple data words in an SDRAM burst that create an uncorrected error fault indication. Value of 0/1 means 2 or more 1-bit errors in multiple data words will result in an uncorrected error fault indication, value of 2 means 3 or more 1-bit errors will result in an uncorrected error fault indication, and so on. Value of 8 or greater disables this feature. This field must always be kept at default, and only changed for debug.
7-5	RESERVED	R	X	Reserved
4	WR_ALLOC	R/W	0h	When set to 1, an unassigned ECC cache-line will be allocated for a write with routeID that do not match any of the mapped routeID's.
3	RESERVED	R	X	Reserved
2	ECC_CK	R/W	0h	Set 1 to enable ECC verification for read accesses when ecc_en=1. The value of this field is ignored when ecc_en=0. This bit must be set and kept static before using DDR.
1	RMW_EN	R/W	0h	Read modify write enable. Set 1 to enable RMW functionality for sub-quanta accesses when ecc_en=1. This bit must be set to 1 if ecc_en is set to a 1 to ensure subquanta accesses to DRAM do not result in ECC errors. This bit must be set and kept static before using DDR.
0	ECC_EN	R/W	0h	DRAM ECC enable. Setting a 1 causes ECC to be written to DRAM. This bit must be set and kept static before using DDR.

2.5.1.35 DDRSS_ECC_RID_INDX_REG Register (Offset = 124h) [reset = X]

DDRSS_ECC_RID_INDX_REG is shown in Figure 8-78 and described in Table 8-162.

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ECC Cache RouteID Index Register

Table 8-161 DDRSS_ECC_RID_INDX_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0124h

Figure 8-78 DDRSS_ECC_RID_INDX_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED										ECCRID_ADR
R-0h										R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-162 DDRSS_ECC_RID_INDX_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-6	RESERVED	R	X	Reserved
5-0	ECCRID_ADR	R/W	0h	This index specifies the ECC cache entry number that the eccrid_val is mapped to.

2.5.1.36 DDRSS_ECC_RID_VAL_REG Register (Offset = 128h) [reset = X]

DDRSS_ECC_RID_VAL_REG is shown in Figure 8-79 and described in Table 8-164.

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ECC Cache RouteID Write Value Register

Table 8-163 DDRSS_ECC_RID_VAL_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0128h

Figure 8-79 DDRSS_ECC_RID_VAL_REG Register

31	30	29	28	27	26	25	24
RESERVED
R-0h

23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8
ECCRID_VAL_VLD	RESERVED			ECCRID_VAL
R/W-0h	R-0h			R/W-0h

7	6	5	4	3	2	1	0
ECCRID_VAL
R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-164 DDRSS_ECC_RID_VAL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	X	Reserved
15	ECCRID_VAL_VLD	R/W	0h	A 1 in this field indicates that value in eccrid_val is valid.
14-12	RESERVED	R	X	Reserved
11-0	ECCRID_VAL	R/W	0h	RouteID value written or read.

2.5.1.37 DDRSS_ECC_R0_STR_ADDR_REG Register (Offset = 130h) [reset = X]

DDRSS_ECC_R0_STR_ADDR_REG is shown in Figure 8-80 and described in Table 8-166.

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ECC Range 0 Start Address Register

Table 8-165 DDRSS_ECC_R0_STR_ADDR_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0130h

Figure 8-80 DDRSS_ECC_R0_STR_ADDR_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													ECC_STR_ADR_0
R-0h													R/W-0007FFFFh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-166 DDRSS_ECC_R0_STR_ADDR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	X	Reserved
18-0	ECC_STR_ADR_0	R/W	0007FFFFh	Start caddress [34:16] for ECC range 0. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR.

2.5.1.38 DDRSS_ECC_R0_END_ADDR_REG Register (Offset = 134h) [reset = X]

DDRSS_ECC_R0_END_ADDR_REG is shown in Figure 8-81 and described in Table 8-168.

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ECC Range 0 End Address Register

Table 8-167 DDRSS_ECC_R0_END_ADDR_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0134h

Figure 8-81 DDRSS_ECC_R0_END_ADDR_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													ECC_END_ADR_0
R-0h													R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-168 DDRSS_ECC_R0_END_ADDR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	X	Reserved
18-0	ECC_END_ADR_0	R/W	0h	End caddress [34:16] for ECC range 0. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR.

2.5.1.39 DDRSS_ECC_R1_STR_ADDR_REG Register (Offset = 138h) [reset = X]

DDRSS_ECC_R1_STR_ADDR_REG is shown in Figure 8-82 and described in Table 8-170.

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ECC Range 1 Start Address Register

Table 8-169 DDRSS_ECC_R1_STR_ADDR_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0138h

Figure 8-82 DDRSS_ECC_R1_STR_ADDR_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													ECC_STR_ADR_1
R-0h													R/W-0007FFFFh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-170 DDRSS_ECC_R1_STR_ADDR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	X	Reserved
18-0	ECC_STR_ADR_1	R/W	0007FFFFh	Start caddress [34:16] for ECC range 1. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR.

2.5.1.40 DDRSS_ECC_R1_END_ADDR_REG Register (Offset = 13Ch) [reset = X]

DDRSS_ECC_R1_END_ADDR_REG is shown in Figure 8-83 and described in Table 8-172.

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ECC Range 1 End Address Register

Table 8-171 DDRSS_ECC_R1_END_ADDR_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 013Ch

Figure 8-83 DDRSS_ECC_R1_END_ADDR_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													ECC_END_ADR_1
R-0h													R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-172 DDRSS_ECC_R1_END_ADDR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	X	Reserved
18-0	ECC_END_ADR_1	R/W	0h	End caddress [34:16] for ECC range 1. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR.

2.5.1.41 DDRSS_ECC_R2_STR_ADDR_REG Register (Offset = 140h) [reset = X]

DDRSS_ECC_R2_STR_ADDR_REG is shown in Figure 8-84 and described in Table 8-174.

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ECC Range 2 Start Address Register

Table 8-173 DDRSS_ECC_R2_STR_ADDR_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0140h

Figure 8-84 DDRSS_ECC_R2_STR_ADDR_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													ECC_STR_ADR_2
R-0h													R/W-0007FFFFh

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-174 DDRSS_ECC_R2_STR_ADDR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	X	Reserved
18-0	ECC_STR_ADR_2	R/W	0007FFFFh	Start caddress [34:16] for ECC range 2. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR.

2.5.1.42 DDRSS_ECC_R2_END_ADDR_REG Register (Offset = 144h) [reset = X]

DDRSS_ECC_R2_END_ADDR_REG is shown in Figure 8-85 and described in Table 8-176.

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ECC Range 2 End Address Register

Table 8-175 DDRSS_ECC_R2_END_ADDR_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0144h

Figure 8-85 DDRSS_ECC_R2_END_ADDR_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED													ECC_END_ADR_2
R-0h													R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-176 DDRSS_ECC_R2_END_ADDR_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-19	RESERVED	R	X	Reserved
18-0	ECC_END_ADR_2	R/W	0h	End caddress [34:16] for ECC range 2. Setting the start address greater than the end address disables the range. The range is inclusive of the start and end addresses. This field must be set and kept static before using DDR.

2.5.1.43 DDRSS_ECC_1B_ERR_CNT_REG Register (Offset = 150h) [reset = X]

DDRSS_ECC_1B_ERR_CNT_REG is shown in Figure 8-86 and described in Table 8-178.

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ECC 1-Bit Error Count Register

Table 8-177 DDRSS_ECC_1B_ERR_CNT_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0150h

Figure 8-86 DDRSS_ECC_1B_ERR_CNT_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																ECC_1B_ERR_CNT
R-0h																R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 8-178 DDRSS_ECC_1B_ERR_CNT_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	X	Reserved
15-0	ECC_1B_ERR_CNT	R/W1C	0h	16-bit counter that displays number of 1-bit ECC errors on SDRAM data. Writing a 0x1 will clear this count. Writing any other value has no effect.

2.5.1.44 DDRSS_ECC_1B_ERR_THRSH_REG Register (Offset = 154h) [reset = X]

DDRSS_ECC_1B_ERR_THRSH_REG is shown in Figure 8-87 and described in Table 8-180.

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ECC 1-Bit Error Threshold Register

Table 8-179 DDRSS_ECC_1B_ERR_THRSH_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0154h

Figure 8-87 DDRSS_ECC_1B_ERR_THRSH_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																ECC_1B_ERR_THRSH
R-0h																R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-180 DDRSS_ECC_1B_ERR_THRSH_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	X	Reserved
15-0	ECC_1B_ERR_THRSH	R/W	0h	ECC 1-bit error threshold. The bridge will generate an interrupt when the ECC 1-bit error count is equal to or greater than this threshold. A value of 0 will disable the generation of interrupt.

2.5.1.45 DDRSS_ECC_1B_ERR_ADR_LOG_REG Register (Offset = 158h) [reset = X]

DDRSS_ECC_1B_ERR_ADR_LOG_REG is shown in Figure 8-88 and described in Table 8-182.

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ECC 1-Bit Error Address Log Register

Table 8-181 DDRSS_ECC_1B_ERR_ADR_LOG_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0158h

Figure 8-88 DDRSS_ECC_1B_ERR_ADR_LOG_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED		ECC_1B_ERR_ADR
R-0h		R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 8-182 DDRSS_ECC_1B_ERR_ADR_LOG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	X	Reserved
29-0	ECC_1B_ERR_ADR	R/W1C	0h	ECC 1-bit error address. 32-byte aligned address that had the 1-bit ECC error. This field displays the first address logged in the 2 deep logging FIFO. Writing a 0x1 will pop the top element of the FIFO. Writing any other value has no effect.

2.5.1.46 DDRSS_ECC_1B_ERR_MSK_LOG_REG Register (Offset = 15Ch) [reset = X]

DDRSS_ECC_1B_ERR_MSK_LOG_REG is shown in Figure 8-89 and described in Table 8-184.

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ECC 1-Bit Error Mask Log Register

Table 8-183 DDRSS_ECC_1B_ERR_MSK_LOG_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 015Ch

Figure 8-89 DDRSS_ECC_1B_ERR_MSK_LOG_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								ECC_1B_ERR_MSK
R-0h								R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-184 DDRSS_ECC_1B_ERR_MSK_LOG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	X	Reserved
7-0	ECC_1B_ERR_MSK	R	0h	ECC 1-bit error mask. Mask for the 64-byte data block that had the 1-bit ECC errors. Each bit represents an ECC quanta (8 bytes) in the 64-byte data block starting at address specified by ecc_1b_err_adr. Value of 1 on the bit represents an error in that particular 8 bytes. This field displays the first mask logged in the 2 deep logging FIFO along with the ecc_1b_err_adr. The same mechanism used to pop ecc_1b_err_adr is used to pop this field.

2.5.1.47 DDRSS_ECC_2B_ERR_ADR_LOG_REG Register (Offset = 160h) [reset = X]

DDRSS_ECC_2B_ERR_ADR_LOG_REG is shown in Figure 8-90 and described in Table 8-186.

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ECC 2-Bit Error Address Log Register

Table 8-185 DDRSS_ECC_2B_ERR_ADR_LOG_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0160h

Figure 8-90 DDRSS_ECC_2B_ERR_ADR_LOG_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED		ECC_2B_ERR_ADR
R-0h		R/W1C-0h

LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset

Table 8-186 DDRSS_ECC_2B_ERR_ADR_LOG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-30	RESERVED	R	X	Reserved
29-0	ECC_2B_ERR_ADR	R/W1C	0h	ECC 2-bit error address. 32-byte aligned address that had the 2-bit ECC error. Writing a 0x1 will clear this field and the ecc_2b_err_msk field. Writing any other value has no effect.

2.5.1.48 DDRSS_ECC_2B_ERR_MSK_LOG_REG Register (Offset = 164h) [reset = X]

DDRSS_ECC_2B_ERR_MSK_LOG_REG is shown in Figure 8-91 and described in Table 8-188.

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ECC 2-Bit Error Mask Log Register

Table 8-187 DDRSS_ECC_2B_ERR_MSK_LOG_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0164h

Figure 8-91 DDRSS_ECC_2B_ERR_MSK_LOG_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RESERVED
R-0h

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED								ECC_2B_ERR_MSK
R-0h								R-0h

LEGEND: R = Read Only; -n = value after reset

Table 8-188 DDRSS_ECC_2B_ERR_MSK_LOG_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-8	RESERVED	R	X	Reserved
7-0	ECC_2B_ERR_MSK	R	0h	ECC 2-bit error mask. Mask for the 64-byte data block that had the 2-bit ECC errors. Each bit represents an ECC quanta (8 bytes) in the 64-byte data block starting at address specified by ecc_2b_err_adr. Value of 1 on the bit represents an error in that particular 8 bytes.

2.5.1.49 DDRSS_PHY_BIST_CTRL_REG Register (Offset = 180h) [reset = X]

DDRSS_PHY_BIST_CTRL_REG is shown in Figure 8-92 and described in Table 8-190.

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PHY BIST Control Register

Table 8-189 DDRSS_PHY_BIST_CTRL_REG Instances

Instance	Physical Address
COMPUTE_CLUSTER0_SS_CFG	0298 0180h

Figure 8-92 DDRSS_PHY_BIST_CTRL_REG Register

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																BIST_TSEL_SELECT
R-0h																R/W-0h

LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset

Table 8-190 DDRSS_PHY_BIST_CTRL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31-16	RESERVED	R	X	Reserved
15-0	BIST_TSEL_SELECT	R/W	0h	This field controls the bist_tsel_select input of the PHY. For details please refer to the PHY specification.