SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-251 lists the memory-mapped registers for the I2C registers. All register offset addresses not listed in Table 12-251 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
I2C0_CFG | 0200 0000h |
I2C1_CFG | 0201 0000h |
I2C2_CFG | 0202 0000h |
I2C3_CFG | 0203 0000h |
I2C4_CFG | 0204 0000h |
I2C5_CFG | 0205 0000h |
I2C6_CFG | 0206 0000h |
MCU_I2C0_CFG | 40B0 0000h |
MCU_I2C1_CFG | 40B1 0000h |
WKUP_I2C0_CFG | 4212 0000h |
Offset | Acronym | Register Name | I2C0_CFG Physical Address | I2C1_CFG Physical Address | I2C2_CFG Physical Address |
---|---|---|---|---|---|
0h | I2C_REVNB_LO | 0200 0000h | 0201 0000h | 0202 0000h | |
4h | I2C_REVNB_HI | 0200 0004h | 0201 0004h | 0202 0004h | |
10h | I2C_SYSC | 0200 0010h | 0201 0010h | 0202 0010h | |
20h | I2C_EOI | 0200 0020h | 0201 0020h | 0202 0020h | |
24h | I2C_IRQSTATUS_RAW | 0200 0024h | 0201 0024h | 0202 0024h | |
28h | I2C_IRQSTATUS | 0200 0028h | 0201 0028h | 0202 0028h | |
2Ch | I2C_IRQENABLE_SET | 0200 002Ch | 0201 002Ch | 0202 002Ch | |
30h | I2C_IRQENABLE_CLR | 0200 0030h | 0201 0030h | 0202 0030h | |
34h | I2C_WE | 0200 0034h | 0201 0034h | 0202 0034h | |
38h | I2C_DMARXENABLE_SET | 0200 0038h | 0201 0038h | 0202 0038h | |
3Ch | I2C_DMATXENABLE_SET | 0200 003Ch | 0201 003Ch | 0202 003Ch | |
40h | I2C_DMARXENABLE_CLR | 0200 0040h | 0201 0040h | 0202 0040h | |
44h | I2C_DMATXENABLE_CLR | 0200 0044h | 0201 0044h | 0202 0044h | |
48h | I2C_DMARXWAKE_EN | 0200 0048h | 0201 0048h | 0202 0048h | |
4Ch | I2C_DMATXWAKE_EN | 0200 004Ch | 0201 004Ch | 0202 004Ch | |
84h | I2C_IE | 0200 0084h | 0201 0084h | 0202 0084h | |
88h | I2C_STAT | 0200 0088h | 0201 0088h | 0202 0088h | |
90h | I2C_SYSS | 0200 0090h | 0201 0090h | 0202 0090h | |
94h | I2C_BUF | 0200 0094h | 0201 0094h | 0202 0094h | |
98h | I2C_CNT | 0200 0098h | 0201 0098h | 0202 0098h | |
9Ch | I2C_DATA | 0200 009Ch | 0201 009Ch | 0202 009Ch | |
A4h | I2C_CON | 0200 00A4h | 0201 00A4h | 0202 00A4h | |
A8h | I2C_OA | 0200 00A8h | 0201 00A8h | 0202 00A8h | |
ACh | I2C_SA | 0200 00ACh | 0201 00ACh | 0202 00ACh | |
B0h | I2C_PSC | 0200 00B0h | 0201 00B0h | 0202 00B0h | |
B4h | I2C_SCLL | 0200 00B4h | 0201 00B4h | 0202 00B4h | |
B8h | I2C_SCLH | 0200 00B8h | 0201 00B8h | 0202 00B8h | |
BCh | I2C_SYSTEST | 0200 00BCh | 0201 00BCh | 0202 00BCh | |
C0h | I2C_BUFSTAT | 0200 00C0h | 0201 00C0h | 0202 00C0h | |
C4h | I2C_OA1 | 0200 00C4h | 0201 00C4h | 0202 00C4h | |
C8h | I2C_OA2 | 0200 00C8h | 0201 00C8h | 0202 00C8h | |
CCh | I2C_OA3 | 0200 00CCh | 0201 00CCh | 0202 00CCh | |
D0h | I2C_ACTOA | 0200 00D0h | 0201 00D0h | 0202 00D0h | |
D4h | I2C_SBLOCK | 0200 00D4h | 0201 00D4h | 0202 00D4h |
Offset | Acronym | Register Name | I2C3_CFG Physical Address | I2C4_CFG Physical Address | I2C5_CFG Physical Address |
---|---|---|---|---|---|
0h | I2C_REVNB_LO | 0203 0000h | 0204 0000h | 0205 0000h | |
4h | I2C_REVNB_HI | 0203 0004h | 0204 0004h | 0205 0004h | |
10h | I2C_SYSC | 0203 0010h | 0204 0010h | 0205 0010h | |
20h | I2C_EOI | 0203 0020h | 0204 0020h | 0205 0020h | |
24h | I2C_IRQSTATUS_RAW | 0203 0024h | 0204 0024h | 0205 0024h | |
28h | I2C_IRQSTATUS | 0203 0028h | 0204 0028h | 0205 0028h | |
2Ch | I2C_IRQENABLE_SET | 0203 002Ch | 0204 002Ch | 0205 002Ch | |
30h | I2C_IRQENABLE_CLR | 0203 0030h | 0204 0030h | 0205 0030h | |
34h | I2C_WE | 0203 0034h | 0204 0034h | 0205 0034h | |
38h | I2C_DMARXENABLE_SET | 0203 0038h | 0204 0038h | 0205 0038h | |
3Ch | I2C_DMATXENABLE_SET | 0203 003Ch | 0204 003Ch | 0205 003Ch | |
40h | I2C_DMARXENABLE_CLR | 0203 0040h | 0204 0040h | 0205 0040h | |
44h | I2C_DMATXENABLE_CLR | 0203 0044h | 0204 0044h | 0205 0044h | |
48h | I2C_DMARXWAKE_EN | 0203 0048h | 0204 0048h | 0205 0048h | |
4Ch | I2C_DMATXWAKE_EN | 0203 004Ch | 0204 004Ch | 0205 004Ch | |
84h | I2C_IE | 0203 0084h | 0204 0084h | 0205 0084h | |
88h | I2C_STAT | 0203 0088h | 0204 0088h | 0205 0088h | |
90h | I2C_SYSS | 0203 0090h | 0204 0090h | 0205 0090h | |
94h | I2C_BUF | 0203 0094h | 0204 0094h | 0205 0094h | |
98h | I2C_CNT | 0203 0098h | 0204 0098h | 0205 0098h | |
9Ch | I2C_DATA | 0203 009Ch | 0204 009Ch | 0205 009Ch | |
A4h | I2C_CON | 0203 00A4h | 0204 00A4h | 0205 00A4h | |
A8h | I2C_OA | 0203 00A8h | 0204 00A8h | 0205 00A8h | |
ACh | I2C_SA | 0203 00ACh | 0204 00ACh | 0205 00ACh | |
B0h | I2C_PSC | 0203 00B0h | 0204 00B0h | 0205 00B0h | |
B4h | I2C_SCLL | 0203 00B4h | 0204 00B4h | 0205 00B4h | |
B8h | I2C_SCLH | 0203 00B8h | 0204 00B8h | 0205 00B8h | |
BCh | I2C_SYSTEST | 0203 00BCh | 0204 00BCh | 0205 00BCh | |
C0h | I2C_BUFSTAT | 0203 00C0h | 0204 00C0h | 0205 00C0h | |
C4h | I2C_OA1 | 0203 00C4h | 0204 00C4h | 0205 00C4h | |
C8h | I2C_OA2 | 0203 00C8h | 0204 00C8h | 0205 00C8h | |
CCh | I2C_OA3 | 0203 00CCh | 0204 00CCh | 0205 00CCh | |
D0h | I2C_ACTOA | 0203 00D0h | 0204 00D0h | 0205 00D0h | |
D4h | I2C_SBLOCK | 0203 00D4h | 0204 00D4h | 0205 00D4h |
Offset | Acronym | Register Name | I2C6_CFG Physical Address | MCU_I2C0_CFG Physical Address | MCU_I2C1_CFG Physical Address |
---|---|---|---|---|---|
0h | I2C_REVNB_LO | 0206 0000h | 40B0 0000h | 40B1 0000h | |
4h | I2C_REVNB_HI | 0206 0004h | 40B0 0004h | 40B1 0004h | |
10h | I2C_SYSC | 0206 0010h | 40B0 0010h | 40B1 0010h | |
20h | I2C_EOI | 0206 0020h | 40B0 0020h | 40B1 0020h | |
24h | I2C_IRQSTATUS_RAW | 0206 0024h | 40B0 0024h | 40B1 0024h | |
28h | I2C_IRQSTATUS | 0206 0028h | 40B0 0028h | 40B1 0028h | |
2Ch | I2C_IRQENABLE_SET | 0206 002Ch | 40B0 002Ch | 40B1 002Ch | |
30h | I2C_IRQENABLE_CLR | 0206 0030h | 40B0 0030h | 40B1 0030h | |
34h | I2C_WE | 0206 0034h | 40B0 0034h | 40B1 0034h | |
38h | I2C_DMARXENABLE_SET | 0206 0038h | 40B0 0038h | 40B1 0038h | |
3Ch | I2C_DMATXENABLE_SET | 0206 003Ch | 40B0 003Ch | 40B1 003Ch | |
40h | I2C_DMARXENABLE_CLR | 0206 0040h | 40B0 0040h | 40B1 0040h | |
44h | I2C_DMATXENABLE_CLR | 0206 0044h | 40B0 0044h | 40B1 0044h | |
48h | I2C_DMARXWAKE_EN | 0206 0048h | 40B0 0048h | 40B1 0048h | |
4Ch | I2C_DMATXWAKE_EN | 0206 004Ch | 40B0 004Ch | 40B1 004Ch | |
84h | I2C_IE | 0206 0084h | 40B0 0084h | 40B1 0084h | |
88h | I2C_STAT | 0206 0088h | 40B0 0088h | 40B1 0088h | |
90h | I2C_SYSS | 0206 0090h | 40B0 0090h | 40B1 0090h | |
94h | I2C_BUF | 0206 0094h | 40B0 0094h | 40B1 0094h | |
98h | I2C_CNT | 0206 0098h | 40B0 0098h | 40B1 0098h | |
9Ch | I2C_DATA | 0206 009Ch | 40B0 009Ch | 40B1 009Ch | |
A4h | I2C_CON | 0206 00A4h | 40B0 00A4h | 40B1 00A4h | |
A8h | I2C_OA | 0206 00A8h | 40B0 00A8h | 40B1 00A8h | |
ACh | I2C_SA | 0206 00ACh | 40B0 00ACh | 40B1 00ACh | |
B0h | I2C_PSC | 0206 00B0h | 40B0 00B0h | 40B1 00B0h | |
B4h | I2C_SCLL | 0206 00B4h | 40B0 00B4h | 40B1 00B4h | |
B8h | I2C_SCLH | 0206 00B8h | 40B0 00B8h | 40B1 00B8h | |
BCh | I2C_SYSTEST | 0206 00BCh | 40B0 00BCh | 40B1 00BCh | |
C0h | I2C_BUFSTAT | 0206 00C0h | 40B0 00C0h | 40B1 00C0h | |
C4h | I2C_OA1 | 0206 00C4h | 40B0 00C4h | 40B1 00C4h | |
C8h | I2C_OA2 | 0206 00C8h | 40B0 00C8h | 40B1 00C8h | |
CCh | I2C_OA3 | 0206 00CCh | 40B0 00CCh | 40B1 00CCh | |
D0h | I2C_ACTOA | 0206 00D0h | 40B0 00D0h | 40B1 00D0h | |
D4h | I2C_SBLOCK | 0206 00D4h | 40B0 00D4h | 40B1 00D4h |
Offset | Acronym | Register Name | WKUP_I2C0_CFG Physical Address |
---|---|---|---|
0h | I2C_REVNB_LO | 4212 0000h | |
4h | I2C_REVNB_HI | 4212 0004h | |
10h | I2C_SYSC | 4212 0010h | |
20h | I2C_EOI | 4212 0020h | |
24h | I2C_IRQSTATUS_RAW | 4212 0024h | |
28h | I2C_IRQSTATUS | 4212 0028h | |
2Ch | I2C_IRQENABLE_SET | 4212 002Ch | |
30h | I2C_IRQENABLE_CLR | 4212 0030h | |
34h | I2C_WE | 4212 0034h | |
38h | I2C_DMARXENABLE_SET | 4212 0038h | |
3Ch | I2C_DMATXENABLE_SET | 4212 003Ch | |
40h | I2C_DMARXENABLE_CLR | 4212 0040h | |
44h | I2C_DMATXENABLE_CLR | 4212 0044h | |
48h | I2C_DMARXWAKE_EN | 4212 0048h | |
4Ch | I2C_DMATXWAKE_EN | 4212 004Ch | |
84h | I2C_IE | 4212 0084h | |
88h | I2C_STAT | 4212 0088h | |
90h | I2C_SYSS | 4212 0090h | |
94h | I2C_BUF | 4212 0094h | |
98h | I2C_CNT | 4212 0098h | |
9Ch | I2C_DATA | 4212 009Ch | |
A4h | I2C_CON | 4212 00A4h | |
A8h | I2C_OA | 4212 00A8h | |
ACh | I2C_SA | 4212 00ACh | |
B0h | I2C_PSC | 4212 00B0h | |
B4h | I2C_SCLL | 4212 00B4h | |
B8h | I2C_SCLH | 4212 00B8h | |
BCh | I2C_SYSTEST | 4212 00BCh | |
C0h | I2C_BUFSTAT | 4212 00C0h | |
C4h | I2C_OA1 | 4212 00C4h | |
C8h | I2C_OA2 | 4212 00C8h | |
CCh | I2C_OA3 | 4212 00CCh | |
D0h | I2C_ACTOA | 4212 00D0h | |
D4h | I2C_SBLOCK | 4212 00D4h |
I2C_REVNB_LO is shown in Figure 12-138 and described in Table 12-256.
Return to Summary Table.
Revision Number register (Low)
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0000h |
I2C1_CFG | 0201 0000h |
I2C2_CFG | 0202 0000h |
I2C3_CFG | 0203 0000h |
I2C4_CFG | 0204 0000h |
I2C5_CFG | 0205 0000h |
I2C6_CFG | 0206 0000h |
MCU_I2C0_CFG | 40B0 0000h |
MCU_I2C1_CFG | 40B1 0000h |
WKUP_I2C0_CFG | 4212 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R-1h | R-0h | R-0h | R-Ch | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-11 | RTL | R | 1h | RTL version This field changes on bug fix, and resets to |
10-8 | MAJOR | R | 0h | Major Revision This field changes when there is a major feature change This field does not change due to bug fix, or minor feature change |
7-6 | CUSTOM | R | 0h | Indicates a special version for a particular device Consequence of use may avoid use of standard Chip Support Library [CSL] / Drivers 0 if non-custom |
5-0 | MINOR | R | Ch | Minor Revision This field changes when features are scaled up or down This field does not change due to bug fix, or major feature change |
I2C_REVNB_HI is shown in Figure 12-139 and described in Table 12-258.
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Revision Number register (High)
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0004h |
I2C1_CFG | 0201 0004h |
I2C2_CFG | 0202 0004h |
I2C3_CFG | 0203 0004h |
I2C4_CFG | 0204 0004h |
I2C5_CFG | 0205 0004h |
I2C6_CFG | 0206 0004h |
MCU_I2C0_CFG | 40B0 0004h |
MCU_I2C1_CFG | 40B1 0004h |
WKUP_I2C0_CFG | 4212 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SCHEME | RESERVED | FUNC | |||||
R-1h | R-1h | R-40h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FUNC | |||||||
R-40h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-14 | SCHEME | R | 1h | Used to distinguish between old Scheme and current Spare bit to encode future schemes |
13-12 | RESERVED | R | 1h | Reads return 0x1 |
11-0 | FUNC | R | 40h | Function: Indicates a software compatible module family |
I2C_SYSC is shown in Figure 12-140 and described in Table 12-260.
Return to Summary Table.
System Configuration register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0010h |
I2C1_CFG | 0201 0010h |
I2C2_CFG | 0202 0010h |
I2C3_CFG | 0203 0010h |
I2C4_CFG | 0204 0010h |
I2C5_CFG | 0205 0010h |
I2C6_CFG | 0206 0010h |
MCU_I2C0_CFG | 40B0 0010h |
MCU_I2C1_CFG | 40B1 0010h |
WKUP_I2C0_CFG | 4212 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CLKACTIVITY | ||||||
R-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | IDLEMODE | ENAWAKEUP | SRST | AUTOIDLE | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-10 | RESERVED | R | 0h | Reserved |
9-8 | CLKACTIVITY | R/W | 0h | Clock Activity selection bits |
7-5 | RESERVED | R | 0h | Reads return 0 |
4-3 | IDLEMODE | R/W | 0h | Idle Mode selection bits |
2 | ENAWAKEUP | R/W | 0h | Enable Wakeup control bit |
1 | SRST | R/W | 0h | SoftReset bit |
0 | AUTOIDLE | R/W | 1h | Autoidle bit |
I2C_EOI is shown in Figure 12-141 and described in Table 12-262.
Return to Summary Table.
End Of Interrupt number specification
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0020h |
I2C1_CFG | 0201 0020h |
I2C2_CFG | 0202 0020h |
I2C3_CFG | 0203 0020h |
I2C4_CFG | 0204 0020h |
I2C5_CFG | 0205 0020h |
I2C6_CFG | 0206 0020h |
MCU_I2C0_CFG | 40B0 0020h |
MCU_I2C1_CFG | 40B1 0020h |
WKUP_I2C0_CFG | 4212 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINE_NUMBER | ||||||
R-0h | W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-1 | RESERVED | R | 0h | Reserved |
0 | LINE_NUMBER | W | 0h | Software End Of Interrupt [EOI] control Write number of interrupt output |
I2C_IRQSTATUS_RAW is shown in Figure 12-142 and described in Table 12-264.
Return to Summary Table.
Per-event raw interrupt status vector
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0024h |
I2C1_CFG | 0201 0024h |
I2C2_CFG | 0202 0024h |
I2C3_CFG | 0203 0024h |
I2C4_CFG | 0204 0024h |
I2C5_CFG | 0205 0024h |
I2C6_CFG | 0206 0024h |
MCU_I2C0_CFG | 40B0 0024h |
MCU_I2C1_CFG | 40B1 0024h |
WKUP_I2C0_CFG | 4212 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | BB | ROVR | XUDF | AAS | BF |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR | STC | GC | XRDY | RRDY | ARDY | NACK | AL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility Read returns 0 |
14 | XDR | R/W | 0h | Transmit draining IRQ status |
13 | RDR | R/W | 0h | Receive draining IRQ status |
12 | BB | R | 0h | Bus busy statusWriting into this bit has no effect |
11 | ROVR | R/W | 0h | Receive overrun statusWriting into this bit has no effect |
10 | XUDF | R/W | 0h | Transmit underflow statusWriting into this bit has no effect |
9 | AAS | R/W | 0h | Address recognized as slave IRQ status |
8 | BF | R/W | 0h | Bus Free IRQ status |
7 | AERR | R/W | 0h | Access Error IRQ status |
6 | STC | R/W | 0h | Start Condition IRQ status |
5 | GC | R/W | 0h | General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear |
4 | XRDY | R/W | 0h | Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear |
3 | RRDY | R/W | 0h | Receive data ready IRQ status Set to '1' by core when receiver mode, a new data is able to be read When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear |
2 | ARDY | R/W | 0h | Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear |
1 | NACK | R/W | 0h | No acknowledgement IRQ status Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS Write '1' to clear this bit |
0 | AL | R/W | 0h | Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS During reads, it always returns 0 |
I2C_IRQSTATUS is shown in Figure 12-143 and described in Table 12-266.
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Per-event enabled interrupt status vector
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0028h |
I2C1_CFG | 0201 0028h |
I2C2_CFG | 0202 0028h |
I2C3_CFG | 0203 0028h |
I2C4_CFG | 0204 0028h |
I2C5_CFG | 0205 0028h |
I2C6_CFG | 0206 0028h |
MCU_I2C0_CFG | 40B0 0028h |
MCU_I2C1_CFG | 40B1 0028h |
WKUP_I2C0_CFG | 4212 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | BB | ROVR | XUDF | AAS | BF |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR | STC | GC | XRDY | RRDY | ARDY | NACK | AL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility Read returns 0 |
14 | XDR | R/W | 0h | Transmit draining IRQ enabled status |
13 | RDR | R/W | 0h | Receive draining IRQ enabled status |
12 | BB | R | 0h | Bus busy enabled statusWriting into this bit has no effect |
11 | ROVR | R/W | 0h | Receive overrun enabled statusWriting into this bit has no effect |
10 | XUDF | R/W | 0h | Transmit underflow enabled statusWriting into this bit has no effect |
9 | AAS | R/W | 0h | Address recognized as slave IRQ enabled status |
8 | BF | R/W | 0h | Bus Free IRQ enabled status |
7 | AERR | R/W | 0h | Access Error IRQ enabled status |
6 | STC | R/W | 0h | Start Condition IRQ enabled status |
5 | GC | R/W | 0h | General call IRQ enabled status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear |
4 | XRDY | R/W | 0h | Transmit data ready IRQ enabled status Set to '1' by core when transmitter and when new data is requested When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear |
3 | RRDY | R/W | 0h | Receive data ready IRQ enabled status Set to '1' by core when receiver mode, a new data is able to be read When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear |
2 | ARDY | R/W | 0h | Register access ready IRQ enabled status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear |
1 | NACK | R/W | 0h | No acknowledgement IRQ enabled status Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS Write '1' to clear this bit |
0 | AL | R/W | 0h | Arbitration lost IRQ enabled status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS During reads, it always returns 0 |
I2C_IRQENABLE_SET is shown in Figure 12-144 and described in Table 12-268.
Return to Summary Table.
Per-event interrupt enable bit vector.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 002Ch |
I2C1_CFG | 0201 002Ch |
I2C2_CFG | 0202 002Ch |
I2C3_CFG | 0203 002Ch |
I2C4_CFG | 0204 002Ch |
I2C5_CFG | 0205 002Ch |
I2C6_CFG | 0206 002Ch |
MCU_I2C0_CFG | 40B0 002Ch |
MCU_I2C1_CFG | 40B1 002Ch |
WKUP_I2C0_CFG | 4212 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR_IE | RDR_IE | RESERVED | ROVR | XUDF | ASS_IE | BF_IE |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR_IE | STC_IE | GC_IE | XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE | AL_IE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility Read returns 0 |
14 | XDR_IE | R/W | 0h | Transmit Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR] |
13 | RDR_IE | R/W | 0h | Receive Draining interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR] |
12 | RESERVED | R | 0h | reserved |
11 | ROVR | R/W | 0h | Receive overrun enable set |
10 | XUDF | R/W | 0h | Transmit underflow enable set |
9 | ASS_IE | R/W | 0h | Addressed as Slave interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS] |
8 | BF_IE | R/W | 0h | Bus Free interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[BF] |
7 | AERR_IE | R/W | 0h | Access Error interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR] |
6 | STC_IE | R/W | 0h | Start Condition interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[STC] |
5 | GC_IE | R/W | 0h | General call Interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[GC] |
4 | XRDY_IE | R/W | 0h | Transmit data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY] |
3 | RRDY_IE | R/W | 0h | Receive data ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY] |
2 | ARDY_IE | R/W | 0h | Register access ready interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY] |
1 | NACK_IE | R/W | 0h | No acknowledgement interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK] |
0 | AL_IE | R/W | 0h | Arbitration lost interrupt enable set Mask or unmask the interrupt signaled by bit in I2C_STAT[AL] |
I2C_IRQENABLE_CLR is shown in Figure 12-145 and described in Table 12-270.
Return to Summary Table.
Per-event interrupt clear bit vector.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0030h |
I2C1_CFG | 0201 0030h |
I2C2_CFG | 0202 0030h |
I2C3_CFG | 0203 0030h |
I2C4_CFG | 0204 0030h |
I2C5_CFG | 0205 0030h |
I2C6_CFG | 0206 0030h |
MCU_I2C0_CFG | 40B0 0030h |
MCU_I2C1_CFG | 40B1 0030h |
WKUP_I2C0_CFG | 4212 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR_IE | RDR_IE | RESERVED | ROVR | XUDF | ASS_IE | BF_IE |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR_IE | STC_IE | GC_IE | XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE | AL_IE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility Read returns 0 |
14 | XDR_IE | R/W | 0h | Transmit Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR] |
13 | RDR_IE | R/W | 0h | Receive Draining interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR] |
12 | RESERVED | R | 0h | reserved |
11 | ROVR | R/W | 0h | Receive overrun enable clear |
10 | XUDF | R/W | 0h | Transmit underflow enable clear |
9 | ASS_IE | R/W | 0h | Addressed as Slave interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS] |
8 | BF_IE | R/W | 0h | Bus Free interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[BF] |
7 | AERR_IE | R/W | 0h | Access Error interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR] |
6 | STC_IE | R/W | 0h | Start Condition interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[STC] |
5 | GC_IE | R/W | 0h | General call Interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[GC] |
4 | XRDY_IE | R/W | 0h | Transmit data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY] |
3 | RRDY_IE | R/W | 0h | Receive data ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY] |
2 | ARDY_IE | R/W | 0h | Register access ready interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY] |
1 | NACK_IE | R/W | 0h | No acknowledgement interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK] |
0 | AL_IE | R/W | 0h | Arbitration lost interrupt enable clear Mask or unmask the interrupt signaled by bit in I2C_STAT[AL] |
I2C_WE is shown in Figure 12-146 and described in Table 12-272.
Return to Summary Table.
I2C wakeup enable vector (legacy).
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0034h |
I2C1_CFG | 0201 0034h |
I2C2_CFG | 0202 0034h |
I2C3_CFG | 0203 0034h |
I2C4_CFG | 0204 0034h |
I2C5_CFG | 0205 0034h |
I2C6_CFG | 0206 0034h |
MCU_I2C0_CFG | 40B0 0034h |
MCU_I2C1_CFG | 40B1 0034h |
WKUP_I2C0_CFG | 4212 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | RESERVED | ROVR | XUDF | AAS | BF |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STC | GC | RESERVED | DRDY | ARDY | NACK | AL |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R | 0h | Reserved |
14 | XDR | R/W | 0h | Transmit Draining wakeup set |
13 | RDR | R/W | 0h | Receive Draining wakeup set |
12 | RESERVED | R | 0h | Reserved |
11 | ROVR | R/W | 0h | Receive overrun wakeup set |
10 | XUDF | R/W | 0h | Transmit underflow wakeup set |
9 | AAS | R/W | 0h | Address as slave IRQ wakeup set |
8 | BF | R/W | 0h | Bus Free IRQ wakeup set |
7 | RESERVED | R | 0h | Reserved |
6 | STC | R/W | 0h | Start Condition IRQ wakeup set |
5 | GC | R/W | 0h | General call IRQ wakeup set |
4 | RESERVED | R | 0h | Reserved |
3 | DRDY | R/W | 0h | Receive/Transmit data ready IRQ wakeup set |
2 | ARDY | R/W | 0h | Register access ready IRQ wakeup set |
1 | NACK | R/W | 0h | No acknowledgment IRQ wakeup set |
0 | AL | R/W | 0h | Arbitration lost IRQ wakeup set |
I2C_DMARXENABLE_SET is shown in Figure 12-147 and described in Table 12-274.
Return to Summary Table.
Per-event DMA RX enable set.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0038h |
I2C1_CFG | 0201 0038h |
I2C2_CFG | 0202 0038h |
I2C3_CFG | 0203 0038h |
I2C4_CFG | 0204 0038h |
I2C5_CFG | 0205 0038h |
I2C6_CFG | 0206 0038h |
MCU_I2C0_CFG | 40B0 0038h |
MCU_I2C1_CFG | 40B1 0038h |
WKUP_I2C0_CFG | 4212 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMARX_ENABLE_SET | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-1 | RESERVED | R | 0h | Reserved |
0 | DMARX_ENABLE_SET | R/W | 0h | Receive DMA channel enable set |
I2C_DMATXENABLE_SET is shown in Figure 12-148 and described in Table 12-276.
Return to Summary Table.
Per-event DMA TX enable set.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 003Ch |
I2C1_CFG | 0201 003Ch |
I2C2_CFG | 0202 003Ch |
I2C3_CFG | 0203 003Ch |
I2C4_CFG | 0204 003Ch |
I2C5_CFG | 0205 003Ch |
I2C6_CFG | 0206 003Ch |
MCU_I2C0_CFG | 40B0 003Ch |
MCU_I2C1_CFG | 40B1 003Ch |
WKUP_I2C0_CFG | 4212 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMATX_ENABLE_SET | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-1 | RESERVED | R | 0h | Reserved |
0 | DMATX_ENABLE_SET | R/W | 0h | Transmit DMA channel enable set |
I2C_DMARXENABLE_CLR is shown in Figure 12-149 and described in Table 12-278.
Return to Summary Table.
Per-event DMA RX enable clear.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0040h |
I2C1_CFG | 0201 0040h |
I2C2_CFG | 0202 0040h |
I2C3_CFG | 0203 0040h |
I2C4_CFG | 0204 0040h |
I2C5_CFG | 0205 0040h |
I2C6_CFG | 0206 0040h |
MCU_I2C0_CFG | 40B0 0040h |
MCU_I2C1_CFG | 40B1 0040h |
WKUP_I2C0_CFG | 4212 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMARX_ENABLE_CLEAR | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-1 | RESERVED | R | 0h | Reserved |
0 | DMARX_ENABLE_CLEAR | R/W | 0h | Receive DMA channel enable clear |
I2C_DMATXENABLE_CLR is shown in Figure 12-150 and described in Table 12-280.
Return to Summary Table.
Per-event DMA TX enable clear.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0044h |
I2C1_CFG | 0201 0044h |
I2C2_CFG | 0202 0044h |
I2C3_CFG | 0203 0044h |
I2C4_CFG | 0204 0044h |
I2C5_CFG | 0205 0044h |
I2C6_CFG | 0206 0044h |
MCU_I2C0_CFG | 40B0 0044h |
MCU_I2C1_CFG | 40B1 0044h |
WKUP_I2C0_CFG | 4212 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DMATX_ENABLE_CLEAR | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-1 | RESERVED | R | 0h | Reserved |
0 | DMATX_ENABLE_CLEAR | R/W | 0h | Transmit DMA channel enable clear |
I2C_DMARXWAKE_EN is shown in Figure 12-151 and described in Table 12-282.
Return to Summary Table.
Per-event DMA RX wakeup enable.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0048h |
I2C1_CFG | 0201 0048h |
I2C2_CFG | 0202 0048h |
I2C3_CFG | 0203 0048h |
I2C4_CFG | 0204 0048h |
I2C5_CFG | 0205 0048h |
I2C6_CFG | 0206 0048h |
MCU_I2C0_CFG | 40B0 0048h |
MCU_I2C1_CFG | 40B1 0048h |
WKUP_I2C0_CFG | 4212 0048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | RESERVED | ROVR | XUDF | AAS | BF |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STC | GC | RESERVED | DRDY | ARDY | NACK | AL |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R | 0h | Reserved |
14 | XDR | R/W | 0h | Transmit Draining wakeup set |
13 | RDR | R/W | 0h | Receive Draining wakeup set |
12 | RESERVED | R | 0h | Reserved |
11 | ROVR | R/W | 0h | Receive overrun wakeup set |
10 | XUDF | R/W | 0h | Transmit underflow wakeup set |
9 | AAS | R/W | 0h | Address as slave IRQ wakeup set |
8 | BF | R/W | 0h | Bus Free IRQ wakeup set |
7 | RESERVED | R | 0h | Reserved |
6 | STC | R/W | 0h | Start Condition IRQ wakeup set |
5 | GC | R/W | 0h | General call IRQ wakeup set |
4 | RESERVED | R | 0h | Reserved |
3 | DRDY | R/W | 0h | Receive/Transmit data ready IRQ wakeup set |
2 | ARDY | R/W | 0h | Register access ready IRQ wakeup set |
1 | NACK | R/W | 0h | No acknowledgment IRQ wakeup set |
0 | AL | R/W | 0h | Arbitration lost IRQ wakeup set |
I2C_DMATXWAKE_EN is shown in Figure 12-152 and described in Table 12-284.
Return to Summary Table.
Per-event DMA TX wakeup enable.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 004Ch |
I2C1_CFG | 0201 004Ch |
I2C2_CFG | 0202 004Ch |
I2C3_CFG | 0203 004Ch |
I2C4_CFG | 0204 004Ch |
I2C5_CFG | 0205 004Ch |
I2C6_CFG | 0206 004Ch |
MCU_I2C0_CFG | 40B0 004Ch |
MCU_I2C1_CFG | 40B1 004Ch |
WKUP_I2C0_CFG | 4212 004Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | RESERVED | ROVR | XUDF | AAS | BF |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | STC | GC | RESERVED | DRDY | ARDY | NACK | AL |
R-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R | 0h | Reserved |
14 | XDR | R/W | 0h | Transmit Draining wakeup set |
13 | RDR | R/W | 0h | Receive Draining wakeup set |
12 | RESERVED | R | 0h | Reserved |
11 | ROVR | R/W | 0h | Receive overrun wakeup set |
10 | XUDF | R/W | 0h | Transmit underflow wakeup set |
9 | AAS | R/W | 0h | Address as slave IRQ wakeup set |
8 | BF | R/W | 0h | Bus Free IRQ wakeup set |
7 | RESERVED | R | 0h | Reserved |
6 | STC | R/W | 0h | Start Condition IRQ wakeup set |
5 | GC | R/W | 0h | General call IRQ wakeup set |
4 | RESERVED | R | 0h | Reserved |
3 | DRDY | R/W | 0h | Receive/Transmit data ready IRQ wakeup set |
2 | ARDY | R/W | 0h | Register access ready IRQ wakeup set |
1 | NACK | R/W | 0h | No acknowledgment IRQ wakeup set |
0 | AL | R/W | 0h | Arbitration lost IRQ wakeup set |
I2C_IE is shown in Figure 12-153 and described in Table 12-286.
Return to Summary Table.
I2C interrupt enable vector (legacy).
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0084h |
I2C1_CFG | 0201 0084h |
I2C2_CFG | 0202 0084h |
I2C3_CFG | 0203 0084h |
I2C4_CFG | 0204 0084h |
I2C5_CFG | 0205 0084h |
I2C6_CFG | 0206 0084h |
MCU_I2C0_CFG | 40B0 0084h |
MCU_I2C1_CFG | 40B1 0084h |
WKUP_I2C0_CFG | 4212 0084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR_IE | RDR_IE | RESERVED | ROVR | XUDF | ASS_IE | BF_IE |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR_IE | STC_IE | GC_IE | XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE | AL_IE |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility Read returns 0 |
14 | XDR_IE | R/W | 0h | Transmit Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XDR] |
13 | RDR_IE | R/W | 0h | Receive Draining interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RDR] |
12 | RESERVED | R | 0h | reserved |
11 | ROVR | R/W | 0h | Receive overrun enable set |
10 | XUDF | R/W | 0h | Transmit underflow enable set |
9 | ASS_IE | R/W | 0h | Addressed as Slave interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AAS] |
8 | BF_IE | R/W | 0h | Bus Free interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[BF] |
7 | AERR_IE | R/W | 0h | Access Error interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AERR] |
6 | STC_IE | R/W | 0h | Start Condition interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[STC] |
5 | GC_IE | R/W | 0h | General call Interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[GC] |
4 | XRDY_IE | R/W | 0h | Transmit data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[XRDY] |
3 | RRDY_IE | R/W | 0h | Receive data ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[RRDY] |
2 | ARDY_IE | R/W | 0h | Register access ready interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[ARDY] |
1 | NACK_IE | R/W | 0h | No acknowledgement interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[NACK] |
0 | AL_IE | R/W | 0h | Arbitration lost interrupt enable Mask or unmask the interrupt signaled by bit in I2C_STAT[AL] |
I2C_STAT is shown in Figure 12-154 and described in Table 12-288.
Return to Summary Table.
I2C interrupt status vector (legacy).
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0088h |
I2C1_CFG | 0201 0088h |
I2C2_CFG | 0202 0088h |
I2C3_CFG | 0203 0088h |
I2C4_CFG | 0204 0088h |
I2C5_CFG | 0205 0088h |
I2C6_CFG | 0206 0088h |
MCU_I2C0_CFG | 40B0 0088h |
MCU_I2C1_CFG | 40B1 0088h |
WKUP_I2C0_CFG | 4212 0088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | XDR | RDR | BB | ROVR | XUDF | AAS | BF |
R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AERR | STC | GC | XRDY | RRDY | ARDY | NACK | AL |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RESERVED | R/W | 0h | Write 0s for future compatibility Read returns 0 |
14 | XDR | R/W | 0h | Transmit draining IRQ status |
13 | RDR | R/W | 0h | Receive draining IRQ status |
12 | BB | R | 0h | Bus busy statusWriting into this bit has no effect |
11 | ROVR | R/W | 0h | Receive overrun statusWriting into this bit has no effect |
10 | XUDF | R/W | 0h | Transmit underflow statusWriting into this bit has no effect |
9 | AAS | R/W | 0h | Address recognized as slave IRQ status |
8 | BF | R/W | 0h | Bus Free IRQ status |
7 | AERR | R/W | 0h | Access Error IRQ status |
6 | STC | R/W | 0h | Start Condition IRQ status |
5 | GC | R/W | 0h | General call IRQ status Set to '1' by core when General call address detected and interrupt signaled to MPUSS Write '1' to clear |
4 | XRDY | R/W | 0h | Transmit data ready IRQ status Set to '1' by core when transmitter and when new data is requested When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear |
3 | RRDY | R/W | 0h | Receive data ready IRQ status Set to '1' by core when receiver mode, a new data is able to be read When set to '1' by core, an interrupt is signaled to MPUSS Write '1' to clear |
2 | ARDY | R/W | 0h | Register access ready IRQ status When set to '1' it indicates that previous access has been performed and registers are ready to be accessed again An interrupt is signaled to MPUSS Write '1' to clear |
1 | NACK | R/W | 0h | No acknowledgement IRQ status Bit is set when No Acknowledge has been received, an interrupt is signaled to MPUSS Write '1' to clear this bit |
0 | AL | R/W | 0h | Arbitration lost IRQ status This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to MPUSS During reads, it always returns 0 |
I2C_SYSS is shown in Figure 12-155 and described in Table 12-290.
Return to Summary Table.
System Status register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0090h |
I2C1_CFG | 0201 0090h |
I2C2_CFG | 0202 0090h |
I2C3_CFG | 0203 0090h |
I2C4_CFG | 0204 0090h |
I2C5_CFG | 0205 0090h |
I2C6_CFG | 0206 0090h |
MCU_I2C0_CFG | 40B0 0090h |
MCU_I2C1_CFG | 40B1 0090h |
WKUP_I2C0_CFG | 4212 0090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RDONE | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-1 | RESERVED | R | 0h | Reserved |
0 | RDONE | R | 0h | Reset done bit |
I2C_BUF is shown in Figure 12-156 and described in Table 12-292.
Return to Summary Table.
Buffer Configuration register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0094h |
I2C1_CFG | 0201 0094h |
I2C2_CFG | 0202 0094h |
I2C3_CFG | 0203 0094h |
I2C4_CFG | 0204 0094h |
I2C5_CFG | 0205 0094h |
I2C6_CFG | 0206 0094h |
MCU_I2C0_CFG | 40B0 0094h |
MCU_I2C1_CFG | 40B1 0094h |
WKUP_I2C0_CFG | 4212 0094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RDMA_EN | RXFIFO_CLR | RXTRSH | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XDMA_EN | TXFIFO_CLR | TXTRSH | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | RDMA_EN | R/W | 0h | Receive DMA channel enable |
14 | RXFIFO_CLR | R/W | 0h | Receive FIFO clear |
13-8 | RXTRSH | R/W | 0h | Threshold value for FIFO buffer in RX mode |
7 | XDMA_EN | R/W | 0h | Transmit DMA channel enable |
6 | TXFIFO_CLR | R/W | 0h | Transmit FIFO clear |
5-0 | TXTRSH | R/W | 0h | Threshold value for FIFO buffer in TX mode |
I2C_CNT is shown in Figure 12-157 and described in Table 12-294.
Return to Summary Table.
Data counter register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 0098h |
I2C1_CFG | 0201 0098h |
I2C2_CFG | 0202 0098h |
I2C3_CFG | 0203 0098h |
I2C4_CFG | 0204 0098h |
I2C5_CFG | 0205 0098h |
I2C6_CFG | 0206 0098h |
MCU_I2C0_CFG | 40B0 0098h |
MCU_I2C1_CFG | 40B1 0098h |
WKUP_I2C0_CFG | 4212 0098h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DCOUNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | DCOUNT | R/W | 0h | Data count |
I2C_DATA is shown in Figure 12-158 and described in Table 12-296.
Return to Summary Table.
Data access register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 009Ch |
I2C1_CFG | 0201 009Ch |
I2C2_CFG | 0202 009Ch |
I2C3_CFG | 0203 009Ch |
I2C4_CFG | 0204 009Ch |
I2C5_CFG | 0205 009Ch |
I2C6_CFG | 0206 009Ch |
MCU_I2C0_CFG | 40B0 009Ch |
MCU_I2C1_CFG | 40B1 009Ch |
WKUP_I2C0_CFG | 4212 009Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | DATA | |||||||||||||||||||||||||||||
R/W-X | R-0h | R/W-0h | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | R/W | 0h | Transmit/Receive data FIFO endpoint |
I2C_CON is shown in Figure 12-159 and described in Table 12-298.
Return to Summary Table.
I2C configuration register.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00A4h |
I2C1_CFG | 0201 00A4h |
I2C2_CFG | 0202 00A4h |
I2C3_CFG | 0203 00A4h |
I2C4_CFG | 0204 00A4h |
I2C5_CFG | 0205 00A4h |
I2C6_CFG | 0206 00A4h |
MCU_I2C0_CFG | 40B0 00A4h |
MCU_I2C1_CFG | 40B1 00A4h |
WKUP_I2C0_CFG | 4212 00A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
I2C_EN | RESERVED | OPMODE | STB | MST | TRX | XSA | |
R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
XOA0 | XOA1 | XOA2 | XOA3 | RESERVED | STP | STT | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | I2C_EN | R/W | 0h | I2C module enable |
14 | RESERVED | R | 0h | Reserved |
13-12 | OPMODE | R/W | 0h | Operation mode selection |
11 | STB | R/W | 0h | Start byte mode [master mode only] |
10 | MST | R/W | 0h | Master/slave mode |
9 | TRX | R/W | 0h | Transmitter/Receiver mode [master mode only] |
8 | XSA | R/W | 0h | Expand Slave address |
7 | XOA0 | R/W | 0h | Expand Own address 0 |
6 | XOA1 | R/W | 0h | Expand Own address 1 |
5 | XOA2 | R/W | 0h | Expand Own address 2 |
4 | XOA3 | R/W | 0h | Expand Own address 3 |
3-2 | RESERVED | R | 0h | Reserved |
1 | STP | R/W | 0h | Stop condition [master mode only] |
0 | STT | R/W | 0h | Start condition [master mode only] |
I2C_OA is shown in Figure 12-160 and described in Table 12-300.
Return to Summary Table.
Own address register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00A8h |
I2C1_CFG | 0201 00A8h |
I2C2_CFG | 0202 00A8h |
I2C3_CFG | 0203 00A8h |
I2C4_CFG | 0204 00A8h |
I2C5_CFG | 0205 00A8h |
I2C6_CFG | 0206 00A8h |
MCU_I2C0_CFG | 40B0 00A8h |
MCU_I2C1_CFG | 40B1 00A8h |
WKUP_I2C0_CFG | 4212 00A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCODE | RESERVED | OA | |||||||||||||
R/W-0h | R-0h | R/W-0h | |||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-13 | MCODE | R/W | 0h | Master Code |
12-10 | RESERVED | R | 0h | Reserved |
9-0 | OA | R/W | 0h | Own address |
I2C_SA is shown in Figure 12-161 and described in Table 12-302.
Return to Summary Table.
Slave address register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00ACh |
I2C1_CFG | 0201 00ACh |
I2C2_CFG | 0202 00ACh |
I2C3_CFG | 0203 00ACh |
I2C4_CFG | 0204 00ACh |
I2C5_CFG | 0205 00ACh |
I2C6_CFG | 0206 00ACh |
MCU_I2C0_CFG | 40B0 00ACh |
MCU_I2C1_CFG | 40B1 00ACh |
WKUP_I2C0_CFG | 4212 00ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SA | ||||||||||||||
R-0h | R/W-3FFh | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-10 | RESERVED | R | 0h | Reserved |
9-0 | SA | R/W | 3FFh | Slave address |
I2C_PSC is shown in Figure 12-162 and described in Table 12-304.
Return to Summary Table.
I2C Clock Prescaler Register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00B0h |
I2C1_CFG | 0201 00B0h |
I2C2_CFG | 0202 00B0h |
I2C3_CFG | 0203 00B0h |
I2C4_CFG | 0204 00B0h |
I2C5_CFG | 0205 00B0h |
I2C6_CFG | 0206 00B0h |
MCU_I2C0_CFG | 40B0 00B0h |
MCU_I2C1_CFG | 40B1 00B0h |
WKUP_I2C0_CFG | 4212 00B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | PSC | |||||||||||||||||||||||||||||
R/W-X | R-0h | R/W-0h | |||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | RESERVED | R | 0h | Reserved |
7-0 | PSC | R/W | 0h | Fast/Standard mode prescale sampling clock divider value 0x |
I2C_SCLL is shown in Figure 12-163 and described in Table 12-306.
Return to Summary Table.
I2C SCL Low Time Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00B4h |
I2C1_CFG | 0201 00B4h |
I2C2_CFG | 0202 00B4h |
I2C3_CFG | 0203 00B4h |
I2C4_CFG | 0204 00B4h |
I2C5_CFG | 0205 00B4h |
I2C6_CFG | 0206 00B4h |
MCU_I2C0_CFG | 40B0 00B4h |
MCU_I2C1_CFG | 40B1 00B4h |
WKUP_I2C0_CFG | 4212 00B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSSCLL | SCLL | |||||||||||||||||||||||||||||
R/W-X | R/W-0h | R/W-0h | |||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | HSSCLL | R/W | 0h | High Speed mode SCL low time |
7-0 | SCLL | R/W | 0h | Fast/Standard mode SCL low time |
I2C_SCLH is shown in Figure 12-164 and described in Table 12-308.
Return to Summary Table.
I2C SCL High Time Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00B8h |
I2C1_CFG | 0201 00B8h |
I2C2_CFG | 0202 00B8h |
I2C3_CFG | 0203 00B8h |
I2C4_CFG | 0204 00B8h |
I2C5_CFG | 0205 00B8h |
I2C6_CFG | 0206 00B8h |
MCU_I2C0_CFG | 40B0 00B8h |
MCU_I2C1_CFG | 40B1 00B8h |
WKUP_I2C0_CFG | 4212 00B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HSSCLH | SCLH | |||||||||||||||||||||||||||||
R/W-X | R/W-0h | R/W-0h | |||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | HSSCLH | R/W | 0h | High Speed mode SCL high time |
7-0 | SCLH | R/W | 0h | Fast/Standard mode SCL high time |
I2C_SYSTEST is shown in Figure 12-165 and described in Table 12-310.
Return to Summary Table.
I2C System Test Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00BCh |
I2C1_CFG | 0201 00BCh |
I2C2_CFG | 0202 00BCh |
I2C3_CFG | 0203 00BCh |
I2C4_CFG | 0204 00BCh |
I2C5_CFG | 0205 00BCh |
I2C6_CFG | 0206 00BCh |
MCU_I2C0_CFG | 40B0 00BCh |
MCU_I2C1_CFG | 40B1 00BCh |
WKUP_I2C0_CFG | 4212 00BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
ST_EN | FREE | TMODE | SSB | RESERVED | SCL_I_FUNC | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R-1h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCL_O_FUNC | SDA_I_FUNC | SDA_O_FUNC | SCCB_E_O | SCL_I | SCL_O | SDA_I | SDA_O |
R-1h | R-1h | R-1h | R/W-0h | R-0h | R/W-0h | R-0h | R/W-0h |
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15 | ST_EN | R/W | 0h | System test enable |
14 | FREE | R/W | 0h | Free running mode [on breakpoint] |
13-12 | TMODE | R/W | 0h | Test mode select |
11 | SSB | R/W | 0h | Set status bits |
10-9 | RESERVED | R | 0h | Reserved |
8 | SCL_I_FUNC | R | 1h | SCL line input value [functional mode] |
7 | SCL_O_FUNC | R | 1h | SCL line output value [functional mode] |
6 | SDA_I_FUNC | R | 1h | SDA line input value [functional mode] |
5 | SDA_O_FUNC | R | 1h | SDA line output value [functional mode] |
4 | SCCB_E_O | R/W | 0h | SCCB_E line sense output value |
3 | SCL_I | R | 0h | SCL line sense input value |
2 | SCL_O | R/W | 0h | SCL line drive output value |
1 | SDA_I | R | 0h | SDA line sense input value |
0 | SDA_O | R/W | 0h | SDA line drive output value |
I2C_BUFSTAT is shown in Figure 12-166 and described in Table 12-312.
Return to Summary Table.
I2C Buffer Status Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00C0h |
I2C1_CFG | 0201 00C0h |
I2C2_CFG | 0202 00C0h |
I2C3_CFG | 0203 00C0h |
I2C4_CFG | 0204 00C0h |
I2C5_CFG | 0205 00C0h |
I2C6_CFG | 0206 00C0h |
MCU_I2C0_CFG | 40B0 00C0h |
MCU_I2C1_CFG | 40B1 00C0h |
WKUP_I2C0_CFG | 4212 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
FIFODEPTH | RXSTAT | ||||||
R-2h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXSTAT | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-14 | FIFODEPTH | R | 2h | Internal FIFO buffers depth |
13-8 | RXSTAT | R | 0h | RX Buffer Status |
7-6 | RESERVED | R | 0h | Reserved |
5-0 | TXSTAT | R | 0h | TX Buffer Status |
I2C_OA1 is shown in Figure 12-167 and described in Table 12-314.
Return to Summary Table.
I2C Own Address 1 Register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00C4h |
I2C1_CFG | 0201 00C4h |
I2C2_CFG | 0202 00C4h |
I2C3_CFG | 0203 00C4h |
I2C4_CFG | 0204 00C4h |
I2C5_CFG | 0205 00C4h |
I2C6_CFG | 0206 00C4h |
MCU_I2C0_CFG | 40B0 00C4h |
MCU_I2C1_CFG | 40B1 00C4h |
WKUP_I2C0_CFG | 4212 00C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OA1 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-10 | RESERVED | R | 0h | Reserved |
9-0 | OA1 | R/W | 0h | Own address 1 |
I2C_OA2 is shown in Figure 12-168 and described in Table 12-316.
Return to Summary Table.
I2C Own Address 2 Register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00C8h |
I2C1_CFG | 0201 00C8h |
I2C2_CFG | 0202 00C8h |
I2C3_CFG | 0203 00C8h |
I2C4_CFG | 0204 00C8h |
I2C5_CFG | 0205 00C8h |
I2C6_CFG | 0206 00C8h |
MCU_I2C0_CFG | 40B0 00C8h |
MCU_I2C1_CFG | 40B1 00C8h |
WKUP_I2C0_CFG | 4212 00C8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OA2 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-10 | RESERVED | R | 0h | Reserved |
9-0 | OA2 | R/W | 0h | Own address 2 |
I2C_OA3 is shown in Figure 12-169 and described in Table 12-318.
Return to Summary Table.
I2C Own Address 3 Register
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00CCh |
I2C1_CFG | 0201 00CCh |
I2C2_CFG | 0202 00CCh |
I2C3_CFG | 0203 00CCh |
I2C4_CFG | 0204 00CCh |
I2C5_CFG | 0205 00CCh |
I2C6_CFG | 0206 00CCh |
MCU_I2C0_CFG | 40B0 00CCh |
MCU_I2C1_CFG | 40B1 00CCh |
WKUP_I2C0_CFG | 4212 00CCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OA3 | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-10 | RESERVED | R | 0h | Reserved |
9-0 | OA3 | R/W | 0h | Own address 3 |
I2C_ACTOA is shown in Figure 12-170 and described in Table 12-320.
Return to Summary Table.
I2C Active Own Address Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00D0h |
I2C1_CFG | 0201 00D0h |
I2C2_CFG | 0202 00D0h |
I2C3_CFG | 0203 00D0h |
I2C4_CFG | 0204 00D0h |
I2C5_CFG | 0205 00D0h |
I2C6_CFG | 0206 00D0h |
MCU_I2C0_CFG | 40B0 00D0h |
MCU_I2C1_CFG | 40B1 00D0h |
WKUP_I2C0_CFG | 4212 00D0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OA3_ACT | OA2_ACT | OA1_ACT | OA0_ACT | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-4 | RESERVED | R | 0h | Reserved |
3 | OA3_ACT | R | 0h | Own Address 3 active |
2 | OA2_ACT | R | 0h | Own Address 2 active |
1 | OA1_ACT | R | 0h | Own Address 1 active |
0 | OA0_ACT | R | 0h | Own Address 0 active |
I2C_SBLOCK is shown in Figure 12-171 and described in Table 12-322.
Return to Summary Table.
I2C Clock Blocking Enable Register.
Instance | Physical Address |
---|---|
I2C0_CFG | 0200 00D4h |
I2C1_CFG | 0201 00D4h |
I2C2_CFG | 0202 00D4h |
I2C3_CFG | 0203 00D4h |
I2C4_CFG | 0204 00D4h |
I2C5_CFG | 0205 00D4h |
I2C6_CFG | 0206 00D4h |
MCU_I2C0_CFG | 40B0 00D4h |
MCU_I2C1_CFG | 40B1 00D4h |
WKUP_I2C0_CFG | 4212 00D4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | OA3_EN | OA2_EN | OA1_EN | OA0_EN | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-4 | RESERVED | R | 0h | Reserved |
3 | OA3_EN | R/W | 0h | Enable I2C Clock Blocking for Own Address 3 |
2 | OA2_EN | R/W | 0h | Enable I2C Clock Blocking for Own Address 2 |
1 | OA1_EN | R/W | 0h | Enable I2C Clock Blocking for Own Address 1 |
0 | OA0_EN | R/W | 0h | Enable I2C Clock Blocking for Own Address 0 |