SPRUIU1 User guide

SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1

12.2.1.3 MCU_CPSW0 Integration

Figure 12-493 shows the integration of the MCU_CPSW0 module in the device.

Figure 12-493 MCU_CPSW0 Integration

The following MCU_CPSW0 control registers are located in MCU_CTRL_MMR0 module: CTRLMMR_MCU_ENET_CTRL, CTRLMMR_MCU_ENET_CLKSEL, CTRLMMR_MCU_MAC_ID0, CTRLMMR_MCU_MAC_ID1.

Table 12-928 through Table 12-930 summarize the integration of the MCU_CPSW0 module in the device.

Table 12-928 MCU_CPSW0 Integration Attributes

Module Instance		Attributes
Module Instance	Power Sleep Controller	Power Domain	Module Domain	Interconnect
MCU_CPSW0	WKUP_PSC0	PD0	LPSC0	MCU_CBASS0

Table 12-929 MCU_CPSW0 Clocks and Resets

Clocks
Module Instance	Module Clock Input	Source Clock Signal	Source	Description
MCU_CPSW0	CPPI_ICLK	MCU_SYSCLK0/3	MCU_PLLCTRL	CPPI packet streaming interface clock (333-MHz). Main clock for MCU_CPSW0.
	GMII_RFT_CLK	MCU_PLL2_HSDIV0_CLKOUT/2	MCU_PLL2 (HSDIV0 of MCU_CPSW0 PLL)	125-MHz GMII Gigabit mode clock.
	RGMII_MHZ_5_CLK	MCU_PLL2_HSDIV0_CLKOUT/50	MCU_PLL2 (HSDIV0 of MCU_CPSW0 PLL)	5-MHz RGMII reference clock.
	RGMII_MHZ_50_CLK	MCU_PLL2_HSDIV0_CLKOUT/5	MCU_PLL2 (HSDIV0 of MCU_CPSW0 PLL)	50-MHz RGMII reference clock.
	RGMII_MHZ_250_CLK	MCU_PLL2_HSDIV0_CLKOUT	MCU_PLL2 (HSDIV0 of MCU_CPSW0 PLL)	250-MHz RGMII reference clock.
	RMII_MHZ_50_CLK	MCU_RMII1_REF_CLK	MCU_RMII1_REF_CLK pad	50-MHz RMII reference clock. This clock is derived from the MCU_RMII1_REF_CLK pad.
	CPTS_RFT_CLK	MAIN_PLL3_HSDIV1_CLKOUT	HSDIV1 of CPSW0 PLL Controller, selected through CPTS Multiplexer (200 or 250-MHz clock)	CPTS IEEE 1588 clock. Selected through the CTRLMMR_MCU_ENET_CLKSEL register.
		MAIN_PLL0_HSDIV6_CLKOUT	HSDIV6 of MAIN PLL0 Controller, selected through CPTS Multiplexer (200 or 250-MHz clock)
		MCU_CPTS_RFT_CLK pad	MCU_CPTS_RFT_CLK pad, selected through CPTS Multiplexer (200-MHz clock)
		CPTS_RFT_CLK pad	CPTS_RFT_CLK pad, selected through CPTS Multiplexer (200-MHz clock)
		MCU_EXT_REFCLK0 pad	MCU_EXT_REFCLK0 pad, selected through CPTS Multiplexer (100-MHz clock)
		EXT_REFCLK1 pad	EXT_REFCLK1 pad, selected through CPTS Multiplexer (100-MHz clock)
		SERDES0_IP2_LN0_TXMCLK	SERDES0 Lane0 (500-MHz clock)
		SERDES0_IP2_LN1_TXMCLK	SERDES0 Lane1 (500-MHz clock)
		SERDES0_IP2_LN2_TXMCLK	SERDES0 Lane2 (500-MHz clock)
		SERDES0_IP2_LN3_TXMCLK	SERDES0 Lane3 (500-MHz clock)
		MCU_PLL2_HSDIV1_CLKOUT	HSDIV1 of MCU_CPSW0 PLL Controller, selected through CPTS Multiplexer (500-MHz clock)
		MCU_SYSCLK0/2	MCU_PLLCTRL (500-MHz clock)
	GMII1_MT_CLK	RGMII_MHZ_250_CLK/10	RGMII_MHZ_250_CLK	Note: GMII mode is not supported on this device. GMII1_MT_CLK transmit reference clock is needed to enable clock-stop protocol on this module.
	GMII1_MR_CLK	RGMII_MHZ_250_CLK/10	RGMII_MHZ_250_CLK	Note: GMII mode is not supported on this device. GMII1_MR_CLK receive reference clock is needed to enable clock-stop protocol on this module.
	RGMII1_RXC_I	RGMII1_RXC	MCU_RGMII1_RXC pad	RGMII reference clock that provides the timing reference for receive operations.
	RGMII1_TXC_O	RGMII1_TXC	MCU_RGMII1_TXC pad	RGMII transmit reference clock.
	MDIO_MCLK	MDIO_MCLK	MCU_MDIO0_MDC pad	Management data clock (MDIO_MCLK). The MDIO data clock is sourced by the MDIO module on the system. It is used to synchronize MDIO data access operations done on the MDIO pin.
Resets
Module Instance	Module Reset Input	Source Reset Signal	Source	Description
MCU_CPSW0	MCU_CPSW0_RST	MOD_G_RST	LPSC0	Module Reset

Table 12-930 MCU_CPSW0 Hardware Requests

Interrupt Requests
Module Instance	Module Interrupt Signal	Destination Interrupt Input	Destination	Description	Type
MCU_CPSW0	MCU_CPSW0_STAT_PEND_0	MCU_R5FSS0_CORE0_INTR_IN_32	MCU_R5FSS0_CORE0	MCU_CPSW0 statistic pending interrupt 0	Level
		MCU_R5FSS0_CORE1_INTR_IN_32	MCU_R5FSS0_CORE1
		GIC500_SPI_IN_888	GIC500
		R5FSS0_CORE0_INTR_IN_446	R5FSS0_CORE0
		R5FSS0_CORE1_INTR_IN_446	R5FSS0_CORE1
	MCU_CPSW0_MDIO_PEND_0	MCU_R5FSS0_CORE0_INTR_IN_35	MCU_R5FSS0_CORE0	MCU_CPSW0 MDIO interrupt	Level
		MCU_R5FSS0_CORE1_INTR_IN_35	MCU_R5FSS0_CORE1
		GIC500_SPI_IN_889	GIC500
		R5FSS0_CORE0_INTR_IN_447	R5FSS0_CORE0
		R5FSS0_CORE1_INTR_IN_447	R5FSS0_CORE1
	MCU_CPSW0_EVNT_PEND_0	MCU_R5FSS0_CORE0_INTR_IN_34	MCU_R5FSS0_CORE0	MCU_CPSW0 event pending interrupt	Level
		MCU_R5FSS0_CORE1_INTR_IN_34	MCU_R5FSS0_CORE1
		GIC500_SPI_IN_890	GIC500
		R5FSS0_CORE0_INTR_IN_448	R5FSS0_CORE0
		R5FSS0_CORE1_INTR_IN_448	R5FSS0_CORE1
	MCU_CPSW0_ECC_SEC_PEND_0	MCU_ESM0_LVL_IN_14	MCU_ESM0	MCU_CPSW0 SEC ECC error interrupt	Level
	MCU_CPSW0_ECC_DED_PEND_0	MCU_ESM0_LVL_IN_15	MCU_ESM0	MCU_CPSW0 DED ECC error interrupt	Level
Time Sync and Compare Events
Module Instance	Module Event	Destination Event Input	Destination	Description	Type
MCU_CPSW0	MCU_CPSW0_CPTS_COMP_0	CMPEVENT_INTRTR0_IN_10	CMPEVT_INTRTR0	MCU_CPSW0 compare event interrupt	Edge
	MCU_CPSW0_CPTS_GENF0_0	TIMESYNC_INTRTR0_IN_16	TIMESYNC_INTRTR0	MCU_CPSW0 CPTS generator function event interrupt 0	Edge
	MCU_CPSW0_CPTS_GENF1_0	TIMESYNC_INTRTR0_IN_17	TIMESYNC_INTRTR0	MCU_CPSW0 CPTS generator function event interrupt 1	Edge
	MCU_CPSW0_CPTS_SYNC_0	TIMESYNC_INTRTR0_IN_38	TIMESYNC_INTRTR0	MCU_CPSW0 CPTS sync event interrupt	Edge