To accomplish the DDR write transfer, the host must perform the following steps:
- Prepare HDR-DDR message words (each 20-bit word is LSB aligned in TX FIFO cell; set bits unspecified below to 0):
- Write command word for write HDR-DDR command to TX FIFO using following field values:
- Preamble (bits [19:18]): 0x01
- CMD (bits[17:10]): Write Command Code (from 0x00 to 0x7F)
- DA (bits[9:3]): Slave Dynamic Address
- Parity (bits[1:0]): Parity (XOR of odd and even bits of 16-bit payload)
- Write first data word to TX FIFO using following field values:
- Preamble (bits [19:18]): 0x10
- Data (bits[17:2]): 16-bit data
- Parity (bits[1:0]): Parity
- Write zero or more subsequent data words to TX FIFO using following field values:
- Preamble (bits [19:18]): 0x11
- Data (bits[17:2]): 16-bit data
- Parity (bits[1:0]): Parity
- Write CRC word to TX FIFO:
- Preamble (bits [19:18]): 0x01
- Token (bits[17:14]): Ch
- CRC (bits[13:9]): CRC5
- Repeat steps 1(a) to 1(d) as many write commands are to be sent.
- Write ENTHDR CCC command to command queue:
- Write the Command Word1 (I3C_CMD1_FIFO) of ENTHDR
CCC.
- Write the Command Word0 (I3C_CMD0_FIFO) of ENTHDR
CCC with following data fields:
- I3C_CMD0_FIFO[31] IS_DDR: 0x0
- I3C_CMD0_FIFO[30] IS_CCC: 0x1
- I3C_CMD0_FIFO[0] RNW: 0x0
- Write HDR-DDR command(s) to command queue:
- Write the Command Word1 (I3C_CMD1_FIFO).
- Write the Command Word0 (I3C_CMD0_FIFO) with
following data fields:
- I3C_CMD0_FIFO[31] IS_DDR: 0x1
- I3C_CMD0_FIFO[23-12] PL_LEN: Number of TX FIFO words
- Repeat steps 2(a) and 2(b) as many write commands are prepared in TX FIFO in step 1.
- Wait for transfer completion notified by
I3C_MST_ISR[16] IMM_COMP bit, which indicates that all data of particular
command are successfully transmitted to the slave.
If I3C_MST_ISR[16] IMM_COMP interrupt is utilized,
the controller allows the application processor to perform other tasks or sleep
while message is being sent.
In case of multiple command issued to command
queue, I3C_MST_ISR[5] CMDD_EMP interrupt may be utilized instead. It indicates
completion of all commands in command queue and allows yet more efficient
application processor resources management. It is issued simultaneously with the
I3C_MST_ISR[5] CMDD_EMP interrupt corresponding to the last command in the
queue.