SPRUIW7A October   2020  – February 2022

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Key Features
    2. 1.2 Thermal Compliance
    3. 1.3 REACH Compliance
    4. 1.4 Electrostatic Discharge (ESD) Compliance
  3. 2J7200 EVM Overview
    1. 2.1 J7200 EVM Board Identification
    2. 2.2 J7200 SOM Component Identification
    3. 2.3 Jacinto7 Common Processor Component Identification
    4. 2.4 Quad Ethernet Components Identification
  4. 3EVM User Setup/Configuration
    1. 3.1 Power Requirements
    2. 3.2 Power ON Switch and Power LEDs
      1. 3.2.1 Over Voltage and Under Voltage Protection Circuit
      2. 3.2.2 Power Regulators and Power Status LEDs
    3. 3.3 EVM Reset/Interrupt Push Buttons
    4. 3.4 EVM DIP Switches
      1. 3.4.1 EVM Configuration DIP Switch
      2. 3.4.2 SOM Configuration DIP Switch
      3. 3.4.3 Boot Modes
      4. 3.4.4 Other Selection Switches
    5. 3.5 EVM UART/COM Port Mapping
  5. 4J7200 EVM Hardware Architecture
    1. 4.1  J7200 EVM Hardware Top Level Diagram
    2. 4.2  J7200 EVM Interface Mapping
    3. 4.3  I2C Address Mapping
    4. 4.4  GPIO Mapping
    5. 4.5  Power Supply
      1. 4.5.1 Power Sequencing
      2. 4.5.2 Voltage Supervisor
      3. 4.5.3 DDR I/O Voltage Selection
      4. 4.5.4 J7200 SoC SLEEP Logic Operation
      5. 4.5.5 J7200 SoC MCU Only Operation
      6. 4.5.6 J7200 SoC GPIO Retention Operation
      7. 4.5.7 J7200 SoC DDR Retention Operation
      8. 4.5.8 Power Monitoring
      9. 4.5.9 Power Test Points
    6. 4.6  Reset
    7. 4.7  Clock
      1. 4.7.1 Processor’s Primary Clock
      2. 4.7.2 Processor’s Secondary/SERDES Ref Clock
      3. 4.7.3 EVM Peripheral Ref Clock
    8. 4.8  Memory Interfaces
      1. 4.8.1 LPDDR4 Interface
      2. 4.8.2 OSPI Interface
      3. 4.8.3 MMC Interface
        1. 4.8.3.1 MMC0 - eMMC Interface
        2. 4.8.3.2 MMC1 – Micro SD Interface
      4. 4.8.4 Board ID EEPROM Interface
      5. 4.8.5 Boot EEPROM Interface
    9. 4.9  MCU Ethernet Interface
      1. 4.9.1 Gigabit Ethernet PHY Default Configuration
    10. 4.10 QSGMII Ethernet Interface
    11. 4.11 PCIe Interface
      1. 4.11.1 X2 Lane PCIe Interface
    12. 4.12 USB Interface
      1. 4.12.1 USB 3.1 Interface
      2. 4.12.2 USB 2.0 Interface
        1. 4.12.2.1 To PCIe Card Wi-Fi/BT
        2. 4.12.2.2 To Expansion Connector
      3. 4.12.3 USB 3.0 Micro AB Interface (Reserved Port)
    13. 4.13 Audio Interface
      1. 4.13.1 Line IN Port
      2. 4.13.2 MIC Input Port
      3. 4.13.3 Line Out Port
      4. 4.13.4 Head Phone Port
      5. 4.13.5 Port Mapping
    14. 4.14 CAN Interface
      1. 4.14.1 MCU CAN0
      2. 4.14.2 MCU CAN1
      3. 4.14.3 MAIN CAN3 (supports WAKE function)
      4. 4.14.4 MAIN CAN0
    15. 4.15 FPD Interface (Audio Deserializer)
    16. 4.16 I3C Interface
      1. 4.16.1 Gyroscope
      2. 4.16.2 I3C Header
    17. 4.17 ADC Interface
    18. 4.18 RTC Interface
    19. 4.19 Apple Authentication Header
      1. 4.19.1 Module Interface
    20. 4.20 JTAG Emulation
    21. 4.21 EVM Expansion Connectors
    22. 4.22 ENET Expansion Connector
      1. 4.22.1 Power Requirements
      2. 4.22.2 Clock
        1. 4.22.2.1 Main Clock
        2. 4.22.2.2 Optional Clock
      3. 4.22.3 Reset Signals
      4. 4.22.4 Ethernet Interface
        1. 4.22.4.1 Quad Port SGMII PHY Default Configuration
      5. 4.22.5 Board ID EEPROM Interface
  6. 5Functional Safety
  7. 6Revision History

4.5.7 J7200 SoC DDR Retention Operation

The EVM supports a low power state referred to as DDR retention. This state allows the processor (or optionally the entire system) to be powered off while the LPDDR4 memory is maintained in self refresh mode. The power state is managed through the PMIC(s). Table 23 shows the steps required to enter the DDR retention state.

Table 4-8 J7200 DDR Retention Logic Flow
PMIC Transition From Active Mode to DDR Retention Mode
Action Address Bits Data Register/Bit Names
Unmask MASK_GPIO9_11 on PMIC (I2CID: 0x48) 0x51 [5:0] 0x2F MASK_GPIO9_11
Read and write default values of INT_GPIO to clear the WKUP1 interrupt 0x63 [7:0] Read value INT_GPIO
Set GPIO2 & GPIO3 to GPIO mode 0x32, 0x33 [7:0] 0xD GPIO2_CONF GPIO3_CONF
Write ‘1’ to GPIO2_OUT 0x3D [7:0] 0x2 GPIO_OUT_1
Write ‘1’ to GPIO2_OUT and GPIO3_OUT 0x3D [7:0] 0x06 GPIO_OUT_1
Reconfigure GPIO4 of Leo to LP_WKUP1 0x34 [7:0] 0xC8 GPIO4_CONFIG
Set GPIO4_RISE_MASK to ‘0’ to enable CAN_WKUP 0x50 [3] 0x0 GPIO4_RISE_MASK
Read and write default values of GPIO_INT to clear the LP_WKUP1 interrupt 0x64 [7:0] Read value GPIO_INT
Set TRIGGER_I2C_7 on Leo to '1' to enable (I2CID: 0x48) 0x85 [7] 0x80 FSM_I2C_TRIGGERS
Set TRIGGER_I2C_7 on Hera to '1' to enable (I2CID: 0x4C) 0x85 [7] 0x80 FSM_I2C_TRIGGERS
Set nSLEEP2b and nSLEEP1b to '00' to go to S2R state 0x86 [1:0] 0x0 NSLEEP2b, NSLEEP1b
Read and write to clear the ENABLE_INT interrupt 0x65 [1] 0x1 ENABLE_INT

The EVM can be woke from the low power state either by pressing the CAN_WAKEn button (SW12) or by issuing commands to the PMIC through I2C.