SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Table 9-6 lists the memory-mapped registers for the BGCRC_REGS registers. All register offset addresses not listed in Table 9-6 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | BGCRC_EN | BGCRC Enable | EALLOW | Go |
2h | BGCRC_CTRL1 | BGCRC Control register 1 | EALLOW | Go |
4h | BGCRC_CTRL2 | BGCRC Control register 2 | EALLOW | Go |
6h | BGCRC_START_ADDR | Start address for the BGCRC check | EALLOW | Go |
8h | BGCRC_SEED | Seed for CRC calculation | EALLOW | Go |
Eh | BGCRC_GOLDEN | Golden CRC to be compared against | EALLOW | Go |
10h | BGCRC_RESULT | CRC calculated | Go | |
12h | BGCRC_CURR_ADDR | Current address regsiter | Go | |
1Ch | BGCRC_WD_CFG | BGCRC windowed watchdog configuration | EALLOW | Go |
1Eh | BGCRC_WD_MIN | BGCRC windowed watchdog min value | EALLOW | Go |
20h | BGCRC_WD_MAX | BGCRC windowed watchdog max value | EALLOW | Go |
22h | BGCRC_WD_CNT | BGCRC windowed watchdog count | Go | |
2Ah | BGCRC_NMIFLG | BGCRC NMI flag register | Go | |
2Ch | BGCRC_NMICLR | BGCRC NMI flag clear register | EALLOW | Go |
2Eh | BGCRC_NMIFRC | BGCRC NMI flag force register | EALLOW | Go |
34h | BGCRC_INTEN | Interrupt enable | EALLOW | Go |
36h | BGCRC_INTFLG | Interrupt flag | Go | |
38h | BGCRC_INTCLR | Interrupt flag clear | EALLOW | Go |
3Ah | BGCRC_INTFRC | Interrupt flag force | EALLOW | Go |
3Ch | BGCRC_LOCK | BGCRC register map lockconfiguration | EALLOW | Go |
3Eh | BGCRC_COMMIT | BGCRC register map commit configuration | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 9-7 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value |
BGCRC_EN is shown in Figure 9-7 and described in Table 9-8.
Return to the Summary Table.
BGCRC Enable
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RUN_STS | RESERVED | ||||||
R-0h | R-0-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | START | ||||||
R-0-0h | R-0/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RUN_STS | R | 0h | Status bit: 0 : CRC module is IDLE 1 : CRC module is Active This bit will remain set during BGCRC_CTRL2.TEST_HALT = 1 Reset type: CPUx.SYSRSn |
30-16 | RESERVED | R-0 | 0h | Reserved |
15-4 | RESERVED | R-0 | 0h | Reserved |
3-0 | START | R-0/W | 0h | Start Bit: '1010': Kick-off CRC calculations 'any other value': ignored Notes: BGCRC_WD_CNT regsters will be reset CRCEN.START = '1010'. BGCRC_INTFLG, BGCRC_NMIFLG will not be impacted by this configuration. This bit should not be set before the previous CRC computation completes. Reset type: CPUx.SYSRSn |
BGCRC_CTRL1 is shown in Figure 9-8 and described in Table 9-9.
Return to the Summary Table.
BGCRC Control register 1
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | NMIDIS | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FREE_SOFT | RESERVED | |||||
R-0-0h | R/W-0h | R-0-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19-16 | NMIDIS | R/W | 0h | 1010 : NMI is disabled Any other value : NMI is enabled. Reset type: CPUx.SYSRSn |
15-5 | RESERVED | R-0 | 0h | Reserved |
4 | FREE_SOFT | R/W | 0h | Emulation control bit : This bit controls behaviour of CRC calculation during emulation 0 : Soft, CRC module and CRC Watchdog stops immediately on DEBUG SUSPEND (of CRC-controller ). 1 : Free, CRC calcuation and CRC watchdog is not affected by DEBUG HALT (of CRC-controller ) Reset type: CPUx.SYSRSn |
3-0 | RESERVED | R-0 | 0h | Reserved |
BGCRC_CTRL2 is shown in Figure 9-9 and described in Table 9-10.
Return to the Summary Table.
BGCRC Control register 2
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | SCRUB_MODE | ||||||
R-0-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TEST_HALT | RESERVED | BLOCK_SIZE | |||||
R/W-0h | R-0-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BLOCK_SIZE | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19-16 | SCRUB_MODE | R/W | 0h | Scrub mode configuration 1010 : Scrub mode, CRC of data is not compared with the golden CRC. Error check is done using the ECC/Parity logic. Any other value: CRC value is compared with golden CRC at the end in addition to the data correctness check by ECC/Parity logic. Notes: 1010 configuration is used for scrub mode (for data memories) where the memory value is read and ECC/Parity logic is used for the error detection. BGCRC_RESULT.CRC_VALUE is not updated in this configuration. Reset type: CPUx.SYSRSn |
15-12 | TEST_HALT | R/W | 0h | Halt Bit : 1010 : Module operation is stopped Any other value : CRC calaculation will continue/resume from where it was halted Notes: BGCRC_EN.START = 1010 configuration with TEST_HALT = 1010 will halt the CRC calculation. The new check will resume when TEST_HALT is configured to a value other than 1010 Reset type: CPUx.SYSRSn |
11-10 | RESERVED | R-0 | 0h | Reserved |
9-0 | BLOCK_SIZE | R/W | 0h | Configures the block size for the check 0x0 : 256 Byte (default) 0x1 : 512 Byte 0x2 : 768 Byte 0x3 : 1KB ... 0x3FF : 256KB (0xn : (n+1)*256Byte) Reset type: CPUx.SYSRSn |
BGCRC_START_ADDR is shown in Figure 9-10 and described in Table 9-11.
Return to the Summary Table.
Start address for the BGCRC check
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
START_ADDRESS | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | START_ADDRESS | R/W | 0h | START_ADDRESS indicates the start point of the test. (For CPU_CRC, this will be the CPU address. For CLA_CRC, this will be the CLA address where the memory is mapped) Reset type: CPUx.SYSRSn |
BGCRC_SEED is shown in Figure 9-11 and described in Table 9-12.
Return to the Summary Table.
Seed for CRC calculation
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEED | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SEED | R/W | 0h | Initial value of CRC, this value is coiped to the CRC register on triggering CRC calculation by writing to START bit. Reset type: CPUx.SYSRSn |
BGCRC_GOLDEN is shown in Figure 9-12 and described in Table 9-13.
Return to the Summary Table.
Golden CRC to be compared against
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC_VALUE | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC_VALUE | R/W | 0h | Golden CRC register: If CRC check is enabled, the calcuated CRC value is compared with golden CRC and status is updated. Reset type: CPUx.SYSRSn |
BGCRC_RESULT is shown in Figure 9-13 and described in Table 9-14.
Return to the Summary Table.
CRC calculated
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CRC_VALUE | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CRC_VALUE | R | 0h | CRC result register This reister value will be updated only on the completion of CRC check on a block of data as programmed by BGCRC_CTRL2.BLOCK_SIZE. Reset type: CPUx.SYSRSn |
BGCRC_CURR_ADDR is shown in Figure 9-14 and described in Table 9-15.
Return to the Summary Table.
Current address regsiter
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CURRENT_ADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CURRENT_ADDR | R | 0h | Current address from where the data is fetched. During a failure, the CURRENT_ADDR field indicates the value from where the last fetch happened. Reset type: CPUx.SYSRSn |
BGCRC_WD_CFG is shown in Figure 9-15 and described in Table 9-16.
Return to the Summary Table.
BGCRC windowed watchdog configuration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WDDIS | ||||||||||||||
R-0-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3-0 | WDDIS | R/W | 0h | 1010: CRC Watchdog counter is disabled. Any other value: CRC watchdog is enabled Watchdog is an upcounter and starts counting when BGCRC_EN.START is asserted. Watchdog continues to count during TEST_HALT state also(BGCRC_CTRL2.TEST_HALT = '1010'). CRC watchdog can be disabled during TEST_HALT by explicit configuration. (BGCRC_WD_CFG.WDDIS = 1010). Once the watchdog is disabled and re-enabled, watchdog count resumes from the previous disabled point. Reset type: CPUx.SYSRSn |
BGCRC_WD_MIN is shown in Figure 9-16 and described in Table 9-17.
Return to the Summary Table.
BGCRC windowed watchdog min value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MINVAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MINVAL | R/W | 0h | If the CRC computation completes before BGCRC_WD_MIN.MINVAL FAIL_STATUS.WD_UNDERFLOW flag gets set. Reset type: CPUx.SYSRSn |
BGCRC_WD_MAX is shown in Figure 9-17 and described in Table 9-18.
Return to the Summary Table.
BGCRC windowed watchdog max value
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MAXVAL | |||||||||||||||||||||||||||||||
R/W-FFFFFFFFh | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MAXVAL | R/W | FFFFFFFFh | If the CRC computation doesn't complete before BGCRC_WD_MIN.MAXVAL FAIL_STATUS.WD_OVERFLOW flag gets set. Reset type: CPUx.SYSRSn |
BGCRC_WD_CNT is shown in Figure 9-18 and described in Table 9-19.
Return to the Summary Table.
BGCRC windowed watchdog count
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
WD_CNT | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WD_CNT | R | 0h | CRC windowed watchdog counter value Counter value freezes at the end of CRC computation and will be reloaded only by BGCRC_EN.START = '1010' configuration. BGCRC_WD_CNT register freezes when a failure occurs. Reset type: CPUx.SYSRSn |
BGCRC_NMIFLG is shown in Figure 9-19 and described in Table 9-20.
Return to the Summary Table.
BGCRC NMI flag register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WD_OVERFLOW | WD_UNDERFLOW | CORRECTABLE_ERR | UNCORRECTABLE_ERR | CRC_FAIL | RESERVED | RESERVED |
R-0-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R-0 | 0h | Reserved |
6 | WD_OVERFLOW | R | 0h | Windowed watchdog Overflow. 1 : Test did not complete before BGCRC_WD_MAX.MAXVAL 0 : No such errors Reset type: CPUx.SYSRSn |
5 | WD_UNDERFLOW | R | 0h | Windowed watchdog underflow. 1 : Test completed before BGCRC_WD_MIN.MINVAL 0 : No such errors Reset type: CPUx.SYSRSn |
4 | CORRECTABLE_ERR | R | 0h | Correctable error indication: 0 : No ECC correctable error during memory read 1 : Correctable ECC error during memory read Note: ECC computation is done during every memory read. (Correctable errors are not ignored since the module doesn't write-back corrected value. The error remains in the memory and required corrective action need to be taken by CPU/CLA as part of ISR) Reset type: CPUx.SYSRSn |
3 | UNCORRECTABLE_ERR | R | 0h | Uncorrectable error indication: 0 : No ECC-uncorrectable/Parity error during memory read 1 : ECC-uncorrectable/Parity error during memory read Note: ECC/Parity check is done during every memory read. Reset type: CPUx.SYSRSn |
2 | CRC_FAIL | R | 0h | CRC FAIL interrupt 0 : No failure in CRC check. 1 : CRC check failure Note: Comparion is enabled only after CRC calc is completed Reset type: CPUx.SYSRSn |
1 | RESERVED | R-0 | 0h | Reserved |
0 | RESERVED | R-0 | 0h | Reserved |
BGCRC_NMICLR is shown in Figure 9-20 and described in Table 9-21.
Return to the Summary Table.
BGCRC NMI flag clear register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WD_OVERFLOW | WD_UNDERFLOW | CORRECTABLE_ERR | UNCORRECTABLE_ERR | CRC_FAIL | RESERVED | RESERVED |
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R-0 | 0h | Reserved |
6 | WD_OVERFLOW | R-0/W1S | 0h | Clear WD_OVERFLOW NMI flag 0 No effect 1 Clears NMI flag Reset type: CPUx.SYSRSn |
5 | WD_UNDERFLOW | R-0/W1S | 0h | Clear WD_UNDERFLOW NMI flag 0 No effect 1 Clears NMI flag Reset type: CPUx.SYSRSn |
4 | CORRECTABLE_ERR | R-0/W1S | 0h | Clear CORRECTABLE_ERR NMI flag 0 No effect 1 Clears NMI flag Reset type: CPUx.SYSRSn |
3 | UNCORRECTABLE_ERR | R-0/W1S | 0h | Clear UNCORRECTABLE_ERROR NMI flag 0 No effect 1 Clears NMI flag Reset type: CPUx.SYSRSn |
2 | CRC_FAIL | R-0/W1S | 0h | Clear CRC_FAIL NMI flag 0 No effect 1 Clears NMI flag Reset type: CPUx.SYSRSn |
1 | RESERVED | R-0 | 0h | Reserved |
0 | RESERVED | R-0 | 0h | Reserved |
BGCRC_NMIFRC is shown in Figure 9-21 and described in Table 9-22.
Return to the Summary Table.
BGCRC NMI flag force register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WD_OVERFLOW | WD_UNDERFLOW | CORRECTABLE_ERR | UNCORRECTABLE_ERR | CRC_FAIL | RESERVED | RESERVED |
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R-0 | 0h | Reserved |
6 | WD_OVERFLOW | R-0/W1S | 0h | Force WD_OVERFLOW NMI flag 0 No effect 1 force NMI flag Reset type: CPUx.SYSRSn |
5 | WD_UNDERFLOW | R-0/W1S | 0h | Force WD_UNDERFLOW NMI flag 0 No effect 1 force NMI flag Reset type: CPUx.SYSRSn |
4 | CORRECTABLE_ERR | R-0/W1S | 0h | Force CORRECTABLE_ERR NMI flag 0 No effect 1 force NMI flag Reset type: CPUx.SYSRSn |
3 | UNCORRECTABLE_ERR | R-0/W1S | 0h | Force UNCORRECTABLE_ERR NMI flag 0 No effect 1 force NMI flag Reset type: CPUx.SYSRSn |
2 | CRC_FAIL | R-0/W1S | 0h | Force CRC_FAIL NMI flag 0 No effect 1 force NMI flag Reset type: CPUx.SYSRSn |
1 | RESERVED | R-0 | 0h | Reserved |
0 | RESERVED | R-0 | 0h | Reserved |
BGCRC_INTEN is shown in Figure 9-22 and described in Table 9-23.
Return to the Summary Table.
Interrupt enable
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WD_OVERFLOW | WD_UNDERFLOW | CORRECTABLE_ERR | UNCORRECTABLE_ERR | CRC_FAIL | TEST_DONE | RESERVED |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | Reserved |
6 | WD_OVERFLOW | R/W | 0h | 0 WD_OVERFLOW Interrupt disabled 1 WD_OVERFLOW Interrupt enabled Reset type: CPUx.SYSRSn |
5 | WD_UNDERFLOW | R/W | 0h | 0 WD_UNDERFLOW Interrupt disabled 1 WD_UNDERFLOW Interrupt enabled Reset type: CPUx.SYSRSn |
4 | CORRECTABLE_ERR | R/W | 0h | 0 CORRECTABLE_ERR Interrupt disabled 1 CORRECTABLE_ERR Interrupt enabled Reset type: CPUx.SYSRSn |
3 | UNCORRECTABLE_ERR | R/W | 0h | 0 UNCORRECTABLE_ERR Interrupt disabled 1 UNCORRECTABLE_ERR Interrupt enabled Reset type: CPUx.SYSRSn |
2 | CRC_FAIL | R/W | 0h | 0 CRC_FAIL Interrupt disabled 1 CRC_FAIL Interrupt enabled Reset type: CPUx.SYSRSn |
1 | TEST_DONE | R/W | 0h | 0 TEST_DONE Interrupt disabled 1 TEST_DONE Interrupt enabled Reset type: CPUx.SYSRSn |
0 | RESERVED | R-0 | 0h | Reserved |
BGCRC_INTFLG is shown in Figure 9-23 and described in Table 9-24.
Return to the Summary Table.
Interrupt flag
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WD_OVERFLOW | WD_UNDERFLOW | CORRECTABLE_ERR | UNCORRECTABLE_ERR | CRC_FAIL | TEST_DONE | INT |
R-0-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R-0 | 0h | Reserved |
6 | WD_OVERFLOW | R | 0h | Windowed watchdog Overflow. 1 : Test did not completed before BGCRC_WD_MAX.MAXVAL 0 : No such errors Reset type: CPUx.SYSRSn |
5 | WD_UNDERFLOW | R | 0h | Windowed watchdog underflow. 1 : Test completed before BGCRC_WD_MIN.MINVAL 0 : No such errors Reset type: CPUx.SYSRSn |
4 | CORRECTABLE_ERR | R | 0h | Correctable error indication: 0 : No ECC correctable error during memory read 1 : Correctable ECC error during memory read Note: ECC computation is done during every memory read. (Correctable errors are not ignored since the module doesn't write-back corrected value. The error remains in the memory and required corrective action need to be taken by CPU/CLA as part of ISR) Reset type: CPUx.SYSRSn |
3 | UNCORRECTABLE_ERR | R | 0h | uncorrectable error indication: 0 : No ECC-uncorrectable/Parity error during memory read 1 : ECC-uncorrectable/Parity error during memory read Note: ECC/Parity check is done during every memory read. Reset type: CPUx.SYSRSn |
2 | CRC_FAIL | R | 0h | CRC fail interrupt 0 : No failure of CRC check 1 : CRC check failure Note: Comparion is enabled only after CRC calc is completed Reset type: CPUx.SYSRSn |
1 | TEST_DONE | R | 0h | Done Interrupt Status flag 0 CRC calculation is in progress or CRC module is idle. 1 CRC calculation is done. Note: TEST_DONE flag will get set on CRC calculation completion even in case of CRC mismatch Reset type: CPUx.SYSRSn |
0 | INT | R | 0h | Global Interrupt Status flag 0 No interrupt generated 1 Interrupt was generated Reset type: CPUx.SYSRSn |
BGCRC_INTCLR is shown in Figure 9-24 and described in Table 9-25.
Return to the Summary Table.
Interrupt flag clear
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WD_OVERFLOW | WD_UNDERFLOW | CORRECTABLE_ERR | UNCORRECTABLE_ERR | CRC_FAIL | TEST_DONE | INT |
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R-0 | 0h | Reserved |
6 | WD_OVERFLOW | R-0/W1S | 0h | Clear interrupt flag 0 No effect 1 Clears the interrupt flag Reset type: CPUx.SYSRSn |
5 | WD_UNDERFLOW | R-0/W1S | 0h | Clear interrupt flag 0 No effect 1 Clears the interrupt flag Reset type: CPUx.SYSRSn |
4 | CORRECTABLE_ERR | R-0/W1S | 0h | Clear interrupt flag 0 No effect 1 Clears the interrupt flag Reset type: CPUx.SYSRSn |
3 | UNCORRECTABLE_ERR | R-0/W1S | 0h | Clear interrupt flag 0 No effect 1 Clears the interrupt flag Reset type: CPUx.SYSRSn |
2 | CRC_FAIL | R-0/W1S | 0h | Clear interrupt flag 0 No effect 1 Clears the interrupt flag Reset type: CPUx.SYSRSn |
1 | TEST_DONE | R-0/W1S | 0h | Clear interrupt flag 0 No effect 1 Clears the interrupt flag Reset type: CPUx.SYSRSn |
0 | INT | R-0/W1S | 0h | Global Interrupt Clear 0 No effect 1 Clears the interrupt flag and enables further interrupts to be generated if an event flags is set to 1. Reset type: CPUx.SYSRSn |
BGCRC_INTFRC is shown in Figure 9-25 and described in Table 9-26.
Return to the Summary Table.
Interrupt flag force
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | WD_OVERFLOW | WD_UNDERFLOW | CORRECTABLE_ERR | UNCORRECTABLE_ERR | CRC_FAIL | TEST_DONE | RESERVED |
R-0-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R-0 | 0h | Reserved |
6 | WD_OVERFLOW | R-0/W1S | 0h | Force interrupt flag 0 No effect 1 force the interrupt flag Reset type: CPUx.SYSRSn |
5 | WD_UNDERFLOW | R-0/W1S | 0h | Force interrupt flag 0 No effect 1 force the interrupt flag Reset type: CPUx.SYSRSn |
4 | CORRECTABLE_ERR | R-0/W1S | 0h | Force interrupt flag 0 No effect 1 force the interrupt flag Reset type: CPUx.SYSRSn |
3 | UNCORRECTABLE_ERR | R-0/W1S | 0h | Force interrupt flag 0 No effect 1 force the interrupt flag Reset type: CPUx.SYSRSn |
2 | CRC_FAIL | R-0/W1S | 0h | Force interrupt flag 0 No effect 1 force the interrupt flag Reset type: CPUx.SYSRSn |
1 | TEST_DONE | R-0/W1S | 0h | Force interrupt flag 0 No effect 1 force the interrupt flag Reset type: CPUx.SYSRSn |
0 | RESERVED | R-0 | 0h | Reserved |
BGCRC_LOCK is shown in Figure 9-26 and described in Table 9-27.
Return to the Summary Table.
BGCRC register map lockconfiguration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | BGCRC_INTFRC | RESERVED | RESERVED | BGCRC_INTEN | RESERVED | RESERVED |
R-0-0h | R-0-0h | R/W-0h | R-0-0h | R-0-0h | R/W-0h | R-0-0h | R-0-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BGCRC_NMIFRC | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | BGCRC_WD_MAX |
R/W-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BGCRC_WD_MIN | BGCRC_WD_CFG | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BGCRC_GOLDEN | RESERVED | RESERVED | BGCRC_SEED | BGCRC_START_ADDR | BGCRC_CTRL2 | BGCRC_CTRL1 | BGCRC_EN |
R/W-0h | R-0-0h | R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R-0 | 0h | Reserved |
30 | RESERVED | R-0 | 0h | Reserved |
29 | BGCRC_INTFRC | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
28 | RESERVED | R-0 | 0h | Reserved |
27 | RESERVED | R-0 | 0h | Reserved |
26 | BGCRC_INTEN | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
25 | RESERVED | R-0 | 0h | Reserved |
24 | RESERVED | R-0 | 0h | Reserved |
23 | BGCRC_NMIFRC | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
22 | RESERVED | R-0 | 0h | Reserved |
21 | RESERVED | R-0 | 0h | Reserved |
20 | RESERVED | R-0 | 0h | Reserved |
19 | RESERVED | R-0 | 0h | Reserved |
18 | RESERVED | R-0 | 0h | Reserved |
17 | RESERVED | R-0 | 0h | Reserved |
16 | BGCRC_WD_MAX | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
15 | BGCRC_WD_MIN | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
14 | BGCRC_WD_CFG | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
13 | RESERVED | R-0 | 0h | Reserved |
12 | RESERVED | R-0 | 0h | Reserved |
11 | RESERVED | R-0 | 0h | Reserved |
10 | RESERVED | R-0 | 0h | Reserved |
9 | RESERVED | R-0 | 0h | Reserved |
8 | RESERVED | R-0 | 0h | Reserved |
7 | BGCRC_GOLDEN | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
6 | RESERVED | R-0 | 0h | Reserved |
5 | RESERVED | R-0 | 0h | Reserved |
4 | BGCRC_SEED | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
3 | BGCRC_START_ADDR | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
2 | BGCRC_CTRL2 | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
1 | BGCRC_CTRL1 | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
0 | BGCRC_EN | R/W | 0h | 0: Register configuration is not locked. 1: Register configuration is locked. Reset type: CPUx.SYSRSn |
BGCRC_COMMIT is shown in Figure 9-27 and described in Table 9-28.
Return to the Summary Table.
BGCRC register map commit configuration
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | BGCRC_INTFRC | RESERVED | RESERVED | BGCRC_INTEN | RESERVED | RESERVED |
R-0-0h | R-0-0h | R/WSonce-0h | R-0-0h | R-0-0h | R/WSonce-0h | R-0-0h | R-0-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
BGCRC_NMIFRC | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | BGCRC_WD_MAX |
R/WSonce-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h | R/WSonce-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BGCRC_WD_MIN | BGCRC_WD_CFG | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/WSonce-0h | R/WSonce-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h | R-0-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BGCRC_GOLDEN | RESERVED | RESERVED | BGCRC_SEED | BGCRC_START_ADDR | BGCRC_CTRL2 | BGCRC_CTRL1 | BGCRC_EN |
R/WSonce-0h | R-0-0h | R-0-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R-0 | 0h | Reserved |
30 | RESERVED | R-0 | 0h | Reserved |
29 | BGCRC_INTFRC | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
28 | RESERVED | R-0 | 0h | Reserved |
27 | RESERVED | R-0 | 0h | Reserved |
26 | BGCRC_INTEN | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
25 | RESERVED | R-0 | 0h | Reserved |
24 | RESERVED | R-0 | 0h | Reserved |
23 | BGCRC_NMIFRC | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
22 | RESERVED | R-0 | 0h | Reserved |
21 | RESERVED | R-0 | 0h | Reserved |
20 | RESERVED | R-0 | 0h | Reserved |
19 | RESERVED | R-0 | 0h | Reserved |
18 | RESERVED | R-0 | 0h | Reserved |
17 | RESERVED | R-0 | 0h | Reserved |
16 | BGCRC_WD_MAX | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
15 | BGCRC_WD_MIN | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
14 | BGCRC_WD_CFG | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
13 | RESERVED | R-0 | 0h | Reserved |
12 | RESERVED | R-0 | 0h | Reserved |
11 | RESERVED | R-0 | 0h | Reserved |
10 | RESERVED | R-0 | 0h | Reserved |
9 | RESERVED | R-0 | 0h | Reserved |
8 | RESERVED | R-0 | 0h | Reserved |
7 | BGCRC_GOLDEN | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
6 | RESERVED | R-0 | 0h | Reserved |
5 | RESERVED | R-0 | 0h | Reserved |
4 | BGCRC_SEED | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
3 | BGCRC_START_ADDR | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
2 | BGCRC_CTRL2 | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
1 | BGCRC_CTRL1 | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |
0 | BGCRC_EN | R/WSonce | 0h | 0: Register lock configuration is not committed. 1: Register configuration is committed. Once configuration is committed, only reset can change the configuration. Reset type: CPUx.SYSRSn |