SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Table 3-103 lists the memory-mapped registers for the DEV_CFG_REGS registers. All register offset addresses not listed in Table 3-103 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
8h | PARTIDL | Lower 32-bit of Device PART Identification Number | Go | |
Ah | PARTIDH | Upper 32-bit of Device PART Identification Number | Go | |
Ch | REVID | Device Revision Number | Go | |
74h | FUSEERR | e-Fuse error Status register | Go | |
82h | SOFTPRES0 | Processing Block Software Reset register | EALLOW | Go |
86h | SOFTPRES2 | EPWM Software Reset register | EALLOW | Go |
88h | SOFTPRES3 | ECAP Software Reset register | EALLOW | Go |
8Ah | SOFTPRES4 | EQEP Software Reset register | EALLOW | Go |
8Eh | SOFTPRES6 | Sigma Delta Software Reset register | EALLOW | Go |
90h | SOFTPRES7 | SCI Software Reset register | EALLOW | Go |
92h | SOFTPRES8 | SPI Software Reset register | EALLOW | Go |
94h | SOFTPRES9 | I2C Software Reset register | EALLOW | Go |
96h | SOFTPRES10 | CAN Software Reset register | EALLOW | Go |
9Ch | SOFTPRES13 | ADC Software Reset register | EALLOW | Go |
9Eh | SOFTPRES14 | CMPSS Software Reset register | EALLOW | Go |
A2h | SOFTPRES16 | DAC Software Reset register | EALLOW | Go |
A4h | SOFTPRES17 | CLB Software Reset register | EALLOW | Go |
A6h | SOFTPRES18 | FSI Software Reset register | EALLOW | Go |
A8h | SOFTPRES19 | LIN Software Reset register | EALLOW | Go |
AAh | SOFTPRES20 | PMBUS Software Reset register | EALLOW | Go |
ACh | SOFTPRES21 | DCC Software Reset register | EALLOW | Go |
B4h | SOFTPRES25 | HIC Software Reset register | EALLOW | Go |
B6h | SOFTPRES26 | AES Software Reset register | EALLOW | Go |
B8h | SOFTPRES27 | EPG Software Reset register | EALLOW | Go |
130h | TAP_STATUS | Status of JTAG State machine & Debugger Connect | Go | |
19Bh | ECAPTYPE | Configures ECAP Type for the device | EALLOW | Go |
19Ch | SDFMTYPE | Configures SDFM Type for the device | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-104 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1C | W 1C | Write 1 to clear |
W1S | W 1S | Write 1 to set |
WOnce | W Once | Write Write once |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
PARTIDL is shown in Figure 3-97 and described in Table 3-105.
Return to the Summary Table.
Lower 32-bit of Device PART Identification Number
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RESERVED | ||||||
R-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FLASH_SIZE | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | INSTASPIN | RESERVED | RESERVED | PIN_COUNT | |||
R-0h | R-X | R-0h | R-X | R-X | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUAL | RESERVED | RESERVED | RESERVED | ||||
R-X | R-0h | R-0h | R-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-24 | RESERVED | R | 0h | Reserved |
23-16 | FLASH_SIZE | R | X | 0x7 - 384KB 0x6 - 256KB 0x5 - 128KB Reset type: PORESETn |
15 | RESERVED | R | 0h | Reserved |
14-13 | INSTASPIN | R | X | 1 = InstaSPIN-FOC 2 = NONE 3 = NONE Reset type: PORESETn |
12 | RESERVED | R | 0h | Reserved |
11 | RESERVED | R | X | Reserved |
10-8 | PIN_COUNT | R | X | 1 = 64 pin (QFP - Q100) 2 = 64 pin (QFP) 3 = 80 pin (QFP) 4 = 48 pin (QFP) 5 = 100 pin (QFP) Reset type: PORESETn |
7-6 | QUAL | R | X | 0 = Engineering sample (TMX) 1 = Pilot production (TMP) 2 = Fully qualified (TMS) Reset type: PORESETn |
5 | RESERVED | R | 0h | Reserved |
4-3 | RESERVED | R | 0h | Reserved |
2-0 | RESERVED | R | 0h | Reserved |
PARTIDH is shown in Figure 3-98 and described in Table 3-106.
Return to the Summary Table.
Upper 32-bit of Device PART Identification Number
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DEVICE_CLASS_ID | PARTNO | ||||||||||||||
R-5h | R-X | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FAMILY | RESERVED | RESERVED | |||||||||||||
R-5h | R-0h | R-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | DEVICE_CLASS_ID | R | 5h | Device class ID Reset type: PORESETn |
23-16 | PARTNO | R | X | Refer to Datasheet for Device Part Number Reset type: PORESETn |
15-8 | FAMILY | R | 5h | Device Family Reset type: PORESETn |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | RESERVED | R | 0h | Reserved |
REVID is shown in Figure 3-99 and described in Table 3-107.
Return to the Summary Table.
Device Revision Number
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REVID | ||||||||||||||||||||||||||||||
R-0-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15-0 | REVID | R | 0h | Device Revision Reset type: N/A |
FUSEERR is shown in Figure 3-100 and described in Table 3-108.
Return to the Summary Table.
e-Fuse error Status register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ERR | ALERR | |||||||||||||
R-0-0h | R-0h | R-0h | |||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R-0 | 0h | Reserved |
5 | ERR | R | 0h | Efuse Self Test Error Status set by hardware after fuse self test completes, in case of self test error 0: No error during fuse self test 1: Fuse self test error Reset type: XRSn |
4-0 | ALERR | R | 0h | Efuse Autoload Error Status set by hardware after fuse auto load completes 00000: No error in auto load Other: Non zero value indicates error in autoload Note: [1] 10101 means a single-bit error during autoload. Since this gets corrected by the ECC mechanism, this value shouldn't be treated as an error condition. Reset type: XRSn |
SOFTPRES0 is shown in Figure 3-101 and described in Table 3-109.
Return to the Summary Table.
Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPU1_ERAD | ||||||
R-0-0h | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | CPU1_CLA1BGCRC | CPU1_CPUBGCRC | RESERVED | ||||
R-0-0h | R/W-0h | R/W-0h | R-0-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | CPU1_CLA1 | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R-0 | 0h | Reserved |
24 | CPU1_ERAD | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
23-16 | RESERVED | R-0 | 0h | Reserved |
15 | RESERVED | R-0 | 0h | Reserved |
14 | CPU1_CLA1BGCRC | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
13 | CPU1_CPUBGCRC | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
12-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | CPU1_CLA1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES2 is shown in Figure 3-102 and described in Table 3-110.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EPWM8 | EPWM7 | EPWM6 | EPWM5 | EPWM4 | EPWM3 | EPWM2 | EPWM1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R-0 | 0h | Reserved |
15 | RESERVED | R/W | 0h | Reserved |
14 | RESERVED | R/W | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12 | RESERVED | R/W | 0h | Reserved |
11 | RESERVED | R/W | 0h | Reserved |
10 | RESERVED | R/W | 0h | Reserved |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | EPWM8 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
6 | EPWM7 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
5 | EPWM6 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
4 | EPWM5 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
3 | EPWM4 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
2 | EPWM3 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | EPWM2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | EPWM1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES3 is shown in Figure 3-103 and described in Table 3-111.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | ECAP3 | ECAP2 | ECAP1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | ECAP3 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | ECAP2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | ECAP1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES4 is shown in Figure 3-104 and described in Table 3-112.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | EQEP2 | EQEP1 | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | EQEP2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | EQEP1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES6 is shown in Figure 3-105 and described in Table 3-113.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | SD2 | SD1 | |||||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | SD2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | SD1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES7 is shown in Figure 3-106 and described in Table 3-114.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | SCI_B | SCI_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | SCI_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | SCI_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES8 is shown in Figure 3-107 and described in Table 3-115.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | SPI_B | SPI_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R-0 | 0h | Reserved |
17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R/W | 0h | Reserved |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | SPI_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | SPI_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES9 is shown in Figure 3-108 and described in Table 3-116.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | I2C_B | I2C_A | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | I2C_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | I2C_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES10 is shown in Figure 3-109 and described in Table 3-117.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | MCAN_A | RESERVED | RESERVED | RESERVED | CAN_A |
R-X | R-X | R-X | R-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R | X | Reserved |
6 | RESERVED | R | X | Reserved |
5 | RESERVED | R | X | Reserved |
4 | MCAN_A | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | CAN_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES13 is shown in Figure 3-110 and described in Table 3-118.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | ADC_C | ADC_B | ADC_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | ADC_C | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | ADC_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | ADC_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES14 is shown in Figure 3-111 and described in Table 3-119.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | CMPSS4 | CMPSS3 | CMPSS2 | CMPSS1 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R-0 | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | CMPSS4 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
2 | CMPSS3 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | CMPSS2 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | CMPSS1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES16 is shown in Figure 3-112 and described in Table 3-120.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | DAC_B | DAC_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R-0 | 0h | Reserved |
19 | RESERVED | R/W | 0h | Reserved |
18 | RESERVED | R/W | 0h | Reserved |
17 | DAC_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
16 | DAC_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
15-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
SOFTPRES17 is shown in Figure 3-113 and described in Table 3-121.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLB4 | CLB3 | CLB2 | CLB1 | |||
R-0h | R/W-0h | R/W-0h | R-X | R-X | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CLB4 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
2 | CLB3 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
1 | CLB2 | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | CLB1 | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES18 is shown in Figure 3-114 and described in Table 3-122.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | FSIRX_A | FSITX_A | |||
R-0h | R/W-0h | R/W-0h | R-X | R-X | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | FSIRX_A | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | FSITX_A | R | X | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES19 is shown in Figure 3-115 and described in Table 3-123.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | LIN_B | LIN_A | |||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R-0 | 0h | Reserved |
3 | RESERVED | R/W | 0h | Reserved |
2 | RESERVED | R/W | 0h | Reserved |
1 | LIN_B | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | LIN_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES20 is shown in Figure 3-116 and described in Table 3-124.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | PMBUS_A | |||||
R-0h | R-0h | R-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R | 0h | Reserved |
0 | PMBUS_A | R | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES21 is shown in Figure 3-117 and described in Table 3-125.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DCC1 | DCC0 | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R-0 | 0h | Reserved |
1 | DCC1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
0 | DCC0 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES25 is shown in Figure 3-118 and described in Table 3-126.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HIC_A | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | HIC_A | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES26 is shown in Figure 3-119 and described in Table 3-127.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | AESA | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | AESA | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
SOFTPRES27 is shown in Figure 3-120 and described in Table 3-128.
Return to the Summary Table.
Peripheral Software Reset register
When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EPG1 | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R-0 | 0h | Reserved |
0 | EPG1 | R/W | 0h | 1: Module is under reset 0: Module reset is determined by the normal device reset structure Reset type: SYSRSn |
TAP_STATUS is shown in Figure 3-121 and described in Table 3-129.
Return to the Summary Table.
Status of JTAG State machine & Debugger Connect
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DCON | RESERVED | ||||||
R-0h | R-0-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TAP_STATE | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TAP_STATE | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | DCON | R | 0h | DebugConnect indication from IcePick. Reset type: PORESETn |
30-16 | RESERVED | R-0 | 0h | Reserved |
15-0 | TAP_STATE | R | 0h | TAP State Vector. With bits representing, Connect coresponding POTAP* output to the 0:TLR, 1:IDLE, 2:SELECTDR, 3:CAPDR, 4:SHIFTDR, 5:EXIT1DR, 6:PAUSEDR, 7:EXIT2DR, 8:UPDTDR, 9:SLECTIR, 10:CAPIR, 11:SHIFTIR, 12:EXIT1IR, 13:PAUSEIR, 14:EXIT2IR, 15:UPDTIR, Reset type: PORESETn |
ECAPTYPE is shown in Figure 3-122 and described in Table 3-130.
Return to the Summary Table.
Based on the configuration enables disables features associated with the ECAP type.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOCK | RESERVED | ||||||
R/WSonce-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TYPE | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LOCK | R/WSonce | 0h | 1: Write to this register is not allowed. 0: Write to this register is allowed. Reset type: SYSRSn |
14-2 | RESERVED | R-0 | 0h | Reserved |
1-0 | TYPE | R/W | 0h | '00,10,11' : 1. No EALLOW protection to ECAP registers. '01' : 1. ECAP registers are EALLOW protected. Reset type: SYSRSn |
SDFMTYPE is shown in Figure 3-123 and described in Table 3-131.
Return to the Summary Table.
Based on the configuration enables disables features associated with the SDFM type.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
LOCK | RESERVED | ||||||
R/WSonce-0h | R-0-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TYPE | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | LOCK | R/WSonce | 0h | 1: Write to this register is not allowed. 0: Write to this register is allowed. Reset type: SYSRSn |
14-2 | RESERVED | R-0 | 0h | Reserved |
1-0 | TYPE | R/W | 0h | '00,10,11' : 1. Data Ready conditions combined with the fault conditions on the SDFM interrupt line. 2. Data ready interrupts from individual filters are not generated. '01' : 1. Data Ready conditions do not generate the SDFMINT. 2. Each filter generates a separate data ready interrupts. Reset type: SYSRSn |