SPRUIW9C October 2021 – March 2024 TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1
Table 3-17 lists the memory-mapped registers for the ACCESS_PROTECTION_REGS registers. All register offset addresses not listed in Table 3-17 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
0h | NMAVFLG | Non-Master Access Violation Flag Register | Go | |
2h | NMAVSET | Non-Master Access Violation Flag Set Register | EALLOW | Go |
4h | NMAVCLR | Non-Master Access Violation Flag Clear Register | EALLOW | Go |
6h | NMAVINTEN | Non-Master Access Violation Interrupt Enable Register | EALLOW | Go |
8h | NMCPURDAVADDR | Non-Master CPU Read Access Violation Address | Go | |
Ah | NMCPUWRAVADDR | Non-Master CPU Write Access Violation Address | Go | |
Ch | NMCPUFAVADDR | Non-Master CPU Fetch Access Violation Address | Go | |
Eh | NMDMAWRAVADDR | Non-Master DMA Write Access Violation Address | Go | |
10h | NMCLA1RDAVADDR | Non-Master CLA1 Read Access Violation Address | Go | |
12h | NMCLA1WRAVADDR | Non-Master CLA1 Write Access Violation Address | Go | |
14h | NMCLA1FAVADDR | Non-Master CLA1 Fetch Access Violation Address | Go | |
1Ch | NMDMARDAVADDR | Non-Master DMA Read Access Violation Address | Go | |
20h | MAVFLG | Master Access Violation Flag Register | Go | |
22h | MAVSET | Master Access Violation Flag Set Register | EALLOW | Go |
24h | MAVCLR | Master Access Violation Flag Clear Register | EALLOW | Go |
26h | MAVINTEN | Master Access Violation Interrupt Enable Register | EALLOW | Go |
28h | MCPUFAVADDR | Master CPU Fetch Access Violation Address | Go | |
2Ah | MCPUWRAVADDR | Master CPU Write Access Violation Address | Go | |
2Ch | MDMAWRAVADDR | Master DMA Write Access Violation Address | Go | |
2Eh + formula | MHICWRAVADDR_y | Master HIC Write Access Violation Address | Go | |
3Ch | NMHICRDAVADDR | Non-Master HIC Read Access Violation Address | Go | |
3Eh | NMHICWRAVADDR | Non-Master HIC Write Access Violation Address | Go |
Complex bit access types are encoded to fit into small table cells. Table 3-18 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
NMAVFLG is shown in Figure 3-19 and described in Table 3-19.
Return to the Summary Table.
Non-Master Access Violation Flag Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HICWRITE | HICREAD | DMAREAD | RESERVED | RESERVED | ||
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLA1FETCH | CLA1WRITE | CLA1READ | DMAWRITE | CPUFETCH | CPUWRITE | CPUREAD |
R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-13 | RESERVED | R | 0h | Reserved |
12 | HICWRITE | R | 0h | Non Master HIC Write Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
11 | HICREAD | R | 0h | Non Master HIC Read Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
10 | DMAREAD | R | 0h | Non Master DMA Read Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
9 | RESERVED | R | 0h | Reserved |
8 | RESERVED | R | 0h | Reserved |
7 | RESERVED | R | 0h | Reserved |
6 | CLA1FETCH | R | 0h | Non Master CLA1 Fetch Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
5 | CLA1WRITE | R | 0h | Non Master CLA1 Write Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
4 | CLA1READ | R | 0h | Non Master CLA1 Read Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
3 | DMAWRITE | R | 0h | Non Master DMA Write Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
2 | CPUFETCH | R | 0h | Non Master CPU Fetch Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
1 | CPUWRITE | R | 0h | Non Master CPU Write Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
0 | CPUREAD | R | 0h | Non Master CPU Read Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
NMAVSET is shown in Figure 3-20 and described in Table 3-20.
Return to the Summary Table.
Non-Master Access Violation Flag Set Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HICWRITE | HICREAD | DMAREAD | RESERVED | RESERVED | ||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLA1FETCH | CLA1WRITE | CLA1READ | DMAWRITE | CPUFETCH | CPUWRITE | CPUREAD |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-13 | RESERVED | R | 0h | Reserved |
12 | HICWRITE | R-0/W1S | 0h | 0: No action. 1: HIC Write Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
11 | HICREAD | R-0/W1S | 0h | 0: No action. 1: HIC Read Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
10 | DMAREAD | R-0/W1S | 0h | 0: No action. 1: DMA Read Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | CLA1FETCH | R-0/W1S | 0h | 0: No action. 1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
5 | CLA1WRITE | R-0/W1S | 0h | 0: No action. 1: CLA1 Write Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
4 | CLA1READ | R-0/W1S | 0h | 0: No action. 1: CLA1 Read Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
3 | DMAWRITE | R-0/W1S | 0h | 0: No action. 1: DMA Write Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
2 | CPUFETCH | R-0/W1S | 0h | 0: No action. 1: CPU Fetch Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
1 | CPUWRITE | R-0/W1S | 0h | 0: No action. 1: CPU Write Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
0 | CPUREAD | R-0/W1S | 0h | 0: No action. 1: CPU Read Access Violation Flag in NMAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
NMAVCLR is shown in Figure 3-21 and described in Table 3-21.
Return to the Summary Table.
Non-Master Access Violation Flag Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HICWRITE | HICREAD | DMAREAD | RESERVED | RESERVED | ||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLA1FETCH | CLA1WRITE | CLA1READ | DMAWRITE | CPUFETCH | CPUWRITE | CPUREAD |
R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-13 | RESERVED | R | 0h | Reserved |
12 | HICWRITE | R-0/W1S | 0h | 0: No action. 1: HIC Write Access Violation Flag in NMAVFLG register will be cleared. Reset type: SYSRSn |
11 | HICREAD | R-0/W1S | 0h | 0: No action. 1: HIC Read Access Violation Flag in NMAVFLG register will be cleared. Reset type: SYSRSn |
10 | DMAREAD | R-0/W1S | 0h | 0: No action. 1: DMA Read Access Violation Flag in NMAVFLG register will be cleared. Reset type: SYSRSn |
9 | RESERVED | R-0/W1S | 0h | Reserved |
8 | RESERVED | R-0/W1S | 0h | Reserved |
7 | RESERVED | R-0/W1S | 0h | Reserved |
6 | CLA1FETCH | R-0/W1S | 0h | 0: No action. 1: CLA1 Fetch Access Violation Flag in NMAVFLG register will be cleared. Reset type: SYSRSn |
5 | CLA1WRITE | R-0/W1S | 0h | 0: No action. 1: CLA1 Write Access Violation Flag in NMAVFLG register will be cleared. Reset type: SYSRSn |
4 | CLA1READ | R-0/W1S | 0h | 0: No action. 1: CLA1 Read Access Violation Flag in NMAVFLG register will be cleared. Reset type: SYSRSn |
3 | DMAWRITE | R-0/W1S | 0h | 0: No action. 1: DMA Write Access Violation Flag in NMAVFLG register will be cleared. Reset type: SYSRSn |
2 | CPUFETCH | R-0/W1S | 0h | 0: No action. 1: CPU Fetch Access Violation Flag in NMAVFLG register will be cleared. Reset type: SYSRSn |
1 | CPUWRITE | R-0/W1S | 0h | 0: No action. 1: CPU Write Access Violation Flag in NMAVFLG register will be cleared. Reset type: SYSRSn |
0 | CPUREAD | R-0/W1S | 0h | 0: No action. 1: CPU Read Access Violation Flag in NMAVFLG register will be cleared. Reset type: SYSRSn |
NMAVINTEN is shown in Figure 3-22 and described in Table 3-22.
Return to the Summary Table.
Non-Master Access Violation Interrupt Enable Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | HICWRITE | HICREAD | DMAREAD | RESERVED | RESERVED | ||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLA1FETCH | CLA1WRITE | CLA1READ | DMAWRITE | CPUFETCH | CPUWRITE | CPUREAD |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-13 | RESERVED | R | 0h | Reserved |
12 | HICWRITE | R/W | 0h | 0: HIC Non Master Write Access Violation Interrupt is disabled. 1: HIC Non Master Write Access Violation Interrupt is enabled. Reset type: SYSRSn |
11 | HICREAD | R/W | 0h | 0: HIC Non Master Read Access Violation Interrupt is disabled. 1: HIC Non Master Read Access Violation Interrupt is enabled. Reset type: SYSRSn |
10 | DMAREAD | R/W | 0h | 0: DMA Non Master Read Access Violation Interrupt is disabled. 1: DMA Non Master Read Access Violation Interrupt is enabled. Reset type: SYSRSn |
9 | RESERVED | R/W | 0h | Reserved |
8 | RESERVED | R/W | 0h | Reserved |
7 | RESERVED | R/W | 0h | Reserved |
6 | CLA1FETCH | R/W | 0h | 0: CLA1 Non Master Fetch Access Violation Interrupt is disabled. 1: CLA1 Non Master Fetch Access Violation Interrupt is enabled. Reset type: SYSRSn |
5 | CLA1WRITE | R/W | 0h | 0: CLA1 Non Master Write Access Violation Interrupt is disabled. 1: CLA1 Non Master Write Access Violation Interrupt is enabled. Reset type: SYSRSn |
4 | CLA1READ | R/W | 0h | 0: CLA1 Non Master Read Access Violation Interrupt is disabled. 1: CLA1 Non Master Read Access Violation Interrupt is enabled. Reset type: SYSRSn |
3 | DMAWRITE | R/W | 0h | 0: DMA Non Master Write Access Violation Interrupt is disabled. 1: DMA Non Master Write Access Violation Interrupt is enabled. Reset type: SYSRSn |
2 | CPUFETCH | R/W | 0h | 0: CPU Non Master Fetch Access Violation Interrupt is disabled. 1: CPU Non Master Fetch Access Violation Interrupt is enabled. Reset type: SYSRSn |
1 | CPUWRITE | R/W | 0h | 0: CPU Non Master Write Access Violation Interrupt is disabled. 1: CPU Non Master Write Access Violation Interrupt is enabled. Reset type: SYSRSn |
0 | CPUREAD | R/W | 0h | 0: CPU Non Master Read Access Violation Interrupt is disabled. 1: CPU Non Master Read Access Violation Interrupt is enabled. Reset type: SYSRSn |
NMCPURDAVADDR is shown in Figure 3-23 and described in Table 3-23.
Return to the Summary Table.
Non-Master CPU Read Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMCPURDAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NMCPURDAVADDR | R | 0h | This register captures the address location for which non master CPU read access violation occurred. Reset type: SYSRSn |
NMCPUWRAVADDR is shown in Figure 3-24 and described in Table 3-24.
Return to the Summary Table.
Non-Master CPU Write Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMCPUWRAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NMCPUWRAVADDR | R | 0h | This register captures the address location for which non master CPU write access violation occurred. Reset type: SYSRSn |
NMCPUFAVADDR is shown in Figure 3-25 and described in Table 3-25.
Return to the Summary Table.
Non-Master CPU Fetch Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMCPUFAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NMCPUFAVADDR | R | 0h | This register captures the address location for which non master CPU fetch access violation occurred. Reset type: SYSRSn |
NMDMAWRAVADDR is shown in Figure 3-26 and described in Table 3-26.
Return to the Summary Table.
Non-Master DMA Write Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMDMAWRAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NMDMAWRAVADDR | R | 0h | This register captures the address location for which non master DMA write access violation occurred. Reset type: SYSRSn |
NMCLA1RDAVADDR is shown in Figure 3-27 and described in Table 3-27.
Return to the Summary Table.
Non-Master CLA1 Read Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMCLA1RDAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NMCLA1RDAVADDR | R | 0h | This register captures the address location for which non master CLA1 read access violation occurred. Reset type: SYSRSn |
NMCLA1WRAVADDR is shown in Figure 3-28 and described in Table 3-28.
Return to the Summary Table.
Non-Master CLA1 Write Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMCLA1WRAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NMCLA1WRAVADDR | R | 0h | This register captures the address location for which non master CLA1 write access violation occurred. Reset type: SYSRSn |
NMCLA1FAVADDR is shown in Figure 3-29 and described in Table 3-29.
Return to the Summary Table.
Non-Master CLA1 Fetch Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMCLA1FAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NMCLA1FAVADDR | R | 0h | This register captures the address location for which non master CLA1 fetch access violation occurred. Reset type: SYSRSn |
NMDMARDAVADDR is shown in Figure 3-30 and described in Table 3-30.
Return to the Summary Table.
Non-Master DMA Read Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMDMARDAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NMDMARDAVADDR | R | 0h | This register captures the address location for which non master DMA read access violation occurred. Reset type: SYSRSn |
MAVFLG is shown in Figure 3-31 and described in Table 3-31.
Return to the Summary Table.
Master Access Violation Flag Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HICAWRITE | DMAWRITE | CPUWRITE | CPUFETCH | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | HICAWRITE | R | 0h | Master HICA Write Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
2 | DMAWRITE | R | 0h | Master DMA Write Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
1 | CPUWRITE | R | 0h | Master CPU Write Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
0 | CPUFETCH | R | 0h | Master CPU Fetch Access Violation Flag: 0: No violation. 1: Access violation occured. Reset type: SYSRSn |
MAVSET is shown in Figure 3-32 and described in Table 3-32.
Return to the Summary Table.
Master Access Violation Flag Set Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HICAWRITE | DMAWRITE | CPUWRITE | CPUFETCH | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | HICAWRITE | R-0/W1S | 0h | 0: No action. 1: HICA Write Access Violation Flag in MAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
2 | DMAWRITE | R-0/W1S | 0h | 0: No action. 1: DMA Write Access Violation Flag in MAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
1 | CPUWRITE | R-0/W1S | 0h | 0: No action. 1: CPU Write Access Violation Flag in MAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
0 | CPUFETCH | R-0/W1S | 0h | 0: No action. 1: CPU Fetch Access Violation Flag in MAVFLG register will be set and interrupt will be generated if enabled. Reset type: SYSRSn |
MAVCLR is shown in Figure 3-33 and described in Table 3-33.
Return to the Summary Table.
Master Access Violation Flag Clear Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HICAWRITE | DMAWRITE | CPUWRITE | CPUFETCH | |||
R-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | R-0/W1S-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | HICAWRITE | R-0/W1S | 0h | 0: No action. 1: HICA Write Access Violation Flag in MAVFLG register will be cleared. Reset type: SYSRSn |
2 | DMAWRITE | R-0/W1S | 0h | 0: No action. 1: DMA Write Access Violation Flag in MAVFLG register will be cleared. Reset type: SYSRSn |
1 | CPUWRITE | R-0/W1S | 0h | 0: No action. 1: CPU Write Access Violation Flag in MAVFLG register will be cleared . Reset type: SYSRSn |
0 | CPUFETCH | R-0/W1S | 0h | 0: No action. 1: CPU Fetch Access Violation Flag in MAVFLG register will be cleared. Reset type: SYSRSn |
MAVINTEN is shown in Figure 3-34 and described in Table 3-34.
Return to the Summary Table.
Master Access Violation Interrupt Enable Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | HICAWRITE | DMAWRITE | CPUWRITE | CPUFETCH | |||
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-4 | RESERVED | R | 0h | Reserved |
3 | HICAWRITE | R/W | 0h | 0: HICA Write Access Violation Interrupt is disabled. 1: HICA Write Access Violation Interrupt is enabled. Reset type: SYSRSn |
2 | DMAWRITE | R/W | 0h | 0: DMA Write Access Violation Interrupt is disabled. 1: DMA Write Access Violation Interrupt is enabled. Reset type: SYSRSn |
1 | CPUWRITE | R/W | 0h | 0: CPU Write Access Violation Interrupt is disabled. 1: CPU Write Access Violation Interrupt is enabled. Reset type: SYSRSn |
0 | CPUFETCH | R/W | 0h | 0: CPU Fetch Access Violation Interrupt is disabled. 1: CPU Fetch Access Violation Interrupt is enabled. Reset type: SYSRSn |
MCPUFAVADDR is shown in Figure 3-35 and described in Table 3-35.
Return to the Summary Table.
Master CPU Fetch Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCPUFAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MCPUFAVADDR | R | 0h | This register captures the address location for which master CPU fetch access violation occurred. Reset type: SYSRSn |
MCPUWRAVADDR is shown in Figure 3-36 and described in Table 3-36.
Return to the Summary Table.
Master CPU Write Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MCPUWRAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MCPUWRAVADDR | R | 0h | This register captures the address location for which master CPU write access violation occurred. Reset type: SYSRSn |
MDMAWRAVADDR is shown in Figure 3-37 and described in Table 3-37.
Return to the Summary Table.
Master DMA Write Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MDMAWRAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MDMAWRAVADDR | R | 0h | This register captures the address location for which master DMA write access violation occurred. Reset type: SYSRSn |
MHICWRAVADDR_y is shown in Figure 3-38 and described in Table 3-38.
Return to the Summary Table.
Master HIC Write Access Violation Address
Offset = 2Eh + (y * 2h); where y = 0h to 1h
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MHICWRAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MHICWRAVADDR | R | 0h | This register captures the address location for which master HICA write access violation occurred. Reset type: SYSRSn |
NMHICRDAVADDR is shown in Figure 3-39 and described in Table 3-39.
Return to the Summary Table.
Non-Master HIC Read Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMHICRDAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NMHICRDAVADDR | R | 0h | This register captures the address location for which non master HIC read access violation occurred. Reset type: SYSRSn |
NMHICWRAVADDR is shown in Figure 3-40 and described in Table 3-40.
Return to the Summary Table.
Non-Master HIC Write Access Violation Address
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NMHICWRAVADDR | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | NMHICWRAVADDR | R | 0h | This register captures the address location for which non master HIC write access violation occurred. Reset type: SYSRSn |